trm.c revision 1.34
1 /* $NetBSD: trm.c,v 1.34 2013/09/15 14:53:03 martin Exp $ */ 2 /*- 3 * Copyright (c) 2002 Izumi Tsutsui. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 /* 27 * Device Driver for Tekram DC395U/UW/F, DC315/U 28 * PCI SCSI Bus Master Host Adapter 29 * (SCSI chip set used Tekram ASIC TRM-S1040) 30 * 31 * Copyright (c) 2001 Rui-Xiang Guo 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. The name of the author may not be used to endorse or promote products 43 * derived from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 /* 57 * Ported from 58 * dc395x_trm.c 59 * 60 * Written for NetBSD 1.4.x by 61 * Erich Chen (erich (at) tekram.com.tw) 62 * 63 * Provided by 64 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.34 2013/09/15 14:53:03 martin Exp $"); 69 70 /* #define TRM_DEBUG */ 71 #ifdef TRM_DEBUG 72 int trm_debug = 1; 73 #define DPRINTF(arg) if (trm_debug > 0) printf arg; 74 #else 75 #define DPRINTF(arg) 76 #endif 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/malloc.h> 81 #include <sys/buf.h> 82 #include <sys/kernel.h> 83 #include <sys/device.h> 84 #include <sys/queue.h> 85 86 #include <sys/bus.h> 87 #include <sys/intr.h> 88 89 #include <dev/scsipi/scsi_spc.h> 90 #include <dev/scsipi/scsi_all.h> 91 #include <dev/scsipi/scsi_message.h> 92 #include <dev/scsipi/scsipi_all.h> 93 #include <dev/scsipi/scsiconf.h> 94 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/trmreg.h> 99 100 /* 101 * feature of chip set MAX value 102 */ 103 #define TRM_MAX_TARGETS 16 104 #define TRM_MAX_LUNS 8 105 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 106 #define TRM_MAX_SRB 32 /* XXX */ 107 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 108 #define TRM_MAX_OFFSET 15 109 #define TRM_MAX_PERIOD 125 110 111 /* 112 * Segment Entry 113 */ 114 struct trm_sg_entry { 115 uint32_t address; 116 uint32_t length; 117 }; 118 119 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 120 121 /* 122 ********************************************************************** 123 * The SEEPROM structure for TRM_S1040 124 ********************************************************************** 125 */ 126 struct nvram_target { 127 uint8_t config0; /* Target configuration byte 0 */ 128 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 129 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 130 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 131 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 132 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 133 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 134 uint8_t period; /* Target period */ 135 uint8_t config2; /* Target configuration byte 2 */ 136 uint8_t config3; /* Target configuration byte 3 */ 137 }; 138 139 struct trm_nvram { 140 uint8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 141 uint8_t subsys_id[2]; /* 2,3 Sub System ID */ 142 uint8_t subclass; /* 4 Sub Class */ 143 uint8_t vendor_id[2]; /* 5,6 Vendor ID */ 144 uint8_t device_id[2]; /* 7,8 Device ID */ 145 uint8_t reserved0; /* 9 Reserved */ 146 struct nvram_target target[TRM_MAX_TARGETS]; 147 /* 10,11,12,13 148 * 14,15,16,17 149 * .... 150 * 70,71,72,73 */ 151 uint8_t scsi_id; /* 74 Host Adapter SCSI ID */ 152 uint8_t channel_cfg; /* 75 Channel configuration */ 153 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 154 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 155 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 156 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 157 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 158 uint8_t delay_time; /* 76 Power on delay time */ 159 uint8_t max_tag; /* 77 Maximum tags */ 160 uint8_t reserved1; /* 78 */ 161 uint8_t boot_target; /* 79 */ 162 uint8_t boot_lun; /* 80 */ 163 uint8_t reserved2; /* 81 */ 164 uint8_t reserved3[44]; /* 82,..125 */ 165 uint8_t checksum0; /* 126 */ 166 uint8_t checksum1; /* 127 */ 167 #define TRM_NVRAM_CKSUM 0x1234 168 }; 169 170 /* Nvram Initiater bits definition */ 171 #define MORE2_DRV 0x00000001 172 #define GREATER_1G 0x00000002 173 #define RST_SCSI_BUS 0x00000004 174 #define ACTIVE_NEGATION 0x00000008 175 #define NO_SEEK 0x00000010 176 #define LUN_CHECK 0x00000020 177 178 #define trm_eeprom_wait() DELAY(30) 179 180 /* 181 *----------------------------------------------------------------------- 182 * SCSI Request Block 183 *----------------------------------------------------------------------- 184 */ 185 struct trm_srb { 186 TAILQ_ENTRY(trm_srb) next; 187 188 struct trm_sg_entry *sgentry; 189 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 190 bus_dmamap_t dmap; 191 bus_size_t sgoffset; /* Xfer buf offset */ 192 193 uint32_t buflen; /* Total xfer length */ 194 uint32_t sgaddr; /* SGList physical starting address */ 195 196 int sgcnt; 197 int sgindex; 198 199 int hastat; /* Host Adapter Status */ 200 #define H_STATUS_GOOD 0x00 201 #define H_SEL_TIMEOUT 0x11 202 #define H_OVER_UNDER_RUN 0x12 203 #define H_UNEXP_BUS_FREE 0x13 204 #define H_TARGET_PHASE_F 0x14 205 #define H_INVALID_CCB_OP 0x16 206 #define H_LINK_CCB_BAD 0x17 207 #define H_BAD_TARGET_DIR 0x18 208 #define H_DUPLICATE_CCB 0x19 209 #define H_BAD_CCB_OR_SG 0x1A 210 #define H_ABORT 0xFF 211 int tastat; /* Target SCSI Status Byte */ 212 int flag; /* SRBFlag */ 213 #define AUTO_REQSENSE 0x0001 214 #define PARITY_ERROR 0x0002 215 #define SRB_TIMEOUT 0x0004 216 217 int cmdlen; /* SCSI command length */ 218 uint8_t cmd[12]; /* SCSI command */ 219 220 uint8_t tag[2]; 221 }; 222 223 /* 224 * some info about each target and lun on the SCSI bus 225 */ 226 struct trm_linfo { 227 int used; /* number of slots in use */ 228 int avail; /* where to start scanning */ 229 int busy; /* lun in use */ 230 struct trm_srb *untagged; 231 struct trm_srb *queued[TRM_MAX_TAG]; 232 }; 233 234 struct trm_tinfo { 235 u_int flag; /* Sync mode ? (1 sync):(0 async) */ 236 #define SYNC_NEGO_ENABLE 0x0001 237 #define SYNC_NEGO_DOING 0x0002 238 #define SYNC_NEGO_DONE 0x0004 239 #define WIDE_NEGO_ENABLE 0x0008 240 #define WIDE_NEGO_DOING 0x0010 241 #define WIDE_NEGO_DONE 0x0020 242 #define USE_TAG_QUEUING 0x0040 243 #define NO_RESELECT 0x0080 244 struct trm_linfo *linfo[TRM_MAX_LUNS]; 245 246 uint8_t config0; /* Target Config */ 247 uint8_t period; /* Max Period for nego. */ 248 uint8_t synctl; /* Sync control for reg. */ 249 uint8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 250 }; 251 252 /* 253 *----------------------------------------------------------------------- 254 * Adapter Control Block 255 *----------------------------------------------------------------------- 256 */ 257 struct trm_softc { 258 device_t sc_dev; 259 260 bus_space_tag_t sc_iot; 261 bus_space_handle_t sc_ioh; 262 bus_dma_tag_t sc_dmat; 263 bus_dmamap_t sc_dmamap; /* Map the control structures */ 264 265 struct trm_srb *sc_actsrb; 266 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 267 268 TAILQ_HEAD(, trm_srb) sc_freesrb, 269 sc_readysrb; 270 struct trm_srb *sc_srb; /* SRB array */ 271 272 struct trm_sg_entry *sc_sglist; 273 274 int sc_maxid; 275 /* 276 * Link to the generic SCSI driver 277 */ 278 struct scsipi_channel sc_channel; 279 struct scsipi_adapter sc_adapter; 280 281 int sc_id; /* Adapter SCSI Target ID */ 282 283 int sc_state; /* SRB State */ 284 #define TRM_IDLE 0 285 #define TRM_WAIT 1 286 #define TRM_READY 2 287 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 288 #define TRM_MSGIN 4 289 #define TRM_EXTEND_MSGIN 5 290 #define TRM_COMMAND 6 291 #define TRM_START 7 /* arbitration+msg_out+command_out */ 292 #define TRM_DISCONNECTED 8 293 #define TRM_DATA_XFER 9 294 #define TRM_XFERPAD 10 295 #define TRM_STATUS 11 296 #define TRM_COMPLETED 12 297 #define TRM_ABORT_SENT 13 298 #define TRM_UNEXPECT_RESEL 14 299 300 int sc_phase; /* SCSI phase */ 301 int sc_config; 302 #define HCC_WIDE_CARD 0x01 303 #define HCC_SCSI_RESET 0x02 304 #define HCC_PARITY 0x04 305 #define HCC_AUTOTERM 0x08 306 #define HCC_LOW8TERM 0x10 307 #define HCC_UP8TERM 0x20 308 309 int sc_flag; 310 #define RESET_DEV 0x01 311 #define RESET_DETECT 0x02 312 #define RESET_DONE 0x04 313 #define WAIT_TAGMSG 0x08 /* XXX */ 314 315 int sc_msgcnt; 316 317 int resel_target; /* XXX */ 318 int resel_lun; /* XXX */ 319 320 uint8_t *sc_msg; 321 uint8_t sc_msgbuf[6]; 322 }; 323 324 /* 325 * SCSI Status codes not defined in scsi_all.h 326 */ 327 #define SCSI_COND_MET 0x04 /* Condition Met */ 328 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 329 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 330 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 331 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 332 333 static int trm_match(device_t, cfdata_t, void *); 334 static void trm_attach(device_t, device_t, void *); 335 336 static int trm_init(struct trm_softc *); 337 338 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 339 void *); 340 static void trm_update_xfer_mode(struct trm_softc *, int); 341 static void trm_sched(struct trm_softc *); 342 static int trm_select(struct trm_softc *, struct trm_srb *); 343 static void trm_reset(struct trm_softc *); 344 static void trm_timeout(void *); 345 static int trm_intr(void *); 346 347 static void trm_dataout_phase0(struct trm_softc *, int); 348 static void trm_datain_phase0(struct trm_softc *, int); 349 static void trm_status_phase0(struct trm_softc *); 350 static void trm_msgin_phase0(struct trm_softc *); 351 static void trm_command_phase1(struct trm_softc *); 352 static void trm_status_phase1(struct trm_softc *); 353 static void trm_msgout_phase1(struct trm_softc *); 354 static void trm_msgin_phase1(struct trm_softc *); 355 356 static void trm_dataio_xfer(struct trm_softc *, int); 357 static void trm_disconnect(struct trm_softc *); 358 static void trm_reselect(struct trm_softc *); 359 static void trm_done(struct trm_softc *, struct trm_srb *); 360 static int trm_request_sense(struct trm_softc *, struct trm_srb *); 361 static void trm_dequeue(struct trm_softc *, struct trm_srb *); 362 363 static void trm_scsi_reset_detect(struct trm_softc *); 364 static void trm_reset_scsi_bus(struct trm_softc *); 365 366 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 367 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 368 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 369 static void trm_eeprom_set_data(struct trm_softc *, uint8_t, uint8_t); 370 static void trm_eeprom_write_cmd(struct trm_softc *, uint8_t, uint8_t); 371 static uint8_t trm_eeprom_get_data(struct trm_softc *, uint8_t); 372 373 CFATTACH_DECL_NEW(trm, sizeof(struct trm_softc), 374 trm_match, trm_attach, NULL, NULL); 375 376 /* real period: */ 377 static const uint8_t trm_clock_period[] = { 378 12, /* 48 ns 20.0 MB/sec */ 379 18, /* 72 ns 13.3 MB/sec */ 380 25, /* 100 ns 10.0 MB/sec */ 381 31, /* 124 ns 8.0 MB/sec */ 382 37, /* 148 ns 6.6 MB/sec */ 383 43, /* 172 ns 5.7 MB/sec */ 384 50, /* 200 ns 5.0 MB/sec */ 385 62 /* 248 ns 4.0 MB/sec */ 386 }; 387 #define NPERIOD __arraycount(trm_clock_period) 388 389 static int 390 trm_match(device_t parent, cfdata_t cf, void *aux) 391 { 392 struct pci_attach_args *pa = aux; 393 394 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 395 switch (PCI_PRODUCT(pa->pa_id)) { 396 case PCI_PRODUCT_TEKRAM2_DC315: 397 return 1; 398 } 399 return 0; 400 } 401 402 /* 403 * attach and init a host adapter 404 */ 405 static void 406 trm_attach(device_t parent, device_t self, void *aux) 407 { 408 struct trm_softc *sc = device_private(self); 409 struct pci_attach_args *const pa = aux; 410 bus_space_tag_t iot; 411 bus_space_handle_t ioh; 412 pci_intr_handle_t ih; 413 pcireg_t command; 414 const char *intrstr; 415 int fl = 0; 416 417 sc->sc_dev = self; 418 419 /* 420 * Some cards do not allow memory mapped accesses 421 * pa_pc: chipset tag 422 * pa_tag: pci tag 423 */ 424 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 425 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 426 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 427 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 428 pci_conf_write(pa->pa_pc, pa->pa_tag, 429 PCI_COMMAND_STATUS_REG, command); 430 } 431 /* 432 * mask for get correct base address of pci IO port 433 */ 434 if (command & PCI_COMMAND_MEM_ENABLE) { 435 fl = pci_mapreg_map(pa, TRM_BAR_MMIO, PCI_MAPREG_TYPE_MEM, 0, &iot, 436 &ioh, NULL, NULL); 437 } 438 if (fl != 0) { 439 aprint_verbose_dev(self, "couldn't map MMIO registers, tryion PIO\n"); 440 if ((fl = pci_mapreg_map(pa, TRM_BAR_PIO, PCI_MAPREG_TYPE_IO, 0, 441 &iot, &ioh, NULL, NULL)) != 0) { 442 aprint_error(": unable to map registers (%d)\n", fl); 443 return; 444 } 445 } 446 /* 447 * test checksum of eeprom.. & initialize softc... 448 */ 449 sc->sc_iot = iot; 450 sc->sc_ioh = ioh; 451 sc->sc_dmat = pa->pa_dmat; 452 453 if (trm_init(sc) != 0) { 454 /* 455 * Error during initialization! 456 */ 457 return; 458 } 459 /* 460 * Now try to attach all the sub-devices 461 */ 462 if ((sc->sc_config & HCC_WIDE_CARD) != 0) 463 aprint_normal(": Tekram DC395UW/F (TRM-S1040) Fast40 " 464 "Ultra Wide SCSI Adapter\n"); 465 else 466 aprint_normal(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 467 "Ultra SCSI Adapter\n"); 468 469 /* 470 * Now tell the generic SCSI layer about our bus. 471 * map and establish interrupt 472 */ 473 if (pci_intr_map(pa, &ih)) { 474 aprint_error_dev(self, "couldn't map interrupt\n"); 475 return; 476 } 477 intrstr = pci_intr_string(pa->pa_pc, ih); 478 479 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 480 aprint_error_dev(self, "couldn't establish interrupt"); 481 if (intrstr != NULL) 482 aprint_error(" at %s", intrstr); 483 aprint_error("\n"); 484 return; 485 } 486 if (intrstr != NULL) 487 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 488 489 sc->sc_adapter.adapt_dev = self; 490 sc->sc_adapter.adapt_nchannels = 1; 491 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 492 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 493 sc->sc_adapter.adapt_request = trm_scsipi_request; 494 sc->sc_adapter.adapt_minphys = minphys; 495 496 sc->sc_channel.chan_adapter = &sc->sc_adapter; 497 sc->sc_channel.chan_bustype = &scsi_bustype; 498 sc->sc_channel.chan_channel = 0; 499 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 500 sc->sc_channel.chan_nluns = 8; 501 sc->sc_channel.chan_id = sc->sc_id; 502 503 config_found(self, &sc->sc_channel, scsiprint); 504 } 505 506 /* 507 * initialize the internal structures for a given SCSI host 508 */ 509 static int 510 trm_init(struct trm_softc *sc) 511 { 512 bus_space_tag_t iot = sc->sc_iot; 513 bus_space_handle_t ioh = sc->sc_ioh; 514 bus_dma_segment_t seg; 515 struct trm_nvram eeprom; 516 struct trm_srb *srb; 517 struct trm_tinfo *ti; 518 struct nvram_target *tconf; 519 int error, rseg, all_sgsize; 520 int i, target; 521 uint8_t bval; 522 523 DPRINTF(("\n")); 524 525 /* 526 * allocate the space for all SCSI control blocks (SRB) for DMA memory 527 */ 528 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 529 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 530 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 531 aprint_error(": unable to allocate SCSI REQUEST BLOCKS, " 532 "error = %d\n", error); 533 return 1; 534 } 535 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 536 all_sgsize, (void **) &sc->sc_sglist, 537 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 538 aprint_error(": unable to map SCSI REQUEST BLOCKS, " 539 "error = %d\n", error); 540 return 1; 541 } 542 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 543 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 544 aprint_error(": unable to create SRB DMA maps, " 545 "error = %d\n", error); 546 return 1; 547 } 548 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 549 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 550 aprint_error(": unable to load SRB DMA maps, " 551 "error = %d\n", error); 552 return 1; 553 } 554 DPRINTF(("all_sgsize=%x\n", all_sgsize)); 555 memset(sc->sc_sglist, 0, all_sgsize); 556 557 /* 558 * EEPROM CHECKSUM 559 */ 560 trm_check_eeprom(sc, &eeprom); 561 562 sc->sc_maxid = 7; 563 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 564 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 565 sc->sc_config |= HCC_WIDE_CARD; 566 sc->sc_maxid = 15; 567 } 568 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 569 sc->sc_config |= HCC_SCSI_RESET; 570 571 sc->sc_actsrb = NULL; 572 sc->sc_id = eeprom.scsi_id; 573 sc->sc_flag = 0; 574 575 /* 576 * initialize and link all device's SRB queues of this adapter 577 */ 578 TAILQ_INIT(&sc->sc_freesrb); 579 TAILQ_INIT(&sc->sc_readysrb); 580 581 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 582 M_DEVBUF, M_NOWAIT|M_ZERO); 583 DPRINTF(("all SRB size=%zx\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 584 if (sc->sc_srb == NULL) { 585 aprint_error(": can not allocate SRB\n"); 586 return 1; 587 } 588 589 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 590 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 591 srb->sgoffset = TRM_SG_SIZE * i; 592 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 593 /* 594 * map all SRB space to SRB_array 595 */ 596 if (bus_dmamap_create(sc->sc_dmat, 597 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 598 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 599 aprint_error(": unable to create DMA transfer map.\n"); 600 free(sc->sc_srb, M_DEVBUF); 601 return 1; 602 } 603 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 604 srb++; 605 } 606 607 /* 608 * initialize all target info structures 609 */ 610 for (target = 0; target < TRM_MAX_TARGETS; target++) { 611 ti = &sc->sc_tinfo[target]; 612 ti->synctl = 0; 613 ti->offset = 0; 614 tconf = &eeprom.target[target]; 615 ti->config0 = tconf->config0; 616 ti->period = trm_clock_period[tconf->period & 0x07]; 617 ti->flag = 0; 618 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 619 #ifdef notyet 620 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 621 ti->flag |= USE_TAG_QUEUING; 622 #endif 623 } else 624 ti->flag |= NO_RESELECT; 625 626 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 627 target, ti->config0, ti->period)); 628 DPRINTF((", flag = 0x%02x\n", ti->flag)); 629 } 630 631 /* program configuration 0 */ 632 bval = PHASELATCH | INITIATOR | BLOCKRST; 633 if ((sc->sc_config & HCC_PARITY) != 0) 634 bval |= PARITYCHECK; 635 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 636 637 /* program configuration 1 */ 638 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 639 ACTIVE_NEG | ACTIVE_NEGPLUS); 640 641 /* 250ms selection timeout */ 642 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 643 644 /* Mask all interrupts */ 645 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 646 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 647 648 /* Reset SCSI module */ 649 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 650 651 /* program Host ID */ 652 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 653 654 /* set asynchronous transfer */ 655 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 656 657 /* Turn LED control off */ 658 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 659 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 660 661 /* DMA config */ 662 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 663 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 664 665 /* Clear pending interrupt status */ 666 (void)bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 667 668 /* Enable SCSI interrupt */ 669 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 670 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 671 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 672 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 673 674 trm_reset(sc); 675 676 return 0; 677 } 678 679 /* 680 * enqueues a SCSI command 681 * called by the higher level SCSI driver 682 */ 683 static void 684 trm_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 685 void *arg) 686 { 687 bus_space_tag_t iot; 688 bus_space_handle_t ioh; 689 struct trm_softc *sc; 690 struct trm_srb *srb; 691 struct scsipi_xfer *xs; 692 int error, i, s; 693 694 sc = device_private(chan->chan_adapter->adapt_dev); 695 iot = sc->sc_iot; 696 ioh = sc->sc_ioh; 697 698 switch (req) { 699 case ADAPTER_REQ_RUN_XFER: 700 xs = arg; 701 DPRINTF(("trm_scsipi_request.....\n")); 702 DPRINTF(("target= %d lun= %d\n", xs->xs_periph->periph_target, 703 xs->xs_periph->periph_lun)); 704 if (xs->xs_control & XS_CTL_RESET) { 705 trm_reset(sc); 706 xs->error = XS_NOERROR | XS_RESET; 707 return; 708 } 709 if (xs->xs_status & XS_STS_DONE) { 710 printf("%s: Is it done?\n", device_xname(sc->sc_dev)); 711 xs->xs_status &= ~XS_STS_DONE; 712 } 713 714 s = splbio(); 715 716 /* Get SRB */ 717 srb = TAILQ_FIRST(&sc->sc_freesrb); 718 if (srb != NULL) { 719 TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 720 } else { 721 xs->error = XS_RESOURCE_SHORTAGE; 722 scsipi_done(xs); 723 splx(s); 724 return; 725 } 726 727 srb->xs = xs; 728 srb->cmdlen = xs->cmdlen; 729 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 730 731 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 732 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 733 xs->data, xs->datalen, NULL, 734 ((xs->xs_control & XS_CTL_NOSLEEP) ? 735 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 736 BUS_DMA_STREAMING | 737 ((xs->xs_control & XS_CTL_DATA_IN) ? 738 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 739 printf("%s: DMA transfer map unable to load, " 740 "error = %d\n", device_xname(sc->sc_dev), 741 error); 742 xs->error = XS_DRIVER_STUFFUP; 743 /* 744 * free SRB 745 */ 746 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 747 splx(s); 748 return; 749 } 750 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 751 srb->dmap->dm_mapsize, 752 (xs->xs_control & XS_CTL_DATA_IN) ? 753 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 754 755 /* Set up the scatter gather list */ 756 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 757 srb->sgentry[i].address = 758 htole32(srb->dmap->dm_segs[i].ds_addr); 759 srb->sgentry[i].length = 760 htole32(srb->dmap->dm_segs[i].ds_len); 761 } 762 srb->buflen = xs->datalen; 763 srb->sgcnt = srb->dmap->dm_nsegs; 764 } else { 765 srb->sgentry[0].address = 0; 766 srb->sgentry[0].length = 0; 767 srb->buflen = 0; 768 srb->sgcnt = 0; 769 } 770 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 771 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 772 773 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 774 775 srb->sgindex = 0; 776 srb->hastat = 0; 777 srb->tastat = 0; 778 srb->flag = 0; 779 780 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 781 if (sc->sc_actsrb == NULL) 782 trm_sched(sc); 783 splx(s); 784 785 if ((xs->xs_control & XS_CTL_POLL) != 0) { 786 int timeout = xs->timeout; 787 788 s = splbio(); 789 do { 790 while (--timeout) { 791 DELAY(1000); 792 if (bus_space_read_2(iot, ioh, 793 TRM_SCSI_STATUS) & SCSIINTERRUPT) 794 break; 795 } 796 if (timeout == 0) { 797 trm_timeout(srb); 798 break; 799 } else 800 trm_intr(sc); 801 } while ((xs->xs_status & XS_STS_DONE) == 0); 802 splx(s); 803 } 804 return; 805 806 case ADAPTER_REQ_GROW_RESOURCES: 807 /* XXX Not supported. */ 808 return; 809 810 case ADAPTER_REQ_SET_XFER_MODE: 811 { 812 struct trm_tinfo *ti; 813 struct scsipi_xfer_mode *xm; 814 815 xm = arg; 816 ti = &sc->sc_tinfo[xm->xm_target]; 817 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 818 819 #ifdef notyet 820 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 821 ti->flag |= USE_TAG_QUEUING; 822 else 823 #endif 824 ti->flag &= ~USE_TAG_QUEUING; 825 826 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 827 (sc->sc_config & HCC_WIDE_CARD) != 0 && 828 (ti->config0 & NTC_DO_WIDE_NEGO) != 0) { 829 ti->flag |= WIDE_NEGO_ENABLE; 830 ti->flag &= ~WIDE_NEGO_DONE; 831 } 832 833 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 834 (ti->config0 & NTC_DO_SYNC_NEGO) != 0) { 835 ti->flag |= SYNC_NEGO_ENABLE; 836 ti->flag &= ~SYNC_NEGO_DONE; 837 ti->period = trm_clock_period[0]; 838 } 839 840 /* 841 * If we're not going to negotiate, send the 842 * notification now, since it won't happen later. 843 */ 844 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 845 (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 846 trm_update_xfer_mode(sc, xm->xm_target); 847 848 return; 849 } 850 } 851 } 852 853 static void 854 trm_update_xfer_mode(struct trm_softc *sc, int target) 855 { 856 struct scsipi_xfer_mode xm; 857 struct trm_tinfo *ti; 858 859 ti = &sc->sc_tinfo[target]; 860 xm.xm_target = target; 861 xm.xm_mode = 0; 862 xm.xm_period = 0; 863 xm.xm_offset = 0; 864 865 if ((ti->synctl & WIDE_SYNC) != 0) 866 xm.xm_mode |= PERIPH_CAP_WIDE16; 867 868 if (ti->period > 0) { 869 xm.xm_mode |= PERIPH_CAP_SYNC; 870 xm.xm_period = ti->period; 871 xm.xm_offset = ti->offset; 872 } 873 874 #ifdef notyet 875 if ((ti->flag & USE_TAG_QUEUING) != 0) 876 xm.xm_mode |= PERIPH_CAP_TQING; 877 #endif 878 879 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 880 } 881 882 static void 883 trm_sched(struct trm_softc *sc) 884 { 885 struct trm_srb *srb; 886 struct scsipi_periph *periph; 887 struct trm_tinfo *ti; 888 struct trm_linfo *li; 889 int s, lun, tag; 890 891 DPRINTF(("trm_sched...\n")); 892 893 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 894 periph = srb->xs->xs_periph; 895 ti = &sc->sc_tinfo[periph->periph_target]; 896 lun = periph->periph_lun; 897 898 /* select type of tag for this command */ 899 if ((ti->flag & NO_RESELECT) != 0 || 900 (ti->flag & USE_TAG_QUEUING) == 0 || 901 (srb->flag & AUTO_REQSENSE) != 0 || 902 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 903 tag = 0; 904 else 905 tag = srb->xs->xs_tag_type; 906 #if 0 907 /* XXX use tags for polled commands? */ 908 if (srb->xs->xs_control & XS_CTL_POLL) 909 tag = 0; 910 #endif 911 912 s = splbio(); 913 li = ti->linfo[lun]; 914 if (li == NULL) { 915 /* initialize lun info */ 916 if ((li = malloc(sizeof(*li), M_DEVBUF, 917 M_NOWAIT|M_ZERO)) == NULL) { 918 splx(s); 919 continue; 920 } 921 ti->linfo[lun] = li; 922 } 923 924 if (tag == 0) { 925 /* try to issue this srb as an un-tagged command */ 926 if (li->untagged == NULL) 927 li->untagged = srb; 928 } 929 if (li->untagged != NULL) { 930 tag = 0; 931 if (li->busy != 1 && li->used == 0) { 932 /* we need to issue the untagged command now */ 933 srb = li->untagged; 934 periph = srb->xs->xs_periph; 935 } else { 936 /* not ready yet */ 937 splx(s); 938 continue; 939 } 940 } 941 srb->tag[0] = tag; 942 if (tag != 0) { 943 li->queued[srb->xs->xs_tag_id] = srb; 944 srb->tag[1] = srb->xs->xs_tag_id; 945 li->used++; 946 } 947 948 if (li->untagged != NULL && li->busy != 1) { 949 li->busy = 1; 950 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 951 sc->sc_actsrb = srb; 952 trm_select(sc, srb); 953 splx(s); 954 break; 955 } 956 if (li->untagged == NULL && tag != 0) { 957 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 958 sc->sc_actsrb = srb; 959 trm_select(sc, srb); 960 splx(s); 961 break; 962 } else 963 splx(s); 964 } 965 } 966 967 static int 968 trm_select(struct trm_softc *sc, struct trm_srb *srb) 969 { 970 bus_space_tag_t iot = sc->sc_iot; 971 bus_space_handle_t ioh = sc->sc_ioh; 972 struct scsipi_periph *periph = srb->xs->xs_periph; 973 int target = periph->periph_target; 974 int lun = periph->periph_lun; 975 struct trm_tinfo *ti = &sc->sc_tinfo[target]; 976 uint8_t scsicmd; 977 978 DPRINTF(("trm_select.....\n")); 979 980 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 981 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), 982 trm_timeout, srb); 983 } 984 985 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 986 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 987 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 988 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 989 /* Flush FIFO */ 990 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 991 DELAY(10); 992 993 sc->sc_phase = PH_BUS_FREE; /* initial phase */ 994 995 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 996 997 if (((ti->flag & WIDE_NEGO_ENABLE) && 998 (ti->flag & WIDE_NEGO_DONE) == 0) || 999 ((ti->flag & SYNC_NEGO_ENABLE) && 1000 (ti->flag & SYNC_NEGO_DONE) == 0)) { 1001 sc->sc_state = TRM_MSGOUT; 1002 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1003 MSG_IDENTIFY(lun, 0)); 1004 bus_space_write_multi_1(iot, ioh, 1005 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1006 /* it's important for atn stop */ 1007 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1008 DO_DATALATCH | DO_HWRESELECT); 1009 /* SCSI command */ 1010 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 1011 DPRINTF(("select with SEL_ATNSTOP\n")); 1012 return 0; 1013 } 1014 1015 if (srb->tag[0] != 0) { 1016 /* Send identify message */ 1017 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1018 MSG_IDENTIFY(lun, 1)); 1019 /* Send Tag id */ 1020 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 1021 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 1022 scsicmd = SCMD_SEL_ATN3; 1023 DPRINTF(("select with SEL_ATN3\n")); 1024 } else { 1025 /* Send identify message */ 1026 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1027 MSG_IDENTIFY(lun, 1028 (ti->flag & NO_RESELECT) == 0 && 1029 (srb->flag & AUTO_REQSENSE) == 0 && 1030 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1031 scsicmd = SCMD_SEL_ATN; 1032 DPRINTF(("select with SEL_ATN\n")); 1033 } 1034 sc->sc_state = TRM_START; 1035 1036 /* 1037 * Send CDB ..command block... 1038 */ 1039 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1040 1041 /* 1042 * If trm_select returns 0: current interrupt status 1043 * is interrupt enable. It's said that SCSI processor is 1044 * unoccupied. 1045 */ 1046 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1047 /* SCSI command */ 1048 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1049 return 0; 1050 } 1051 1052 /* 1053 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1054 */ 1055 static void 1056 trm_reset(struct trm_softc *sc) 1057 { 1058 bus_space_tag_t iot = sc->sc_iot; 1059 bus_space_handle_t ioh = sc->sc_ioh; 1060 int s; 1061 1062 DPRINTF(("trm_reset.........\n")); 1063 1064 s = splbio(); 1065 1066 /* disable SCSI and DMA interrupt */ 1067 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1068 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1069 1070 trm_reset_scsi_bus(sc); 1071 DELAY(100000); 1072 1073 /* Enable SCSI interrupt */ 1074 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1075 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1076 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1077 1078 /* Enable DMA interrupt */ 1079 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1080 1081 /* Clear DMA FIFO */ 1082 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1083 1084 /* Clear SCSI FIFO */ 1085 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1086 1087 sc->sc_actsrb = NULL; 1088 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1089 1090 splx(s); 1091 } 1092 1093 static void 1094 trm_timeout(void *arg) 1095 { 1096 struct trm_srb *srb = (struct trm_srb *)arg; 1097 struct scsipi_xfer *xs; 1098 struct scsipi_periph *periph; 1099 struct trm_softc *sc; 1100 int s; 1101 1102 if (srb == NULL) { 1103 printf("trm_timeout called with srb == NULL\n"); 1104 return; 1105 } 1106 1107 xs = srb->xs; 1108 if (xs == NULL) { 1109 printf("trm_timeout called with xs == NULL\n"); 1110 return; 1111 } 1112 1113 periph = xs->xs_periph; 1114 scsipi_printaddr(xs->xs_periph); 1115 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1116 1117 sc = device_private(periph->periph_channel->chan_adapter->adapt_dev); 1118 1119 trm_reset_scsi_bus(sc); 1120 s = splbio(); 1121 srb->flag |= SRB_TIMEOUT; 1122 trm_done(sc, srb); 1123 /* XXX needs more.. */ 1124 splx(s); 1125 } 1126 1127 /* 1128 * Catch an interrupt from the adapter 1129 * Process pending device interrupts. 1130 */ 1131 static int 1132 trm_intr(void *arg) 1133 { 1134 bus_space_tag_t iot; 1135 bus_space_handle_t ioh; 1136 struct trm_softc *sc; 1137 int intstat, stat; 1138 1139 DPRINTF(("trm_intr......\n")); 1140 sc = arg; 1141 if (sc == NULL) 1142 return 0; 1143 1144 iot = sc->sc_iot; 1145 ioh = sc->sc_ioh; 1146 1147 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1148 if ((stat & SCSIINTERRUPT) == 0) 1149 return 0; 1150 1151 DPRINTF(("stat = %04x, ", stat)); 1152 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1153 1154 DPRINTF(("intstat=%02x, ", intstat)); 1155 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1156 DPRINTF(("\n")); 1157 trm_disconnect(sc); 1158 return 1; 1159 } 1160 if (intstat & INT_RESELECTED) { 1161 DPRINTF(("\n")); 1162 trm_reselect(sc); 1163 return 1; 1164 } 1165 if (intstat & INT_SCSIRESET) { 1166 DPRINTF(("\n")); 1167 trm_scsi_reset_detect(sc); 1168 return 1; 1169 } 1170 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1171 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1172 sc->sc_phase, sc->sc_state)); 1173 /* 1174 * software sequential machine 1175 */ 1176 1177 /* 1178 * call phase0 functions... "phase entry" handle 1179 * every phase before start transfer 1180 */ 1181 switch (sc->sc_phase) { 1182 case PH_DATA_OUT: 1183 trm_dataout_phase0(sc, stat); 1184 break; 1185 case PH_DATA_IN: 1186 trm_datain_phase0(sc, stat); 1187 break; 1188 case PH_COMMAND: 1189 break; 1190 case PH_STATUS: 1191 trm_status_phase0(sc); 1192 stat = PH_BUS_FREE; 1193 break; 1194 case PH_MSG_OUT: 1195 if (sc->sc_state == TRM_UNEXPECT_RESEL || 1196 sc->sc_state == TRM_ABORT_SENT) 1197 stat = PH_BUS_FREE; 1198 break; 1199 case PH_MSG_IN: 1200 trm_msgin_phase0(sc); 1201 stat = PH_BUS_FREE; 1202 break; 1203 case PH_BUS_FREE: 1204 break; 1205 default: 1206 printf("%s: unexpected phase in trm_intr() phase0\n", 1207 device_xname(sc->sc_dev)); 1208 break; 1209 } 1210 1211 sc->sc_phase = stat & PHASEMASK; 1212 1213 switch (sc->sc_phase) { 1214 case PH_DATA_OUT: 1215 trm_dataio_xfer(sc, XFERDATAOUT); 1216 break; 1217 case PH_DATA_IN: 1218 trm_dataio_xfer(sc, XFERDATAIN); 1219 break; 1220 case PH_COMMAND: 1221 trm_command_phase1(sc); 1222 break; 1223 case PH_STATUS: 1224 trm_status_phase1(sc); 1225 break; 1226 case PH_MSG_OUT: 1227 trm_msgout_phase1(sc); 1228 break; 1229 case PH_MSG_IN: 1230 trm_msgin_phase1(sc); 1231 break; 1232 case PH_BUS_FREE: 1233 break; 1234 default: 1235 printf("%s: unexpected phase in trm_intr() phase1\n", 1236 device_xname(sc->sc_dev)); 1237 break; 1238 } 1239 1240 return 1; 1241 } 1242 return 0; 1243 } 1244 1245 static void 1246 trm_msgout_phase1(struct trm_softc *sc) 1247 { 1248 bus_space_tag_t iot = sc->sc_iot; 1249 bus_space_handle_t ioh = sc->sc_ioh; 1250 struct trm_srb *srb; 1251 struct scsipi_periph *periph; 1252 struct trm_tinfo *ti; 1253 1254 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1255 1256 srb = sc->sc_actsrb; 1257 1258 /* message out phase */ 1259 if (srb != NULL) { 1260 periph = srb->xs->xs_periph; 1261 ti = &sc->sc_tinfo[periph->periph_target]; 1262 1263 if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1264 (ti->flag & WIDE_NEGO_ENABLE)) { 1265 /* send WDTR */ 1266 ti->flag &= ~SYNC_NEGO_DONE; 1267 1268 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1269 sc->sc_msgbuf[1] = MSG_EXTENDED; 1270 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1271 sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1272 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1273 sc->sc_msgcnt = 5; 1274 1275 ti->flag |= WIDE_NEGO_DOING; 1276 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1277 (ti->flag & SYNC_NEGO_ENABLE)) { 1278 /* send SDTR */ 1279 int cnt = 0; 1280 1281 if ((ti->flag & WIDE_NEGO_DONE) == 0) 1282 sc->sc_msgbuf[cnt++] = 1283 MSG_IDENTIFY(periph->periph_lun, 0); 1284 1285 sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1286 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1287 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1288 sc->sc_msgbuf[cnt++] = ti->period; 1289 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1290 sc->sc_msgcnt = cnt; 1291 ti->flag |= SYNC_NEGO_DOING; 1292 } 1293 } 1294 if (sc->sc_msgcnt == 0) { 1295 sc->sc_msgbuf[0] = MSG_ABORT; 1296 sc->sc_msgcnt = 1; 1297 sc->sc_state = TRM_ABORT_SENT; 1298 } 1299 1300 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1301 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1302 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1303 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1304 1305 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1306 sc->sc_msgbuf, sc->sc_msgcnt); 1307 sc->sc_msgcnt = 0; 1308 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1309 1310 /* it's important for atn stop */ 1311 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1312 1313 /* 1314 * SCSI command 1315 */ 1316 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1317 } 1318 1319 static void 1320 trm_command_phase1(struct trm_softc *sc) 1321 { 1322 bus_space_tag_t iot = sc->sc_iot; 1323 bus_space_handle_t ioh = sc->sc_ioh; 1324 struct trm_srb *srb; 1325 1326 srb = sc->sc_actsrb; 1327 if (srb == NULL) { 1328 DPRINTF(("trm_command_phase1: no active srb\n")); 1329 return; 1330 } 1331 1332 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1333 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1334 1335 sc->sc_state = TRM_COMMAND; 1336 /* it's important for atn stop */ 1337 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1338 1339 /* 1340 * SCSI command 1341 */ 1342 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1343 } 1344 1345 static void 1346 trm_dataout_phase0(struct trm_softc *sc, int stat) 1347 { 1348 bus_space_tag_t iot = sc->sc_iot; 1349 bus_space_handle_t ioh = sc->sc_ioh; 1350 struct trm_srb *srb; 1351 struct scsipi_periph *periph; 1352 struct trm_tinfo *ti; 1353 struct trm_sg_entry *sg; 1354 int sgindex; 1355 uint32_t xferlen, leftcnt = 0; 1356 1357 if (sc->sc_state == TRM_XFERPAD) 1358 return; 1359 1360 srb = sc->sc_actsrb; 1361 if (srb == NULL) { 1362 DPRINTF(("trm_dataout_phase0: no active srb\n")); 1363 return; 1364 } 1365 periph = srb->xs->xs_periph; 1366 ti = &sc->sc_tinfo[periph->periph_target]; 1367 1368 if ((stat & PARITYERROR) != 0) 1369 srb->flag |= PARITY_ERROR; 1370 1371 if ((stat & SCSIXFERDONE) == 0) { 1372 /* 1373 * when data transfer from DMA FIFO to SCSI FIFO 1374 * if there was some data left in SCSI FIFO 1375 */ 1376 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1377 SCSI_FIFOCNT_MASK; 1378 if (ti->synctl & WIDE_SYNC) 1379 /* 1380 * if WIDE scsi SCSI FIFOCNT unit is word 1381 * so need to * 2 1382 */ 1383 leftcnt <<= 1; 1384 } 1385 /* 1386 * calculate all the residue data that was not yet transferred 1387 * SCSI transfer counter + left in SCSI FIFO data 1388 * 1389 * .....TRM_SCSI_XCNT (24bits) 1390 * The counter always decrements by one for every SCSI 1391 * byte transfer. 1392 * .....TRM_SCSI_FIFOCNT ( 5bits) 1393 * The counter is SCSI FIFO offset counter 1394 */ 1395 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1396 if (leftcnt == 1) { 1397 leftcnt = 0; 1398 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1399 } 1400 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1401 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1402 DMAXFERCOMP) == 0) 1403 ; /* XXX needs timeout */ 1404 1405 srb->buflen = 0; 1406 } else { 1407 /* Update SG list */ 1408 1409 /* 1410 * if transfer not yet complete 1411 * there were some data residue in SCSI FIFO or 1412 * SCSI transfer counter not empty 1413 */ 1414 if (srb->buflen != leftcnt) { 1415 /* data that had transferred length */ 1416 xferlen = srb->buflen - leftcnt; 1417 1418 /* next time to be transferred length */ 1419 srb->buflen = leftcnt; 1420 1421 /* 1422 * parsing from last time disconnect sgindex 1423 */ 1424 sg = srb->sgentry + srb->sgindex; 1425 for (sgindex = srb->sgindex; 1426 sgindex < srb->sgcnt; 1427 sgindex++, sg++) { 1428 /* 1429 * find last time which SG transfer 1430 * be disconnect 1431 */ 1432 if (xferlen >= le32toh(sg->length)) 1433 xferlen -= le32toh(sg->length); 1434 else { 1435 /* 1436 * update last time 1437 * disconnected SG list 1438 */ 1439 /* residue data length */ 1440 sg->length = 1441 htole32(le32toh(sg->length) 1442 - xferlen); 1443 /* residue data pointer */ 1444 sg->address = 1445 htole32(le32toh(sg->address) 1446 + xferlen); 1447 srb->sgindex = sgindex; 1448 break; 1449 } 1450 } 1451 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1452 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1453 } 1454 } 1455 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1456 } 1457 1458 static void 1459 trm_datain_phase0(struct trm_softc *sc, int stat) 1460 { 1461 bus_space_tag_t iot = sc->sc_iot; 1462 bus_space_handle_t ioh = sc->sc_ioh; 1463 struct trm_srb *srb; 1464 struct trm_sg_entry *sg; 1465 int sgindex; 1466 uint32_t xferlen, leftcnt = 0; 1467 1468 if (sc->sc_state == TRM_XFERPAD) 1469 return; 1470 1471 srb = sc->sc_actsrb; 1472 if (srb == NULL) { 1473 DPRINTF(("trm_datain_phase0: no active srb\n")); 1474 return; 1475 } 1476 1477 if (stat & PARITYERROR) 1478 srb->flag |= PARITY_ERROR; 1479 1480 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1481 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1482 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1483 DMAXFERCOMP) == 0) 1484 ; /* XXX needs timeout */ 1485 1486 srb->buflen = 0; 1487 } else { /* phase changed */ 1488 /* 1489 * parsing the case: 1490 * when a transfer not yet complete 1491 * but be disconnected by upper layer 1492 * if transfer not yet complete 1493 * there were some data residue in SCSI FIFO or 1494 * SCSI transfer counter not empty 1495 */ 1496 if (srb->buflen != leftcnt) { 1497 /* 1498 * data that had transferred length 1499 */ 1500 xferlen = srb->buflen - leftcnt; 1501 1502 /* 1503 * next time to be transferred length 1504 */ 1505 srb->buflen = leftcnt; 1506 1507 /* 1508 * parsing from last time disconnect sgindex 1509 */ 1510 sg = srb->sgentry + srb->sgindex; 1511 for (sgindex = srb->sgindex; 1512 sgindex < srb->sgcnt; 1513 sgindex++, sg++) { 1514 /* 1515 * find last time which SG transfer 1516 * be disconnect 1517 */ 1518 if (xferlen >= le32toh(sg->length)) 1519 xferlen -= le32toh(sg->length); 1520 else { 1521 /* 1522 * update last time 1523 * disconnected SG list 1524 */ 1525 /* residue data length */ 1526 sg->length = 1527 htole32(le32toh(sg->length) 1528 - xferlen); 1529 /* residue data pointer */ 1530 sg->address = 1531 htole32(le32toh(sg->address) 1532 + xferlen); 1533 srb->sgindex = sgindex; 1534 break; 1535 } 1536 } 1537 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1538 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1539 } 1540 } 1541 } 1542 1543 static void 1544 trm_dataio_xfer(struct trm_softc *sc, int iodir) 1545 { 1546 bus_space_tag_t iot = sc->sc_iot; 1547 bus_space_handle_t ioh = sc->sc_ioh; 1548 struct trm_srb *srb; 1549 struct scsipi_periph *periph; 1550 struct trm_tinfo *ti; 1551 1552 srb = sc->sc_actsrb; 1553 if (srb == NULL) { 1554 DPRINTF(("trm_dataio_xfer: no active srb\n")); 1555 return; 1556 } 1557 periph = srb->xs->xs_periph; 1558 ti = &sc->sc_tinfo[periph->periph_target]; 1559 1560 if (srb->sgindex < srb->sgcnt) { 1561 if (srb->buflen > 0) { 1562 /* 1563 * load what physical address of Scatter/Gather 1564 * list table want to be transfer 1565 */ 1566 sc->sc_state = TRM_DATA_XFER; 1567 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1568 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1569 srb->sgaddr + 1570 srb->sgindex * sizeof(struct trm_sg_entry)); 1571 /* 1572 * load how many bytes in the Scatter/Gather list table 1573 */ 1574 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1575 (srb->sgcnt - srb->sgindex) 1576 * sizeof(struct trm_sg_entry)); 1577 /* 1578 * load total xfer length (24bits) max value 16Mbyte 1579 */ 1580 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1581 /* Start DMA transfer */ 1582 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1583 iodir | SGXFER); 1584 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1585 STARTDMAXFER); 1586 1587 /* Start SCSI transfer */ 1588 /* it's important for atn stop */ 1589 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1590 DO_DATALATCH); 1591 1592 /* 1593 * SCSI command 1594 */ 1595 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1596 (iodir == XFERDATAOUT) ? 1597 SCMD_DMA_OUT : SCMD_DMA_IN); 1598 } else { /* xfer pad */ 1599 if (srb->sgcnt) { 1600 srb->hastat = H_OVER_UNDER_RUN; 1601 } 1602 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1603 (ti->synctl & WIDE_SYNC) ? 2 : 1); 1604 1605 if (iodir == XFERDATAOUT) 1606 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1607 else 1608 (void)bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1609 1610 sc->sc_state = TRM_XFERPAD; 1611 /* it's important for atn stop */ 1612 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1613 DO_DATALATCH); 1614 1615 /* 1616 * SCSI command 1617 */ 1618 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1619 (iodir == XFERDATAOUT) ? 1620 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1621 } 1622 } 1623 } 1624 1625 static void 1626 trm_status_phase0(struct trm_softc *sc) 1627 { 1628 bus_space_tag_t iot = sc->sc_iot; 1629 bus_space_handle_t ioh = sc->sc_ioh; 1630 struct trm_srb *srb; 1631 1632 srb = sc->sc_actsrb; 1633 if (srb == NULL) { 1634 DPRINTF(("trm_status_phase0: no active srb\n")); 1635 return; 1636 } 1637 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1638 sc->sc_state = TRM_COMPLETED; 1639 /* it's important for atn stop */ 1640 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1641 1642 /* 1643 * SCSI command 1644 */ 1645 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1646 } 1647 1648 static void 1649 trm_status_phase1(struct trm_softc *sc) 1650 { 1651 bus_space_tag_t iot = sc->sc_iot; 1652 bus_space_handle_t ioh = sc->sc_ioh; 1653 1654 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1655 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1656 & SCSI_FIFO_EMPTY) == 0) 1657 bus_space_write_2(iot, ioh, 1658 TRM_SCSI_CONTROL, DO_CLRFIFO); 1659 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1660 & DMA_FIFO_EMPTY) == 0) 1661 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1662 } else { 1663 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1664 & DMA_FIFO_EMPTY) == 0) 1665 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1666 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1667 & SCSI_FIFO_EMPTY) == 0) 1668 bus_space_write_2(iot, ioh, 1669 TRM_SCSI_CONTROL, DO_CLRFIFO); 1670 } 1671 sc->sc_state = TRM_STATUS; 1672 /* it's important for atn stop */ 1673 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1674 1675 /* 1676 * SCSI command 1677 */ 1678 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1679 } 1680 1681 static void 1682 trm_msgin_phase0(struct trm_softc *sc) 1683 { 1684 bus_space_tag_t iot = sc->sc_iot; 1685 bus_space_handle_t ioh = sc->sc_ioh; 1686 struct trm_srb *srb; 1687 struct scsipi_periph *periph; 1688 struct trm_tinfo *ti; 1689 int index; 1690 uint8_t msgin_code; 1691 1692 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1693 if (sc->sc_state != TRM_EXTEND_MSGIN) { 1694 DPRINTF(("msgin: code = %02x\n", msgin_code)); 1695 switch (msgin_code) { 1696 case MSG_DISCONNECT: 1697 sc->sc_state = TRM_DISCONNECTED; 1698 break; 1699 1700 case MSG_SAVEDATAPOINTER: 1701 break; 1702 1703 case MSG_EXTENDED: 1704 case MSG_SIMPLE_Q_TAG: 1705 case MSG_HEAD_OF_Q_TAG: 1706 case MSG_ORDERED_Q_TAG: 1707 sc->sc_state = TRM_EXTEND_MSGIN; 1708 /* extended message (01h) */ 1709 sc->sc_msgbuf[0] = msgin_code; 1710 1711 sc->sc_msgcnt = 1; 1712 /* extended message length (n) */ 1713 sc->sc_msg = &sc->sc_msgbuf[1]; 1714 1715 break; 1716 case MSG_MESSAGE_REJECT: 1717 /* Reject message */ 1718 srb = sc->sc_actsrb; 1719 if (srb == NULL) { 1720 DPRINTF(("trm_msgin_phase0: " 1721 " message reject without actsrb\n")); 1722 break; 1723 } 1724 periph = srb->xs->xs_periph; 1725 ti = &sc->sc_tinfo[periph->periph_target]; 1726 1727 if (ti->flag & WIDE_NEGO_ENABLE) { 1728 /* do wide nego reject */ 1729 ti->flag |= WIDE_NEGO_DONE; 1730 ti->flag &= 1731 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1732 if ((ti->flag & SYNC_NEGO_ENABLE) && 1733 (ti->flag & SYNC_NEGO_DONE) == 0) { 1734 /* Set ATN, in case ATN was clear */ 1735 sc->sc_state = TRM_MSGOUT; 1736 bus_space_write_2(iot, ioh, 1737 TRM_SCSI_CONTROL, DO_SETATN); 1738 } else 1739 /* Clear ATN */ 1740 bus_space_write_2(iot, ioh, 1741 TRM_SCSI_CONTROL, DO_CLRATN); 1742 } else if (ti->flag & SYNC_NEGO_ENABLE) { 1743 /* do sync nego reject */ 1744 bus_space_write_2(iot, ioh, 1745 TRM_SCSI_CONTROL, DO_CLRATN); 1746 if (ti->flag & SYNC_NEGO_DOING) { 1747 ti->flag &=~(SYNC_NEGO_ENABLE | 1748 SYNC_NEGO_DONE); 1749 ti->synctl = 0; 1750 ti->offset = 0; 1751 bus_space_write_1(iot, ioh, 1752 TRM_SCSI_SYNC, ti->synctl); 1753 bus_space_write_1(iot, ioh, 1754 TRM_SCSI_OFFSET, ti->offset); 1755 } 1756 } 1757 break; 1758 1759 case MSG_IGN_WIDE_RESIDUE: 1760 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1761 (void)bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1762 break; 1763 1764 default: 1765 /* 1766 * Restore data pointer message 1767 * Save data pointer message 1768 * Completion message 1769 * NOP message 1770 */ 1771 break; 1772 } 1773 } else { 1774 /* 1775 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1776 * Parsing incoming extented messages 1777 */ 1778 *sc->sc_msg++ = msgin_code; 1779 sc->sc_msgcnt++; 1780 1781 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1782 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1783 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1784 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1785 1786 switch (sc->sc_msgbuf[0]) { 1787 case MSG_SIMPLE_Q_TAG: 1788 case MSG_HEAD_OF_Q_TAG: 1789 case MSG_ORDERED_Q_TAG: 1790 /* 1791 * is QUEUE tag message : 1792 * 1793 * byte 0: 1794 * HEAD QUEUE TAG (20h) 1795 * ORDERED QUEUE TAG (21h) 1796 * SIMPLE QUEUE TAG (22h) 1797 * byte 1: 1798 * Queue tag (00h - FFh) 1799 */ 1800 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1801 /* XXX XXX XXX */ 1802 struct trm_linfo *li; 1803 int tagid; 1804 1805 sc->sc_flag &= ~WAIT_TAGMSG; 1806 tagid = sc->sc_msgbuf[1]; 1807 ti = &sc->sc_tinfo[sc->resel_target]; 1808 li = ti->linfo[sc->resel_lun]; 1809 srb = li->queued[tagid]; 1810 if (srb != NULL) { 1811 sc->sc_actsrb = srb; 1812 sc->sc_state = TRM_DATA_XFER; 1813 break; 1814 } else { 1815 printf("%s: invalid tag id\n", 1816 device_xname(sc->sc_dev)); 1817 } 1818 1819 sc->sc_state = TRM_UNEXPECT_RESEL; 1820 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1821 sc->sc_msgcnt = 1; 1822 bus_space_write_2(iot, ioh, 1823 TRM_SCSI_CONTROL, DO_SETATN); 1824 } else 1825 sc->sc_state = TRM_IDLE; 1826 break; 1827 1828 case MSG_EXTENDED: 1829 srb = sc->sc_actsrb; 1830 if (srb == NULL) { 1831 DPRINTF(("trm_msgin_phase0: " 1832 "extended message without actsrb\n")); 1833 break; 1834 } 1835 periph = srb->xs->xs_periph; 1836 ti = &sc->sc_tinfo[periph->periph_target]; 1837 1838 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1839 sc->sc_msgcnt == 4) { 1840 /* 1841 * is Wide data xfer Extended message : 1842 * ====================================== 1843 * WIDE DATA TRANSFER REQUEST 1844 * ====================================== 1845 * byte 0 : Extended message (01h) 1846 * byte 1 : Extended message length (02h) 1847 * byte 2 : WIDE DATA TRANSFER code (03h) 1848 * byte 3 : Transfer width exponent 1849 */ 1850 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1851 /* Length is wrong, reject it */ 1852 ti->flag &= ~(WIDE_NEGO_ENABLE | 1853 WIDE_NEGO_DONE); 1854 sc->sc_state = TRM_MSGOUT; 1855 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1856 sc->sc_msgcnt = 1; 1857 bus_space_write_2(iot, ioh, 1858 TRM_SCSI_CONTROL, DO_SETATN); 1859 break; 1860 } 1861 1862 if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1863 sc->sc_msgbuf[3] = 1864 MSG_EXT_WDTR_BUS_8_BIT; 1865 1866 if (sc->sc_msgbuf[3] > 1867 MSG_EXT_WDTR_BUS_32_BIT) { 1868 /* reject_msg: */ 1869 ti->flag &= ~(WIDE_NEGO_ENABLE | 1870 WIDE_NEGO_DONE); 1871 sc->sc_state = TRM_MSGOUT; 1872 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1873 sc->sc_msgcnt = 1; 1874 bus_space_write_2(iot, ioh, 1875 TRM_SCSI_CONTROL, DO_SETATN); 1876 break; 1877 } 1878 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1879 /* do 16 bits */ 1880 sc->sc_msgbuf[3] = 1881 MSG_EXT_WDTR_BUS_16_BIT; 1882 if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1883 ti->flag |= WIDE_NEGO_DONE; 1884 ti->flag &= ~(SYNC_NEGO_DONE | 1885 WIDE_NEGO_ENABLE); 1886 if (sc->sc_msgbuf[3] != 1887 MSG_EXT_WDTR_BUS_8_BIT) 1888 /* is Wide data xfer */ 1889 ti->synctl |= WIDE_SYNC; 1890 trm_update_xfer_mode(sc, 1891 periph->periph_target); 1892 } 1893 1894 sc->sc_state = TRM_MSGOUT; 1895 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1896 DO_SETATN); 1897 break; 1898 1899 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1900 sc->sc_msgcnt == 5) { 1901 /* 1902 * is 8bit transfer Extended message : 1903 * ================================= 1904 * SYNCHRONOUS DATA TRANSFER REQUEST 1905 * ================================= 1906 * byte 0 : Extended message (01h) 1907 * byte 1 : Extended message length (03) 1908 * byte 2 : SYNC DATA TRANSFER code (01h) 1909 * byte 3 : Transfer period factor 1910 * byte 4 : REQ/ACK offset 1911 */ 1912 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1913 /* reject_msg */ 1914 sc->sc_state = TRM_MSGOUT; 1915 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1916 sc->sc_msgcnt = 1; 1917 bus_space_write_2(iot, ioh, 1918 TRM_SCSI_CONTROL, DO_SETATN); 1919 break; 1920 } 1921 1922 if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1923 ti->flag &= 1924 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1925 ti->flag |= SYNC_NEGO_DONE; 1926 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1927 sc->sc_msgbuf[3] = 0; 1928 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1929 sc->sc_msgbuf[4] = 1930 TRM_MAX_OFFSET; 1931 1932 if (sc->sc_msgbuf[3] == 0 || 1933 sc->sc_msgbuf[4] == 0) { 1934 /* set async */ 1935 ti->synctl = 0; 1936 ti->offset = 0; 1937 } else { 1938 /* set sync */ 1939 /* Transfer period factor */ 1940 ti->period = sc->sc_msgbuf[3]; 1941 /* REQ/ACK offset */ 1942 ti->offset = sc->sc_msgbuf[4]; 1943 for (index = 0; 1944 index < NPERIOD; 1945 index++) 1946 if (ti->period <= 1947 trm_clock_period[ 1948 index]) 1949 break; 1950 1951 ti->synctl |= ALT_SYNC | index; 1952 } 1953 /* 1954 * program SCSI control register 1955 */ 1956 bus_space_write_1(iot, ioh, 1957 TRM_SCSI_SYNC, ti->synctl); 1958 bus_space_write_1(iot, ioh, 1959 TRM_SCSI_OFFSET, ti->offset); 1960 trm_update_xfer_mode(sc, 1961 periph->periph_target); 1962 } 1963 sc->sc_state = TRM_IDLE; 1964 } 1965 break; 1966 default: 1967 break; 1968 } 1969 } 1970 1971 /* it's important for atn stop */ 1972 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1973 1974 /* 1975 * SCSI command 1976 */ 1977 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1978 } 1979 1980 static void 1981 trm_msgin_phase1(struct trm_softc *sc) 1982 { 1983 bus_space_tag_t iot = sc->sc_iot; 1984 bus_space_handle_t ioh = sc->sc_ioh; 1985 1986 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1987 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1988 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1989 sc->sc_state = TRM_MSGIN; 1990 } 1991 1992 /* it's important for atn stop */ 1993 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1994 1995 /* 1996 * SCSI command 1997 */ 1998 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1999 } 2000 2001 static void 2002 trm_disconnect(struct trm_softc *sc) 2003 { 2004 bus_space_tag_t iot = sc->sc_iot; 2005 bus_space_handle_t ioh = sc->sc_ioh; 2006 struct trm_srb *srb; 2007 int s; 2008 2009 s = splbio(); 2010 2011 srb = sc->sc_actsrb; 2012 DPRINTF(("trm_disconnect...............\n")); 2013 2014 if (srb == NULL) { 2015 DPRINTF(("trm_disconnect: no active srb\n")); 2016 DELAY(1000); /* 1 msec */ 2017 2018 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2019 DO_CLRFIFO | DO_HWRESELECT); 2020 return; 2021 } 2022 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2023 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2024 DO_CLRFIFO | DO_HWRESELECT); 2025 DELAY(100); 2026 2027 switch (sc->sc_state) { 2028 case TRM_UNEXPECT_RESEL: 2029 sc->sc_state = TRM_IDLE; 2030 break; 2031 2032 case TRM_ABORT_SENT: 2033 goto finish; 2034 2035 case TRM_START: 2036 case TRM_MSGOUT: 2037 { 2038 /* Selection time out - discard all LUNs if empty */ 2039 struct scsipi_periph *periph; 2040 struct trm_tinfo *ti; 2041 struct trm_linfo *li; 2042 int lun; 2043 2044 DPRINTF(("selection timeout\n")); 2045 2046 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2047 2048 periph = srb->xs->xs_periph; 2049 ti = &sc->sc_tinfo[periph->periph_target]; 2050 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2051 li = ti->linfo[lun]; 2052 if (li != NULL && 2053 li->untagged == NULL && li->used == 0) { 2054 ti->linfo[lun] = NULL; 2055 free(li, M_DEVBUF); 2056 } 2057 } 2058 } 2059 goto finish; 2060 2061 case TRM_DISCONNECTED: 2062 sc->sc_actsrb = NULL; 2063 sc->sc_state = TRM_IDLE; 2064 goto sched; 2065 2066 case TRM_COMPLETED: 2067 goto finish; 2068 } 2069 2070 out: 2071 splx(s); 2072 return; 2073 2074 finish: 2075 sc->sc_state = TRM_IDLE; 2076 trm_done(sc, srb); 2077 goto out; 2078 2079 sched: 2080 trm_sched(sc); 2081 goto out; 2082 } 2083 2084 static void 2085 trm_reselect(struct trm_softc *sc) 2086 { 2087 bus_space_tag_t iot = sc->sc_iot; 2088 bus_space_handle_t ioh = sc->sc_ioh; 2089 struct trm_tinfo *ti; 2090 struct trm_linfo *li; 2091 int target, lun; 2092 2093 DPRINTF(("trm_reselect.................\n")); 2094 2095 if (sc->sc_actsrb != NULL) { 2096 /* arbitration lost but reselection win */ 2097 sc->sc_state = TRM_READY; 2098 target = sc->sc_actsrb->xs->xs_periph->periph_target; 2099 ti = &sc->sc_tinfo[target]; 2100 } else { 2101 /* Read Reselected Target Id and LUN */ 2102 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2103 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2104 ti = &sc->sc_tinfo[target]; 2105 li = ti->linfo[lun]; 2106 DPRINTF(("target = %d, lun = %d\n", target, lun)); 2107 2108 /* 2109 * Check to see if we are running an un-tagged command. 2110 * Otherwise ack the IDENTIFY and wait for a tag message. 2111 */ 2112 if (li != NULL) { 2113 if (li->untagged != NULL && li->busy) { 2114 sc->sc_actsrb = li->untagged; 2115 sc->sc_state = TRM_DATA_XFER; 2116 } else { 2117 sc->resel_target = target; 2118 sc->resel_lun = lun; 2119 /* XXX XXX XXX */ 2120 sc->sc_flag |= WAIT_TAGMSG; 2121 } 2122 } 2123 2124 if ((ti->flag & USE_TAG_QUEUING) == 0 && 2125 sc->sc_actsrb == NULL) { 2126 printf("%s: reselect from target %d lun %d " 2127 "without nexus; sending abort\n", 2128 device_xname(sc->sc_dev), target, lun); 2129 sc->sc_state = TRM_UNEXPECT_RESEL; 2130 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2131 sc->sc_msgcnt = 1; 2132 bus_space_write_2(iot, ioh, 2133 TRM_SCSI_CONTROL, DO_SETATN); 2134 } 2135 } 2136 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2137 /* 2138 * Program HA ID, target ID, period and offset 2139 */ 2140 /* target ID */ 2141 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2142 2143 /* host ID */ 2144 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2145 2146 /* period */ 2147 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2148 2149 /* offset */ 2150 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2151 2152 /* it's important for atn stop */ 2153 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2154 /* 2155 * SCSI command 2156 */ 2157 /* to rls the /ACK signal */ 2158 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2159 } 2160 2161 /* 2162 * Complete execution of a SCSI command 2163 * Signal completion to the generic SCSI driver 2164 */ 2165 static void 2166 trm_done(struct trm_softc *sc, struct trm_srb *srb) 2167 { 2168 struct scsipi_xfer *xs = srb->xs; 2169 2170 DPRINTF(("trm_done..................\n")); 2171 2172 if (xs == NULL) 2173 return; 2174 2175 if ((xs->xs_control & XS_CTL_POLL) == 0) 2176 callout_stop(&xs->xs_callout); 2177 2178 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2179 srb->flag & AUTO_REQSENSE) { 2180 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2181 srb->dmap->dm_mapsize, 2182 ((xs->xs_control & XS_CTL_DATA_IN) || 2183 (srb->flag & AUTO_REQSENSE)) ? 2184 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2185 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2186 } 2187 2188 /* 2189 * target status 2190 */ 2191 xs->status = srb->tastat; 2192 2193 DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2194 2195 switch (xs->status) { 2196 case SCSI_OK: 2197 /* 2198 * process initiator status...... 2199 * Adapter (initiator) status 2200 */ 2201 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2202 printf("%s: over/under run error\n", 2203 device_xname(sc->sc_dev)); 2204 srb->tastat = 0; 2205 /* Illegal length (over/under run) */ 2206 xs->error = XS_DRIVER_STUFFUP; 2207 } else if ((srb->flag & PARITY_ERROR) != 0) { 2208 printf("%s: parity error\n", device_xname(sc->sc_dev)); 2209 /* Driver failed to perform operation */ 2210 xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2211 } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2212 xs->resid = srb->buflen; 2213 xs->error = XS_TIMEOUT; 2214 } else { 2215 /* No error */ 2216 xs->resid = srb->buflen; 2217 srb->hastat = 0; 2218 if (srb->flag & AUTO_REQSENSE) { 2219 /* there is no error, (sense is invalid) */ 2220 xs->error = XS_SENSE; 2221 } else { 2222 srb->tastat = 0; 2223 xs->error = XS_NOERROR; 2224 } 2225 } 2226 break; 2227 2228 case SCSI_CHECK: 2229 if ((srb->flag & AUTO_REQSENSE) != 0 || 2230 trm_request_sense(sc, srb) != 0) { 2231 printf("%s: request sense failed\n", 2232 device_xname(sc->sc_dev)); 2233 xs->error = XS_DRIVER_STUFFUP; 2234 break; 2235 } 2236 xs->error = XS_SENSE; 2237 return; 2238 2239 case SCSI_SEL_TIMEOUT: 2240 srb->hastat = H_SEL_TIMEOUT; 2241 srb->tastat = 0; 2242 xs->error = XS_SELTIMEOUT; 2243 break; 2244 2245 case SCSI_QUEUE_FULL: 2246 case SCSI_BUSY: 2247 xs->error = XS_BUSY; 2248 break; 2249 2250 case SCSI_RESV_CONFLICT: 2251 DPRINTF(("%s: target reserved at ", device_xname(sc->sc_dev))); 2252 DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2253 xs->error = XS_BUSY; 2254 break; 2255 2256 default: 2257 srb->hastat = 0; 2258 printf("%s: trm_done(): unknown status = %02x\n", 2259 device_xname(sc->sc_dev), xs->status); 2260 xs->error = XS_DRIVER_STUFFUP; 2261 break; 2262 } 2263 2264 trm_dequeue(sc, srb); 2265 if (srb == sc->sc_actsrb) { 2266 sc->sc_actsrb = NULL; 2267 trm_sched(sc); 2268 } 2269 2270 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2271 2272 /* Notify cmd done */ 2273 scsipi_done(xs); 2274 } 2275 2276 static int 2277 trm_request_sense(struct trm_softc *sc, struct trm_srb *srb) 2278 { 2279 struct scsipi_xfer *xs; 2280 struct scsipi_periph *periph; 2281 struct trm_tinfo *ti; 2282 struct trm_linfo *li; 2283 struct scsi_request_sense *ss = (struct scsi_request_sense *)srb->cmd; 2284 int error; 2285 2286 DPRINTF(("trm_request_sense...\n")); 2287 2288 xs = srb->xs; 2289 periph = xs->xs_periph; 2290 2291 srb->flag |= AUTO_REQSENSE; 2292 2293 /* Status of initiator/target */ 2294 srb->hastat = 0; 2295 srb->tastat = 0; 2296 2297 memset(ss, 0, sizeof(*ss)); 2298 ss->opcode = SCSI_REQUEST_SENSE; 2299 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2300 ss->length = sizeof(struct scsi_sense_data); 2301 2302 srb->buflen = sizeof(struct scsi_sense_data); 2303 srb->sgcnt = 1; 2304 srb->sgindex = 0; 2305 srb->cmdlen = sizeof(struct scsi_request_sense); 2306 2307 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2308 &xs->sense.scsi_sense, srb->buflen, NULL, 2309 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2310 return error; 2311 } 2312 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2313 srb->buflen, BUS_DMASYNC_PREREAD); 2314 2315 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2316 srb->sgentry[0].length = htole32(sizeof(struct scsi_sense_data)); 2317 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2318 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2319 2320 ti = &sc->sc_tinfo[periph->periph_target]; 2321 li = ti->linfo[periph->periph_lun]; 2322 if (li->busy > 0) 2323 li->busy = 0; 2324 trm_dequeue(sc, srb); 2325 li->untagged = srb; /* must be executed first to fix C/A */ 2326 li->busy = 2; 2327 2328 if (srb == sc->sc_actsrb) 2329 trm_select(sc, srb); 2330 else { 2331 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2332 if (sc->sc_actsrb == NULL) 2333 trm_sched(sc); 2334 } 2335 return 0; 2336 } 2337 2338 static void 2339 trm_dequeue(struct trm_softc *sc, struct trm_srb *srb) 2340 { 2341 struct scsipi_periph *periph; 2342 struct trm_tinfo *ti; 2343 struct trm_linfo *li; 2344 2345 periph = srb->xs->xs_periph; 2346 ti = &sc->sc_tinfo[periph->periph_target]; 2347 li = ti->linfo[periph->periph_lun]; 2348 2349 if (li->untagged == srb) { 2350 li->busy = 0; 2351 li->untagged = NULL; 2352 } 2353 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2354 li->queued[srb->tag[1]] = NULL; 2355 li->used--; 2356 } 2357 } 2358 2359 static void 2360 trm_reset_scsi_bus(struct trm_softc *sc) 2361 { 2362 bus_space_tag_t iot = sc->sc_iot; 2363 bus_space_handle_t ioh = sc->sc_ioh; 2364 int timeout, s; 2365 2366 DPRINTF(("trm_reset_scsi_bus.........\n")); 2367 2368 s = splbio(); 2369 2370 sc->sc_flag |= RESET_DEV; 2371 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2372 for (timeout = 20000; timeout >= 0; timeout--) { 2373 DELAY(1); 2374 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2375 INT_SCSIRESET) == 0) 2376 break; 2377 } 2378 if (timeout == 0) 2379 printf(": scsibus reset timeout\n"); 2380 2381 splx(s); 2382 } 2383 2384 static void 2385 trm_scsi_reset_detect(struct trm_softc *sc) 2386 { 2387 bus_space_tag_t iot = sc->sc_iot; 2388 bus_space_handle_t ioh = sc->sc_ioh; 2389 int s; 2390 2391 DPRINTF(("trm_scsi_reset_detect...............\n")); 2392 DELAY(1000000); /* delay 1 sec */ 2393 2394 s = splbio(); 2395 2396 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2397 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2398 2399 if (sc->sc_flag & RESET_DEV) { 2400 sc->sc_flag |= RESET_DONE; 2401 } else { 2402 sc->sc_flag |= RESET_DETECT; 2403 sc->sc_actsrb = NULL; 2404 sc->sc_flag = 0; 2405 trm_sched(sc); 2406 } 2407 splx(s); 2408 } 2409 2410 /* 2411 * read seeprom 128 bytes to struct eeprom and check checksum. 2412 * If it is wrong, update with default value. 2413 */ 2414 static void 2415 trm_check_eeprom(struct trm_softc *sc, struct trm_nvram *eeprom) 2416 { 2417 struct nvram_target *target; 2418 uint16_t *ep; 2419 uint16_t chksum; 2420 int i; 2421 2422 DPRINTF(("trm_check_eeprom......\n")); 2423 trm_eeprom_read_all(sc, eeprom); 2424 ep = (uint16_t *)eeprom; 2425 chksum = 0; 2426 for (i = 0; i < 64; i++) 2427 chksum += le16toh(*ep++); 2428 2429 if (chksum != TRM_NVRAM_CKSUM) { 2430 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2431 /* 2432 * Checksum error, load default 2433 */ 2434 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2435 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2436 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2437 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2438 eeprom->subclass = 0x00; 2439 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2440 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2441 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2442 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2443 eeprom->reserved0 = 0x00; 2444 2445 for (i = 0, target = eeprom->target; 2446 i < TRM_MAX_TARGETS; 2447 i++, target++) { 2448 target->config0 = 0x77; 2449 target->period = 0x00; 2450 target->config2 = 0x00; 2451 target->config3 = 0x00; 2452 } 2453 2454 eeprom->scsi_id = 7; 2455 eeprom->channel_cfg = 0x0F; 2456 eeprom->delay_time = 0; 2457 eeprom->max_tag = 4; 2458 eeprom->reserved1 = 0x15; 2459 eeprom->boot_target = 0; 2460 eeprom->boot_lun = 0; 2461 eeprom->reserved2 = 0; 2462 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2463 2464 chksum = 0; 2465 ep = (uint16_t *)eeprom; 2466 for (i = 0; i < 63; i++) 2467 chksum += le16toh(*ep++); 2468 2469 chksum = TRM_NVRAM_CKSUM - chksum; 2470 eeprom->checksum0 = chksum & 0xFF; 2471 eeprom->checksum1 = chksum >> 8; 2472 2473 trm_eeprom_write_all(sc, eeprom); 2474 } 2475 } 2476 2477 /* 2478 * write struct eeprom 128 bytes to seeprom 2479 */ 2480 static void 2481 trm_eeprom_write_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2482 { 2483 bus_space_tag_t iot = sc->sc_iot; 2484 bus_space_handle_t ioh = sc->sc_ioh; 2485 uint8_t *sbuf = (uint8_t *)eeprom; 2486 uint8_t addr; 2487 2488 /* Enable SEEPROM */ 2489 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2490 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2491 2492 /* 2493 * Write enable 2494 */ 2495 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2496 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2497 trm_eeprom_wait(); 2498 2499 for (addr = 0; addr < 128; addr++, sbuf++) 2500 trm_eeprom_set_data(sc, addr, *sbuf); 2501 2502 /* 2503 * Write disable 2504 */ 2505 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2506 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2507 trm_eeprom_wait(); 2508 2509 /* Disable SEEPROM */ 2510 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2511 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2512 } 2513 2514 /* 2515 * write one byte to seeprom 2516 */ 2517 static void 2518 trm_eeprom_set_data(struct trm_softc *sc, uint8_t addr, uint8_t data) 2519 { 2520 bus_space_tag_t iot = sc->sc_iot; 2521 bus_space_handle_t ioh = sc->sc_ioh; 2522 int i; 2523 uint8_t send; 2524 2525 /* 2526 * Send write command & address 2527 */ 2528 trm_eeprom_write_cmd(sc, 0x05, addr); 2529 /* 2530 * Write data 2531 */ 2532 for (i = 0; i < 8; i++, data <<= 1) { 2533 send = NVR_SELECT; 2534 if (data & 0x80) /* Start from bit 7 */ 2535 send |= NVR_BITOUT; 2536 2537 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2538 trm_eeprom_wait(); 2539 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2540 trm_eeprom_wait(); 2541 } 2542 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2543 trm_eeprom_wait(); 2544 /* 2545 * Disable chip select 2546 */ 2547 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2548 trm_eeprom_wait(); 2549 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2550 trm_eeprom_wait(); 2551 /* 2552 * Wait for write ready 2553 */ 2554 for (;;) { 2555 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2556 NVR_SELECT | NVR_CLOCK); 2557 trm_eeprom_wait(); 2558 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2559 trm_eeprom_wait(); 2560 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2561 break; 2562 } 2563 /* 2564 * Disable chip select 2565 */ 2566 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2567 } 2568 2569 /* 2570 * read seeprom 128 bytes to struct eeprom 2571 */ 2572 static void 2573 trm_eeprom_read_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2574 { 2575 bus_space_tag_t iot = sc->sc_iot; 2576 bus_space_handle_t ioh = sc->sc_ioh; 2577 uint8_t *sbuf = (uint8_t *)eeprom; 2578 uint8_t addr; 2579 2580 /* 2581 * Enable SEEPROM 2582 */ 2583 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2584 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2585 2586 for (addr = 0; addr < 128; addr++) 2587 *sbuf++ = trm_eeprom_get_data(sc, addr); 2588 2589 /* 2590 * Disable SEEPROM 2591 */ 2592 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2593 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2594 } 2595 2596 /* 2597 * read one byte from seeprom 2598 */ 2599 static uint8_t 2600 trm_eeprom_get_data(struct trm_softc *sc, uint8_t addr) 2601 { 2602 bus_space_tag_t iot = sc->sc_iot; 2603 bus_space_handle_t ioh = sc->sc_ioh; 2604 int i; 2605 uint8_t read, data = 0; 2606 2607 /* 2608 * Send read command & address 2609 */ 2610 trm_eeprom_write_cmd(sc, 0x06, addr); 2611 2612 for (i = 0; i < 8; i++) { /* Read data */ 2613 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2614 NVR_SELECT | NVR_CLOCK); 2615 trm_eeprom_wait(); 2616 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2617 /* 2618 * Get data bit while falling edge 2619 */ 2620 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2621 data <<= 1; 2622 if (read & NVR_BITIN) 2623 data |= 1; 2624 2625 trm_eeprom_wait(); 2626 } 2627 /* 2628 * Disable chip select 2629 */ 2630 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2631 return data; 2632 } 2633 2634 /* 2635 * write SB and Op Code into seeprom 2636 */ 2637 static void 2638 trm_eeprom_write_cmd(struct trm_softc *sc, uint8_t cmd, uint8_t addr) 2639 { 2640 bus_space_tag_t iot = sc->sc_iot; 2641 bus_space_handle_t ioh = sc->sc_ioh; 2642 int i; 2643 uint8_t send; 2644 2645 /* Program SB+OP code */ 2646 for (i = 0; i < 3; i++, cmd <<= 1) { 2647 send = NVR_SELECT; 2648 if (cmd & 0x04) /* Start from bit 2 */ 2649 send |= NVR_BITOUT; 2650 2651 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2652 trm_eeprom_wait(); 2653 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2654 trm_eeprom_wait(); 2655 } 2656 2657 /* Program address */ 2658 for (i = 0; i < 7; i++, addr <<= 1) { 2659 send = NVR_SELECT; 2660 if (addr & 0x40) /* Start from bit 6 */ 2661 send |= NVR_BITOUT; 2662 2663 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2664 trm_eeprom_wait(); 2665 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2666 trm_eeprom_wait(); 2667 } 2668 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2669 trm_eeprom_wait(); 2670 } 2671
Indexes created Wed Sep 24 22:09:59 GMT 2025