trm.c revision 1.40
1 /* $NetBSD: trm.c,v 1.40 2018/12/09 11:14:02 jdolecek Exp $ */ 2 /*- 3 * Copyright (c) 2002 Izumi Tsutsui. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 /* 27 * Device Driver for Tekram DC395U/UW/F, DC315/U 28 * PCI SCSI Bus Master Host Adapter 29 * (SCSI chip set used Tekram ASIC TRM-S1040) 30 * 31 * Copyright (c) 2001 Rui-Xiang Guo 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. The name of the author may not be used to endorse or promote products 43 * derived from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 /* 57 * Ported from 58 * dc395x_trm.c 59 * 60 * Written for NetBSD 1.4.x by 61 * Erich Chen (erich (at) tekram.com.tw) 62 * 63 * Provided by 64 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.40 2018/12/09 11:14:02 jdolecek Exp $"); 69 70 /* #define TRM_DEBUG */ 71 #ifdef TRM_DEBUG 72 int trm_debug = 1; 73 #define DPRINTF(arg) if (trm_debug > 0) printf arg; 74 #else 75 #define DPRINTF(arg) 76 #endif 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/malloc.h> 81 #include <sys/buf.h> 82 #include <sys/kernel.h> 83 #include <sys/device.h> 84 #include <sys/queue.h> 85 86 #include <sys/bus.h> 87 #include <sys/intr.h> 88 89 #include <dev/scsipi/scsi_spc.h> 90 #include <dev/scsipi/scsi_all.h> 91 #include <dev/scsipi/scsi_message.h> 92 #include <dev/scsipi/scsipi_all.h> 93 #include <dev/scsipi/scsiconf.h> 94 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/trmreg.h> 99 100 /* 101 * feature of chip set MAX value 102 */ 103 #define TRM_MAX_TARGETS 16 104 #define TRM_MAX_LUNS 8 105 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 106 #define TRM_MAX_SRB 32 /* XXX */ 107 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 108 #define TRM_MAX_OFFSET 15 109 #define TRM_MAX_PERIOD 125 110 111 /* 112 * Segment Entry 113 */ 114 struct trm_sg_entry { 115 uint32_t address; 116 uint32_t length; 117 }; 118 119 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 120 121 /* 122 ********************************************************************** 123 * The SEEPROM structure for TRM_S1040 124 ********************************************************************** 125 */ 126 struct nvram_target { 127 uint8_t config0; /* Target configuration byte 0 */ 128 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 129 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 130 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 131 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 132 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 133 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 134 uint8_t period; /* Target period */ 135 uint8_t config2; /* Target configuration byte 2 */ 136 uint8_t config3; /* Target configuration byte 3 */ 137 }; 138 139 struct trm_nvram { 140 uint8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 141 uint8_t subsys_id[2]; /* 2,3 Sub System ID */ 142 uint8_t subclass; /* 4 Sub Class */ 143 uint8_t vendor_id[2]; /* 5,6 Vendor ID */ 144 uint8_t device_id[2]; /* 7,8 Device ID */ 145 uint8_t reserved0; /* 9 Reserved */ 146 struct nvram_target target[TRM_MAX_TARGETS]; 147 /* 10,11,12,13 148 * 14,15,16,17 149 * .... 150 * 70,71,72,73 */ 151 uint8_t scsi_id; /* 74 Host Adapter SCSI ID */ 152 uint8_t channel_cfg; /* 75 Channel configuration */ 153 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 154 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 155 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 156 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 157 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 158 uint8_t delay_time; /* 76 Power on delay time */ 159 uint8_t max_tag; /* 77 Maximum tags */ 160 uint8_t reserved1; /* 78 */ 161 uint8_t boot_target; /* 79 */ 162 uint8_t boot_lun; /* 80 */ 163 uint8_t reserved2; /* 81 */ 164 uint8_t reserved3[44]; /* 82,..125 */ 165 uint8_t checksum0; /* 126 */ 166 uint8_t checksum1; /* 127 */ 167 #define TRM_NVRAM_CKSUM 0x1234 168 }; 169 170 /* Nvram Initiater bits definition */ 171 #define MORE2_DRV 0x00000001 172 #define GREATER_1G 0x00000002 173 #define RST_SCSI_BUS 0x00000004 174 #define ACTIVE_NEGATION 0x00000008 175 #define NO_SEEK 0x00000010 176 #define LUN_CHECK 0x00000020 177 178 #define trm_eeprom_wait() DELAY(30) 179 180 /* 181 *----------------------------------------------------------------------- 182 * SCSI Request Block 183 *----------------------------------------------------------------------- 184 */ 185 struct trm_srb { 186 TAILQ_ENTRY(trm_srb) next; 187 188 struct trm_sg_entry *sgentry; 189 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 190 bus_dmamap_t dmap; 191 bus_size_t sgoffset; /* Xfer buf offset */ 192 193 uint32_t buflen; /* Total xfer length */ 194 uint32_t sgaddr; /* SGList physical starting address */ 195 196 int sgcnt; 197 int sgindex; 198 199 int hastat; /* Host Adapter Status */ 200 #define H_STATUS_GOOD 0x00 201 #define H_SEL_TIMEOUT 0x11 202 #define H_OVER_UNDER_RUN 0x12 203 #define H_UNEXP_BUS_FREE 0x13 204 #define H_TARGET_PHASE_F 0x14 205 #define H_INVALID_CCB_OP 0x16 206 #define H_LINK_CCB_BAD 0x17 207 #define H_BAD_TARGET_DIR 0x18 208 #define H_DUPLICATE_CCB 0x19 209 #define H_BAD_CCB_OR_SG 0x1A 210 #define H_ABORT 0xFF 211 int tastat; /* Target SCSI Status Byte */ 212 int flag; /* SRBFlag */ 213 #define AUTO_REQSENSE 0x0001 214 #define PARITY_ERROR 0x0002 215 #define SRB_TIMEOUT 0x0004 216 217 int cmdlen; /* SCSI command length */ 218 uint8_t cmd[12]; /* SCSI command */ 219 220 uint8_t tag[2]; 221 }; 222 223 /* 224 * some info about each target and lun on the SCSI bus 225 */ 226 struct trm_linfo { 227 int used; /* number of slots in use */ 228 int avail; /* where to start scanning */ 229 int busy; /* lun in use */ 230 struct trm_srb *untagged; 231 struct trm_srb *queued[TRM_MAX_TAG]; 232 }; 233 234 struct trm_tinfo { 235 u_int flag; /* Sync mode ? (1 sync):(0 async) */ 236 #define SYNC_NEGO_ENABLE 0x0001 237 #define SYNC_NEGO_DOING 0x0002 238 #define SYNC_NEGO_DONE 0x0004 239 #define WIDE_NEGO_ENABLE 0x0008 240 #define WIDE_NEGO_DOING 0x0010 241 #define WIDE_NEGO_DONE 0x0020 242 #define USE_TAG_QUEUING 0x0040 243 #define NO_RESELECT 0x0080 244 struct trm_linfo *linfo[TRM_MAX_LUNS]; 245 246 uint8_t config0; /* Target Config */ 247 uint8_t period; /* Max Period for nego. */ 248 uint8_t synctl; /* Sync control for reg. */ 249 uint8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 250 }; 251 252 /* 253 *----------------------------------------------------------------------- 254 * Adapter Control Block 255 *----------------------------------------------------------------------- 256 */ 257 struct trm_softc { 258 device_t sc_dev; 259 260 bus_space_tag_t sc_iot; 261 bus_space_handle_t sc_ioh; 262 bus_dma_tag_t sc_dmat; 263 bus_dmamap_t sc_dmamap; /* Map the control structures */ 264 265 struct trm_srb *sc_actsrb; 266 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 267 268 TAILQ_HEAD(, trm_srb) sc_freesrb, 269 sc_readysrb; 270 struct trm_srb *sc_srb; /* SRB array */ 271 272 struct trm_sg_entry *sc_sglist; 273 274 int sc_maxid; 275 /* 276 * Link to the generic SCSI driver 277 */ 278 struct scsipi_channel sc_channel; 279 struct scsipi_adapter sc_adapter; 280 281 int sc_id; /* Adapter SCSI Target ID */ 282 283 int sc_state; /* SRB State */ 284 #define TRM_IDLE 0 285 #define TRM_WAIT 1 286 #define TRM_READY 2 287 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 288 #define TRM_MSGIN 4 289 #define TRM_EXTEND_MSGIN 5 290 #define TRM_COMMAND 6 291 #define TRM_START 7 /* arbitration+msg_out+command_out */ 292 #define TRM_DISCONNECTED 8 293 #define TRM_DATA_XFER 9 294 #define TRM_XFERPAD 10 295 #define TRM_STATUS 11 296 #define TRM_COMPLETED 12 297 #define TRM_ABORT_SENT 13 298 #define TRM_UNEXPECT_RESEL 14 299 300 int sc_phase; /* SCSI phase */ 301 int sc_config; 302 #define HCC_WIDE_CARD 0x01 303 #define HCC_SCSI_RESET 0x02 304 #define HCC_PARITY 0x04 305 #define HCC_AUTOTERM 0x08 306 #define HCC_LOW8TERM 0x10 307 #define HCC_UP8TERM 0x20 308 309 int sc_flag; 310 #define RESET_DEV 0x01 311 #define RESET_DETECT 0x02 312 #define RESET_DONE 0x04 313 #define WAIT_TAGMSG 0x08 /* XXX */ 314 315 int sc_msgcnt; 316 317 int resel_target; /* XXX */ 318 int resel_lun; /* XXX */ 319 320 uint8_t *sc_msg; 321 uint8_t sc_msgbuf[6]; 322 }; 323 324 /* 325 * SCSI Status codes not defined in scsi_all.h 326 */ 327 #define SCSI_COND_MET 0x04 /* Condition Met */ 328 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 329 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 330 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 331 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 332 333 static int trm_match(device_t, cfdata_t, void *); 334 static void trm_attach(device_t, device_t, void *); 335 336 static int trm_init(struct trm_softc *); 337 338 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 339 void *); 340 static void trm_update_xfer_mode(struct trm_softc *, int); 341 static void trm_sched(struct trm_softc *); 342 static int trm_select(struct trm_softc *, struct trm_srb *); 343 static void trm_reset(struct trm_softc *); 344 static void trm_timeout(void *); 345 static int trm_intr(void *); 346 347 static void trm_dataout_phase0(struct trm_softc *, int); 348 static void trm_datain_phase0(struct trm_softc *, int); 349 static void trm_status_phase0(struct trm_softc *); 350 static void trm_msgin_phase0(struct trm_softc *); 351 static void trm_command_phase1(struct trm_softc *); 352 static void trm_status_phase1(struct trm_softc *); 353 static void trm_msgout_phase1(struct trm_softc *); 354 static void trm_msgin_phase1(struct trm_softc *); 355 356 static void trm_dataio_xfer(struct trm_softc *, int); 357 static void trm_disconnect(struct trm_softc *); 358 static void trm_reselect(struct trm_softc *); 359 static void trm_done(struct trm_softc *, struct trm_srb *); 360 static int trm_request_sense(struct trm_softc *, struct trm_srb *); 361 static void trm_dequeue(struct trm_softc *, struct trm_srb *); 362 363 static void trm_scsi_reset_detect(struct trm_softc *); 364 static void trm_reset_scsi_bus(struct trm_softc *); 365 366 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 367 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 368 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 369 static void trm_eeprom_set_data(struct trm_softc *, uint8_t, uint8_t); 370 static void trm_eeprom_write_cmd(struct trm_softc *, uint8_t, uint8_t); 371 static uint8_t trm_eeprom_get_data(struct trm_softc *, uint8_t); 372 373 CFATTACH_DECL_NEW(trm, sizeof(struct trm_softc), 374 trm_match, trm_attach, NULL, NULL); 375 376 /* real period: */ 377 static const uint8_t trm_clock_period[] = { 378 12, /* 48 ns 20.0 MB/sec */ 379 18, /* 72 ns 13.3 MB/sec */ 380 25, /* 100 ns 10.0 MB/sec */ 381 31, /* 124 ns 8.0 MB/sec */ 382 37, /* 148 ns 6.6 MB/sec */ 383 43, /* 172 ns 5.7 MB/sec */ 384 50, /* 200 ns 5.0 MB/sec */ 385 62 /* 248 ns 4.0 MB/sec */ 386 }; 387 #define NPERIOD __arraycount(trm_clock_period) 388 389 static int 390 trm_match(device_t parent, cfdata_t cf, void *aux) 391 { 392 struct pci_attach_args *pa = aux; 393 394 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 395 switch (PCI_PRODUCT(pa->pa_id)) { 396 case PCI_PRODUCT_TEKRAM2_DC315: 397 return 1; 398 } 399 return 0; 400 } 401 402 /* 403 * attach and init a host adapter 404 */ 405 static void 406 trm_attach(device_t parent, device_t self, void *aux) 407 { 408 struct trm_softc *sc = device_private(self); 409 struct pci_attach_args *const pa = aux; 410 bus_space_tag_t iot; 411 bus_space_handle_t ioh; 412 pci_intr_handle_t ih; 413 pcireg_t command; 414 const char *intrstr; 415 int fl = -1; 416 char intrbuf[PCI_INTRSTR_LEN]; 417 418 sc->sc_dev = self; 419 420 /* 421 * Some cards do not allow memory mapped accesses 422 * pa_pc: chipset tag 423 * pa_tag: pci tag 424 */ 425 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 426 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 427 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 428 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 429 pci_conf_write(pa->pa_pc, pa->pa_tag, 430 PCI_COMMAND_STATUS_REG, command); 431 } 432 /* 433 * mask for get correct base address of pci IO port 434 */ 435 if (command & PCI_COMMAND_MEM_ENABLE) { 436 fl = pci_mapreg_map(pa, TRM_BAR_MMIO, PCI_MAPREG_TYPE_MEM, 0, &iot, 437 &ioh, NULL, NULL); 438 } 439 if (fl != 0) { 440 aprint_verbose_dev(self, "couldn't map MMIO registers, trying PIO\n"); 441 if ((fl = pci_mapreg_map(pa, TRM_BAR_PIO, PCI_MAPREG_TYPE_IO, 442 0, &iot, &ioh, NULL, NULL)) != 0) { 443 aprint_error(": unable to map registers (%d)\n", fl); 444 return; 445 } 446 } 447 /* 448 * test checksum of eeprom.. & initialize softc... 449 */ 450 sc->sc_iot = iot; 451 sc->sc_ioh = ioh; 452 sc->sc_dmat = pa->pa_dmat; 453 454 if (trm_init(sc) != 0) { 455 /* 456 * Error during initialization! 457 */ 458 return; 459 } 460 /* 461 * Now try to attach all the sub-devices 462 */ 463 if ((sc->sc_config & HCC_WIDE_CARD) != 0) 464 aprint_normal(": Tekram DC395UW/F (TRM-S1040) Fast40 " 465 "Ultra Wide SCSI Adapter\n"); 466 else 467 aprint_normal(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 468 "Ultra SCSI Adapter\n"); 469 470 /* 471 * Now tell the generic SCSI layer about our bus. 472 * map and establish interrupt 473 */ 474 if (pci_intr_map(pa, &ih)) { 475 aprint_error_dev(self, "couldn't map interrupt\n"); 476 return; 477 } 478 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 479 480 if (pci_intr_establish_xname(pa->pa_pc, ih, IPL_BIO, trm_intr, sc, 481 device_xname(self)) == NULL) { 482 aprint_error_dev(self, "couldn't establish interrupt"); 483 if (intrstr != NULL) 484 aprint_error(" at %s", intrstr); 485 aprint_error("\n"); 486 return; 487 } 488 if (intrstr != NULL) 489 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 490 491 sc->sc_adapter.adapt_dev = self; 492 sc->sc_adapter.adapt_nchannels = 1; 493 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 494 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 495 sc->sc_adapter.adapt_request = trm_scsipi_request; 496 sc->sc_adapter.adapt_minphys = minphys; 497 498 sc->sc_channel.chan_adapter = &sc->sc_adapter; 499 sc->sc_channel.chan_bustype = &scsi_bustype; 500 sc->sc_channel.chan_channel = 0; 501 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 502 sc->sc_channel.chan_nluns = 8; 503 sc->sc_channel.chan_id = sc->sc_id; 504 505 config_found(self, &sc->sc_channel, scsiprint); 506 } 507 508 /* 509 * initialize the internal structures for a given SCSI host 510 */ 511 static int 512 trm_init(struct trm_softc *sc) 513 { 514 bus_space_tag_t iot = sc->sc_iot; 515 bus_space_handle_t ioh = sc->sc_ioh; 516 bus_dma_segment_t seg; 517 struct trm_nvram eeprom; 518 struct trm_srb *srb; 519 struct trm_tinfo *ti; 520 struct nvram_target *tconf; 521 int error, rseg, all_sgsize; 522 int i, target; 523 uint8_t bval; 524 525 DPRINTF(("\n")); 526 527 /* 528 * allocate the space for all SCSI control blocks (SRB) for DMA memory 529 */ 530 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 531 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 532 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 533 aprint_error(": unable to allocate SCSI REQUEST BLOCKS, " 534 "error = %d\n", error); 535 return 1; 536 } 537 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 538 all_sgsize, (void **) &sc->sc_sglist, 539 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 540 aprint_error(": unable to map SCSI REQUEST BLOCKS, " 541 "error = %d\n", error); 542 return 1; 543 } 544 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 545 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 546 aprint_error(": unable to create SRB DMA maps, " 547 "error = %d\n", error); 548 return 1; 549 } 550 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 551 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 552 aprint_error(": unable to load SRB DMA maps, " 553 "error = %d\n", error); 554 return 1; 555 } 556 DPRINTF(("all_sgsize=%x\n", all_sgsize)); 557 memset(sc->sc_sglist, 0, all_sgsize); 558 559 /* 560 * EEPROM CHECKSUM 561 */ 562 trm_check_eeprom(sc, &eeprom); 563 564 sc->sc_maxid = 7; 565 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 566 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 567 sc->sc_config |= HCC_WIDE_CARD; 568 sc->sc_maxid = 15; 569 } 570 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 571 sc->sc_config |= HCC_SCSI_RESET; 572 573 sc->sc_actsrb = NULL; 574 sc->sc_id = eeprom.scsi_id; 575 sc->sc_flag = 0; 576 577 /* 578 * initialize and link all device's SRB queues of this adapter 579 */ 580 TAILQ_INIT(&sc->sc_freesrb); 581 TAILQ_INIT(&sc->sc_readysrb); 582 583 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 584 M_DEVBUF, M_NOWAIT|M_ZERO); 585 DPRINTF(("all SRB size=%zx\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 586 if (sc->sc_srb == NULL) { 587 aprint_error(": can not allocate SRB\n"); 588 return 1; 589 } 590 591 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 592 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 593 srb->sgoffset = TRM_SG_SIZE * i; 594 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 595 /* 596 * map all SRB space to SRB_array 597 */ 598 if (bus_dmamap_create(sc->sc_dmat, 599 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 600 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 601 aprint_error(": unable to create DMA transfer map.\n"); 602 free(sc->sc_srb, M_DEVBUF); 603 return 1; 604 } 605 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 606 srb++; 607 } 608 609 /* 610 * initialize all target info structures 611 */ 612 for (target = 0; target < TRM_MAX_TARGETS; target++) { 613 ti = &sc->sc_tinfo[target]; 614 ti->synctl = 0; 615 ti->offset = 0; 616 tconf = &eeprom.target[target]; 617 ti->config0 = tconf->config0; 618 ti->period = trm_clock_period[tconf->period & 0x07]; 619 ti->flag = 0; 620 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 621 #ifdef notyet 622 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 623 ti->flag |= USE_TAG_QUEUING; 624 #endif 625 } else 626 ti->flag |= NO_RESELECT; 627 628 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 629 target, ti->config0, ti->period)); 630 DPRINTF((", flag = 0x%02x\n", ti->flag)); 631 } 632 633 /* program configuration 0 */ 634 bval = PHASELATCH | INITIATOR | BLOCKRST; 635 if ((sc->sc_config & HCC_PARITY) != 0) 636 bval |= PARITYCHECK; 637 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 638 639 /* program configuration 1 */ 640 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 641 ACTIVE_NEG | ACTIVE_NEGPLUS); 642 643 /* 250ms selection timeout */ 644 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 645 646 /* Mask all interrupts */ 647 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 648 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 649 650 /* Reset SCSI module */ 651 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 652 653 /* program Host ID */ 654 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 655 656 /* set asynchronous transfer */ 657 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 658 659 /* Turn LED control off */ 660 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 661 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 662 663 /* DMA config */ 664 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 665 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 666 667 /* Clear pending interrupt status */ 668 (void)bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 669 670 /* Enable SCSI interrupt */ 671 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 672 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 673 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 674 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 675 676 trm_reset(sc); 677 678 return 0; 679 } 680 681 /* 682 * enqueues a SCSI command 683 * called by the higher level SCSI driver 684 */ 685 static void 686 trm_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 687 void *arg) 688 { 689 bus_space_tag_t iot; 690 bus_space_handle_t ioh; 691 struct trm_softc *sc; 692 struct trm_srb *srb; 693 struct scsipi_xfer *xs; 694 int error, i, s; 695 696 sc = device_private(chan->chan_adapter->adapt_dev); 697 iot = sc->sc_iot; 698 ioh = sc->sc_ioh; 699 700 switch (req) { 701 case ADAPTER_REQ_RUN_XFER: 702 xs = arg; 703 DPRINTF(("trm_scsipi_request.....\n")); 704 DPRINTF(("target= %d lun= %d\n", xs->xs_periph->periph_target, 705 xs->xs_periph->periph_lun)); 706 if (xs->xs_control & XS_CTL_RESET) { 707 trm_reset(sc); 708 xs->error = XS_RESET; 709 return; 710 } 711 if (xs->xs_status & XS_STS_DONE) { 712 printf("%s: Is it done?\n", device_xname(sc->sc_dev)); 713 xs->xs_status &= ~XS_STS_DONE; 714 } 715 716 s = splbio(); 717 718 /* Get SRB */ 719 srb = TAILQ_FIRST(&sc->sc_freesrb); 720 if (srb != NULL) { 721 TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 722 } else { 723 xs->error = XS_RESOURCE_SHORTAGE; 724 scsipi_done(xs); 725 splx(s); 726 return; 727 } 728 729 srb->xs = xs; 730 srb->cmdlen = xs->cmdlen; 731 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 732 733 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 734 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 735 xs->data, xs->datalen, NULL, 736 ((xs->xs_control & XS_CTL_NOSLEEP) ? 737 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 738 BUS_DMA_STREAMING | 739 ((xs->xs_control & XS_CTL_DATA_IN) ? 740 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 741 printf("%s: DMA transfer map unable to load, " 742 "error = %d\n", device_xname(sc->sc_dev), 743 error); 744 xs->error = XS_DRIVER_STUFFUP; 745 /* 746 * free SRB 747 */ 748 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 749 splx(s); 750 return; 751 } 752 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 753 srb->dmap->dm_mapsize, 754 (xs->xs_control & XS_CTL_DATA_IN) ? 755 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 756 757 /* Set up the scatter gather list */ 758 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 759 srb->sgentry[i].address = 760 htole32(srb->dmap->dm_segs[i].ds_addr); 761 srb->sgentry[i].length = 762 htole32(srb->dmap->dm_segs[i].ds_len); 763 } 764 srb->buflen = xs->datalen; 765 srb->sgcnt = srb->dmap->dm_nsegs; 766 } else { 767 srb->sgentry[0].address = 0; 768 srb->sgentry[0].length = 0; 769 srb->buflen = 0; 770 srb->sgcnt = 0; 771 } 772 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 773 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 774 775 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 776 777 srb->sgindex = 0; 778 srb->hastat = 0; 779 srb->tastat = 0; 780 srb->flag = 0; 781 782 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 783 if (sc->sc_actsrb == NULL) 784 trm_sched(sc); 785 splx(s); 786 787 if ((xs->xs_control & XS_CTL_POLL) != 0) { 788 int timeout = xs->timeout; 789 790 s = splbio(); 791 do { 792 while (--timeout) { 793 DELAY(1000); 794 if (bus_space_read_2(iot, ioh, 795 TRM_SCSI_STATUS) & SCSIINTERRUPT) 796 break; 797 } 798 if (timeout == 0) { 799 trm_timeout(srb); 800 break; 801 } else 802 trm_intr(sc); 803 } while ((xs->xs_status & XS_STS_DONE) == 0); 804 splx(s); 805 } 806 return; 807 808 case ADAPTER_REQ_GROW_RESOURCES: 809 /* XXX Not supported. */ 810 return; 811 812 case ADAPTER_REQ_SET_XFER_MODE: 813 { 814 struct trm_tinfo *ti; 815 struct scsipi_xfer_mode *xm; 816 817 xm = arg; 818 ti = &sc->sc_tinfo[xm->xm_target]; 819 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 820 821 #ifdef notyet 822 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 823 ti->flag |= USE_TAG_QUEUING; 824 else 825 #endif 826 ti->flag &= ~USE_TAG_QUEUING; 827 828 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 829 (sc->sc_config & HCC_WIDE_CARD) != 0 && 830 (ti->config0 & NTC_DO_WIDE_NEGO) != 0) { 831 ti->flag |= WIDE_NEGO_ENABLE; 832 ti->flag &= ~WIDE_NEGO_DONE; 833 } 834 835 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 836 (ti->config0 & NTC_DO_SYNC_NEGO) != 0) { 837 ti->flag |= SYNC_NEGO_ENABLE; 838 ti->flag &= ~SYNC_NEGO_DONE; 839 ti->period = trm_clock_period[0]; 840 } 841 842 /* 843 * If we're not going to negotiate, send the 844 * notification now, since it won't happen later. 845 */ 846 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 847 (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 848 trm_update_xfer_mode(sc, xm->xm_target); 849 850 return; 851 } 852 } 853 } 854 855 static void 856 trm_update_xfer_mode(struct trm_softc *sc, int target) 857 { 858 struct scsipi_xfer_mode xm; 859 struct trm_tinfo *ti; 860 861 ti = &sc->sc_tinfo[target]; 862 xm.xm_target = target; 863 xm.xm_mode = 0; 864 xm.xm_period = 0; 865 xm.xm_offset = 0; 866 867 if ((ti->synctl & WIDE_SYNC) != 0) 868 xm.xm_mode |= PERIPH_CAP_WIDE16; 869 870 if (ti->period > 0) { 871 xm.xm_mode |= PERIPH_CAP_SYNC; 872 xm.xm_period = ti->period; 873 xm.xm_offset = ti->offset; 874 } 875 876 #ifdef notyet 877 if ((ti->flag & USE_TAG_QUEUING) != 0) 878 xm.xm_mode |= PERIPH_CAP_TQING; 879 #endif 880 881 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 882 } 883 884 static void 885 trm_sched(struct trm_softc *sc) 886 { 887 struct trm_srb *srb; 888 struct scsipi_periph *periph; 889 struct trm_tinfo *ti; 890 struct trm_linfo *li; 891 int s, lun, tag; 892 893 DPRINTF(("trm_sched...\n")); 894 895 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 896 periph = srb->xs->xs_periph; 897 ti = &sc->sc_tinfo[periph->periph_target]; 898 lun = periph->periph_lun; 899 900 /* select type of tag for this command */ 901 if ((ti->flag & NO_RESELECT) != 0 || 902 (ti->flag & USE_TAG_QUEUING) == 0 || 903 (srb->flag & AUTO_REQSENSE) != 0 || 904 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 905 tag = 0; 906 else 907 tag = srb->xs->xs_tag_type; 908 #if 0 909 /* XXX use tags for polled commands? */ 910 if (srb->xs->xs_control & XS_CTL_POLL) 911 tag = 0; 912 #endif 913 914 s = splbio(); 915 li = ti->linfo[lun]; 916 if (li == NULL) { 917 /* initialize lun info */ 918 if ((li = malloc(sizeof(*li), M_DEVBUF, 919 M_NOWAIT|M_ZERO)) == NULL) { 920 splx(s); 921 continue; 922 } 923 ti->linfo[lun] = li; 924 } 925 926 if (tag == 0) { 927 /* try to issue this srb as an un-tagged command */ 928 if (li->untagged == NULL) 929 li->untagged = srb; 930 } 931 if (li->untagged != NULL) { 932 tag = 0; 933 if (li->busy != 1 && li->used == 0) { 934 /* we need to issue the untagged command now */ 935 srb = li->untagged; 936 periph = srb->xs->xs_periph; 937 } else { 938 /* not ready yet */ 939 splx(s); 940 continue; 941 } 942 } 943 srb->tag[0] = tag; 944 if (tag != 0) { 945 li->queued[srb->xs->xs_tag_id] = srb; 946 srb->tag[1] = srb->xs->xs_tag_id; 947 li->used++; 948 } 949 950 if (li->untagged != NULL && li->busy != 1) { 951 li->busy = 1; 952 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 953 sc->sc_actsrb = srb; 954 trm_select(sc, srb); 955 splx(s); 956 break; 957 } 958 if (li->untagged == NULL && tag != 0) { 959 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 960 sc->sc_actsrb = srb; 961 trm_select(sc, srb); 962 splx(s); 963 break; 964 } else 965 splx(s); 966 } 967 } 968 969 static int 970 trm_select(struct trm_softc *sc, struct trm_srb *srb) 971 { 972 bus_space_tag_t iot = sc->sc_iot; 973 bus_space_handle_t ioh = sc->sc_ioh; 974 struct scsipi_periph *periph = srb->xs->xs_periph; 975 int target = periph->periph_target; 976 int lun = periph->periph_lun; 977 struct trm_tinfo *ti = &sc->sc_tinfo[target]; 978 uint8_t scsicmd; 979 980 DPRINTF(("trm_select.....\n")); 981 982 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 983 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), 984 trm_timeout, srb); 985 } 986 987 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 988 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 989 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 990 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 991 /* Flush FIFO */ 992 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 993 DELAY(10); 994 995 sc->sc_phase = PH_BUS_FREE; /* initial phase */ 996 997 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 998 999 if (((ti->flag & WIDE_NEGO_ENABLE) && 1000 (ti->flag & WIDE_NEGO_DONE) == 0) || 1001 ((ti->flag & SYNC_NEGO_ENABLE) && 1002 (ti->flag & SYNC_NEGO_DONE) == 0)) { 1003 sc->sc_state = TRM_MSGOUT; 1004 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1005 MSG_IDENTIFY(lun, 0)); 1006 bus_space_write_multi_1(iot, ioh, 1007 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1008 /* it's important for atn stop */ 1009 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1010 DO_DATALATCH | DO_HWRESELECT); 1011 /* SCSI command */ 1012 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 1013 DPRINTF(("select with SEL_ATNSTOP\n")); 1014 return 0; 1015 } 1016 1017 if (srb->tag[0] != 0) { 1018 /* Send identify message */ 1019 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1020 MSG_IDENTIFY(lun, 1)); 1021 /* Send Tag id */ 1022 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 1023 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 1024 scsicmd = SCMD_SEL_ATN3; 1025 DPRINTF(("select with SEL_ATN3\n")); 1026 } else { 1027 /* Send identify message */ 1028 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1029 MSG_IDENTIFY(lun, 1030 (ti->flag & NO_RESELECT) == 0 && 1031 (srb->flag & AUTO_REQSENSE) == 0 && 1032 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1033 scsicmd = SCMD_SEL_ATN; 1034 DPRINTF(("select with SEL_ATN\n")); 1035 } 1036 sc->sc_state = TRM_START; 1037 1038 /* 1039 * Send CDB ..command block... 1040 */ 1041 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1042 1043 /* 1044 * If trm_select returns 0: current interrupt status 1045 * is interrupt enable. It's said that SCSI processor is 1046 * unoccupied. 1047 */ 1048 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1049 /* SCSI command */ 1050 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1051 return 0; 1052 } 1053 1054 /* 1055 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1056 */ 1057 static void 1058 trm_reset(struct trm_softc *sc) 1059 { 1060 bus_space_tag_t iot = sc->sc_iot; 1061 bus_space_handle_t ioh = sc->sc_ioh; 1062 int s; 1063 1064 DPRINTF(("trm_reset.........\n")); 1065 1066 s = splbio(); 1067 1068 /* disable SCSI and DMA interrupt */ 1069 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1070 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1071 1072 trm_reset_scsi_bus(sc); 1073 DELAY(100000); 1074 1075 /* Enable SCSI interrupt */ 1076 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1077 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1078 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1079 1080 /* Enable DMA interrupt */ 1081 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1082 1083 /* Clear DMA FIFO */ 1084 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1085 1086 /* Clear SCSI FIFO */ 1087 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1088 1089 sc->sc_actsrb = NULL; 1090 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1091 1092 splx(s); 1093 } 1094 1095 static void 1096 trm_timeout(void *arg) 1097 { 1098 struct trm_srb *srb = (struct trm_srb *)arg; 1099 struct scsipi_xfer *xs; 1100 struct scsipi_periph *periph; 1101 struct trm_softc *sc; 1102 int s; 1103 1104 if (srb == NULL) { 1105 printf("trm_timeout called with srb == NULL\n"); 1106 return; 1107 } 1108 1109 xs = srb->xs; 1110 if (xs == NULL) { 1111 printf("trm_timeout called with xs == NULL\n"); 1112 return; 1113 } 1114 1115 periph = xs->xs_periph; 1116 scsipi_printaddr(xs->xs_periph); 1117 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1118 1119 sc = device_private(periph->periph_channel->chan_adapter->adapt_dev); 1120 1121 trm_reset_scsi_bus(sc); 1122 s = splbio(); 1123 srb->flag |= SRB_TIMEOUT; 1124 trm_done(sc, srb); 1125 /* XXX needs more.. */ 1126 splx(s); 1127 } 1128 1129 /* 1130 * Catch an interrupt from the adapter 1131 * Process pending device interrupts. 1132 */ 1133 static int 1134 trm_intr(void *arg) 1135 { 1136 bus_space_tag_t iot; 1137 bus_space_handle_t ioh; 1138 struct trm_softc *sc; 1139 int intstat, stat; 1140 1141 DPRINTF(("trm_intr......\n")); 1142 sc = arg; 1143 if (sc == NULL) 1144 return 0; 1145 1146 iot = sc->sc_iot; 1147 ioh = sc->sc_ioh; 1148 1149 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1150 if ((stat & SCSIINTERRUPT) == 0) 1151 return 0; 1152 1153 DPRINTF(("stat = %04x, ", stat)); 1154 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1155 1156 DPRINTF(("intstat=%02x, ", intstat)); 1157 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1158 DPRINTF(("\n")); 1159 trm_disconnect(sc); 1160 return 1; 1161 } 1162 if (intstat & INT_RESELECTED) { 1163 DPRINTF(("\n")); 1164 trm_reselect(sc); 1165 return 1; 1166 } 1167 if (intstat & INT_SCSIRESET) { 1168 DPRINTF(("\n")); 1169 trm_scsi_reset_detect(sc); 1170 return 1; 1171 } 1172 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1173 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1174 sc->sc_phase, sc->sc_state)); 1175 /* 1176 * software sequential machine 1177 */ 1178 1179 /* 1180 * call phase0 functions... "phase entry" handle 1181 * every phase before start transfer 1182 */ 1183 switch (sc->sc_phase) { 1184 case PH_DATA_OUT: 1185 trm_dataout_phase0(sc, stat); 1186 break; 1187 case PH_DATA_IN: 1188 trm_datain_phase0(sc, stat); 1189 break; 1190 case PH_COMMAND: 1191 break; 1192 case PH_STATUS: 1193 trm_status_phase0(sc); 1194 stat = PH_BUS_FREE; 1195 break; 1196 case PH_MSG_OUT: 1197 if (sc->sc_state == TRM_UNEXPECT_RESEL || 1198 sc->sc_state == TRM_ABORT_SENT) 1199 stat = PH_BUS_FREE; 1200 break; 1201 case PH_MSG_IN: 1202 trm_msgin_phase0(sc); 1203 stat = PH_BUS_FREE; 1204 break; 1205 case PH_BUS_FREE: 1206 break; 1207 default: 1208 printf("%s: unexpected phase in trm_intr() phase0\n", 1209 device_xname(sc->sc_dev)); 1210 break; 1211 } 1212 1213 sc->sc_phase = stat & PHASEMASK; 1214 1215 switch (sc->sc_phase) { 1216 case PH_DATA_OUT: 1217 trm_dataio_xfer(sc, XFERDATAOUT); 1218 break; 1219 case PH_DATA_IN: 1220 trm_dataio_xfer(sc, XFERDATAIN); 1221 break; 1222 case PH_COMMAND: 1223 trm_command_phase1(sc); 1224 break; 1225 case PH_STATUS: 1226 trm_status_phase1(sc); 1227 break; 1228 case PH_MSG_OUT: 1229 trm_msgout_phase1(sc); 1230 break; 1231 case PH_MSG_IN: 1232 trm_msgin_phase1(sc); 1233 break; 1234 case PH_BUS_FREE: 1235 break; 1236 default: 1237 printf("%s: unexpected phase in trm_intr() phase1\n", 1238 device_xname(sc->sc_dev)); 1239 break; 1240 } 1241 1242 return 1; 1243 } 1244 return 0; 1245 } 1246 1247 static void 1248 trm_msgout_phase1(struct trm_softc *sc) 1249 { 1250 bus_space_tag_t iot = sc->sc_iot; 1251 bus_space_handle_t ioh = sc->sc_ioh; 1252 struct trm_srb *srb; 1253 struct scsipi_periph *periph; 1254 struct trm_tinfo *ti; 1255 1256 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1257 1258 srb = sc->sc_actsrb; 1259 1260 /* message out phase */ 1261 if (srb != NULL) { 1262 periph = srb->xs->xs_periph; 1263 ti = &sc->sc_tinfo[periph->periph_target]; 1264 1265 if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1266 (ti->flag & WIDE_NEGO_ENABLE)) { 1267 /* send WDTR */ 1268 ti->flag &= ~SYNC_NEGO_DONE; 1269 1270 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1271 sc->sc_msgbuf[1] = MSG_EXTENDED; 1272 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1273 sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1274 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1275 sc->sc_msgcnt = 5; 1276 1277 ti->flag |= WIDE_NEGO_DOING; 1278 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1279 (ti->flag & SYNC_NEGO_ENABLE)) { 1280 /* send SDTR */ 1281 int cnt = 0; 1282 1283 if ((ti->flag & WIDE_NEGO_DONE) == 0) 1284 sc->sc_msgbuf[cnt++] = 1285 MSG_IDENTIFY(periph->periph_lun, 0); 1286 1287 sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1288 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1289 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1290 sc->sc_msgbuf[cnt++] = ti->period; 1291 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1292 sc->sc_msgcnt = cnt; 1293 ti->flag |= SYNC_NEGO_DOING; 1294 } 1295 } 1296 if (sc->sc_msgcnt == 0) { 1297 sc->sc_msgbuf[0] = MSG_ABORT; 1298 sc->sc_msgcnt = 1; 1299 sc->sc_state = TRM_ABORT_SENT; 1300 } 1301 1302 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1303 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1304 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1305 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1306 1307 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1308 sc->sc_msgbuf, sc->sc_msgcnt); 1309 sc->sc_msgcnt = 0; 1310 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1311 1312 /* it's important for atn stop */ 1313 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1314 1315 /* 1316 * SCSI command 1317 */ 1318 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1319 } 1320 1321 static void 1322 trm_command_phase1(struct trm_softc *sc) 1323 { 1324 bus_space_tag_t iot = sc->sc_iot; 1325 bus_space_handle_t ioh = sc->sc_ioh; 1326 struct trm_srb *srb; 1327 1328 srb = sc->sc_actsrb; 1329 if (srb == NULL) { 1330 DPRINTF(("trm_command_phase1: no active srb\n")); 1331 return; 1332 } 1333 1334 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1335 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1336 1337 sc->sc_state = TRM_COMMAND; 1338 /* it's important for atn stop */ 1339 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1340 1341 /* 1342 * SCSI command 1343 */ 1344 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1345 } 1346 1347 static void 1348 trm_dataout_phase0(struct trm_softc *sc, int stat) 1349 { 1350 bus_space_tag_t iot = sc->sc_iot; 1351 bus_space_handle_t ioh = sc->sc_ioh; 1352 struct trm_srb *srb; 1353 struct scsipi_periph *periph; 1354 struct trm_tinfo *ti; 1355 struct trm_sg_entry *sg; 1356 int sgindex; 1357 uint32_t xferlen, leftcnt = 0; 1358 1359 if (sc->sc_state == TRM_XFERPAD) 1360 return; 1361 1362 srb = sc->sc_actsrb; 1363 if (srb == NULL) { 1364 DPRINTF(("trm_dataout_phase0: no active srb\n")); 1365 return; 1366 } 1367 periph = srb->xs->xs_periph; 1368 ti = &sc->sc_tinfo[periph->periph_target]; 1369 1370 if ((stat & PARITYERROR) != 0) 1371 srb->flag |= PARITY_ERROR; 1372 1373 if ((stat & SCSIXFERDONE) == 0) { 1374 /* 1375 * when data transfer from DMA FIFO to SCSI FIFO 1376 * if there was some data left in SCSI FIFO 1377 */ 1378 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1379 SCSI_FIFOCNT_MASK; 1380 if (ti->synctl & WIDE_SYNC) 1381 /* 1382 * if WIDE scsi SCSI FIFOCNT unit is word 1383 * so need to * 2 1384 */ 1385 leftcnt <<= 1; 1386 } 1387 /* 1388 * calculate all the residue data that was not yet transferred 1389 * SCSI transfer counter + left in SCSI FIFO data 1390 * 1391 * .....TRM_SCSI_XCNT (24bits) 1392 * The counter always decrements by one for every SCSI 1393 * byte transfer. 1394 * .....TRM_SCSI_FIFOCNT ( 5bits) 1395 * The counter is SCSI FIFO offset counter 1396 */ 1397 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1398 if (leftcnt == 1) { 1399 leftcnt = 0; 1400 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1401 } 1402 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1403 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1404 DMAXFERCOMP) == 0) 1405 ; /* XXX needs timeout */ 1406 1407 srb->buflen = 0; 1408 } else { 1409 /* Update SG list */ 1410 1411 /* 1412 * if transfer not yet complete 1413 * there were some data residue in SCSI FIFO or 1414 * SCSI transfer counter not empty 1415 */ 1416 if (srb->buflen != leftcnt) { 1417 /* data that had transferred length */ 1418 xferlen = srb->buflen - leftcnt; 1419 1420 /* next time to be transferred length */ 1421 srb->buflen = leftcnt; 1422 1423 /* 1424 * parsing from last time disconnect sgindex 1425 */ 1426 sg = srb->sgentry + srb->sgindex; 1427 for (sgindex = srb->sgindex; 1428 sgindex < srb->sgcnt; 1429 sgindex++, sg++) { 1430 /* 1431 * find last time which SG transfer 1432 * be disconnect 1433 */ 1434 if (xferlen >= le32toh(sg->length)) 1435 xferlen -= le32toh(sg->length); 1436 else { 1437 /* 1438 * update last time 1439 * disconnected SG list 1440 */ 1441 /* residue data length */ 1442 sg->length = 1443 htole32(le32toh(sg->length) 1444 - xferlen); 1445 /* residue data pointer */ 1446 sg->address = 1447 htole32(le32toh(sg->address) 1448 + xferlen); 1449 srb->sgindex = sgindex; 1450 break; 1451 } 1452 } 1453 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1454 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1455 } 1456 } 1457 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1458 } 1459 1460 static void 1461 trm_datain_phase0(struct trm_softc *sc, int stat) 1462 { 1463 bus_space_tag_t iot = sc->sc_iot; 1464 bus_space_handle_t ioh = sc->sc_ioh; 1465 struct trm_srb *srb; 1466 struct trm_sg_entry *sg; 1467 int sgindex; 1468 uint32_t xferlen, leftcnt = 0; 1469 1470 if (sc->sc_state == TRM_XFERPAD) 1471 return; 1472 1473 srb = sc->sc_actsrb; 1474 if (srb == NULL) { 1475 DPRINTF(("trm_datain_phase0: no active srb\n")); 1476 return; 1477 } 1478 1479 if (stat & PARITYERROR) 1480 srb->flag |= PARITY_ERROR; 1481 1482 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1483 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1484 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1485 DMAXFERCOMP) == 0) 1486 ; /* XXX needs timeout */ 1487 1488 srb->buflen = 0; 1489 } else { /* phase changed */ 1490 /* 1491 * parsing the case: 1492 * when a transfer not yet complete 1493 * but be disconnected by upper layer 1494 * if transfer not yet complete 1495 * there were some data residue in SCSI FIFO or 1496 * SCSI transfer counter not empty 1497 */ 1498 if (srb->buflen != leftcnt) { 1499 /* 1500 * data that had transferred length 1501 */ 1502 xferlen = srb->buflen - leftcnt; 1503 1504 /* 1505 * next time to be transferred length 1506 */ 1507 srb->buflen = leftcnt; 1508 1509 /* 1510 * parsing from last time disconnect sgindex 1511 */ 1512 sg = srb->sgentry + srb->sgindex; 1513 for (sgindex = srb->sgindex; 1514 sgindex < srb->sgcnt; 1515 sgindex++, sg++) { 1516 /* 1517 * find last time which SG transfer 1518 * be disconnect 1519 */ 1520 if (xferlen >= le32toh(sg->length)) 1521 xferlen -= le32toh(sg->length); 1522 else { 1523 /* 1524 * update last time 1525 * disconnected SG list 1526 */ 1527 /* residue data length */ 1528 sg->length = 1529 htole32(le32toh(sg->length) 1530 - xferlen); 1531 /* residue data pointer */ 1532 sg->address = 1533 htole32(le32toh(sg->address) 1534 + xferlen); 1535 srb->sgindex = sgindex; 1536 break; 1537 } 1538 } 1539 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1540 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1541 } 1542 } 1543 } 1544 1545 static void 1546 trm_dataio_xfer(struct trm_softc *sc, int iodir) 1547 { 1548 bus_space_tag_t iot = sc->sc_iot; 1549 bus_space_handle_t ioh = sc->sc_ioh; 1550 struct trm_srb *srb; 1551 struct scsipi_periph *periph; 1552 struct trm_tinfo *ti; 1553 1554 srb = sc->sc_actsrb; 1555 if (srb == NULL) { 1556 DPRINTF(("trm_dataio_xfer: no active srb\n")); 1557 return; 1558 } 1559 periph = srb->xs->xs_periph; 1560 ti = &sc->sc_tinfo[periph->periph_target]; 1561 1562 if (srb->sgindex < srb->sgcnt) { 1563 if (srb->buflen > 0) { 1564 /* 1565 * load what physical address of Scatter/Gather 1566 * list table want to be transfer 1567 */ 1568 sc->sc_state = TRM_DATA_XFER; 1569 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1570 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1571 srb->sgaddr + 1572 srb->sgindex * sizeof(struct trm_sg_entry)); 1573 /* 1574 * load how many bytes in the Scatter/Gather list table 1575 */ 1576 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1577 (srb->sgcnt - srb->sgindex) 1578 * sizeof(struct trm_sg_entry)); 1579 /* 1580 * load total xfer length (24bits) max value 16Mbyte 1581 */ 1582 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1583 /* Start DMA transfer */ 1584 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1585 iodir | SGXFER); 1586 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1587 STARTDMAXFER); 1588 1589 /* Start SCSI transfer */ 1590 /* it's important for atn stop */ 1591 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1592 DO_DATALATCH); 1593 1594 /* 1595 * SCSI command 1596 */ 1597 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1598 (iodir == XFERDATAOUT) ? 1599 SCMD_DMA_OUT : SCMD_DMA_IN); 1600 } else { /* xfer pad */ 1601 if (srb->sgcnt) { 1602 srb->hastat = H_OVER_UNDER_RUN; 1603 } 1604 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1605 (ti->synctl & WIDE_SYNC) ? 2 : 1); 1606 1607 if (iodir == XFERDATAOUT) 1608 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1609 else 1610 (void)bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1611 1612 sc->sc_state = TRM_XFERPAD; 1613 /* it's important for atn stop */ 1614 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1615 DO_DATALATCH); 1616 1617 /* 1618 * SCSI command 1619 */ 1620 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1621 (iodir == XFERDATAOUT) ? 1622 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1623 } 1624 } 1625 } 1626 1627 static void 1628 trm_status_phase0(struct trm_softc *sc) 1629 { 1630 bus_space_tag_t iot = sc->sc_iot; 1631 bus_space_handle_t ioh = sc->sc_ioh; 1632 struct trm_srb *srb; 1633 1634 srb = sc->sc_actsrb; 1635 if (srb == NULL) { 1636 DPRINTF(("trm_status_phase0: no active srb\n")); 1637 return; 1638 } 1639 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1640 sc->sc_state = TRM_COMPLETED; 1641 /* it's important for atn stop */ 1642 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1643 1644 /* 1645 * SCSI command 1646 */ 1647 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1648 } 1649 1650 static void 1651 trm_status_phase1(struct trm_softc *sc) 1652 { 1653 bus_space_tag_t iot = sc->sc_iot; 1654 bus_space_handle_t ioh = sc->sc_ioh; 1655 1656 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1657 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1658 & SCSI_FIFO_EMPTY) == 0) 1659 bus_space_write_2(iot, ioh, 1660 TRM_SCSI_CONTROL, DO_CLRFIFO); 1661 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1662 & DMA_FIFO_EMPTY) == 0) 1663 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1664 } else { 1665 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1666 & DMA_FIFO_EMPTY) == 0) 1667 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1668 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1669 & SCSI_FIFO_EMPTY) == 0) 1670 bus_space_write_2(iot, ioh, 1671 TRM_SCSI_CONTROL, DO_CLRFIFO); 1672 } 1673 sc->sc_state = TRM_STATUS; 1674 /* it's important for atn stop */ 1675 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1676 1677 /* 1678 * SCSI command 1679 */ 1680 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1681 } 1682 1683 static void 1684 trm_msgin_phase0(struct trm_softc *sc) 1685 { 1686 bus_space_tag_t iot = sc->sc_iot; 1687 bus_space_handle_t ioh = sc->sc_ioh; 1688 struct trm_srb *srb; 1689 struct scsipi_periph *periph; 1690 struct trm_tinfo *ti; 1691 int index; 1692 uint8_t msgin_code; 1693 1694 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1695 if (sc->sc_state != TRM_EXTEND_MSGIN) { 1696 DPRINTF(("msgin: code = %02x\n", msgin_code)); 1697 switch (msgin_code) { 1698 case MSG_DISCONNECT: 1699 sc->sc_state = TRM_DISCONNECTED; 1700 break; 1701 1702 case MSG_SAVEDATAPOINTER: 1703 break; 1704 1705 case MSG_EXTENDED: 1706 case MSG_SIMPLE_Q_TAG: 1707 case MSG_HEAD_OF_Q_TAG: 1708 case MSG_ORDERED_Q_TAG: 1709 sc->sc_state = TRM_EXTEND_MSGIN; 1710 /* extended message (01h) */ 1711 sc->sc_msgbuf[0] = msgin_code; 1712 1713 sc->sc_msgcnt = 1; 1714 /* extended message length (n) */ 1715 sc->sc_msg = &sc->sc_msgbuf[1]; 1716 1717 break; 1718 case MSG_MESSAGE_REJECT: 1719 /* Reject message */ 1720 srb = sc->sc_actsrb; 1721 if (srb == NULL) { 1722 DPRINTF(("trm_msgin_phase0: " 1723 " message reject without actsrb\n")); 1724 break; 1725 } 1726 periph = srb->xs->xs_periph; 1727 ti = &sc->sc_tinfo[periph->periph_target]; 1728 1729 if (ti->flag & WIDE_NEGO_ENABLE) { 1730 /* do wide nego reject */ 1731 ti->flag |= WIDE_NEGO_DONE; 1732 ti->flag &= 1733 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1734 if ((ti->flag & SYNC_NEGO_ENABLE) && 1735 (ti->flag & SYNC_NEGO_DONE) == 0) { 1736 /* Set ATN, in case ATN was clear */ 1737 sc->sc_state = TRM_MSGOUT; 1738 bus_space_write_2(iot, ioh, 1739 TRM_SCSI_CONTROL, DO_SETATN); 1740 } else 1741 /* Clear ATN */ 1742 bus_space_write_2(iot, ioh, 1743 TRM_SCSI_CONTROL, DO_CLRATN); 1744 } else if (ti->flag & SYNC_NEGO_ENABLE) { 1745 /* do sync nego reject */ 1746 bus_space_write_2(iot, ioh, 1747 TRM_SCSI_CONTROL, DO_CLRATN); 1748 if (ti->flag & SYNC_NEGO_DOING) { 1749 ti->flag &=~(SYNC_NEGO_ENABLE | 1750 SYNC_NEGO_DONE); 1751 ti->synctl = 0; 1752 ti->offset = 0; 1753 bus_space_write_1(iot, ioh, 1754 TRM_SCSI_SYNC, ti->synctl); 1755 bus_space_write_1(iot, ioh, 1756 TRM_SCSI_OFFSET, ti->offset); 1757 } 1758 } 1759 break; 1760 1761 case MSG_IGN_WIDE_RESIDUE: 1762 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1763 (void)bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1764 break; 1765 1766 default: 1767 /* 1768 * Restore data pointer message 1769 * Save data pointer message 1770 * Completion message 1771 * NOP message 1772 */ 1773 break; 1774 } 1775 } else { 1776 /* 1777 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1778 * Parsing incoming extented messages 1779 */ 1780 *sc->sc_msg++ = msgin_code; 1781 sc->sc_msgcnt++; 1782 1783 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1784 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1785 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1786 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1787 1788 switch (sc->sc_msgbuf[0]) { 1789 case MSG_SIMPLE_Q_TAG: 1790 case MSG_HEAD_OF_Q_TAG: 1791 case MSG_ORDERED_Q_TAG: 1792 /* 1793 * is QUEUE tag message : 1794 * 1795 * byte 0: 1796 * HEAD QUEUE TAG (20h) 1797 * ORDERED QUEUE TAG (21h) 1798 * SIMPLE QUEUE TAG (22h) 1799 * byte 1: 1800 * Queue tag (00h - FFh) 1801 */ 1802 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1803 /* XXX XXX XXX */ 1804 struct trm_linfo *li; 1805 int tagid; 1806 1807 sc->sc_flag &= ~WAIT_TAGMSG; 1808 tagid = sc->sc_msgbuf[1]; 1809 ti = &sc->sc_tinfo[sc->resel_target]; 1810 li = ti->linfo[sc->resel_lun]; 1811 srb = li->queued[tagid]; 1812 if (srb != NULL) { 1813 sc->sc_actsrb = srb; 1814 sc->sc_state = TRM_DATA_XFER; 1815 break; 1816 } else { 1817 printf("%s: invalid tag id\n", 1818 device_xname(sc->sc_dev)); 1819 } 1820 1821 sc->sc_state = TRM_UNEXPECT_RESEL; 1822 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1823 sc->sc_msgcnt = 1; 1824 bus_space_write_2(iot, ioh, 1825 TRM_SCSI_CONTROL, DO_SETATN); 1826 } else 1827 sc->sc_state = TRM_IDLE; 1828 break; 1829 1830 case MSG_EXTENDED: 1831 srb = sc->sc_actsrb; 1832 if (srb == NULL) { 1833 DPRINTF(("trm_msgin_phase0: " 1834 "extended message without actsrb\n")); 1835 break; 1836 } 1837 periph = srb->xs->xs_periph; 1838 ti = &sc->sc_tinfo[periph->periph_target]; 1839 1840 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1841 sc->sc_msgcnt == 4) { 1842 /* 1843 * is Wide data xfer Extended message : 1844 * ====================================== 1845 * WIDE DATA TRANSFER REQUEST 1846 * ====================================== 1847 * byte 0 : Extended message (01h) 1848 * byte 1 : Extended message length (02h) 1849 * byte 2 : WIDE DATA TRANSFER code (03h) 1850 * byte 3 : Transfer width exponent 1851 */ 1852 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1853 /* Length is wrong, reject it */ 1854 ti->flag &= ~(WIDE_NEGO_ENABLE | 1855 WIDE_NEGO_DONE); 1856 sc->sc_state = TRM_MSGOUT; 1857 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1858 sc->sc_msgcnt = 1; 1859 bus_space_write_2(iot, ioh, 1860 TRM_SCSI_CONTROL, DO_SETATN); 1861 break; 1862 } 1863 1864 if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1865 sc->sc_msgbuf[3] = 1866 MSG_EXT_WDTR_BUS_8_BIT; 1867 1868 if (sc->sc_msgbuf[3] > 1869 MSG_EXT_WDTR_BUS_32_BIT) { 1870 /* reject_msg: */ 1871 ti->flag &= ~(WIDE_NEGO_ENABLE | 1872 WIDE_NEGO_DONE); 1873 sc->sc_state = TRM_MSGOUT; 1874 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1875 sc->sc_msgcnt = 1; 1876 bus_space_write_2(iot, ioh, 1877 TRM_SCSI_CONTROL, DO_SETATN); 1878 break; 1879 } 1880 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1881 /* do 16 bits */ 1882 sc->sc_msgbuf[3] = 1883 MSG_EXT_WDTR_BUS_16_BIT; 1884 if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1885 ti->flag |= WIDE_NEGO_DONE; 1886 ti->flag &= ~(SYNC_NEGO_DONE | 1887 WIDE_NEGO_ENABLE); 1888 if (sc->sc_msgbuf[3] != 1889 MSG_EXT_WDTR_BUS_8_BIT) 1890 /* is Wide data xfer */ 1891 ti->synctl |= WIDE_SYNC; 1892 trm_update_xfer_mode(sc, 1893 periph->periph_target); 1894 } 1895 1896 sc->sc_state = TRM_MSGOUT; 1897 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1898 DO_SETATN); 1899 break; 1900 1901 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1902 sc->sc_msgcnt == 5) { 1903 /* 1904 * is 8bit transfer Extended message : 1905 * ================================= 1906 * SYNCHRONOUS DATA TRANSFER REQUEST 1907 * ================================= 1908 * byte 0 : Extended message (01h) 1909 * byte 1 : Extended message length (03) 1910 * byte 2 : SYNC DATA TRANSFER code (01h) 1911 * byte 3 : Transfer period factor 1912 * byte 4 : REQ/ACK offset 1913 */ 1914 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1915 /* reject_msg */ 1916 sc->sc_state = TRM_MSGOUT; 1917 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1918 sc->sc_msgcnt = 1; 1919 bus_space_write_2(iot, ioh, 1920 TRM_SCSI_CONTROL, DO_SETATN); 1921 break; 1922 } 1923 1924 if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1925 ti->flag &= 1926 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1927 ti->flag |= SYNC_NEGO_DONE; 1928 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1929 sc->sc_msgbuf[3] = 0; 1930 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1931 sc->sc_msgbuf[4] = 1932 TRM_MAX_OFFSET; 1933 1934 if (sc->sc_msgbuf[3] == 0 || 1935 sc->sc_msgbuf[4] == 0) { 1936 /* set async */ 1937 ti->synctl = 0; 1938 ti->offset = 0; 1939 } else { 1940 /* set sync */ 1941 /* Transfer period factor */ 1942 ti->period = sc->sc_msgbuf[3]; 1943 /* REQ/ACK offset */ 1944 ti->offset = sc->sc_msgbuf[4]; 1945 for (index = 0; 1946 index < NPERIOD; 1947 index++) 1948 if (ti->period <= 1949 trm_clock_period[ 1950 index]) 1951 break; 1952 1953 ti->synctl |= ALT_SYNC | index; 1954 } 1955 /* 1956 * program SCSI control register 1957 */ 1958 bus_space_write_1(iot, ioh, 1959 TRM_SCSI_SYNC, ti->synctl); 1960 bus_space_write_1(iot, ioh, 1961 TRM_SCSI_OFFSET, ti->offset); 1962 trm_update_xfer_mode(sc, 1963 periph->periph_target); 1964 } 1965 sc->sc_state = TRM_IDLE; 1966 } 1967 break; 1968 default: 1969 break; 1970 } 1971 } 1972 1973 /* it's important for atn stop */ 1974 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1975 1976 /* 1977 * SCSI command 1978 */ 1979 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1980 } 1981 1982 static void 1983 trm_msgin_phase1(struct trm_softc *sc) 1984 { 1985 bus_space_tag_t iot = sc->sc_iot; 1986 bus_space_handle_t ioh = sc->sc_ioh; 1987 1988 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1989 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1990 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1991 sc->sc_state = TRM_MSGIN; 1992 } 1993 1994 /* it's important for atn stop */ 1995 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1996 1997 /* 1998 * SCSI command 1999 */ 2000 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 2001 } 2002 2003 static void 2004 trm_disconnect(struct trm_softc *sc) 2005 { 2006 bus_space_tag_t iot = sc->sc_iot; 2007 bus_space_handle_t ioh = sc->sc_ioh; 2008 struct trm_srb *srb; 2009 int s; 2010 2011 s = splbio(); 2012 2013 srb = sc->sc_actsrb; 2014 DPRINTF(("trm_disconnect...............\n")); 2015 2016 if (srb == NULL) { 2017 DPRINTF(("trm_disconnect: no active srb\n")); 2018 DELAY(1000); /* 1 msec */ 2019 2020 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2021 DO_CLRFIFO | DO_HWRESELECT); 2022 return; 2023 } 2024 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2025 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2026 DO_CLRFIFO | DO_HWRESELECT); 2027 DELAY(100); 2028 2029 switch (sc->sc_state) { 2030 case TRM_UNEXPECT_RESEL: 2031 sc->sc_state = TRM_IDLE; 2032 break; 2033 2034 case TRM_ABORT_SENT: 2035 goto finish; 2036 2037 case TRM_START: 2038 case TRM_MSGOUT: 2039 { 2040 /* Selection time out - discard all LUNs if empty */ 2041 struct scsipi_periph *periph; 2042 struct trm_tinfo *ti; 2043 struct trm_linfo *li; 2044 int lun; 2045 2046 DPRINTF(("selection timeout\n")); 2047 2048 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2049 2050 periph = srb->xs->xs_periph; 2051 ti = &sc->sc_tinfo[periph->periph_target]; 2052 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2053 li = ti->linfo[lun]; 2054 if (li != NULL && 2055 li->untagged == NULL && li->used == 0) { 2056 ti->linfo[lun] = NULL; 2057 free(li, M_DEVBUF); 2058 } 2059 } 2060 } 2061 goto finish; 2062 2063 case TRM_DISCONNECTED: 2064 sc->sc_actsrb = NULL; 2065 sc->sc_state = TRM_IDLE; 2066 goto sched; 2067 2068 case TRM_COMPLETED: 2069 goto finish; 2070 } 2071 2072 out: 2073 splx(s); 2074 return; 2075 2076 finish: 2077 sc->sc_state = TRM_IDLE; 2078 trm_done(sc, srb); 2079 goto out; 2080 2081 sched: 2082 trm_sched(sc); 2083 goto out; 2084 } 2085 2086 static void 2087 trm_reselect(struct trm_softc *sc) 2088 { 2089 bus_space_tag_t iot = sc->sc_iot; 2090 bus_space_handle_t ioh = sc->sc_ioh; 2091 struct trm_tinfo *ti; 2092 struct trm_linfo *li; 2093 int target, lun; 2094 2095 DPRINTF(("trm_reselect.................\n")); 2096 2097 if (sc->sc_actsrb != NULL) { 2098 /* arbitration lost but reselection win */ 2099 sc->sc_state = TRM_READY; 2100 target = sc->sc_actsrb->xs->xs_periph->periph_target; 2101 ti = &sc->sc_tinfo[target]; 2102 } else { 2103 /* Read Reselected Target Id and LUN */ 2104 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2105 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2106 ti = &sc->sc_tinfo[target]; 2107 li = ti->linfo[lun]; 2108 DPRINTF(("target = %d, lun = %d\n", target, lun)); 2109 2110 /* 2111 * Check to see if we are running an un-tagged command. 2112 * Otherwise ack the IDENTIFY and wait for a tag message. 2113 */ 2114 if (li != NULL) { 2115 if (li->untagged != NULL && li->busy) { 2116 sc->sc_actsrb = li->untagged; 2117 sc->sc_state = TRM_DATA_XFER; 2118 } else { 2119 sc->resel_target = target; 2120 sc->resel_lun = lun; 2121 /* XXX XXX XXX */ 2122 sc->sc_flag |= WAIT_TAGMSG; 2123 } 2124 } 2125 2126 if ((ti->flag & USE_TAG_QUEUING) == 0 && 2127 sc->sc_actsrb == NULL) { 2128 printf("%s: reselect from target %d lun %d " 2129 "without nexus; sending abort\n", 2130 device_xname(sc->sc_dev), target, lun); 2131 sc->sc_state = TRM_UNEXPECT_RESEL; 2132 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2133 sc->sc_msgcnt = 1; 2134 bus_space_write_2(iot, ioh, 2135 TRM_SCSI_CONTROL, DO_SETATN); 2136 } 2137 } 2138 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2139 /* 2140 * Program HA ID, target ID, period and offset 2141 */ 2142 /* target ID */ 2143 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2144 2145 /* host ID */ 2146 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2147 2148 /* period */ 2149 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2150 2151 /* offset */ 2152 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2153 2154 /* it's important for atn stop */ 2155 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2156 /* 2157 * SCSI command 2158 */ 2159 /* to rls the /ACK signal */ 2160 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2161 } 2162 2163 /* 2164 * Complete execution of a SCSI command 2165 * Signal completion to the generic SCSI driver 2166 */ 2167 static void 2168 trm_done(struct trm_softc *sc, struct trm_srb *srb) 2169 { 2170 struct scsipi_xfer *xs = srb->xs; 2171 2172 DPRINTF(("trm_done..................\n")); 2173 2174 if (xs == NULL) 2175 return; 2176 2177 if ((xs->xs_control & XS_CTL_POLL) == 0) 2178 callout_stop(&xs->xs_callout); 2179 2180 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2181 srb->flag & AUTO_REQSENSE) { 2182 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2183 srb->dmap->dm_mapsize, 2184 ((xs->xs_control & XS_CTL_DATA_IN) || 2185 (srb->flag & AUTO_REQSENSE)) ? 2186 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2187 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2188 } 2189 2190 /* 2191 * target status 2192 */ 2193 xs->status = srb->tastat; 2194 2195 DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2196 2197 switch (xs->status) { 2198 case SCSI_OK: 2199 /* 2200 * process initiator status...... 2201 * Adapter (initiator) status 2202 */ 2203 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2204 printf("%s: over/under run error\n", 2205 device_xname(sc->sc_dev)); 2206 srb->tastat = 0; 2207 /* Illegal length (over/under run) */ 2208 xs->error = XS_DRIVER_STUFFUP; 2209 } else if ((srb->flag & PARITY_ERROR) != 0) { 2210 printf("%s: parity error\n", device_xname(sc->sc_dev)); 2211 /* Driver failed to perform operation */ 2212 xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2213 } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2214 xs->resid = srb->buflen; 2215 xs->error = XS_TIMEOUT; 2216 } else { 2217 /* No error */ 2218 xs->resid = srb->buflen; 2219 srb->hastat = 0; 2220 if (srb->flag & AUTO_REQSENSE) { 2221 /* there is no error, (sense is invalid) */ 2222 xs->error = XS_SENSE; 2223 } else { 2224 srb->tastat = 0; 2225 xs->error = XS_NOERROR; 2226 } 2227 } 2228 break; 2229 2230 case SCSI_CHECK: 2231 if ((srb->flag & AUTO_REQSENSE) != 0 || 2232 trm_request_sense(sc, srb) != 0) { 2233 printf("%s: request sense failed\n", 2234 device_xname(sc->sc_dev)); 2235 xs->error = XS_DRIVER_STUFFUP; 2236 break; 2237 } 2238 xs->error = XS_SENSE; 2239 return; 2240 2241 case SCSI_SEL_TIMEOUT: 2242 srb->hastat = H_SEL_TIMEOUT; 2243 srb->tastat = 0; 2244 xs->error = XS_SELTIMEOUT; 2245 break; 2246 2247 case SCSI_QUEUE_FULL: 2248 case SCSI_BUSY: 2249 xs->error = XS_BUSY; 2250 break; 2251 2252 case SCSI_RESV_CONFLICT: 2253 DPRINTF(("%s: target reserved at ", device_xname(sc->sc_dev))); 2254 DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2255 xs->error = XS_BUSY; 2256 break; 2257 2258 default: 2259 srb->hastat = 0; 2260 printf("%s: trm_done(): unknown status = %02x\n", 2261 device_xname(sc->sc_dev), xs->status); 2262 xs->error = XS_DRIVER_STUFFUP; 2263 break; 2264 } 2265 2266 trm_dequeue(sc, srb); 2267 if (srb == sc->sc_actsrb) { 2268 sc->sc_actsrb = NULL; 2269 trm_sched(sc); 2270 } 2271 2272 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2273 2274 /* Notify cmd done */ 2275 scsipi_done(xs); 2276 } 2277 2278 static int 2279 trm_request_sense(struct trm_softc *sc, struct trm_srb *srb) 2280 { 2281 struct scsipi_xfer *xs; 2282 struct scsipi_periph *periph; 2283 struct trm_tinfo *ti; 2284 struct trm_linfo *li; 2285 struct scsi_request_sense *ss = (struct scsi_request_sense *)srb->cmd; 2286 int error; 2287 2288 DPRINTF(("trm_request_sense...\n")); 2289 2290 xs = srb->xs; 2291 periph = xs->xs_periph; 2292 2293 srb->flag |= AUTO_REQSENSE; 2294 2295 /* Status of initiator/target */ 2296 srb->hastat = 0; 2297 srb->tastat = 0; 2298 2299 memset(ss, 0, sizeof(*ss)); 2300 ss->opcode = SCSI_REQUEST_SENSE; 2301 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2302 ss->length = sizeof(struct scsi_sense_data); 2303 2304 srb->buflen = sizeof(struct scsi_sense_data); 2305 srb->sgcnt = 1; 2306 srb->sgindex = 0; 2307 srb->cmdlen = sizeof(struct scsi_request_sense); 2308 2309 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2310 &xs->sense.scsi_sense, srb->buflen, NULL, 2311 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2312 return error; 2313 } 2314 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2315 srb->buflen, BUS_DMASYNC_PREREAD); 2316 2317 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2318 srb->sgentry[0].length = htole32(sizeof(struct scsi_sense_data)); 2319 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2320 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2321 2322 ti = &sc->sc_tinfo[periph->periph_target]; 2323 li = ti->linfo[periph->periph_lun]; 2324 if (li->busy > 0) 2325 li->busy = 0; 2326 trm_dequeue(sc, srb); 2327 li->untagged = srb; /* must be executed first to fix C/A */ 2328 li->busy = 2; 2329 2330 if (srb == sc->sc_actsrb) 2331 trm_select(sc, srb); 2332 else { 2333 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2334 if (sc->sc_actsrb == NULL) 2335 trm_sched(sc); 2336 } 2337 return 0; 2338 } 2339 2340 static void 2341 trm_dequeue(struct trm_softc *sc, struct trm_srb *srb) 2342 { 2343 struct scsipi_periph *periph; 2344 struct trm_tinfo *ti; 2345 struct trm_linfo *li; 2346 2347 periph = srb->xs->xs_periph; 2348 ti = &sc->sc_tinfo[periph->periph_target]; 2349 li = ti->linfo[periph->periph_lun]; 2350 2351 if (li->untagged == srb) { 2352 li->busy = 0; 2353 li->untagged = NULL; 2354 } 2355 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2356 li->queued[srb->tag[1]] = NULL; 2357 li->used--; 2358 } 2359 } 2360 2361 static void 2362 trm_reset_scsi_bus(struct trm_softc *sc) 2363 { 2364 bus_space_tag_t iot = sc->sc_iot; 2365 bus_space_handle_t ioh = sc->sc_ioh; 2366 int timeout, s; 2367 2368 DPRINTF(("trm_reset_scsi_bus.........\n")); 2369 2370 s = splbio(); 2371 2372 sc->sc_flag |= RESET_DEV; 2373 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2374 for (timeout = 20000; timeout >= 0; timeout--) { 2375 DELAY(1); 2376 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2377 INT_SCSIRESET) == 0) 2378 break; 2379 } 2380 if (timeout == 0) 2381 printf(": scsibus reset timeout\n"); 2382 2383 splx(s); 2384 } 2385 2386 static void 2387 trm_scsi_reset_detect(struct trm_softc *sc) 2388 { 2389 bus_space_tag_t iot = sc->sc_iot; 2390 bus_space_handle_t ioh = sc->sc_ioh; 2391 int s; 2392 2393 DPRINTF(("trm_scsi_reset_detect...............\n")); 2394 DELAY(1000000); /* delay 1 sec */ 2395 2396 s = splbio(); 2397 2398 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2399 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2400 2401 if (sc->sc_flag & RESET_DEV) { 2402 sc->sc_flag |= RESET_DONE; 2403 } else { 2404 sc->sc_flag |= RESET_DETECT; 2405 sc->sc_actsrb = NULL; 2406 sc->sc_flag = 0; 2407 trm_sched(sc); 2408 } 2409 splx(s); 2410 } 2411 2412 /* 2413 * read seeprom 128 bytes to struct eeprom and check checksum. 2414 * If it is wrong, update with default value. 2415 */ 2416 static void 2417 trm_check_eeprom(struct trm_softc *sc, struct trm_nvram *eeprom) 2418 { 2419 struct nvram_target *target; 2420 uint16_t *ep; 2421 uint16_t chksum; 2422 int i; 2423 2424 DPRINTF(("trm_check_eeprom......\n")); 2425 trm_eeprom_read_all(sc, eeprom); 2426 ep = (uint16_t *)eeprom; 2427 chksum = 0; 2428 for (i = 0; i < 64; i++) 2429 chksum += le16toh(*ep++); 2430 2431 if (chksum != TRM_NVRAM_CKSUM) { 2432 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2433 /* 2434 * Checksum error, load default 2435 */ 2436 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2437 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2438 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2439 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2440 eeprom->subclass = 0x00; 2441 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2442 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2443 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2444 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2445 eeprom->reserved0 = 0x00; 2446 2447 for (i = 0, target = eeprom->target; 2448 i < TRM_MAX_TARGETS; 2449 i++, target++) { 2450 target->config0 = 0x77; 2451 target->period = 0x00; 2452 target->config2 = 0x00; 2453 target->config3 = 0x00; 2454 } 2455 2456 eeprom->scsi_id = 7; 2457 eeprom->channel_cfg = 0x0F; 2458 eeprom->delay_time = 0; 2459 eeprom->max_tag = 4; 2460 eeprom->reserved1 = 0x15; 2461 eeprom->boot_target = 0; 2462 eeprom->boot_lun = 0; 2463 eeprom->reserved2 = 0; 2464 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2465 2466 chksum = 0; 2467 ep = (uint16_t *)eeprom; 2468 for (i = 0; i < 63; i++) 2469 chksum += le16toh(*ep++); 2470 2471 chksum = TRM_NVRAM_CKSUM - chksum; 2472 eeprom->checksum0 = chksum & 0xFF; 2473 eeprom->checksum1 = chksum >> 8; 2474 2475 trm_eeprom_write_all(sc, eeprom); 2476 } 2477 } 2478 2479 /* 2480 * write struct eeprom 128 bytes to seeprom 2481 */ 2482 static void 2483 trm_eeprom_write_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2484 { 2485 bus_space_tag_t iot = sc->sc_iot; 2486 bus_space_handle_t ioh = sc->sc_ioh; 2487 uint8_t *sbuf = (uint8_t *)eeprom; 2488 uint8_t addr; 2489 2490 /* Enable SEEPROM */ 2491 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2492 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2493 2494 /* 2495 * Write enable 2496 */ 2497 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2498 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2499 trm_eeprom_wait(); 2500 2501 for (addr = 0; addr < 128; addr++, sbuf++) 2502 trm_eeprom_set_data(sc, addr, *sbuf); 2503 2504 /* 2505 * Write disable 2506 */ 2507 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2508 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2509 trm_eeprom_wait(); 2510 2511 /* Disable SEEPROM */ 2512 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2513 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2514 } 2515 2516 /* 2517 * write one byte to seeprom 2518 */ 2519 static void 2520 trm_eeprom_set_data(struct trm_softc *sc, uint8_t addr, uint8_t data) 2521 { 2522 bus_space_tag_t iot = sc->sc_iot; 2523 bus_space_handle_t ioh = sc->sc_ioh; 2524 int i; 2525 uint8_t send; 2526 2527 /* 2528 * Send write command & address 2529 */ 2530 trm_eeprom_write_cmd(sc, 0x05, addr); 2531 /* 2532 * Write data 2533 */ 2534 for (i = 0; i < 8; i++, data <<= 1) { 2535 send = NVR_SELECT; 2536 if (data & 0x80) /* Start from bit 7 */ 2537 send |= NVR_BITOUT; 2538 2539 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2540 trm_eeprom_wait(); 2541 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2542 trm_eeprom_wait(); 2543 } 2544 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2545 trm_eeprom_wait(); 2546 /* 2547 * Disable chip select 2548 */ 2549 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2550 trm_eeprom_wait(); 2551 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2552 trm_eeprom_wait(); 2553 /* 2554 * Wait for write ready 2555 */ 2556 for (;;) { 2557 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2558 NVR_SELECT | NVR_CLOCK); 2559 trm_eeprom_wait(); 2560 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2561 trm_eeprom_wait(); 2562 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2563 break; 2564 } 2565 /* 2566 * Disable chip select 2567 */ 2568 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2569 } 2570 2571 /* 2572 * read seeprom 128 bytes to struct eeprom 2573 */ 2574 static void 2575 trm_eeprom_read_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2576 { 2577 bus_space_tag_t iot = sc->sc_iot; 2578 bus_space_handle_t ioh = sc->sc_ioh; 2579 uint8_t *sbuf = (uint8_t *)eeprom; 2580 uint8_t addr; 2581 2582 /* 2583 * Enable SEEPROM 2584 */ 2585 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2586 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2587 2588 for (addr = 0; addr < 128; addr++) 2589 *sbuf++ = trm_eeprom_get_data(sc, addr); 2590 2591 /* 2592 * Disable SEEPROM 2593 */ 2594 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2595 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2596 } 2597 2598 /* 2599 * read one byte from seeprom 2600 */ 2601 static uint8_t 2602 trm_eeprom_get_data(struct trm_softc *sc, uint8_t addr) 2603 { 2604 bus_space_tag_t iot = sc->sc_iot; 2605 bus_space_handle_t ioh = sc->sc_ioh; 2606 int i; 2607 uint8_t read, data = 0; 2608 2609 /* 2610 * Send read command & address 2611 */ 2612 trm_eeprom_write_cmd(sc, 0x06, addr); 2613 2614 for (i = 0; i < 8; i++) { /* Read data */ 2615 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2616 NVR_SELECT | NVR_CLOCK); 2617 trm_eeprom_wait(); 2618 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2619 /* 2620 * Get data bit while falling edge 2621 */ 2622 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2623 data <<= 1; 2624 if (read & NVR_BITIN) 2625 data |= 1; 2626 2627 trm_eeprom_wait(); 2628 } 2629 /* 2630 * Disable chip select 2631 */ 2632 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2633 return data; 2634 } 2635 2636 /* 2637 * write SB and Op Code into seeprom 2638 */ 2639 static void 2640 trm_eeprom_write_cmd(struct trm_softc *sc, uint8_t cmd, uint8_t addr) 2641 { 2642 bus_space_tag_t iot = sc->sc_iot; 2643 bus_space_handle_t ioh = sc->sc_ioh; 2644 int i; 2645 uint8_t send; 2646 2647 /* Program SB+OP code */ 2648 for (i = 0; i < 3; i++, cmd <<= 1) { 2649 send = NVR_SELECT; 2650 if (cmd & 0x04) /* Start from bit 2 */ 2651 send |= NVR_BITOUT; 2652 2653 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2654 trm_eeprom_wait(); 2655 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2656 trm_eeprom_wait(); 2657 } 2658 2659 /* Program address */ 2660 for (i = 0; i < 7; i++, addr <<= 1) { 2661 send = NVR_SELECT; 2662 if (addr & 0x40) /* Start from bit 6 */ 2663 send |= NVR_BITOUT; 2664 2665 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2666 trm_eeprom_wait(); 2667 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2668 trm_eeprom_wait(); 2669 } 2670 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2671 trm_eeprom_wait(); 2672 } 2673
Indexes created Tue Sep 23 07:09:52 GMT 2025