trm.c revision 1.6.2.2
1 /* $NetBSD: trm.c,v 1.6.2.2 2002/01/10 19:57:07 thorpej Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2001 Rui-Xiang Guo 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 /* 33 * Ported from 34 * dc395x_trm.c 35 * 36 * Written for NetBSD 1.4.x by 37 * Erich Chen (erich (at) tekram.com.tw) 38 * 39 * Provided by 40 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.6.2.2 2002/01/10 19:57:07 thorpej Exp $"); 45 46 /* #define TRM_DEBUG */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/malloc.h> 51 #include <sys/buf.h> 52 #include <sys/kernel.h> 53 #include <sys/device.h> 54 55 #include <machine/bus.h> 56 #include <machine/intr.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <dev/scsipi/scsi_all.h> 61 #include <dev/scsipi/scsi_message.h> 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsiconf.h> 64 65 #include <dev/pci/pcidevs.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/trmreg.h> 69 70 /* 71 * feature of chip set MAX value 72 */ 73 #define TRM_MAX_TARGETS 16 74 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 75 #define TRM_MAX_SRB 32 76 77 /* 78 * Segment Entry 79 */ 80 struct trm_sg_entry { 81 u_int32_t address; 82 u_int32_t length; 83 }; 84 85 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 86 87 /* 88 ********************************************************************** 89 * The SEEPROM structure for TRM_S1040 90 ********************************************************************** 91 */ 92 struct nvram_target { 93 u_int8_t config0; /* Target configuration byte 0 */ 94 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 95 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tag queuing */ 96 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 97 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 98 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 99 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 100 u_int8_t period; /* Target period */ 101 u_int8_t config2; /* Target configuration byte 2 */ 102 u_int8_t config3; /* Target configuration byte 3 */ 103 }; 104 105 struct trm_nvram { 106 u_int8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 107 u_int8_t subsys_id[2]; /* 2,3 Sub System ID */ 108 u_int8_t subclass; /* 4 Sub Class */ 109 u_int8_t vendor_id[2]; /* 5,6 Vendor ID */ 110 u_int8_t device_id[2]; /* 7,8 Device ID */ 111 u_int8_t reserved0; /* 9 Reserved */ 112 struct nvram_target target[TRM_MAX_TARGETS]; 113 /* 10,11,12,13 114 * 14,15,16,17 115 * .... 116 * 70,71,72,73 */ 117 u_int8_t scsi_id; /* 74 Host Adapter SCSI ID */ 118 u_int8_t channel_cfg; /* 75 Channel configuration */ 119 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 120 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 121 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 122 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 123 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 124 u_int8_t delay_time; /* 76 Power on delay time */ 125 u_int8_t max_tag; /* 77 Maximum tags */ 126 u_int8_t reserved1; /* 78 */ 127 u_int8_t boot_target; /* 79 */ 128 u_int8_t boot_lun; /* 80 */ 129 u_int8_t reserved2; /* 81 */ 130 u_int8_t reserved3[44]; /* 82,..125 */ 131 u_int8_t checksum0; /* 126 */ 132 u_int8_t checksum1; /* 127 */ 133 #define TRM_NVRAM_CKSUM 0x1234 134 }; 135 136 /* Nvram Initiater bits definition */ 137 #define MORE2_DRV 0x00000001 138 #define GREATER_1G 0x00000002 139 #define RST_SCSI_BUS 0x00000004 140 #define ACTIVE_NEGATION 0x00000008 141 #define NO_SEEK 0x00000010 142 #define LUN_CHECK 0x00000020 143 144 #define trm_wait_30us() DELAY(30) 145 146 /* 147 *----------------------------------------------------------------------- 148 * SCSI Request Block 149 *----------------------------------------------------------------------- 150 */ 151 struct trm_srb { 152 struct trm_srb *next; 153 struct trm_dcb *dcb; 154 155 struct trm_sg_entry *sgentry; 156 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 157 bus_dmamap_t dmap; 158 bus_size_t sgoffset; /* Xfer buf offset */ 159 160 u_int32_t buflen; /* Total xfer length */ 161 u_int32_t sgaddr; /* SGList physical starting address */ 162 163 u_int state; /* SRB State */ 164 #define SRB_FREE 0x0000 165 #define SRB_WAIT 0x0001 166 #define SRB_READY 0x0002 167 #define SRB_MSGOUT 0x0004 /* arbitration+msg_out 1st byte */ 168 #define SRB_MSGIN 0x0008 169 #define SRB_EXTEND_MSGIN 0x0010 170 #define SRB_COMMAND 0x0020 171 #define SRB_START_ 0x0040 /* arbitration+msg_out+command_out */ 172 #define SRB_DISCONNECT 0x0080 173 #define SRB_DATA_XFER 0x0100 174 #define SRB_XFERPAD 0x0200 175 #define SRB_STATUS 0x0400 176 #define SRB_COMPLETED 0x0800 177 #define SRB_ABORT_SENT 0x1000 178 #define SRB_DO_SYNC_NEGO 0x2000 179 #define SRB_DO_WIDE_NEGO 0x4000 180 #define SRB_UNEXPECT_RESEL 0x8000 181 u_int8_t *msg; 182 183 int sgcnt; 184 int sgindex; 185 186 int phase; /* SCSI phase */ 187 int hastat; /* Host Adapter Status */ 188 #define H_STATUS_GOOD 0x00 189 #define H_SEL_TIMEOUT 0x11 190 #define H_OVER_UNDER_RUN 0x12 191 #define H_UNEXP_BUS_FREE 0x13 192 #define H_TARGET_PHASE_F 0x14 193 #define H_INVALID_CCB_OP 0x16 194 #define H_LINK_CCB_BAD 0x17 195 #define H_BAD_TARGET_DIR 0x18 196 #define H_DUPLICATE_CCB 0x19 197 #define H_BAD_CCB_OR_SG 0x1A 198 #define H_ABORT 0xFF 199 int tastat; /* Target SCSI Status Byte */ 200 int flag; /* SRBFlag */ 201 #define DATAOUT 0x0080 202 #define DATAIN 0x0040 203 #define RESIDUAL_VALID 0x0020 204 #define ENABLE_TIMER 0x0010 205 #define RESET_DEV0 0x0004 206 #define ABORT_DEV 0x0002 207 #define AUTO_REQSENSE 0x0001 208 int srbstat; /* SRB Status */ 209 #define SRB_OK 0x01 210 #define ABORTION 0x02 211 #define OVER_RUN 0x04 212 #define UNDER_RUN 0x08 213 #define PARITY_ERROR 0x10 214 #define SRB_ERROR 0x20 215 int tagnum; /* Tag number */ 216 int msgcnt; 217 218 int cmdlen; /* SCSI command length */ 219 u_int8_t cmd[12]; /* SCSI command */ 220 221 u_int8_t msgin[6]; 222 u_int8_t msgout[6]; 223 }; 224 225 /* 226 *----------------------------------------------------------------------- 227 * Device Control Block 228 *----------------------------------------------------------------------- 229 */ 230 struct trm_dcb { 231 struct trm_dcb *next; 232 233 struct trm_srb *waitsrb; 234 struct trm_srb *last_waitsrb; 235 236 struct trm_srb *gosrb; 237 struct trm_srb *last_gosrb; 238 239 struct trm_srb *actsrb; 240 241 int gosrb_cnt; 242 u_int maxcmd; /* Max command */ 243 244 int id; /* SCSI Target ID (SCSI Only) */ 245 int lun; /* SCSI Log. Unit (SCSI Only) */ 246 247 u_int8_t tagmask; /* Tag mask */ 248 249 u_int8_t tacfg; /* Target Config */ 250 u_int8_t idmsg; /* Identify Msg */ 251 u_int8_t period; /* Max Period for nego. */ 252 253 u_int8_t synctl; /* Sync control for reg. */ 254 u_int8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 255 u_int8_t mode; /* Sync mode ? (1 sync):(0 async) */ 256 #define SYNC_NEGO_ENABLE 0x01 257 #define SYNC_NEGO_DONE 0x02 258 #define WIDE_NEGO_ENABLE 0x04 259 #define WIDE_NEGO_DONE 0x08 260 #define EN_TAG_QUEUING 0x10 261 #define EN_ATN_STOP 0x20 262 #define SYNC_NEGO_OFFSET 15 263 u_int8_t flag; 264 #define ABORT_DEV_ 0x01 265 #define SHOW_MESSAGE_ 0x02 266 }; 267 268 /* 269 *----------------------------------------------------------------------- 270 * Adapter Control Block 271 *----------------------------------------------------------------------- 272 */ 273 struct trm_softc { 274 struct device sc_dev; 275 276 bus_space_tag_t sc_iot; 277 bus_space_handle_t sc_ioh; 278 bus_dma_tag_t sc_dmat; 279 bus_dmamap_t sc_dmamap; /* Map the control structures */ 280 281 struct trm_dcb *sc_linkdcb; 282 struct trm_dcb *sc_roundcb; 283 284 struct trm_dcb *sc_actdcb; 285 struct trm_dcb *sc_dcb[TRM_MAX_TARGETS][8]; 286 287 struct trm_srb *sc_freesrb; 288 struct trm_srb *sc_srb; /* SRB array */ 289 struct trm_srb sc_tempsrb; 290 291 struct trm_sg_entry *sc_sglist; 292 293 int maxid; 294 int maxtag; /* Max Tag number */ 295 /* 296 * Link to the generic SCSI driver 297 */ 298 struct scsipi_channel sc_channel; 299 struct scsipi_adapter sc_adapter; 300 301 int sc_id; /* Adapter SCSI Target ID */ 302 303 int devcnt; /* Device Count */ 304 305 int devflag[TRM_MAX_TARGETS][8]; /* flag of initDCB for device */ 306 307 int devscan[TRM_MAX_TARGETS][8]; 308 int devscan_end; 309 int cur_offset; /* Current Sync offset */ 310 311 struct trm_nvram sc_eeprom; 312 int sc_config; 313 #define HCC_WIDE_CARD 0x20 314 #define HCC_SCSI_RESET 0x10 315 #define HCC_PARITY 0x08 316 #define HCC_AUTOTERM 0x04 317 #define HCC_LOW8TERM 0x02 318 #define HCC_UP8TERM 0x01 319 int sc_flag; 320 #define RESET_DEV 0x01 321 #define RESET_DETECT 0x02 322 #define RESET_DONE 0x04 323 }; 324 325 /* 326 * SCSI Status codes not defined in scsi_all.h 327 */ 328 #define SCSI_COND_MET 0x04 /* Condition Met */ 329 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 330 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpect Bus Free */ 331 #define SCSI_BUS_RST_DETECT 0xFE /* Scsi Bus Reset detected */ 332 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Time out */ 333 334 static void trm_rewait_srb(struct trm_dcb *, struct trm_srb *); 335 static void trm_wait_srb(struct trm_softc *); 336 static void trm_reset_device(struct trm_softc *); 337 static void trm_recover_srb(struct trm_softc *); 338 static int trm_start_scsi(struct trm_softc *, struct trm_dcb *, 339 struct trm_srb *); 340 static int trm_intr(void *); 341 342 static void trm_dataout_phase0(struct trm_softc *, struct trm_srb *, int *); 343 static void trm_datain_phase0(struct trm_softc *, struct trm_srb *, int *); 344 static void trm_command_phase0(struct trm_softc *, struct trm_srb *, int *); 345 static void trm_status_phase0(struct trm_softc *, struct trm_srb *, int *); 346 static void trm_msgout_phase0(struct trm_softc *, struct trm_srb *, int *); 347 static void trm_msgin_phase0(struct trm_softc *, struct trm_srb *, int *); 348 static void trm_dataout_phase1(struct trm_softc *, struct trm_srb *, int *); 349 static void trm_datain_phase1(struct trm_softc *, struct trm_srb *, int *); 350 static void trm_command_phase1(struct trm_softc *, struct trm_srb *, int *); 351 static void trm_status_phase1(struct trm_softc *, struct trm_srb *, int *); 352 static void trm_msgout_phase1(struct trm_softc *, struct trm_srb *, int *); 353 static void trm_msgin_phase1(struct trm_softc *, struct trm_srb *, int *); 354 static void trm_nop0(struct trm_softc *, struct trm_srb *, int *); 355 static void trm_nop1(struct trm_softc *, struct trm_srb *, int *); 356 357 static void trm_set_xfer_rate(struct trm_softc *, struct trm_srb *, 358 struct trm_dcb *); 359 static void trm_dataio_xfer(struct trm_softc *, struct trm_srb *, int); 360 static void trm_disconnect(struct trm_softc *); 361 static void trm_reselect(struct trm_softc *); 362 static void trm_srb_done(struct trm_softc *, struct trm_dcb *, 363 struct trm_srb *); 364 static void trm_doing_srb_done(struct trm_softc *); 365 static void trm_scsi_reset_detect(struct trm_softc *); 366 static void trm_reset_scsi_bus(struct trm_softc *); 367 static int trm_request_sense(struct trm_softc *, struct trm_dcb *, 368 struct trm_srb *); 369 static void trm_msgout_abort(struct trm_softc *, struct trm_srb *); 370 static void trm_timeout(void *); 371 static void trm_reset(struct trm_softc *); 372 static void trm_send_srb(struct scsipi_xfer *, struct trm_softc *, 373 struct trm_srb *); 374 static int trm_init(struct trm_softc *); 375 static void trm_init_adapter(struct trm_softc *); 376 static void trm_init_dcb(struct trm_softc *, struct trm_dcb *, 377 struct scsipi_xfer *); 378 static void trm_link_srb(struct trm_softc *); 379 static void trm_init_sc(struct trm_softc *); 380 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 381 static void trm_release_srb(struct trm_softc *, struct trm_dcb *, 382 struct trm_srb *); 383 void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, void *); 384 385 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 386 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 387 static void trm_eeprom_set_data(struct trm_softc *, u_int8_t, u_int8_t); 388 static void trm_eeprom_write_cmd(struct trm_softc *, u_int8_t, u_int8_t); 389 static u_int8_t trm_eeprom_get_data(struct trm_softc *, u_int8_t); 390 391 static int trm_probe(struct device *, struct cfdata *, void *); 392 static void trm_attach(struct device *, struct device *, void *); 393 394 struct cfattach trm_ca = { 395 sizeof(struct trm_softc), trm_probe, trm_attach 396 }; 397 398 399 /* 400 * state_v = (void *) trm_scsi_phase0[phase] 401 */ 402 static void *trm_scsi_phase0[] = { 403 trm_dataout_phase0, /* phase:0 */ 404 trm_datain_phase0, /* phase:1 */ 405 trm_command_phase0, /* phase:2 */ 406 trm_status_phase0, /* phase:3 */ 407 trm_nop0, /* phase:4 */ 408 trm_nop1, /* phase:5 */ 409 trm_msgout_phase0, /* phase:6 */ 410 trm_msgin_phase0, /* phase:7 */ 411 }; 412 413 /* 414 * state_v = (void *) trm_scsi_phase1[phase] 415 */ 416 static void *trm_scsi_phase1[] = { 417 trm_dataout_phase1, /* phase:0 */ 418 trm_datain_phase1, /* phase:1 */ 419 trm_command_phase1, /* phase:2 */ 420 trm_status_phase1, /* phase:3 */ 421 trm_nop0, /* phase:4 */ 422 trm_nop1, /* phase:5 */ 423 trm_msgout_phase1, /* phase:6 */ 424 trm_msgin_phase1, /* phase:7 */ 425 }; 426 427 /* real period: */ 428 static const u_int8_t trm_clock_period[] = { 429 12, /* 48 ns 20.0 MB/sec */ 430 18, /* 72 ns 13.3 MB/sec */ 431 25, /* 100 ns 10.0 MB/sec */ 432 31, /* 124 ns 8.0 MB/sec */ 433 37, /* 148 ns 6.6 MB/sec */ 434 43, /* 172 ns 5.7 MB/sec */ 435 50, /* 200 ns 5.0 MB/sec */ 436 62 /* 248 ns 4.0 MB/sec */ 437 }; 438 439 /* 440 * Q back to pending Q 441 */ 442 static void 443 trm_rewait_srb(dcb, srb) 444 struct trm_dcb *dcb; 445 struct trm_srb *srb; 446 { 447 struct trm_srb *psrb1; 448 int s; 449 450 s = splbio(); 451 452 dcb->gosrb_cnt--; 453 psrb1 = dcb->gosrb; 454 if (srb == psrb1) 455 dcb->gosrb = psrb1->next; 456 else { 457 while (srb != psrb1->next) 458 psrb1 = psrb1->next; 459 460 psrb1->next = srb->next; 461 if (srb == dcb->last_gosrb) 462 dcb->last_gosrb = psrb1; 463 } 464 if (dcb->waitsrb) { 465 srb->next = dcb->waitsrb; 466 dcb->waitsrb = srb; 467 } else { 468 srb->next = NULL; 469 dcb->waitsrb = srb; 470 dcb->last_waitsrb = srb; 471 } 472 dcb->tagmask &= ~(1 << srb->tagnum); /* Free TAG number */ 473 474 splx(s); 475 } 476 477 static void 478 trm_wait_srb(sc) 479 struct trm_softc *sc; 480 { 481 struct trm_dcb *ptr, *ptr1; 482 struct trm_srb *srb; 483 int s; 484 485 s = splbio(); 486 487 if (sc->sc_actdcb == NULL && 488 (sc->sc_flag & (RESET_DETECT | RESET_DONE | RESET_DEV)) == 0) { 489 ptr = sc->sc_roundcb; 490 if (ptr == NULL) { 491 ptr = sc->sc_linkdcb; 492 sc->sc_roundcb = ptr; 493 } 494 for (ptr1 = ptr; ptr1 != NULL;) { 495 sc->sc_roundcb = ptr1->next; 496 if (ptr1->maxcmd <= ptr1->gosrb_cnt || 497 (srb = ptr1->waitsrb) == NULL) { 498 if (sc->sc_roundcb == ptr) 499 break; 500 ptr1 = ptr1->next; 501 } else { 502 if (trm_start_scsi(sc, ptr1, srb) == 0) { 503 /* 504 * If trm_start_scsi return 0 : 505 * current interrupt status is 506 * interrupt enable. It's said that 507 * SCSI processor is unoccupied 508 */ 509 ptr1->gosrb_cnt++; 510 if (ptr1->last_waitsrb == srb) { 511 ptr1->waitsrb = NULL; 512 ptr1->last_waitsrb = NULL; 513 } else 514 ptr1->waitsrb = srb->next; 515 516 srb->next = NULL; 517 if (ptr1->gosrb != NULL) 518 ptr1->last_gosrb->next = srb; 519 else 520 ptr1->gosrb = srb; 521 522 ptr1->last_gosrb = srb; 523 } 524 break; 525 } 526 } 527 } 528 splx(s); 529 } 530 531 static void 532 trm_send_srb(xs, sc, srb) 533 struct scsipi_xfer *xs; 534 struct trm_softc *sc; 535 struct trm_srb *srb; 536 { 537 struct trm_dcb *dcb; 538 int s; 539 540 #ifdef TRM_DEBUG 541 printf("trm_send_srb..........\n"); 542 #endif 543 s = splbio(); 544 545 /* 546 * now get the DCB from upper layer( OS ) 547 */ 548 dcb = srb->dcb; 549 550 if (dcb->maxcmd <= dcb->gosrb_cnt || 551 sc->sc_actdcb != NULL || 552 (sc->sc_flag & (RESET_DETECT | RESET_DONE | RESET_DEV))) { 553 if (dcb->waitsrb != NULL) { 554 dcb->last_waitsrb->next = srb; 555 dcb->last_waitsrb = srb; 556 srb->next = NULL; 557 } else { 558 dcb->waitsrb = srb; 559 dcb->last_waitsrb = srb; 560 } 561 splx(s); 562 return; 563 } 564 if (dcb->waitsrb != NULL) { 565 dcb->last_waitsrb->next = srb; 566 dcb->last_waitsrb = srb; 567 srb->next = NULL; 568 /* srb = GetWaitingSRB(dcb); */ 569 srb = dcb->waitsrb; 570 dcb->waitsrb = srb->next; 571 srb->next = NULL; 572 } 573 if (trm_start_scsi(sc, dcb, srb) == 0) { 574 /* 575 * If trm_start_scsi return 0: current interrupt status 576 * is interrupt enable. It's said that SCSI processor is 577 * unoccupied. 578 */ 579 dcb->gosrb_cnt++; /* stack waiting SRB */ 580 if (dcb->gosrb != NULL) { 581 dcb->last_gosrb->next = srb; 582 dcb->last_gosrb = srb; 583 } else { 584 dcb->gosrb = srb; 585 dcb->last_gosrb = srb; 586 } 587 } else { 588 /* 589 * If trm_start_scsi return 1: current interrupt status 590 * is interrupt disreenable. It's said that SCSI processor 591 * has more one SRB need to do we need reQ back SRB. 592 */ 593 if (dcb->waitsrb != NULL) { 594 srb->next = dcb->waitsrb; 595 dcb->waitsrb = srb; 596 } else { 597 srb->next = NULL; 598 dcb->waitsrb = srb; 599 dcb->last_waitsrb = srb; 600 } 601 } 602 603 splx(s); 604 } 605 606 /* 607 * Called by GENERIC SCSI driver 608 * enqueues a SCSI command 609 */ 610 void 611 trm_scsipi_request(chan, req, arg) 612 struct scsipi_channel *chan; 613 scsipi_adapter_req_t req; 614 void *arg; 615 { 616 bus_space_tag_t iot; 617 bus_space_handle_t ioh; 618 struct trm_softc *sc; 619 struct trm_dcb *dcb = NULL; 620 struct trm_srb *srb; 621 struct scsipi_xfer *xs; 622 int error, i, id, lun, s; 623 624 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 625 iot = sc->sc_iot; 626 ioh = sc->sc_ioh; 627 628 switch (req) { 629 case ADAPTER_REQ_RUN_XFER: 630 xs = arg; 631 id = xs->xs_periph->periph_target; 632 lun = xs->xs_periph->periph_lun; 633 #ifdef TRM_DEBUG 634 printf("trm_scsipi_request.....\n"); 635 printf("%s: id= %d lun= %d\n", sc->sc_dev.dv_xname, id, lun); 636 printf("sc->devscan[id][lun]= %d\n", sc->devscan[id][lun]); 637 #endif 638 if ((id > sc->maxid) || (lun > 7)) { 639 xs->error = XS_DRIVER_STUFFUP; 640 return; 641 } 642 dcb = sc->sc_dcb[id][lun]; 643 if (sc->devscan[id][lun] != 0 && sc->devflag[id][lun] == 0) { 644 /* 645 * Scan SCSI BUS => trm_init_dcb 646 */ 647 if (sc->devcnt < TRM_MAX_TARGETS) { 648 #ifdef TRM_DEBUG 649 printf("trm_init_dcb: dcb=%8x, ", (int) dcb); 650 printf("ID=%2x, LUN=%2x\n", id, lun); 651 #endif 652 sc->devflag[id][lun] = 1; 653 trm_init_dcb(sc, dcb, xs); 654 } else { 655 printf("%s: ", sc->sc_dev.dv_xname); 656 printf("sc->devcnt >= TRM_MAX_TARGETS\n"); 657 xs->error = XS_DRIVER_STUFFUP; 658 return; 659 } 660 } 661 662 if (xs->xs_control & XS_CTL_RESET) { 663 trm_reset(sc); 664 xs->error = XS_NOERROR | XS_RESET; 665 return; 666 } 667 if (xs->xs_status & XS_STS_DONE) { 668 printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 669 xs->xs_status &= ~XS_STS_DONE; 670 } 671 xs->error = 0; 672 xs->status = 0; 673 xs->resid = 0; 674 675 s = splbio(); 676 677 /* Get SRB */ 678 srb = sc->sc_freesrb; 679 if (srb != NULL) { 680 sc->sc_freesrb = srb->next; 681 srb->next = NULL; 682 #ifdef TRM_DEBUG 683 printf("srb = %8p sc->sc_freesrb= %8p\n", 684 srb, sc->sc_freesrb); 685 #endif 686 } else { 687 xs->error = XS_RESOURCE_SHORTAGE; 688 scsipi_done(xs); 689 splx(s); 690 return; 691 } 692 /* 693 * XXX BuildSRB(srb ,dcb); XXX 694 */ 695 srb->dcb = dcb; 696 srb->xs = xs; 697 srb->cmdlen = xs->cmdlen; 698 /* 699 * Move layer of CAM command block to layer of SCSI 700 * Request Block for SCSI processor command doing. 701 */ 702 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 703 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 704 #ifdef TRM_DEBUG 705 printf("xs->datalen...\n"); 706 printf("sc->sc_dmat=%x\n", (int) sc->sc_dmat); 707 printf("srb->dmap=%x\n", (int) srb->dmap); 708 printf("xs->data=%x\n", (int) xs->data); 709 printf("xs->datalen=%x\n", (int) xs->datalen); 710 #endif 711 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 712 xs->data, xs->datalen, NULL, 713 ((xs->xs_control & XS_CTL_NOSLEEP) ? 714 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 715 BUS_DMA_STREAMING | 716 ((xs->xs_control & XS_CTL_DATA_IN) ? 717 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 718 printf("%s: DMA transfer map unable to load, " 719 "error = %d\n", sc->sc_dev.dv_xname, error); 720 xs->error = XS_DRIVER_STUFFUP; 721 /* 722 * free SRB 723 */ 724 srb->next = sc->sc_freesrb; 725 sc->sc_freesrb = srb; 726 splx(s); 727 return; 728 } 729 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 730 srb->dmap->dm_mapsize, 731 (xs->xs_control & XS_CTL_DATA_IN) ? 732 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 733 734 /* Set up the scatter gather list */ 735 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 736 srb->sgentry[i].address = 737 htole32(srb->dmap->dm_segs[i].ds_addr); 738 srb->sgentry[i].length = 739 htole32(srb->dmap->dm_segs[i].ds_len); 740 } 741 srb->buflen = xs->datalen; 742 srb->sgcnt = srb->dmap->dm_nsegs; 743 } else { 744 srb->sgentry[0].address = 0; 745 srb->sgentry[0].length = 0; 746 srb->buflen = 0; 747 srb->sgcnt = 0; 748 } 749 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 750 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 751 752 srb->sgindex = 0; 753 srb->hastat = 0; 754 srb->tastat = 0; 755 srb->msgcnt = 0; 756 srb->srbstat = 0; 757 srb->flag = 0; 758 srb->state = 0; 759 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 760 761 trm_send_srb(xs, sc, srb); 762 splx(s); 763 764 if ((xs->xs_control & XS_CTL_POLL) == 0) { 765 int timeout = xs->timeout; 766 timeout = (timeout > 100000) ? 767 timeout / 1000 * hz : timeout * hz / 1000; 768 callout_reset(&xs->xs_callout, timeout, 769 trm_timeout, srb); 770 } else { 771 s = splbio(); 772 do { 773 while (--xs->timeout) { 774 DELAY(1000); 775 if (bus_space_read_2(iot, ioh, 776 TRM_SCSI_STATUS) & SCSIINTERRUPT) 777 break; 778 } 779 if (xs->timeout == 0) { 780 trm_timeout(srb); 781 break; 782 } else 783 trm_intr(sc); 784 } while ((xs->xs_status & XS_STS_DONE) == 0); 785 splx(s); 786 } 787 return; 788 789 case ADAPTER_REQ_GROW_RESOURCES: 790 /* XXX Not supported. */ 791 return; 792 793 case ADAPTER_REQ_SET_XFER_MODE: 794 /* XXX XXX XXX */ 795 return; 796 } 797 } 798 799 static void 800 trm_reset_device(sc) 801 struct trm_softc *sc; 802 { 803 struct trm_dcb *dcb, *pdcb; 804 struct trm_nvram *eeprom; 805 int index; 806 807 dcb = sc->sc_linkdcb; 808 if (dcb == NULL) 809 return; 810 811 pdcb = dcb; 812 do { 813 dcb->mode &= ~(SYNC_NEGO_DONE | WIDE_NEGO_DONE); 814 dcb->synctl = 0; 815 dcb->offset = 0; 816 eeprom = &sc->sc_eeprom; 817 dcb->tacfg = eeprom->target[dcb->id].config0; 818 index = eeprom->target[dcb->id].period & 0x07; 819 dcb->period = trm_clock_period[index]; 820 if ((dcb->tacfg & NTC_DO_WIDE_NEGO) && 821 (sc->sc_config & HCC_WIDE_CARD)) 822 dcb->mode |= WIDE_NEGO_ENABLE; 823 824 dcb = dcb->next; 825 } 826 while (pdcb != dcb); 827 } 828 829 static void 830 trm_recover_srb(sc) 831 struct trm_softc *sc; 832 { 833 struct trm_dcb *dcb, *pdcb; 834 struct trm_srb *psrb, *psrb2; 835 int i; 836 837 dcb = sc->sc_linkdcb; 838 if (dcb == NULL) 839 return; 840 841 pdcb = dcb; 842 do { 843 psrb = pdcb->gosrb; 844 for (i = 0; i < pdcb->gosrb_cnt; i++) { 845 psrb2 = psrb; 846 psrb = psrb->next; 847 if (pdcb->waitsrb) { 848 psrb2->next = pdcb->waitsrb; 849 pdcb->waitsrb = psrb2; 850 } else { 851 pdcb->waitsrb = psrb2; 852 pdcb->last_waitsrb = psrb2; 853 psrb2->next = NULL; 854 } 855 } 856 pdcb->gosrb_cnt = 0; 857 pdcb->gosrb = NULL; 858 pdcb->tagmask = 0; 859 pdcb = pdcb->next; 860 } 861 while (pdcb != dcb); 862 } 863 864 /* 865 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 866 */ 867 static void 868 trm_reset(sc) 869 struct trm_softc *sc; 870 { 871 bus_space_tag_t iot = sc->sc_iot; 872 bus_space_handle_t ioh = sc->sc_ioh; 873 int s; 874 875 #ifdef TRM_DEBUG 876 printf("%s: SCSI RESET.........", sc->sc_dev.dv_xname); 877 #endif 878 s = splbio(); 879 880 /* disable SCSI and DMA interrupt */ 881 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 882 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 883 884 trm_reset_scsi_bus(sc); 885 DELAY(500000); 886 887 /* Enable SCSI interrupt */ 888 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 889 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 890 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 891 892 /* Enable DMA interrupt */ 893 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 894 895 /* Clear DMA FIFO */ 896 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 897 898 /* Clear SCSI FIFO */ 899 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 900 901 trm_reset_device(sc); 902 trm_doing_srb_done(sc); 903 sc->sc_actdcb = NULL; 904 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 905 trm_wait_srb(sc); 906 907 splx(s); 908 } 909 910 static void 911 trm_timeout(arg) 912 void *arg; 913 { 914 struct trm_srb *srb = (struct trm_srb *)arg; 915 struct scsipi_xfer *xs = srb->xs; 916 struct scsipi_periph *periph = xs->xs_periph; 917 struct trm_softc *sc; 918 int s; 919 920 if (xs == NULL) 921 printf("trm_timeout called with xs == NULL\n"); 922 923 else { 924 scsipi_printaddr(xs->xs_periph); 925 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 926 } 927 928 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 929 930 s = splbio(); 931 trm_reset_scsi_bus(sc); 932 callout_stop(&xs->xs_callout); 933 splx(s); 934 } 935 936 static int 937 trm_start_scsi(sc, dcb, srb) 938 struct trm_softc *sc; 939 struct trm_dcb *dcb; 940 struct trm_srb *srb; 941 { 942 bus_space_tag_t iot = sc->sc_iot; 943 bus_space_handle_t ioh = sc->sc_ioh; 944 int tagnum; 945 u_int32_t tagmask; 946 u_int8_t scsicmd, idmsg; 947 948 srb->tagnum = 31; 949 950 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 951 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, dcb->id); 952 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, dcb->synctl); 953 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, dcb->offset); 954 srb->phase = PH_BUS_FREE; /* initial phase */ 955 /* Flush FIFO */ 956 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 957 958 idmsg = dcb->idmsg; 959 960 if ((srb->cmd[0] == INQUIRY) || 961 (srb->cmd[0] == REQUEST_SENSE)) { 962 if (((dcb->mode & WIDE_NEGO_ENABLE) && 963 (dcb->mode & WIDE_NEGO_DONE) == 0) || 964 ((dcb->mode & SYNC_NEGO_ENABLE) && 965 (dcb->mode & SYNC_NEGO_DONE) == 0)) { 966 if ((dcb->idmsg & 7) == 0 || srb->cmd[0] != INQUIRY) { 967 scsicmd = SCMD_SEL_ATNSTOP; 968 srb->state = SRB_MSGOUT; 969 goto polling; 970 } 971 } 972 /* Send identify message */ 973 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 974 idmsg & ~MSG_IDENTIFY_DISCFLAG); 975 scsicmd = SCMD_SEL_ATN; 976 srb->state = SRB_START_; 977 } else { /* not inquiry,request sense,auto request sense */ 978 /* Send identify message */ 979 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, idmsg); 980 DELAY(30); 981 scsicmd = SCMD_SEL_ATN; 982 srb->state = SRB_START_; 983 if (dcb->mode & EN_TAG_QUEUING) { 984 /* Send Tag message, get tag id */ 985 tagmask = 1; 986 tagnum = 0; 987 while (tagmask & dcb->tagmask) { 988 tagmask = tagmask << 1; 989 tagnum++; 990 } 991 /* Send Tag id */ 992 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 993 MSG_SIMPLE_Q_TAG); 994 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, tagnum); 995 996 dcb->tagmask |= tagmask; 997 srb->tagnum = tagnum; 998 999 scsicmd = SCMD_SEL_ATN3; 1000 srb->state = SRB_START_; 1001 } 1002 } 1003 polling: 1004 /* 1005 * Send CDB ..command block... 1006 */ 1007 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1008 1009 if (bus_space_read_2(iot, ioh, TRM_SCSI_STATUS) & SCSIINTERRUPT) { 1010 /* 1011 * If trm_start_scsi return 1: current interrupt status 1012 * is interrupt disreenable. It's said that SCSI processor 1013 * has more one SRB need to do, SCSI processor has been 1014 * occupied by one SRB. 1015 */ 1016 srb->state = SRB_READY; 1017 dcb->tagmask &= ~(1 << srb->tagnum); 1018 return (1); 1019 } else { 1020 /* 1021 * If trm_start_scsi return 0: current interrupt status 1022 * is interrupt enable. It's said that SCSI processor is 1023 * unoccupied. 1024 */ 1025 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1026 sc->sc_actdcb = dcb; 1027 dcb->actsrb = srb; 1028 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1029 DO_DATALATCH | DO_HWRESELECT); 1030 /* it's important for atn stop */ 1031 /* 1032 * SCSI command 1033 */ 1034 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1035 return (0); 1036 } 1037 } 1038 1039 /* 1040 * Catch an interrupt from the adapter 1041 * Process pending device interrupts. 1042 */ 1043 static int 1044 trm_intr(vsc) 1045 void *vsc; 1046 { 1047 bus_space_tag_t iot; 1048 bus_space_handle_t ioh; 1049 struct trm_softc *sc; 1050 struct trm_dcb *dcb; 1051 struct trm_srb *srb; 1052 void (*state_v) (struct trm_softc *, struct trm_srb *, int *); 1053 int phase, intstat, stat = 0; 1054 1055 #ifdef TRM_DEBUG 1056 printf("trm_intr......\n"); 1057 #endif 1058 sc = (struct trm_softc *)vsc; 1059 iot = sc->sc_iot; 1060 ioh = sc->sc_ioh; 1061 1062 if (sc == NULL) 1063 return (0); 1064 1065 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1066 if ((stat & SCSIINTERRUPT) == 0) 1067 return (0); 1068 1069 #ifdef TRM_DEBUG 1070 printf("stat=%2x,", stat); 1071 #endif 1072 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1073 1074 #ifdef TRM_DEBUG 1075 printf("intstat=%2x,", intstat); 1076 #endif 1077 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1078 trm_disconnect(sc); 1079 return (1); 1080 } 1081 if (intstat & INT_RESELECTED) { 1082 trm_reselect(sc); 1083 return (1); 1084 } 1085 if (intstat & INT_SCSIRESET) { 1086 trm_scsi_reset_detect(sc); 1087 return (1); 1088 } 1089 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1090 dcb = sc->sc_actdcb; 1091 srb = dcb->actsrb; 1092 if (dcb != NULL) 1093 if (dcb->flag & ABORT_DEV_) { 1094 srb->msgout[0] = MSG_ABORT; 1095 trm_msgout_abort(sc, srb); 1096 } 1097 /* 1098 * software sequential machine 1099 */ 1100 phase = srb->phase; /* phase: */ 1101 1102 /* 1103 * 62037 or 62137 call trm_scsi_phase0[]... "phase 1104 * entry" handle every phase before start transfer 1105 */ 1106 state_v = (void *)trm_scsi_phase0[phase]; 1107 state_v(sc, srb, &stat); 1108 1109 /* 1110 * if there were any exception occured 1111 * stat will be modify to bus free phase new 1112 * stat transfer out from ... prvious state_v 1113 * 1114 */ 1115 /* phase:0,1,2,3,4,5,6,7 */ 1116 srb->phase = stat & PHASEMASK; 1117 phase = stat & PHASEMASK; 1118 1119 /* 1120 * call trm_scsi_phase1[]... "phase entry" handle every 1121 * phase do transfer 1122 */ 1123 state_v = (void *)trm_scsi_phase1[phase]; 1124 state_v(sc, srb, &stat); 1125 return (1); 1126 } 1127 return (0); 1128 } 1129 1130 static void 1131 trm_msgout_phase0(sc, srb, pstat) 1132 struct trm_softc *sc; 1133 struct trm_srb *srb; 1134 int *pstat; 1135 { 1136 1137 if (srb->state & (SRB_UNEXPECT_RESEL | SRB_ABORT_SENT)) 1138 *pstat = PH_BUS_FREE; /* .. initial phase */ 1139 } 1140 1141 static void 1142 trm_msgout_phase1(sc, srb, pstat) 1143 struct trm_softc *sc; 1144 struct trm_srb *srb; 1145 int *pstat; 1146 { 1147 bus_space_tag_t iot = sc->sc_iot; 1148 bus_space_handle_t ioh = sc->sc_ioh; 1149 struct trm_dcb *dcb; 1150 1151 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1152 dcb = sc->sc_actdcb; 1153 if ((srb->state & SRB_MSGOUT) == 0) { 1154 if (srb->msgcnt > 0) { 1155 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1156 srb->msgout, srb->msgcnt); 1157 srb->msgcnt = 0; 1158 if ((dcb->flag & ABORT_DEV_) && 1159 (srb->msgout[0] == MSG_ABORT)) 1160 srb->state = SRB_ABORT_SENT; 1161 } else { 1162 if ((srb->cmd[0] == INQUIRY) || 1163 (srb->cmd[0] == REQUEST_SENSE)) 1164 if (dcb->mode & SYNC_NEGO_ENABLE) 1165 goto mop1; 1166 1167 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, MSG_ABORT); 1168 } 1169 } else { 1170 mop1: /* message out phase */ 1171 if ((srb->state & SRB_DO_WIDE_NEGO) == 0 && 1172 (dcb->mode & WIDE_NEGO_ENABLE)) { 1173 /* 1174 * WIDE DATA TRANSFER REQUEST code (03h) 1175 */ 1176 dcb->mode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1177 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1178 dcb->idmsg & ~MSG_IDENTIFY_DISCFLAG); 1179 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1180 MSG_EXTENDED); /* (01h) */ 1181 1182 /* Message length (02h) */ 1183 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1184 MSG_EXT_WDTR_LEN); 1185 1186 /* wide data xfer (03h) */ 1187 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1188 MSG_EXT_WDTR); 1189 1190 /* width: 0(8bit), 1(16bit) ,2(32bit) */ 1191 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1192 MSG_EXT_WDTR_BUS_16_BIT); 1193 1194 srb->state |= SRB_DO_WIDE_NEGO; 1195 } else if ((srb->state & SRB_DO_SYNC_NEGO) == 0 && 1196 (dcb->mode & SYNC_NEGO_ENABLE)) { 1197 /* 1198 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1199 */ 1200 if ((dcb->mode & WIDE_NEGO_DONE) == 0) 1201 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1202 dcb->idmsg & ~MSG_IDENTIFY_DISCFLAG); 1203 1204 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1205 MSG_EXTENDED); /* (01h) */ 1206 1207 /* Message length (03h) */ 1208 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1209 MSG_EXT_SDTR_LEN); 1210 1211 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1212 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1213 MSG_EXT_SDTR); 1214 1215 /* Transfer peeriod factor */ 1216 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, dcb->period); 1217 1218 /* REQ/ACK offset */ 1219 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1220 SYNC_NEGO_OFFSET); 1221 srb->state |= SRB_DO_SYNC_NEGO; 1222 } 1223 } 1224 /* it's important for atn stop */ 1225 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1226 1227 /* 1228 * SCSI cammand 1229 */ 1230 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1231 } 1232 1233 static void 1234 trm_command_phase0(sc, srb, pstat) 1235 struct trm_softc *sc; 1236 struct trm_srb *srb; 1237 int *pstat; 1238 { 1239 1240 } 1241 1242 static void 1243 trm_command_phase1(sc, srb, pstat) 1244 struct trm_softc *sc; 1245 struct trm_srb *srb; 1246 int *pstat; 1247 { 1248 bus_space_tag_t iot = sc->sc_iot; 1249 bus_space_handle_t ioh = sc->sc_ioh; 1250 1251 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1252 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1253 1254 srb->state = SRB_COMMAND; 1255 /* it's important for atn stop */ 1256 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1257 1258 /* 1259 * SCSI cammand 1260 */ 1261 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1262 } 1263 1264 static void 1265 trm_dataout_phase0(sc, srb, pstat) 1266 struct trm_softc *sc; 1267 struct trm_srb *srb; 1268 int *pstat; 1269 { 1270 bus_space_tag_t iot = sc->sc_iot; 1271 bus_space_handle_t ioh = sc->sc_ioh; 1272 struct trm_dcb *dcb; 1273 struct trm_sg_entry *sg; 1274 int sgindex; 1275 u_int32_t xferlen, leftcnt = 0; 1276 1277 dcb = srb->dcb; 1278 1279 if ((srb->state & SRB_XFERPAD) == 0) { 1280 if (*pstat & PARITYERROR) 1281 srb->srbstat |= PARITY_ERROR; 1282 1283 if ((*pstat & SCSIXFERDONE) == 0) { 1284 /* 1285 * when data transfer from DMA FIFO to SCSI FIFO 1286 * if there was some data left in SCSI FIFO 1287 */ 1288 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1289 SCSI_FIFOCNT_MASK; 1290 if (dcb->synctl & WIDE_SYNC) 1291 /* 1292 * if WIDE scsi SCSI FIFOCNT unit is word 1293 * so need to * 2 1294 */ 1295 leftcnt <<= 1; 1296 } 1297 /* 1298 * caculate all the residue data that not yet tranfered 1299 * SCSI transfer counter + left in SCSI FIFO data 1300 * 1301 * .....TRM_SCSI_XCNT (24bits) 1302 * The counter always decrement by one for every SCSI 1303 * byte transfer. 1304 * .....TRM_SCSI_FIFOCNT ( 5bits) 1305 * The counter is SCSI FIFO offset counter 1306 */ 1307 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1308 if (leftcnt == 1) { 1309 leftcnt = 0; 1310 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1311 DO_CLRFIFO); 1312 } 1313 if ((leftcnt == 0) || (*pstat & SCSIXFERCNT_2_ZERO)) { 1314 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1315 DMAXFERCOMP) == 0) 1316 ; 1317 1318 srb->buflen = 0; 1319 } else { /* Update SG list */ 1320 /* 1321 * if transfer not yet complete 1322 * there were some data residue in SCSI FIFO or 1323 * SCSI transfer counter not empty 1324 */ 1325 if (srb->buflen != leftcnt) { 1326 /* data that had transferred length */ 1327 xferlen = srb->buflen - leftcnt; 1328 1329 /* next time to be transferred length */ 1330 srb->buflen = leftcnt; 1331 1332 /* 1333 * parsing from last time disconnect sgindex 1334 */ 1335 sg = srb->sgentry + srb->sgindex; 1336 for (sgindex = srb->sgindex; 1337 sgindex < srb->sgcnt; 1338 sgindex++, sg++) { 1339 /* 1340 * find last time which SG transfer 1341 * be disconnect 1342 */ 1343 if (xferlen >= le32toh(sg->length)) 1344 xferlen -= le32toh(sg->length); 1345 else { 1346 /* 1347 * update last time 1348 * disconnected SG list 1349 */ 1350 /* residue data length */ 1351 sg->length = htole32( 1352 le32toh(sg->length) 1353 - xferlen); 1354 /* residue data pointer */ 1355 sg->address = htole32( 1356 le32toh(sg->address) 1357 + xferlen); 1358 srb->sgindex = sgindex; 1359 break; 1360 } 1361 } 1362 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1363 srb->sgoffset, TRM_SG_SIZE, 1364 BUS_DMASYNC_PREWRITE); 1365 } 1366 } 1367 } 1368 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1369 } 1370 1371 static void 1372 trm_dataout_phase1(sc, srb, pstat) 1373 struct trm_softc *sc; 1374 struct trm_srb *srb; 1375 int *pstat; 1376 { 1377 1378 /* 1379 * do prepare befor transfer when data out phase 1380 */ 1381 trm_dataio_xfer(sc, srb, XFERDATAOUT); 1382 } 1383 1384 static void 1385 trm_datain_phase0(sc, srb, pstat) 1386 struct trm_softc *sc; 1387 struct trm_srb *srb; 1388 int *pstat; 1389 { 1390 bus_space_tag_t iot = sc->sc_iot; 1391 bus_space_handle_t ioh = sc->sc_ioh; 1392 struct trm_sg_entry *sg; 1393 int sgindex; 1394 u_int32_t xferlen, leftcnt = 0; 1395 1396 if ((srb->state & SRB_XFERPAD) == 0) { 1397 if (*pstat & PARITYERROR) 1398 srb->srbstat |= PARITY_ERROR; 1399 1400 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1401 if ((leftcnt == 0) || (*pstat & SCSIXFERCNT_2_ZERO)) { 1402 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1403 DMAXFERCOMP) == 0) 1404 ; 1405 1406 srb->buflen = 0; 1407 } else { /* phase changed */ 1408 /* 1409 * parsing the case: 1410 * when a transfer not yet complete 1411 * but be disconnected by uper layer 1412 * if transfer not yet complete 1413 * there were some data residue in SCSI FIFO or 1414 * SCSI transfer counter not empty 1415 */ 1416 if (srb->buflen != leftcnt) { 1417 /* 1418 * data that had transferred length 1419 */ 1420 xferlen = srb->buflen - leftcnt; 1421 1422 /* 1423 * next time to be transferred length 1424 */ 1425 srb->buflen = leftcnt; 1426 1427 /* 1428 * parsing from last time disconnect sgindex 1429 */ 1430 sg = srb->sgentry + srb->sgindex; 1431 for (sgindex = srb->sgindex; 1432 sgindex < srb->sgcnt; 1433 sgindex++, sg++) { 1434 /* 1435 * find last time which SG transfer 1436 * be disconnect 1437 */ 1438 if (xferlen >= le32toh(sg->length)) 1439 xferlen -= le32toh(sg->length); 1440 else { 1441 /* 1442 * update last time 1443 * disconnected SG list 1444 */ 1445 /* residue data length */ 1446 sg->length = htole32( 1447 le32toh(sg->length) 1448 - xferlen); 1449 /* residue data pointer */ 1450 sg->address = htole32( 1451 le32toh(sg->address) 1452 + xferlen); 1453 srb->sgindex = sgindex; 1454 break; 1455 } 1456 } 1457 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1458 srb->sgoffset, TRM_SG_SIZE, 1459 BUS_DMASYNC_PREWRITE); 1460 } 1461 } 1462 } 1463 } 1464 1465 static void 1466 trm_datain_phase1(sc, srb, pstat) 1467 struct trm_softc *sc; 1468 struct trm_srb *srb; 1469 int *pstat; 1470 { 1471 1472 /* 1473 * do prepare befor transfer when data in phase 1474 */ 1475 trm_dataio_xfer(sc, srb, XFERDATAIN); 1476 } 1477 1478 static void 1479 trm_dataio_xfer(sc, srb, iodir) 1480 struct trm_softc *sc; 1481 struct trm_srb *srb; 1482 int iodir; 1483 { 1484 bus_space_tag_t iot = sc->sc_iot; 1485 bus_space_handle_t ioh = sc->sc_ioh; 1486 struct trm_dcb *dcb = srb->dcb; 1487 1488 if (srb->sgindex < srb->sgcnt) { 1489 if (srb->buflen > 0) { 1490 /* 1491 * load what physical address of Scatter/Gather 1492 * list table want to be transfer 1493 */ 1494 srb->state = SRB_DATA_XFER; 1495 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1496 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1497 srb->sgaddr + 1498 srb->sgindex * sizeof(struct trm_sg_entry)); 1499 /* 1500 * load how many bytes in the Scatter/Gather list table 1501 */ 1502 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1503 (srb->sgcnt - srb->sgindex) 1504 * sizeof(struct trm_sg_entry)); 1505 /* 1506 * load total xfer length (24bits) max value 16Mbyte 1507 */ 1508 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1509 /* Start DMA transfer */ 1510 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1511 iodir | SGXFER); 1512 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1513 STARTDMAXFER); 1514 1515 /* Start SCSI transfer */ 1516 /* it's important for atn stop */ 1517 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1518 DO_DATALATCH); 1519 1520 /* 1521 * SCSI cammand 1522 */ 1523 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1524 (iodir == XFERDATAOUT) ? 1525 SCMD_DMA_OUT : SCMD_DMA_IN); 1526 } else { /* xfer pad */ 1527 if (srb->sgcnt) { 1528 srb->hastat = H_OVER_UNDER_RUN; 1529 srb->srbstat |= OVER_RUN; 1530 } 1531 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1532 (dcb->synctl & WIDE_SYNC) ? 2 : 1); 1533 1534 if (iodir == XFERDATAOUT) 1535 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1536 else 1537 bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1538 1539 srb->state |= SRB_XFERPAD; 1540 /* it's important for atn stop */ 1541 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1542 DO_DATALATCH); 1543 1544 /* 1545 * SCSI cammand 1546 */ 1547 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1548 (iodir == XFERDATAOUT) ? 1549 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1550 } 1551 } 1552 } 1553 1554 static void 1555 trm_status_phase0(sc, srb, pstat) 1556 struct trm_softc *sc; 1557 struct trm_srb *srb; 1558 int *pstat; 1559 { 1560 bus_space_tag_t iot = sc->sc_iot; 1561 bus_space_handle_t ioh = sc->sc_ioh; 1562 1563 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1564 srb->state = SRB_COMPLETED; 1565 *pstat = PH_BUS_FREE; /* .. initial phase */ 1566 /* it's important for atn stop */ 1567 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1568 1569 /* 1570 * SCSI cammand 1571 */ 1572 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1573 } 1574 1575 static void 1576 trm_status_phase1(sc, srb, pstat) 1577 struct trm_softc *sc; 1578 struct trm_srb *srb; 1579 int *pstat; 1580 { 1581 bus_space_tag_t iot = sc->sc_iot; 1582 bus_space_handle_t ioh = sc->sc_ioh; 1583 1584 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1585 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1586 & SCSI_FIFO_EMPTY) == 0) 1587 bus_space_write_2(iot, ioh, 1588 TRM_SCSI_CONTROL, DO_CLRFIFO); 1589 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1590 & DMA_FIFO_EMPTY) == 0) 1591 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1592 } else { 1593 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1594 & DMA_FIFO_EMPTY) == 0) 1595 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1596 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1597 & SCSI_FIFO_EMPTY) == 0) 1598 bus_space_write_2(iot, ioh, 1599 TRM_SCSI_CONTROL, DO_CLRFIFO); 1600 } 1601 srb->state = SRB_STATUS; 1602 /* it's important for atn stop */ 1603 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1604 1605 /* 1606 * SCSI cammand 1607 */ 1608 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1609 } 1610 1611 static void 1612 trm_msgin_phase0(sc, srb, pstat) 1613 struct trm_softc *sc; 1614 struct trm_srb *srb; 1615 int *pstat; 1616 { 1617 bus_space_tag_t iot = sc->sc_iot; 1618 bus_space_handle_t ioh = sc->sc_ioh; 1619 struct trm_dcb *dcb = sc->sc_actdcb; 1620 struct trm_srb *tempsrb; 1621 int syncxfer, tagid, index; 1622 u_int8_t msgin_code; 1623 1624 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1625 if ((srb->state & SRB_EXTEND_MSGIN) == 0) { 1626 if (msgin_code == MSG_DISCONNECT) { 1627 srb->state = SRB_DISCONNECT; 1628 goto min6; 1629 } else if (msgin_code == MSG_SAVEDATAPOINTER) { 1630 goto min6; 1631 } else if ((msgin_code == MSG_EXTENDED) || 1632 ((msgin_code >= MSG_SIMPLE_Q_TAG) && 1633 (msgin_code <= MSG_ORDERED_Q_TAG))) { 1634 srb->state |= SRB_EXTEND_MSGIN; 1635 /* extended message (01h) */ 1636 srb->msgin[0] = msgin_code; 1637 1638 srb->msgcnt = 1; 1639 /* extended message length (n) */ 1640 srb->msg = &srb->msgin[1]; 1641 1642 goto min6; 1643 } else if (msgin_code == MSG_MESSAGE_REJECT) { 1644 /* Reject message */ 1645 /* do wide nego reject */ 1646 if (dcb->mode & WIDE_NEGO_ENABLE) { 1647 dcb = srb->dcb; 1648 dcb->mode |= WIDE_NEGO_DONE; 1649 dcb->mode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP | 1650 WIDE_NEGO_ENABLE); 1651 srb->state &= ~(SRB_DO_WIDE_NEGO | SRB_MSGIN); 1652 if ((dcb->mode & SYNC_NEGO_ENABLE) && 1653 (dcb->mode & SYNC_NEGO_DONE) == 0) { 1654 /* Set ATN, in case ATN was clear */ 1655 srb->state |= SRB_MSGOUT; 1656 bus_space_write_2(iot, ioh, 1657 TRM_SCSI_CONTROL, DO_SETATN); 1658 } else 1659 /* Clear ATN */ 1660 bus_space_write_2(iot, ioh, 1661 TRM_SCSI_CONTROL, DO_CLRATN); 1662 } else if (dcb->mode & SYNC_NEGO_ENABLE) { 1663 /* do sync nego reject */ 1664 bus_space_write_2(iot, ioh, 1665 TRM_SCSI_CONTROL, DO_CLRATN); 1666 if (srb->state & SRB_DO_SYNC_NEGO) { 1667 dcb = srb->dcb; 1668 dcb->mode &= ~(SYNC_NEGO_ENABLE | 1669 SYNC_NEGO_DONE); 1670 dcb->synctl = 0; 1671 dcb->offset = 0; 1672 goto re_prog; 1673 } 1674 } 1675 goto min6; 1676 } else if (msgin_code == MSG_IGN_WIDE_RESIDUE) { 1677 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1678 bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1679 goto min6; 1680 } else { 1681 /* 1682 * Restore data pointer message 1683 * Save data pointer message 1684 * Completion message 1685 * NOP message 1686 */ 1687 goto min6; 1688 } 1689 } else { 1690 /* 1691 * when extend message in:srb->state = SRB_EXTEND_MSGIN 1692 * Parsing incomming extented messages 1693 */ 1694 *srb->msg = msgin_code; 1695 srb->msgcnt++; 1696 srb->msg++; 1697 #ifdef TRM_DEBUG 1698 printf("srb->msgin[0]=%2x\n", srb->msgin[0]); 1699 printf("srb->msgin[1]=%2x\n", srb->msgin[1]); 1700 printf("srb->msgin[2]=%2x\n", srb->msgin[2]); 1701 printf("srb->msgin[3]=%2x\n", srb->msgin[3]); 1702 printf("srb->msgin[4]=%2x\n", srb->msgin[4]); 1703 #endif 1704 if ((srb->msgin[0] >= MSG_SIMPLE_Q_TAG) && 1705 (srb->msgin[0] <= MSG_ORDERED_Q_TAG)) { 1706 /* 1707 * is QUEUE tag message : 1708 * 1709 * byte 0: 1710 * HEAD QUEUE TAG (20h) 1711 * ORDERED QUEUE TAG (21h) 1712 * SIMPLE QUEUE TAG (22h) 1713 * byte 1: 1714 * Queue tag (00h - FFh) 1715 */ 1716 if (srb->msgcnt == 2) { 1717 srb->state = 0; 1718 tagid = srb->msgin[1]; 1719 srb = dcb->gosrb; 1720 tempsrb = dcb->last_gosrb; 1721 if (srb) { 1722 for (;;) { 1723 if (srb->tagnum != tagid) { 1724 if (srb == tempsrb) 1725 goto mingx0; 1726 1727 srb = srb->next; 1728 } else 1729 break; 1730 } 1731 if (dcb->flag & ABORT_DEV_) { 1732 srb->state = SRB_ABORT_SENT; 1733 srb->msgout[0] = MSG_ABORT; 1734 trm_msgout_abort(sc, srb); 1735 } 1736 if ((srb->state & SRB_DISCONNECT) == 0) 1737 goto mingx0; 1738 1739 dcb->actsrb = srb; 1740 srb->state = SRB_DATA_XFER; 1741 } else { 1742 mingx0: 1743 srb = &sc->sc_tempsrb; 1744 srb->state = SRB_UNEXPECT_RESEL; 1745 dcb->actsrb = srb; 1746 srb->msgout[0] = MSG_ABORT_TAG; 1747 trm_msgout_abort(sc, srb); 1748 } 1749 } 1750 } else if ((srb->msgin[0] == MSG_EXTENDED) && 1751 (srb->msgin[2] == MSG_EXT_WDTR) && 1752 (srb->msgcnt == 4)) { 1753 /* 1754 * is Wide data xfer Extended message : 1755 * ====================================== 1756 * WIDE DATA TRANSFER REQUEST 1757 * ====================================== 1758 * byte 0 : Extended message (01h) 1759 * byte 1 : Extended message length (02h) 1760 * byte 2 : WIDE DATA TRANSFER code (03h) 1761 * byte 3 : Transfer width exponent 1762 */ 1763 dcb = srb->dcb; 1764 srb->state &= ~(SRB_EXTEND_MSGIN | SRB_DO_WIDE_NEGO); 1765 if ((srb->msgin[1] != MSG_EXT_WDTR_LEN)) { 1766 /* Length is wrong, reject it */ 1767 dcb->mode &= 1768 ~(WIDE_NEGO_ENABLE | WIDE_NEGO_DONE); 1769 srb->msgcnt = 1; 1770 srb->msgin[0] = MSG_MESSAGE_REJECT; 1771 bus_space_write_2(iot, ioh, 1772 TRM_SCSI_CONTROL, DO_SETATN); 1773 goto min6; 1774 } 1775 if (dcb->mode & WIDE_NEGO_ENABLE) { 1776 /* Do wide negoniation */ 1777 if (srb->msgin[3] > MSG_EXT_WDTR_BUS_32_BIT) { 1778 /* reject_msg: */ 1779 dcb->mode &= ~(WIDE_NEGO_ENABLE | 1780 WIDE_NEGO_DONE); 1781 srb->msgcnt = 1; 1782 srb->msgin[0] = MSG_MESSAGE_REJECT; 1783 bus_space_write_2(iot, ioh, 1784 TRM_SCSI_CONTROL, DO_SETATN); 1785 goto min6; 1786 } 1787 if (srb->msgin[3] == MSG_EXT_WDTR_BUS_32_BIT) 1788 /* do 16 bits */ 1789 srb->msgin[3] = MSG_EXT_WDTR_BUS_16_BIT; 1790 else { 1791 if ((dcb->mode & WIDE_NEGO_DONE) == 0) { 1792 srb->state &= 1793 ~(SRB_DO_WIDE_NEGO | 1794 SRB_MSGIN); 1795 dcb->mode |= WIDE_NEGO_DONE; 1796 dcb->mode &= 1797 ~(SYNC_NEGO_DONE | 1798 EN_ATN_STOP | 1799 WIDE_NEGO_ENABLE); 1800 if (srb->msgin[3] != 1801 MSG_EXT_WDTR_BUS_8_BIT) 1802 /* is Wide data xfer */ 1803 dcb->synctl |= 1804 WIDE_SYNC; 1805 } 1806 } 1807 } else 1808 srb->msgin[3] = MSG_EXT_WDTR_BUS_8_BIT; 1809 1810 srb->state |= SRB_MSGOUT; 1811 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1812 DO_SETATN); 1813 goto min6; 1814 } else if ((srb->msgin[0] == MSG_EXTENDED) && 1815 (srb->msgin[2] == MSG_EXT_SDTR) && 1816 (srb->msgcnt == 5)) { 1817 /* 1818 * is 8bit transfer Extended message : 1819 * ================================= 1820 * SYNCHRONOUS DATA TRANSFER REQUEST 1821 * ================================= 1822 * byte 0 : Extended message (01h) 1823 * byte 1 : Extended message length (03) 1824 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 1825 * byte 3 : Transfer period factor 1826 * byte 4 : REQ/ACK offset 1827 */ 1828 srb->state &= ~(SRB_EXTEND_MSGIN | SRB_DO_SYNC_NEGO); 1829 if (srb->msgin[1] != MSG_EXT_SDTR_LEN) { 1830 /* reject_msg: */ 1831 srb->msgcnt = 1; 1832 srb->msgin[0] = MSG_MESSAGE_REJECT; 1833 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1834 DO_SETATN); 1835 } else if (srb->msgin[3] == 0 || srb->msgin[4] == 0) { 1836 /* set async */ 1837 dcb = srb->dcb; 1838 /* disable sync & sync nego */ 1839 dcb->mode &= 1840 ~(SYNC_NEGO_ENABLE | SYNC_NEGO_DONE); 1841 dcb->synctl = 0; 1842 dcb->offset = 0; 1843 if (((dcb->flag & SHOW_MESSAGE_) == 0) && 1844 (dcb->lun == 0)) { 1845 printf("%s: target %d, Sync period=0 " 1846 "or Sync offset=0 to be " 1847 "asynchronous transfer\n", 1848 sc->sc_dev.dv_xname, dcb->id); 1849 dcb->flag |= SHOW_MESSAGE_; 1850 } 1851 goto re_prog; 1852 } else { /* set sync */ 1853 dcb = srb->dcb; 1854 dcb->mode |= SYNC_NEGO_ENABLE | SYNC_NEGO_DONE; 1855 1856 /* Transfer period factor */ 1857 dcb->period = srb->msgin[3]; 1858 1859 /* REQ/ACK offset */ 1860 dcb->offset = srb->msgin[4]; 1861 for (index = 0; index < 7; index++) 1862 if (srb->msgin[3] <= 1863 trm_clock_period[index]) 1864 break; 1865 1866 dcb->synctl |= (index | ALT_SYNC); 1867 /* 1868 * show negotiation message 1869 */ 1870 if (((dcb->flag & SHOW_MESSAGE_) == 0) && 1871 (dcb->lun == 0)) { 1872 syncxfer = 100000 / 1873 (trm_clock_period[index] * 4); 1874 if (dcb->synctl & WIDE_SYNC) { 1875 printf("%s: target %d, " 1876 "16bits Wide transfer\n", 1877 sc->sc_dev.dv_xname, 1878 dcb->id); 1879 syncxfer = syncxfer * 2; 1880 } else 1881 printf("%s: target %d, " 1882 "8bits Narrow transfer\n", 1883 sc->sc_dev.dv_xname, 1884 dcb->id); 1885 1886 printf("%s: target %d, " 1887 "Sync transfer %d.%01d MB/sec, " 1888 "Offset %d\n", sc->sc_dev.dv_xname, 1889 dcb->id, syncxfer / 100, 1890 syncxfer % 100, dcb->offset); 1891 dcb->flag |= SHOW_MESSAGE_; 1892 } 1893 re_prog: 1894 /* 1895 * program SCSI control register 1896 */ 1897 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, 1898 dcb->synctl); 1899 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 1900 dcb->offset); 1901 trm_set_xfer_rate(sc, srb, dcb); 1902 } 1903 } 1904 } 1905 min6: 1906 *pstat = PH_BUS_FREE; /* .. initial phase */ 1907 /* it's important for atn stop */ 1908 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1909 1910 /* 1911 * SCSI cammand 1912 */ 1913 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1914 } 1915 1916 static void 1917 trm_msgin_phase1(sc, srb, pstat) 1918 struct trm_softc *sc; 1919 struct trm_srb *srb; 1920 int *pstat; 1921 { 1922 bus_space_tag_t iot = sc->sc_iot; 1923 bus_space_handle_t ioh = sc->sc_ioh; 1924 1925 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1926 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1927 if ((srb->state & SRB_MSGIN) == 0) { 1928 srb->state &= SRB_DISCONNECT; 1929 srb->state |= SRB_MSGIN; 1930 } 1931 /* it's important for atn stop */ 1932 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1933 1934 /* 1935 * SCSI cammand 1936 */ 1937 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1938 } 1939 1940 static void 1941 trm_nop0(sc, srb, pstat) 1942 struct trm_softc *sc; 1943 struct trm_srb *srb; 1944 int *pstat; 1945 { 1946 1947 } 1948 1949 static void 1950 trm_nop1(sc, srb, pstat) 1951 struct trm_softc *sc; 1952 struct trm_srb *srb; 1953 int *pstat; 1954 { 1955 1956 } 1957 1958 static void 1959 trm_set_xfer_rate(sc, srb, dcb) 1960 struct trm_softc *sc; 1961 struct trm_srb *srb; 1962 struct trm_dcb *dcb; 1963 { 1964 struct trm_dcb *tempdcb; 1965 int i; 1966 1967 /* 1968 * set all lun device's (period, offset) 1969 */ 1970 #ifdef TRM_DEBUG 1971 printf("trm_set_xfer_rate............\n"); 1972 #endif 1973 if ((dcb->idmsg & 0x07) == 0) { 1974 if (sc->devscan_end == 0) 1975 sc->cur_offset = dcb->offset; 1976 else { 1977 tempdcb = sc->sc_linkdcb; 1978 for (i = 0; i < sc->devcnt; i++) { 1979 /* 1980 * different LUN but had same target ID 1981 */ 1982 if (tempdcb->id == dcb->id) { 1983 tempdcb->synctl = dcb->synctl; 1984 tempdcb->offset = dcb->offset; 1985 tempdcb->mode = dcb->mode; 1986 } 1987 tempdcb = tempdcb->next; 1988 } 1989 } 1990 } 1991 } 1992 1993 static void 1994 trm_disconnect(sc) 1995 struct trm_softc *sc; 1996 { 1997 bus_space_tag_t iot = sc->sc_iot; 1998 bus_space_handle_t ioh = sc->sc_ioh; 1999 struct trm_dcb *dcb; 2000 struct trm_srb *srb, *psrb; 2001 int i, s; 2002 2003 #ifdef TRM_DEBUG 2004 printf("trm_disconnect...............\n"); 2005 #endif 2006 s = splbio(); 2007 2008 dcb = sc->sc_actdcb; 2009 if (dcb == NULL) { 2010 DELAY(1000); /* 1 msec */ 2011 2012 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2013 DO_CLRFIFO | DO_HWRESELECT); 2014 return; 2015 } 2016 srb = dcb->actsrb; 2017 sc->sc_actdcb = 0; 2018 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2019 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2020 DO_CLRFIFO | DO_HWRESELECT); 2021 DELAY(100); 2022 if (srb->state & SRB_UNEXPECT_RESEL) { 2023 srb->state = 0; 2024 trm_wait_srb(sc); 2025 } else if (srb->state & SRB_ABORT_SENT) { 2026 dcb->tagmask = 0; 2027 dcb->flag &= ~ABORT_DEV_; 2028 srb = dcb->gosrb; 2029 for (i = 0; i < dcb->gosrb_cnt; i++) { 2030 psrb = srb->next; 2031 srb->next = sc->sc_freesrb; 2032 sc->sc_freesrb = srb; 2033 srb = psrb; 2034 } 2035 dcb->gosrb_cnt = 0; 2036 dcb->gosrb = 0; 2037 trm_wait_srb(sc); 2038 } else { 2039 if ((srb->state & (SRB_START_ | SRB_MSGOUT)) || 2040 (srb->state & (SRB_DISCONNECT | SRB_COMPLETED)) == 0) { 2041 /* Selection time out */ 2042 if (sc->devscan_end) { 2043 srb->state = SRB_READY; 2044 trm_rewait_srb(dcb, srb); 2045 } else { 2046 srb->tastat = SCSI_SEL_TIMEOUT; 2047 goto disc1; 2048 } 2049 } else if (srb->state & SRB_DISCONNECT) { 2050 /* 2051 * SRB_DISCONNECT 2052 */ 2053 trm_wait_srb(sc); 2054 } else if (srb->state & SRB_COMPLETED) { 2055 disc1: 2056 /* 2057 * SRB_COMPLETED 2058 */ 2059 if (dcb->maxcmd > 1) { 2060 /* free tag mask */ 2061 dcb->tagmask &= ~(1 << srb->tagnum); 2062 } 2063 dcb->actsrb = 0; 2064 srb->state = SRB_FREE; 2065 trm_srb_done(sc, dcb, srb); 2066 } 2067 } 2068 splx(s); 2069 } 2070 2071 static void 2072 trm_reselect(sc) 2073 struct trm_softc *sc; 2074 { 2075 bus_space_tag_t iot = sc->sc_iot; 2076 bus_space_handle_t ioh = sc->sc_ioh; 2077 struct trm_dcb *dcb; 2078 struct trm_srb *srb; 2079 int id, lun; 2080 2081 #ifdef TRM_DEBUG 2082 printf("trm_reselect.................\n"); 2083 #endif 2084 dcb = sc->sc_actdcb; 2085 if (dcb != NULL) { /* Arbitration lost but Reselection win */ 2086 srb = dcb->actsrb; 2087 srb->state = SRB_READY; 2088 trm_rewait_srb(dcb, srb); 2089 } 2090 /* Read Reselected Target Id and LUN */ 2091 id = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2092 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2093 dcb = sc->sc_linkdcb; 2094 while (id != dcb->id && lun != dcb->lun) 2095 /* get dcb of the reselect id */ 2096 dcb = dcb->next; 2097 2098 sc->sc_actdcb = dcb; 2099 if (dcb->mode & EN_TAG_QUEUING) { 2100 srb = &sc->sc_tempsrb; 2101 dcb->actsrb = srb; 2102 } else { 2103 srb = dcb->actsrb; 2104 if (srb == NULL || (srb->state & SRB_DISCONNECT) == 0) { 2105 /* 2106 * abort command 2107 */ 2108 srb = &sc->sc_tempsrb; 2109 srb->state = SRB_UNEXPECT_RESEL; 2110 dcb->actsrb = srb; 2111 srb->msgout[0] = MSG_ABORT; 2112 trm_msgout_abort(sc, srb); 2113 } else { 2114 if (dcb->flag & ABORT_DEV_) { 2115 srb->state = SRB_ABORT_SENT; 2116 srb->msgout[0] = MSG_ABORT; 2117 trm_msgout_abort(sc, srb); 2118 } else 2119 srb->state = SRB_DATA_XFER; 2120 } 2121 } 2122 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2123 /* 2124 * Program HA ID, target ID, period and offset 2125 */ 2126 /* target ID */ 2127 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, id); 2128 2129 /* host ID */ 2130 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2131 2132 /* period */ 2133 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, dcb->synctl); 2134 2135 /* offset */ 2136 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, dcb->offset); 2137 2138 /* it's important for atn stop */ 2139 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2140 DELAY(30); 2141 /* 2142 * SCSI cammand 2143 */ 2144 /* to rls the /ACK signal */ 2145 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2146 } 2147 2148 /* 2149 * Complete execution of a SCSI command 2150 * Signal completion to the generic SCSI driver 2151 */ 2152 static void 2153 trm_srb_done(sc, dcb, srb) 2154 struct trm_softc *sc; 2155 struct trm_dcb *dcb; 2156 struct trm_srb *srb; 2157 { 2158 struct scsipi_xfer *xs = srb->xs; 2159 struct scsipi_inquiry_data *ptr; 2160 struct trm_dcb *tempdcb; 2161 int i, j, id, lun, s; 2162 u_int8_t bval; 2163 2164 #ifdef TRM_DEBUG 2165 printf("trm_srb_done..................\n"); 2166 #endif 2167 2168 if (xs == NULL) 2169 return; 2170 2171 if ((xs->xs_control & XS_CTL_POLL) == 0) 2172 callout_stop(&xs->xs_callout); 2173 2174 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2175 srb->flag & AUTO_REQSENSE) { 2176 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2177 srb->dmap->dm_mapsize, 2178 ((xs->xs_control & XS_CTL_DATA_IN) || 2179 (srb->flag & AUTO_REQSENSE)) ? 2180 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2181 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2182 } 2183 2184 /* 2185 * target status 2186 */ 2187 xs->status = srb->tastat; 2188 2189 switch (xs->status) { 2190 case SCSI_OK: 2191 /* 2192 * process initiator status...... 2193 * Adapter (initiator) status 2194 */ 2195 if (srb->hastat & H_OVER_UNDER_RUN) { 2196 srb->tastat = 0; 2197 /* Illegal length (over/under run) */ 2198 xs->error = XS_DRIVER_STUFFUP; 2199 } else if (srb->srbstat & PARITY_ERROR) { 2200 #ifdef TRM_DEBUG 2201 printf("%s: driver stuffup at %s %d\n", 2202 sc->sc_dev.dv_xname, __FILE__, __LINE__); 2203 #endif 2204 /* Driver failed to perform operation */ 2205 xs->error = XS_DRIVER_STUFFUP; 2206 } else { 2207 /* No error */ 2208 srb->hastat = 0; 2209 if (srb->flag & AUTO_REQSENSE) { 2210 /* there is no error, (sense is invalid) */ 2211 xs->error = XS_SENSE; 2212 } else { 2213 srb->tastat = 0; 2214 xs->error = XS_NOERROR; 2215 } 2216 } 2217 break; 2218 case SCSI_CHECK: 2219 if ((srb->flag & AUTO_REQSENSE) != 0 || 2220 trm_request_sense(sc, dcb, srb) != 0) { 2221 printf("%s: request sense failed\n", 2222 sc->sc_dev.dv_xname); 2223 xs->error = XS_DRIVER_STUFFUP; 2224 break; 2225 } 2226 xs->error = XS_SENSE; 2227 return; 2228 case SCSI_QUEUE_FULL: 2229 dcb->maxcmd = dcb->gosrb_cnt - 1; 2230 trm_rewait_srb(dcb, srb); 2231 srb->hastat = 0; 2232 srb->tastat = 0; 2233 break; 2234 case SCSI_SEL_TIMEOUT: 2235 srb->hastat = H_SEL_TIMEOUT; 2236 srb->tastat = 0; 2237 xs->error = XS_TIMEOUT; 2238 break; 2239 case SCSI_BUSY: 2240 xs->error = XS_BUSY; 2241 break; 2242 case SCSI_RESV_CONFLICT: 2243 #ifdef TRM_DEBUG 2244 printf("%s: target reserved at ", sc->sc_dev.dv_xname); 2245 printf("%s %d\n", __FILE__, __LINE__); 2246 #endif 2247 xs->error = XS_BUSY; 2248 break; 2249 default: 2250 srb->hastat = 0; 2251 #ifdef TRM_DEBUG 2252 printf("%s: driver stuffup at %s %d\n", 2253 sc->sc_dev.dv_xname, __FILE__, __LINE__); 2254 #endif 2255 xs->error = XS_DRIVER_STUFFUP; 2256 break; 2257 } 2258 2259 id = srb->xs->xs_periph->periph_target; 2260 lun = srb->xs->xs_periph->periph_lun; 2261 if (sc->devscan[id][lun]) { 2262 /* 2263 * if SCSI command in "scan devices" duty 2264 * XXX XXX XXX should not be done here! XXX XXX XXX 2265 */ 2266 if (srb->cmd[0] == INQUIRY) { 2267 /* 2268 * SCSI command phase: inquiry scsi device data 2269 * (type,capacity,manufacture.... 2270 */ 2271 if (xs->error == XS_TIMEOUT) 2272 goto NO_DEV; 2273 2274 ptr = (struct scsipi_inquiry_data *)xs->data; 2275 bval = ptr->device & SID_TYPE; 2276 2277 if (bval == T_NODEVICE) { 2278 NO_DEV: 2279 #ifdef TRM_DEBUG 2280 printf("trm_srb_done NO Device: "); 2281 printf("id= %d ,lun= %d\n", id, lun); 2282 #endif 2283 s = splbio(); 2284 /* 2285 * dcb Q link 2286 * move the head of DCB to temdcb 2287 */ 2288 tempdcb = sc->sc_linkdcb; 2289 2290 /* 2291 * search current DCB for pass link 2292 */ 2293 while (tempdcb->next != dcb) 2294 tempdcb = tempdcb->next; 2295 2296 /* 2297 * when the current DCB been found 2298 * than connect current DCB tail 2299 * to the DCB tail that before current DCB 2300 */ 2301 tempdcb->next = dcb->next; 2302 2303 /* 2304 * if there was only one DCB ,connect his 2305 * tail to his head 2306 */ 2307 if (sc->sc_linkdcb == dcb) 2308 sc->sc_linkdcb = tempdcb->next; 2309 2310 if (sc->sc_roundcb == dcb) 2311 sc->sc_roundcb = tempdcb->next; 2312 2313 /* 2314 * if no device than free this device DCB 2315 * free( dcb, M_DEVBUF); 2316 */ 2317 sc->devcnt--; 2318 #ifdef TRM_DEBUG 2319 printf("sc->devcnt=%d\n", sc->devcnt); 2320 #endif 2321 if (sc->devcnt == 0) { 2322 sc->sc_linkdcb = NULL; 2323 sc->sc_roundcb = NULL; 2324 } 2325 /* no device set scan device flag=0 */ 2326 sc->devscan[id][lun] = 0; 2327 i = 0; 2328 j = 0; 2329 while (i <= sc->maxid) { 2330 while (j < 8) { 2331 if (sc->devscan[i][j] == 1) { 2332 sc->devscan_end = 0; 2333 splx(s); 2334 goto exit; 2335 } else 2336 sc->devscan_end = 1; 2337 2338 j++; 2339 } 2340 j = 0; 2341 i++; 2342 } 2343 splx(s); 2344 } else { 2345 if (bval == T_DIRECT || bval == T_OPTICAL) { 2346 if ((((ptr->version & 0x07) >= 2) || 2347 ((ptr->response_format & 0x0F) 2348 == 2)) && 2349 (ptr->flags3 & SID_CmdQue) && 2350 (dcb->tacfg & NTC_DO_TAG_QUEUING) && 2351 (dcb->tacfg & NTC_DO_DISCONNECT)) { 2352 dcb->maxcmd = sc->maxtag; 2353 dcb->mode |= EN_TAG_QUEUING; 2354 dcb->tagmask = 0; 2355 } else 2356 dcb->mode |= EN_ATN_STOP; 2357 } 2358 } 2359 } 2360 } 2361 exit: 2362 trm_release_srb(sc, dcb, srb); 2363 trm_wait_srb(sc); 2364 xs->xs_status |= XS_STS_DONE; 2365 /* Notify cmd done */ 2366 scsipi_done(xs); 2367 } 2368 2369 static void 2370 trm_release_srb(sc, dcb, srb) 2371 struct trm_softc *sc; 2372 struct trm_dcb *dcb; 2373 struct trm_srb *srb; 2374 { 2375 struct trm_srb *psrb; 2376 int s; 2377 2378 s = splbio(); 2379 if (srb == dcb->gosrb) 2380 dcb->gosrb = srb->next; 2381 else { 2382 psrb = dcb->gosrb; 2383 while (psrb->next != srb) 2384 psrb = psrb->next; 2385 2386 psrb->next = srb->next; 2387 if (srb == dcb->last_gosrb) 2388 dcb->last_gosrb = psrb; 2389 } 2390 srb->next = sc->sc_freesrb; 2391 sc->sc_freesrb = srb; 2392 dcb->gosrb_cnt--; 2393 splx(s); 2394 return; 2395 } 2396 2397 static void 2398 trm_doing_srb_done(sc) 2399 struct trm_softc *sc; 2400 { 2401 struct trm_dcb *dcb, *pdcb; 2402 struct trm_srb *psrb, *psrb2; 2403 struct scsipi_xfer *xs; 2404 int i; 2405 2406 dcb = sc->sc_linkdcb; 2407 if (dcb == NULL) 2408 return; 2409 2410 pdcb = dcb; 2411 do { 2412 psrb = pdcb->gosrb; 2413 for (i = 0; i < pdcb->gosrb_cnt; i++) { 2414 psrb2 = psrb->next; 2415 xs = psrb->xs; 2416 xs->error = XS_TIMEOUT; 2417 /* ReleaseSRB( dcb, srb ); */ 2418 psrb->next = sc->sc_freesrb; 2419 sc->sc_freesrb = psrb; 2420 scsipi_done(xs); 2421 psrb = psrb2; 2422 } 2423 pdcb->gosrb_cnt = 0;; 2424 pdcb->gosrb = NULL; 2425 pdcb->tagmask = 0; 2426 pdcb = pdcb->next; 2427 } 2428 while (pdcb != dcb); 2429 } 2430 2431 static void 2432 trm_reset_scsi_bus(sc) 2433 struct trm_softc *sc; 2434 { 2435 bus_space_tag_t iot = sc->sc_iot; 2436 bus_space_handle_t ioh = sc->sc_ioh; 2437 int s; 2438 2439 s = splbio(); 2440 2441 sc->sc_flag |= RESET_DEV; 2442 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2443 while ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2444 INT_SCSIRESET) == 0) 2445 ; 2446 2447 splx(s); 2448 } 2449 2450 static void 2451 trm_scsi_reset_detect(sc) 2452 struct trm_softc *sc; 2453 { 2454 bus_space_tag_t iot = sc->sc_iot; 2455 bus_space_handle_t ioh = sc->sc_ioh; 2456 int s; 2457 2458 #ifdef TRM_DEBUG 2459 printf("trm_scsi_reset_detect...............\n"); 2460 #endif 2461 DELAY(1000000); /* delay 1 sec */ 2462 2463 s = splbio(); 2464 2465 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2466 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2467 2468 if (sc->sc_flag & RESET_DEV) { 2469 sc->sc_flag |= RESET_DONE; 2470 } else { 2471 sc->sc_flag |= RESET_DETECT; 2472 trm_reset_device(sc); 2473 /* trm_doing_srb_done( sc ); ???? */ 2474 trm_recover_srb(sc); 2475 sc->sc_actdcb = NULL; 2476 sc->sc_flag = 0; 2477 trm_wait_srb(sc); 2478 } 2479 splx(s); 2480 } 2481 2482 static int 2483 trm_request_sense(sc, dcb, srb) 2484 struct trm_softc *sc; 2485 struct trm_dcb *dcb; 2486 struct trm_srb *srb; 2487 { 2488 struct scsipi_xfer *xs = srb->xs; 2489 struct scsipi_sense *ss; 2490 int error, lun = xs->xs_periph->periph_lun; 2491 2492 srb->flag |= AUTO_REQSENSE; 2493 2494 /* Status of initiator/target */ 2495 srb->hastat = 0; 2496 srb->tastat = 0; 2497 2498 ss = (struct scsipi_sense *)srb->cmd; 2499 ss->opcode = REQUEST_SENSE; 2500 ss->byte2 = lun << SCSI_CMD_LUN_SHIFT; 2501 ss->unused[0] = ss->unused[1] = 0; 2502 ss->length = sizeof(struct scsipi_sense_data); 2503 ss->control = 0; 2504 2505 srb->buflen = sizeof(struct scsipi_sense_data); 2506 srb->sgcnt = 1; 2507 srb->sgindex = 0; 2508 srb->cmdlen = sizeof(struct scsipi_sense); 2509 2510 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2511 &xs->sense.scsi_sense, srb->buflen, NULL, 2512 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2513 return error; 2514 } 2515 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2516 srb->buflen, BUS_DMASYNC_PREREAD); 2517 2518 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2519 srb->sgentry[0].length = htole32(sizeof(struct scsipi_sense_data)); 2520 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2521 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2522 2523 if (trm_start_scsi(sc, dcb, srb)) 2524 /* 2525 * If trm_start_scsi return 1: current interrupt status 2526 * is interrupt disreenable. It's said that SCSI processor 2527 * has more one SRB need to do. 2528 */ 2529 trm_rewait_srb(dcb, srb); 2530 return 0; 2531 } 2532 2533 static void 2534 trm_msgout_abort(sc, srb) 2535 struct trm_softc *sc; 2536 struct trm_srb *srb; 2537 { 2538 bus_space_tag_t iot = sc->sc_iot; 2539 bus_space_handle_t ioh = sc->sc_ioh; 2540 2541 srb->msgcnt = 1; 2542 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_SETATN); 2543 srb->dcb->flag &= ~ABORT_DEV_; 2544 } 2545 2546 /* 2547 * initialize the internal structures for a given DCB 2548 */ 2549 static void 2550 trm_init_dcb(sc, dcb, xs) 2551 struct trm_softc *sc; 2552 struct trm_dcb *dcb; 2553 struct scsipi_xfer *xs; 2554 { 2555 struct trm_nvram *eeprom; 2556 struct trm_dcb *tempdcb; 2557 int index, id, lun, s; 2558 2559 id = xs->xs_periph->periph_target; 2560 lun = xs->xs_periph->periph_lun; 2561 2562 s = splbio(); 2563 if (sc->sc_linkdcb == 0) { 2564 sc->sc_linkdcb = dcb; 2565 /* 2566 * RunRobin impersonate the role that let each device had 2567 * good proportion about SCSI command proceeding. 2568 */ 2569 sc->sc_roundcb = dcb; 2570 dcb->next = dcb; 2571 } else { 2572 tempdcb = sc->sc_linkdcb; 2573 /* search the last nod of DCB link */ 2574 while (tempdcb->next != sc->sc_linkdcb) 2575 tempdcb = tempdcb->next; 2576 2577 /* connect current DCB with last DCB tail */ 2578 tempdcb->next = dcb; 2579 /* connect current DCB tail to this DCB Q head */ 2580 dcb->next = sc->sc_linkdcb; 2581 } 2582 splx(s); 2583 2584 sc->devcnt++; 2585 dcb->id = id; 2586 dcb->lun = lun; 2587 dcb->waitsrb = NULL; 2588 dcb->gosrb = NULL; 2589 dcb->gosrb_cnt = 0; 2590 dcb->actsrb = NULL; 2591 dcb->tagmask = 0; 2592 dcb->maxcmd = 1; 2593 dcb->flag = 0; 2594 2595 eeprom = &sc->sc_eeprom; 2596 dcb->tacfg = eeprom->target[id].config0; 2597 /* 2598 * disconnect enable? 2599 */ 2600 dcb->idmsg = MSG_IDENTIFY(lun, dcb->tacfg & NTC_DO_DISCONNECT); 2601 /* 2602 * tag Qing enable? 2603 * wide nego, sync nego enable? 2604 */ 2605 dcb->synctl = 0; 2606 dcb->offset = 0; 2607 index = eeprom->target[id].period & 0x07; 2608 dcb->period = trm_clock_period[index]; 2609 dcb->mode = 0; 2610 if ((dcb->tacfg & NTC_DO_WIDE_NEGO) && (sc->sc_config & HCC_WIDE_CARD)) 2611 /* enable wide nego */ 2612 dcb->mode |= WIDE_NEGO_ENABLE; 2613 2614 if ((dcb->tacfg & NTC_DO_SYNC_NEGO) && (lun == 0 || sc->cur_offset > 0)) 2615 /* enable sync nego */ 2616 dcb->mode |= SYNC_NEGO_ENABLE; 2617 } 2618 2619 static void 2620 trm_link_srb(sc) 2621 struct trm_softc *sc; 2622 { 2623 struct trm_srb *srb; 2624 int i; 2625 2626 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 2627 M_DEVBUF, M_NOWAIT|M_ZERO); 2628 if (sc->sc_srb == NULL) { 2629 printf("%s: can not allocate SRB\n", sc->sc_dev.dv_xname); 2630 return; 2631 } 2632 2633 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++, srb++) { 2634 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 2635 srb->sgoffset = TRM_SG_SIZE * i; 2636 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 2637 /* 2638 * map all SRB space to SRB_array 2639 */ 2640 if (bus_dmamap_create(sc->sc_dmat, 2641 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 2642 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 2643 printf("%s: unable to create DMA transfer map...\n", 2644 sc->sc_dev.dv_xname); 2645 free(sc->sc_srb, M_DEVBUF); 2646 return; 2647 } 2648 if (i != TRM_MAX_SRB - 1) { 2649 /* 2650 * link all SRB 2651 */ 2652 srb->next = srb + 1; 2653 #ifdef TRM_DEBUG 2654 printf("srb->next = %8x ", (int) (srb + 1)); 2655 #endif 2656 } else { 2657 /* 2658 * load NULL to NextSRB of the last SRB 2659 */ 2660 srb->next = NULL; 2661 } 2662 #ifdef TRM_DEBUG 2663 printf("srb = %8x\n", (int) srb); 2664 #endif 2665 } 2666 return; 2667 } 2668 2669 /* 2670 * initialize the internal structures for a given SCSI host 2671 */ 2672 static void 2673 trm_init_sc(sc) 2674 struct trm_softc *sc; 2675 { 2676 bus_space_tag_t iot = sc->sc_iot; 2677 bus_space_handle_t ioh = sc->sc_ioh; 2678 struct trm_nvram *eeprom; 2679 int i, j; 2680 2681 eeprom = &sc->sc_eeprom; 2682 sc->maxid = 7; 2683 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 2684 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 2685 sc->sc_config |= HCC_WIDE_CARD; 2686 sc->maxid = 15; 2687 } 2688 if (eeprom->channel_cfg & NAC_POWERON_SCSI_RESET) 2689 sc->sc_config |= HCC_SCSI_RESET; 2690 2691 sc->sc_linkdcb = NULL; 2692 sc->sc_roundcb = NULL; 2693 sc->sc_actdcb = NULL; 2694 sc->sc_id = eeprom->scsi_id; 2695 sc->devcnt = 0; 2696 sc->maxtag = 2 << eeprom->max_tag; 2697 sc->sc_flag = 0; 2698 sc->devscan_end = 0; 2699 /* 2700 * link all device's SRB Q of this adapter 2701 */ 2702 trm_link_srb(sc); 2703 sc->sc_freesrb = sc->sc_srb; 2704 /* allocate DCB array for scan device */ 2705 for (i = 0; i <= sc->maxid; i++) 2706 if (sc->sc_id != i) 2707 for (j = 0; j < 8; j++) { 2708 sc->devscan[i][j] = 1; 2709 sc->devflag[i][j] = 0; 2710 sc->sc_dcb[i][j] = 2711 malloc(sizeof(struct trm_dcb), 2712 M_DEVBUF, M_WAITOK); 2713 } 2714 2715 #ifdef TRM_DEBUG 2716 printf("sizeof(struct trm_dcb)= %8x\n", sizeof(struct trm_dcb)); 2717 printf("sizeof(struct trm_softc)= %8x\n", sizeof(struct trm_softc)); 2718 printf("sizeof(struct trm_srb)= %8x\n", sizeof(struct trm_srb)); 2719 #endif 2720 sc->sc_adapter.adapt_dev = &sc->sc_dev; 2721 sc->sc_adapter.adapt_nchannels = 1; 2722 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 2723 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 2724 sc->sc_adapter.adapt_request = trm_scsipi_request; 2725 sc->sc_adapter.adapt_minphys = minphys; 2726 2727 sc->sc_channel.chan_adapter = &sc->sc_adapter; 2728 sc->sc_channel.chan_bustype = &scsi_bustype; 2729 sc->sc_channel.chan_channel = 0; 2730 sc->sc_channel.chan_ntargets = sc->maxid + 1; 2731 sc->sc_channel.chan_nluns = 8; 2732 sc->sc_channel.chan_id = sc->sc_id; 2733 } 2734 2735 /* 2736 * write sc_eeprom 128 bytes to seeprom 2737 */ 2738 static void 2739 trm_eeprom_write_all(sc, eeprom) 2740 struct trm_softc *sc; 2741 struct trm_nvram *eeprom; 2742 { 2743 bus_space_tag_t iot = sc->sc_iot; 2744 bus_space_handle_t ioh = sc->sc_ioh; 2745 u_int8_t *buf = (u_int8_t *)eeprom; 2746 u_int8_t addr; 2747 2748 /* Enable SEEPROM */ 2749 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2750 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2751 2752 /* 2753 * Write enable 2754 */ 2755 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2756 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2757 trm_wait_30us(); 2758 2759 for (addr = 0; addr < 128; addr++, buf++) 2760 trm_eeprom_set_data(sc, addr, *buf); 2761 2762 /* 2763 * Write disable 2764 */ 2765 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2766 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2767 trm_wait_30us(); 2768 2769 /* Disable SEEPROM */ 2770 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2771 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2772 } 2773 2774 /* 2775 * write one byte to seeprom 2776 */ 2777 static void 2778 trm_eeprom_set_data(sc, addr, data) 2779 struct trm_softc *sc; 2780 u_int8_t addr; 2781 u_int8_t data; 2782 { 2783 bus_space_tag_t iot = sc->sc_iot; 2784 bus_space_handle_t ioh = sc->sc_ioh; 2785 int i; 2786 u_int8_t send; 2787 2788 /* 2789 * Send write command & address 2790 */ 2791 trm_eeprom_write_cmd(sc, 0x05, addr); 2792 /* 2793 * Write data 2794 */ 2795 for (i = 0; i < 8; i++, data <<= 1) { 2796 send = NVR_SELECT; 2797 if (data & 0x80) /* Start from bit 7 */ 2798 send |= NVR_BITOUT; 2799 2800 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2801 trm_wait_30us(); 2802 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2803 trm_wait_30us(); 2804 } 2805 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2806 trm_wait_30us(); 2807 /* 2808 * Disable chip select 2809 */ 2810 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2811 trm_wait_30us(); 2812 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2813 trm_wait_30us(); 2814 /* 2815 * Wait for write ready 2816 */ 2817 for (;;) { 2818 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2819 NVR_SELECT | NVR_CLOCK); 2820 trm_wait_30us(); 2821 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2822 trm_wait_30us(); 2823 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2824 break; 2825 } 2826 /* 2827 * Disable chip select 2828 */ 2829 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2830 } 2831 2832 /* 2833 * read seeprom 128 bytes to sc_eeprom 2834 */ 2835 static void 2836 trm_eeprom_read_all(sc, eeprom) 2837 struct trm_softc *sc; 2838 struct trm_nvram *eeprom; 2839 { 2840 bus_space_tag_t iot = sc->sc_iot; 2841 bus_space_handle_t ioh = sc->sc_ioh; 2842 u_int8_t *buf = (u_int8_t *)eeprom; 2843 u_int8_t addr; 2844 2845 /* 2846 * Enable SEEPROM 2847 */ 2848 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2849 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2850 2851 for (addr = 0; addr < 128; addr++, buf++) 2852 *buf = trm_eeprom_get_data(sc, addr); 2853 2854 /* 2855 * Disable SEEPROM 2856 */ 2857 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2858 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2859 } 2860 2861 /* 2862 * read one byte from seeprom 2863 */ 2864 static u_int8_t 2865 trm_eeprom_get_data(sc, addr) 2866 struct trm_softc *sc; 2867 u_int8_t addr; 2868 { 2869 bus_space_tag_t iot = sc->sc_iot; 2870 bus_space_handle_t ioh = sc->sc_ioh; 2871 int i; 2872 u_int8_t read, data = 0; 2873 2874 /* 2875 * Send read command & address 2876 */ 2877 trm_eeprom_write_cmd(sc, 0x06, addr); 2878 2879 for (i = 0; i < 8; i++) { /* Read data */ 2880 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2881 NVR_SELECT | NVR_CLOCK); 2882 trm_wait_30us(); 2883 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2884 /* 2885 * Get data bit while falling edge 2886 */ 2887 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2888 data <<= 1; 2889 if (read & NVR_BITIN) 2890 data |= 1; 2891 2892 trm_wait_30us(); 2893 } 2894 /* 2895 * Disable chip select 2896 */ 2897 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2898 return (data); 2899 } 2900 2901 /* 2902 * write SB and Op Code into seeprom 2903 */ 2904 static void 2905 trm_eeprom_write_cmd(sc, cmd, addr) 2906 struct trm_softc *sc; 2907 u_int8_t cmd; 2908 u_int8_t addr; 2909 { 2910 bus_space_tag_t iot = sc->sc_iot; 2911 bus_space_handle_t ioh = sc->sc_ioh; 2912 int i; 2913 u_int8_t send; 2914 2915 /* Program SB+OP code */ 2916 for (i = 0; i < 3; i++, cmd <<= 1) { 2917 send = NVR_SELECT; 2918 if (cmd & 0x04) /* Start from bit 2 */ 2919 send |= NVR_BITOUT; 2920 2921 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2922 trm_wait_30us(); 2923 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2924 trm_wait_30us(); 2925 } 2926 2927 /* Program address */ 2928 for (i = 0; i < 7; i++, addr <<= 1) { 2929 send = NVR_SELECT; 2930 if (addr & 0x40) /* Start from bit 6 */ 2931 send |= NVR_BITOUT; 2932 2933 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2934 trm_wait_30us(); 2935 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2936 trm_wait_30us(); 2937 } 2938 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2939 trm_wait_30us(); 2940 } 2941 2942 /* 2943 * read seeprom 128 bytes to sc_eeprom and check checksum. 2944 * If it is wrong, updated with default value. 2945 */ 2946 static void 2947 trm_check_eeprom(sc, eeprom) 2948 struct trm_softc *sc; 2949 struct trm_nvram *eeprom; 2950 { 2951 struct nvram_target *target; 2952 u_int16_t *ep; 2953 u_int16_t chksum; 2954 int i; 2955 2956 #ifdef TRM_DEBUG 2957 printf("\n trm_check_eeprom......\n"); 2958 #endif 2959 trm_eeprom_read_all(sc, eeprom); 2960 ep = (u_int16_t *)eeprom; 2961 chksum = 0; 2962 for (i = 0; i < 64; i++) 2963 chksum += le16toh(*ep++); 2964 2965 if (chksum != TRM_NVRAM_CKSUM) { 2966 #ifdef TRM_DEBUG 2967 printf("TRM_S1040 EEPROM Check Sum ERROR (load default).\n"); 2968 #endif 2969 /* 2970 * Checksum error, load default 2971 */ 2972 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2973 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2974 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2975 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2976 eeprom->subclass = 0x00; 2977 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2978 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2979 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2980 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2981 eeprom->reserved0 = 0x00; 2982 2983 for (i = 0, target = eeprom->target; 2984 i < TRM_MAX_TARGETS; 2985 i++, target++) { 2986 target->config0 = 0x77; 2987 target->period = 0x00; 2988 target->config2 = 0x00; 2989 target->config3 = 0x00; 2990 } 2991 2992 eeprom->scsi_id = 7; 2993 eeprom->channel_cfg = 0x0F; 2994 eeprom->delay_time = 0; 2995 eeprom->max_tag = 4; 2996 eeprom->reserved1 = 0x15; 2997 eeprom->boot_target = 0; 2998 eeprom->boot_lun = 0; 2999 eeprom->reserved2 = 0; 3000 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 3001 3002 chksum = 0; 3003 ep = (u_int16_t *)eeprom; 3004 for (i = 0; i < 63; i++) 3005 chksum += le16toh(*ep++); 3006 3007 chksum = TRM_NVRAM_CKSUM - chksum; 3008 eeprom->checksum0 = chksum & 0xFF; 3009 eeprom->checksum1 = chksum >> 8; 3010 3011 trm_eeprom_write_all(sc, eeprom); 3012 } 3013 } 3014 3015 /* 3016 * initialize the SCSI chip ctrl registers 3017 */ 3018 static void 3019 trm_init_adapter(sc) 3020 struct trm_softc *sc; 3021 { 3022 bus_space_tag_t iot = sc->sc_iot; 3023 bus_space_handle_t ioh = sc->sc_ioh; 3024 u_int8_t bval; 3025 3026 /* program configuration 0 */ 3027 bval = PHASELATCH | INITIATOR | BLOCKRST; 3028 if (sc->sc_config & HCC_PARITY) 3029 bval |= PARITYCHECK; 3030 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 3031 3032 /* program configuration 1 */ 3033 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 3034 ACTIVE_NEG | ACTIVE_NEGPLUS); 3035 3036 /* 250ms selection timeout */ 3037 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 3038 3039 /* Mask all the interrupt */ 3040 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 3041 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 3042 3043 /* Reset SCSI module */ 3044 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 3045 3046 /* program Host ID */ 3047 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 3048 3049 /* set ansynchronous transfer */ 3050 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 3051 3052 /* Trun LED control off */ 3053 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 3054 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 3055 3056 /* DMA config */ 3057 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 3058 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 3059 3060 /* Clear pending interrupt status */ 3061 bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 3062 3063 /* Enable SCSI interrupt */ 3064 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 3065 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 3066 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 3067 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 3068 } 3069 3070 /* 3071 * initialize the internal structures for a given SCSI host 3072 */ 3073 static int 3074 trm_init(sc) 3075 struct trm_softc *sc; 3076 { 3077 bus_dma_segment_t seg; 3078 int error, rseg, all_sgsize; 3079 3080 /* 3081 * EEPROM CHECKSUM 3082 */ 3083 trm_check_eeprom(sc, &sc->sc_eeprom); 3084 /* 3085 * MEMORY ALLOCATE FOR ADAPTER CONTROL BLOCK 3086 * allocate the space for all SCSI control blocks (SRB) for DMA memory 3087 */ 3088 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 3089 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 3090 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 3091 printf("%s: unable to allocate SCSI REQUEST BLOCKS, " 3092 "error = %d\n", sc->sc_dev.dv_xname, error); 3093 return (-1); 3094 } 3095 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 3096 all_sgsize, (caddr_t *) &sc->sc_sglist, 3097 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 3098 printf("%s: unable to map SCSI REQUEST BLOCKS, " 3099 "error = %d\n", sc->sc_dev.dv_xname, error); 3100 return (-1); 3101 } 3102 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 3103 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 3104 printf("%s: unable to create SRB DMA maps, " 3105 "error = %d\n", sc->sc_dev.dv_xname, error); 3106 return (-1); 3107 } 3108 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 3109 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 3110 printf("%s: unable to load SRB DMA maps, " 3111 "error = %d\n", sc->sc_dev.dv_xname, error); 3112 return (-1); 3113 } 3114 #ifdef TRM_DEBUG 3115 printf("\n\n%s: all_sgsize=%x\n", sc->sc_dev.dv_xname, all_sgsize); 3116 #endif 3117 memset(sc->sc_sglist, 0, all_sgsize); 3118 trm_init_sc(sc); 3119 trm_init_adapter(sc); 3120 trm_reset(sc); 3121 return (0); 3122 } 3123 3124 /* 3125 * attach and init a host adapter 3126 */ 3127 static void 3128 trm_attach(parent, self, aux) 3129 struct device *parent; 3130 struct device *self; 3131 void *aux; 3132 { 3133 struct pci_attach_args *const pa = aux; 3134 struct trm_softc *sc = (void *) self; 3135 bus_space_tag_t iot; /* bus space tag */ 3136 bus_space_handle_t ioh; /* bus space handle */ 3137 pci_intr_handle_t ih; 3138 pcireg_t command; 3139 const char *intrstr; 3140 3141 /* 3142 * These cards do not allow memory mapped accesses 3143 * pa_pc: chipset tag 3144 * pa_tag: pci tag 3145 */ 3146 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 3147 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 3148 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 3149 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3150 pci_conf_write(pa->pa_pc, pa->pa_tag, 3151 PCI_COMMAND_STATUS_REG, command); 3152 } 3153 /* 3154 * mask for get correct base address of pci IO port 3155 */ 3156 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 3157 &iot, &ioh, NULL, NULL)) { 3158 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 3159 return; 3160 } 3161 /* 3162 * test checksum of eeprom..& initial "ACB" adapter control block... 3163 */ 3164 sc->sc_iot = iot; 3165 sc->sc_ioh = ioh; 3166 sc->sc_dmat = pa->pa_dmat; 3167 if (trm_init(sc)) { 3168 /* 3169 * Error during initialization! 3170 */ 3171 printf(": Error during initialization\n"); 3172 return; 3173 } 3174 /* 3175 * Now try to attach all the sub-devices 3176 */ 3177 if (sc->sc_config & HCC_WIDE_CARD) 3178 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 3179 "Ultra Wide SCSI Adapter\n"); 3180 else 3181 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 3182 "Ultra SCSI Adapter\n"); 3183 3184 printf("%s: Adapter ID=%d, Max tag number=%d, %d SCBs\n", 3185 sc->sc_dev.dv_xname, sc->sc_id, sc->maxtag, TRM_MAX_SRB); 3186 /* 3187 * Now tell the generic SCSI layer about our bus. 3188 * map and establish interrupt 3189 */ 3190 if (pci_intr_map(pa, &ih)) { 3191 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 3192 return; 3193 } 3194 intrstr = pci_intr_string(pa->pa_pc, ih); 3195 3196 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 3197 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 3198 if (intrstr != NULL) 3199 printf(" at %s", intrstr); 3200 printf("\n"); 3201 return; 3202 } 3203 if (intrstr != NULL) 3204 printf("%s: interrupting at %s\n", 3205 sc->sc_dev.dv_xname, intrstr); 3206 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 3207 } 3208 3209 /* 3210 * match pci device 3211 */ 3212 static int 3213 trm_probe(parent, match, aux) 3214 struct device *parent; 3215 struct cfdata *match; 3216 void *aux; 3217 { 3218 struct pci_attach_args *pa = aux; 3219 3220 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 3221 switch (PCI_PRODUCT(pa->pa_id)) { 3222 case PCI_PRODUCT_TEKRAM2_DC315: 3223 return (1); 3224 } 3225 return (0); 3226 } 3227
Indexes created Sun Oct 12 20:09:57 GMT 2025