trm.c revision 1.6.2.3
1 /* $NetBSD: trm.c,v 1.6.2.3 2002/03/16 16:01:20 jdolecek Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2002 Izumi Tsutsui 8 * Copyright (c) 2001 Rui-Xiang Guo 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from 35 * dc395x_trm.c 36 * 37 * Written for NetBSD 1.4.x by 38 * Erich Chen (erich (at) tekram.com.tw) 39 * 40 * Provided by 41 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.6.2.3 2002/03/16 16:01:20 jdolecek Exp $"); 46 47 /* #define TRM_DEBUG */ 48 #ifdef TRM_DEBUG 49 int trm_debug = 1; 50 #define DPRINTF(arg) if (trm_debug > 0) printf arg; 51 #else 52 #define DPRINTF(arg) 53 #endif 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/buf.h> 59 #include <sys/kernel.h> 60 #include <sys/device.h> 61 #include <sys/queue.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <dev/scsipi/scsi_all.h> 69 #include <dev/scsipi/scsi_message.h> 70 #include <dev/scsipi/scsipi_all.h> 71 #include <dev/scsipi/scsiconf.h> 72 73 #include <dev/pci/pcidevs.h> 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/trmreg.h> 77 78 /* 79 * feature of chip set MAX value 80 */ 81 #define TRM_MAX_TARGETS 16 82 #define TRM_MAX_LUNS 8 83 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 84 #define TRM_MAX_SRB 32 /* XXX */ 85 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 86 #define TRM_MAX_OFFSET 15 87 #define TRM_MAX_PERIOD 125 88 89 /* 90 * Segment Entry 91 */ 92 struct trm_sg_entry { 93 u_int32_t address; 94 u_int32_t length; 95 }; 96 97 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 98 99 /* 100 ********************************************************************** 101 * The SEEPROM structure for TRM_S1040 102 ********************************************************************** 103 */ 104 struct nvram_target { 105 u_int8_t config0; /* Target configuration byte 0 */ 106 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 107 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 108 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 109 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 110 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 111 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 112 u_int8_t period; /* Target period */ 113 u_int8_t config2; /* Target configuration byte 2 */ 114 u_int8_t config3; /* Target configuration byte 3 */ 115 }; 116 117 struct trm_nvram { 118 u_int8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 119 u_int8_t subsys_id[2]; /* 2,3 Sub System ID */ 120 u_int8_t subclass; /* 4 Sub Class */ 121 u_int8_t vendor_id[2]; /* 5,6 Vendor ID */ 122 u_int8_t device_id[2]; /* 7,8 Device ID */ 123 u_int8_t reserved0; /* 9 Reserved */ 124 struct nvram_target target[TRM_MAX_TARGETS]; 125 /* 10,11,12,13 126 * 14,15,16,17 127 * .... 128 * 70,71,72,73 */ 129 u_int8_t scsi_id; /* 74 Host Adapter SCSI ID */ 130 u_int8_t channel_cfg; /* 75 Channel configuration */ 131 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 132 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 133 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 134 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 135 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 136 u_int8_t delay_time; /* 76 Power on delay time */ 137 u_int8_t max_tag; /* 77 Maximum tags */ 138 u_int8_t reserved1; /* 78 */ 139 u_int8_t boot_target; /* 79 */ 140 u_int8_t boot_lun; /* 80 */ 141 u_int8_t reserved2; /* 81 */ 142 u_int8_t reserved3[44]; /* 82,..125 */ 143 u_int8_t checksum0; /* 126 */ 144 u_int8_t checksum1; /* 127 */ 145 #define TRM_NVRAM_CKSUM 0x1234 146 }; 147 148 /* Nvram Initiater bits definition */ 149 #define MORE2_DRV 0x00000001 150 #define GREATER_1G 0x00000002 151 #define RST_SCSI_BUS 0x00000004 152 #define ACTIVE_NEGATION 0x00000008 153 #define NO_SEEK 0x00000010 154 #define LUN_CHECK 0x00000020 155 156 #define trm_eeprom_wait() DELAY(30) 157 158 /* 159 *----------------------------------------------------------------------- 160 * SCSI Request Block 161 *----------------------------------------------------------------------- 162 */ 163 struct trm_srb { 164 TAILQ_ENTRY(trm_srb) next; 165 166 struct trm_sg_entry *sgentry; 167 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 168 bus_dmamap_t dmap; 169 bus_size_t sgoffset; /* Xfer buf offset */ 170 171 u_int32_t buflen; /* Total xfer length */ 172 u_int32_t sgaddr; /* SGList physical starting address */ 173 174 int sgcnt; 175 int sgindex; 176 177 int hastat; /* Host Adapter Status */ 178 #define H_STATUS_GOOD 0x00 179 #define H_SEL_TIMEOUT 0x11 180 #define H_OVER_UNDER_RUN 0x12 181 #define H_UNEXP_BUS_FREE 0x13 182 #define H_TARGET_PHASE_F 0x14 183 #define H_INVALID_CCB_OP 0x16 184 #define H_LINK_CCB_BAD 0x17 185 #define H_BAD_TARGET_DIR 0x18 186 #define H_DUPLICATE_CCB 0x19 187 #define H_BAD_CCB_OR_SG 0x1A 188 #define H_ABORT 0xFF 189 int tastat; /* Target SCSI Status Byte */ 190 int flag; /* SRBFlag */ 191 #define AUTO_REQSENSE 0x0001 192 #define PARITY_ERROR 0x0002 193 #define SRB_TIMEOUT 0x0004 194 195 int cmdlen; /* SCSI command length */ 196 u_int8_t cmd[12]; /* SCSI command */ 197 198 u_int8_t tag[2]; 199 }; 200 201 /* 202 * some info about each target and lun on the SCSI bus 203 */ 204 struct trm_linfo { 205 int used; /* number of slots in use */ 206 int avail; /* where to start scanning */ 207 int busy; /* lun in use */ 208 struct trm_srb *untagged; 209 struct trm_srb *queued[TRM_MAX_TAG]; 210 }; 211 212 struct trm_tinfo { 213 u_int flag; /* Sync mode ? (1 sync):(0 async) */ 214 #define SYNC_NEGO_ENABLE 0x0001 215 #define SYNC_NEGO_DOING 0x0002 216 #define SYNC_NEGO_DONE 0x0004 217 #define WIDE_NEGO_ENABLE 0x0008 218 #define WIDE_NEGO_DOING 0x0010 219 #define WIDE_NEGO_DONE 0x0020 220 #define USE_TAG_QUEUING 0x0040 221 #define NO_RESELECT 0x0080 222 struct trm_linfo *linfo[TRM_MAX_LUNS]; 223 224 u_int8_t config0; /* Target Config */ 225 u_int8_t period; /* Max Period for nego. */ 226 u_int8_t synctl; /* Sync control for reg. */ 227 u_int8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 228 }; 229 230 /* 231 *----------------------------------------------------------------------- 232 * Adapter Control Block 233 *----------------------------------------------------------------------- 234 */ 235 struct trm_softc { 236 struct device sc_dev; 237 238 bus_space_tag_t sc_iot; 239 bus_space_handle_t sc_ioh; 240 bus_dma_tag_t sc_dmat; 241 bus_dmamap_t sc_dmamap; /* Map the control structures */ 242 243 struct trm_srb *sc_actsrb; 244 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 245 246 TAILQ_HEAD(, trm_srb) sc_freesrb, 247 sc_readysrb; 248 struct trm_srb *sc_srb; /* SRB array */ 249 250 struct trm_sg_entry *sc_sglist; 251 252 int sc_maxid; 253 /* 254 * Link to the generic SCSI driver 255 */ 256 struct scsipi_channel sc_channel; 257 struct scsipi_adapter sc_adapter; 258 259 int sc_id; /* Adapter SCSI Target ID */ 260 261 int sc_state; /* SRB State */ 262 #define TRM_IDLE 0 263 #define TRM_WAIT 1 264 #define TRM_READY 2 265 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 266 #define TRM_MSGIN 4 267 #define TRM_EXTEND_MSGIN 5 268 #define TRM_COMMAND 6 269 #define TRM_START 7 /* arbitration+msg_out+command_out */ 270 #define TRM_DISCONNECTED 8 271 #define TRM_DATA_XFER 9 272 #define TRM_XFERPAD 10 273 #define TRM_STATUS 11 274 #define TRM_COMPLETED 12 275 #define TRM_ABORT_SENT 13 276 #define TRM_UNEXPECT_RESEL 14 277 278 int sc_phase; /* SCSI phase */ 279 int sc_config; 280 #define HCC_WIDE_CARD 0x01 281 #define HCC_SCSI_RESET 0x02 282 #define HCC_PARITY 0x04 283 #define HCC_AUTOTERM 0x08 284 #define HCC_LOW8TERM 0x10 285 #define HCC_UP8TERM 0x20 286 287 int sc_flag; 288 #define RESET_DEV 0x01 289 #define RESET_DETECT 0x02 290 #define RESET_DONE 0x04 291 #define WAIT_TAGMSG 0x08 /* XXX */ 292 293 int sc_msgcnt; 294 295 int resel_target; /* XXX */ 296 int resel_lun; /* XXX */ 297 298 u_int8_t *sc_msg; 299 u_int8_t sc_msgbuf[6]; 300 }; 301 302 /* 303 * SCSI Status codes not defined in scsi_all.h 304 */ 305 #define SCSI_COND_MET 0x04 /* Condition Met */ 306 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 307 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 308 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 309 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 310 311 static int trm_probe(struct device *, struct cfdata *, void *); 312 static void trm_attach(struct device *, struct device *, void *); 313 314 static int trm_init(struct trm_softc *); 315 316 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 317 void *); 318 static void trm_update_xfer_mode(struct trm_softc *, int); 319 static void trm_sched(struct trm_softc *); 320 static int trm_select(struct trm_softc *, struct trm_srb *); 321 static void trm_reset(struct trm_softc *); 322 static void trm_timeout(void *); 323 static int trm_intr(void *); 324 325 static void trm_dataout_phase0(struct trm_softc *, int); 326 static void trm_datain_phase0(struct trm_softc *, int); 327 static void trm_status_phase0(struct trm_softc *); 328 static void trm_msgin_phase0(struct trm_softc *); 329 static void trm_command_phase1(struct trm_softc *); 330 static void trm_status_phase1(struct trm_softc *); 331 static void trm_msgout_phase1(struct trm_softc *); 332 static void trm_msgin_phase1(struct trm_softc *); 333 334 static void trm_dataio_xfer(struct trm_softc *, int); 335 static void trm_disconnect(struct trm_softc *); 336 static void trm_reselect(struct trm_softc *); 337 static void trm_done(struct trm_softc *, struct trm_srb *); 338 static int trm_request_sense(struct trm_softc *, struct trm_srb *); 339 static void trm_dequeue(struct trm_softc *, struct trm_srb *); 340 341 static void trm_scsi_reset_detect(struct trm_softc *); 342 static void trm_reset_scsi_bus(struct trm_softc *); 343 344 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 345 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 346 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 347 static void trm_eeprom_set_data(struct trm_softc *, u_int8_t, u_int8_t); 348 static void trm_eeprom_write_cmd(struct trm_softc *, u_int8_t, u_int8_t); 349 static u_int8_t trm_eeprom_get_data(struct trm_softc *, u_int8_t); 350 351 struct cfattach trm_ca = { 352 sizeof(struct trm_softc), trm_probe, trm_attach 353 }; 354 355 /* real period: */ 356 static const u_int8_t trm_clock_period[] = { 357 12, /* 48 ns 20.0 MB/sec */ 358 18, /* 72 ns 13.3 MB/sec */ 359 25, /* 100 ns 10.0 MB/sec */ 360 31, /* 124 ns 8.0 MB/sec */ 361 37, /* 148 ns 6.6 MB/sec */ 362 43, /* 172 ns 5.7 MB/sec */ 363 50, /* 200 ns 5.0 MB/sec */ 364 62 /* 248 ns 4.0 MB/sec */ 365 }; 366 #define NPERIOD (sizeof(trm_clock_period)/sizeof(trm_clock_period[0])) 367 368 static int 369 trm_probe(parent, match, aux) 370 struct device *parent; 371 struct cfdata *match; 372 void *aux; 373 { 374 struct pci_attach_args *pa = aux; 375 376 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 377 switch (PCI_PRODUCT(pa->pa_id)) { 378 case PCI_PRODUCT_TEKRAM2_DC315: 379 return (1); 380 } 381 return (0); 382 } 383 384 /* 385 * attach and init a host adapter 386 */ 387 static void 388 trm_attach(parent, self, aux) 389 struct device *parent; 390 struct device *self; 391 void *aux; 392 { 393 struct pci_attach_args *const pa = aux; 394 struct trm_softc *sc = (struct trm_softc *)self; 395 bus_space_tag_t iot; 396 bus_space_handle_t ioh; 397 pci_intr_handle_t ih; 398 pcireg_t command; 399 const char *intrstr; 400 401 /* 402 * These cards do not allow memory mapped accesses 403 * pa_pc: chipset tag 404 * pa_tag: pci tag 405 */ 406 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 407 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 408 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 409 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 410 pci_conf_write(pa->pa_pc, pa->pa_tag, 411 PCI_COMMAND_STATUS_REG, command); 412 } 413 /* 414 * mask for get correct base address of pci IO port 415 */ 416 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 417 &iot, &ioh, NULL, NULL)) { 418 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 419 return; 420 } 421 /* 422 * test checksum of eeprom.. & initialize softc... 423 */ 424 sc->sc_iot = iot; 425 sc->sc_ioh = ioh; 426 sc->sc_dmat = pa->pa_dmat; 427 428 if (trm_init(sc) != 0) { 429 /* 430 * Error during initialization! 431 */ 432 printf(": Error during initialization\n"); 433 return; 434 } 435 /* 436 * Now try to attach all the sub-devices 437 */ 438 if ((sc->sc_config & HCC_WIDE_CARD) != 0) 439 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 440 "Ultra Wide SCSI Adapter\n"); 441 else 442 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 443 "Ultra SCSI Adapter\n"); 444 445 /* 446 * Now tell the generic SCSI layer about our bus. 447 * map and establish interrupt 448 */ 449 if (pci_intr_map(pa, &ih)) { 450 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 451 return; 452 } 453 intrstr = pci_intr_string(pa->pa_pc, ih); 454 455 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 456 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 457 if (intrstr != NULL) 458 printf(" at %s", intrstr); 459 printf("\n"); 460 return; 461 } 462 if (intrstr != NULL) 463 printf("%s: interrupting at %s\n", 464 sc->sc_dev.dv_xname, intrstr); 465 466 sc->sc_adapter.adapt_dev = &sc->sc_dev; 467 sc->sc_adapter.adapt_nchannels = 1; 468 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 469 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 470 sc->sc_adapter.adapt_request = trm_scsipi_request; 471 sc->sc_adapter.adapt_minphys = minphys; 472 473 sc->sc_channel.chan_adapter = &sc->sc_adapter; 474 sc->sc_channel.chan_bustype = &scsi_bustype; 475 sc->sc_channel.chan_channel = 0; 476 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 477 sc->sc_channel.chan_nluns = 8; 478 sc->sc_channel.chan_id = sc->sc_id; 479 480 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 481 } 482 483 /* 484 * initialize the internal structures for a given SCSI host 485 */ 486 static int 487 trm_init(sc) 488 struct trm_softc *sc; 489 { 490 bus_space_tag_t iot = sc->sc_iot; 491 bus_space_handle_t ioh = sc->sc_ioh; 492 bus_dma_segment_t seg; 493 struct trm_nvram eeprom; 494 struct trm_srb *srb; 495 struct trm_tinfo *ti; 496 struct nvram_target *tconf; 497 int error, rseg, all_sgsize; 498 int i, target; 499 u_int8_t bval; 500 501 DPRINTF(("\n")); 502 503 /* 504 * allocate the space for all SCSI control blocks (SRB) for DMA memory 505 */ 506 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 507 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 508 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 509 printf(": unable to allocate SCSI REQUEST BLOCKS, " 510 "error = %d\n", error); 511 return (1); 512 } 513 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 514 all_sgsize, (caddr_t *) &sc->sc_sglist, 515 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 516 printf(": unable to map SCSI REQUEST BLOCKS, " 517 "error = %d\n", error); 518 return (1); 519 } 520 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 521 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 522 printf(": unable to create SRB DMA maps, " 523 "error = %d\n", error); 524 return (1); 525 } 526 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 527 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 528 printf(": unable to load SRB DMA maps, " 529 "error = %d\n", error); 530 return (1); 531 } 532 DPRINTF(("all_sgsize=%x\n", all_sgsize)); 533 memset(sc->sc_sglist, 0, all_sgsize); 534 535 /* 536 * EEPROM CHECKSUM 537 */ 538 trm_check_eeprom(sc, &eeprom); 539 540 sc->sc_maxid = 7; 541 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 542 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 543 sc->sc_config |= HCC_WIDE_CARD; 544 sc->sc_maxid = 15; 545 } 546 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 547 sc->sc_config |= HCC_SCSI_RESET; 548 549 sc->sc_actsrb = NULL; 550 sc->sc_id = eeprom.scsi_id; 551 sc->sc_flag = 0; 552 553 /* 554 * initialize and link all device's SRB queues of this adapter 555 */ 556 TAILQ_INIT(&sc->sc_freesrb); 557 TAILQ_INIT(&sc->sc_readysrb); 558 559 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 560 M_DEVBUF, M_NOWAIT|M_ZERO); 561 DPRINTF(("all SRB size=%x\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 562 if (sc->sc_srb == NULL) { 563 printf(": can not allocate SRB\n"); 564 return (1); 565 } 566 567 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 568 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 569 srb->sgoffset = TRM_SG_SIZE * i; 570 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 571 /* 572 * map all SRB space to SRB_array 573 */ 574 if (bus_dmamap_create(sc->sc_dmat, 575 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 576 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 577 printf(": unable to create DMA transfer map...\n", 578 sc->sc_dev.dv_xname); 579 free(sc->sc_srb, M_DEVBUF); 580 return (1); 581 } 582 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 583 srb++; 584 } 585 586 /* 587 * initialize all target info structures 588 */ 589 for (target = 0; target < TRM_MAX_TARGETS; target++) { 590 ti = &sc->sc_tinfo[target]; 591 ti->synctl = 0; 592 ti->offset = 0; 593 tconf = &eeprom.target[target]; 594 ti->config0 = tconf->config0; 595 ti->period = trm_clock_period[tconf->period & 0x07]; 596 ti->flag = 0; 597 if ((ti->config0 & NTC_DO_WIDE_NEGO) != 0 && 598 (sc->sc_config & HCC_WIDE_CARD) != 0) 599 ti->flag |= WIDE_NEGO_ENABLE; 600 if ((ti->config0 & NTC_DO_SYNC_NEGO) != 0) 601 ti->flag |= SYNC_NEGO_ENABLE; 602 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 603 #ifdef notyet 604 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 605 ti->flag |= USE_TAG_QUEUING; 606 #endif 607 } else 608 ti->flag |= NO_RESELECT; 609 610 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 611 target, ti->config0, ti->period)); 612 DPRINTF((", flag = 0x%02x\n", ti->flag)); 613 } 614 615 /* program configuration 0 */ 616 bval = PHASELATCH | INITIATOR | BLOCKRST; 617 if ((sc->sc_config & HCC_PARITY) != 0) 618 bval |= PARITYCHECK; 619 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 620 621 /* program configuration 1 */ 622 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 623 ACTIVE_NEG | ACTIVE_NEGPLUS); 624 625 /* 250ms selection timeout */ 626 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 627 628 /* Mask all interrupts */ 629 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 630 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 631 632 /* Reset SCSI module */ 633 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 634 635 /* program Host ID */ 636 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 637 638 /* set asynchronous transfer */ 639 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 640 641 /* Turn LED control off */ 642 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 643 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 644 645 /* DMA config */ 646 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 647 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 648 649 /* Clear pending interrupt status */ 650 bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 651 652 /* Enable SCSI interrupt */ 653 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 654 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 655 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 656 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 657 658 trm_reset(sc); 659 660 return (0); 661 } 662 663 /* 664 * enqueues a SCSI command 665 * called by the higher level SCSI driver 666 */ 667 static void 668 trm_scsipi_request(chan, req, arg) 669 struct scsipi_channel *chan; 670 scsipi_adapter_req_t req; 671 void *arg; 672 { 673 bus_space_tag_t iot; 674 bus_space_handle_t ioh; 675 struct trm_softc *sc; 676 struct trm_srb *srb; 677 struct scsipi_xfer *xs; 678 int error, i, target, lun, s; 679 680 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 681 iot = sc->sc_iot; 682 ioh = sc->sc_ioh; 683 684 switch (req) { 685 case ADAPTER_REQ_RUN_XFER: 686 xs = arg; 687 target = xs->xs_periph->periph_target; 688 lun = xs->xs_periph->periph_lun; 689 DPRINTF(("trm_scsipi_request.....\n")); 690 DPRINTF(("target= %d lun= %d\n", target, lun)); 691 if (xs->xs_control & XS_CTL_RESET) { 692 trm_reset(sc); 693 xs->error = XS_NOERROR | XS_RESET; 694 return; 695 } 696 if (xs->xs_status & XS_STS_DONE) { 697 printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 698 xs->xs_status &= ~XS_STS_DONE; 699 } 700 701 s = splbio(); 702 703 /* Get SRB */ 704 srb = TAILQ_FIRST(&sc->sc_freesrb); 705 if (srb != NULL) { 706 TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 707 } else { 708 xs->error = XS_RESOURCE_SHORTAGE; 709 scsipi_done(xs); 710 splx(s); 711 return; 712 } 713 714 srb->xs = xs; 715 srb->cmdlen = xs->cmdlen; 716 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 717 718 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 719 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 720 xs->data, xs->datalen, NULL, 721 ((xs->xs_control & XS_CTL_NOSLEEP) ? 722 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 723 BUS_DMA_STREAMING | 724 ((xs->xs_control & XS_CTL_DATA_IN) ? 725 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 726 printf("%s: DMA transfer map unable to load, " 727 "error = %d\n", sc->sc_dev.dv_xname, error); 728 xs->error = XS_DRIVER_STUFFUP; 729 /* 730 * free SRB 731 */ 732 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 733 splx(s); 734 return; 735 } 736 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 737 srb->dmap->dm_mapsize, 738 (xs->xs_control & XS_CTL_DATA_IN) ? 739 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 740 741 /* Set up the scatter gather list */ 742 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 743 srb->sgentry[i].address = 744 htole32(srb->dmap->dm_segs[i].ds_addr); 745 srb->sgentry[i].length = 746 htole32(srb->dmap->dm_segs[i].ds_len); 747 } 748 srb->buflen = xs->datalen; 749 srb->sgcnt = srb->dmap->dm_nsegs; 750 } else { 751 srb->sgentry[0].address = 0; 752 srb->sgentry[0].length = 0; 753 srb->buflen = 0; 754 srb->sgcnt = 0; 755 } 756 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 757 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 758 759 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 760 761 srb->sgindex = 0; 762 srb->hastat = 0; 763 srb->tastat = 0; 764 srb->flag = 0; 765 766 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 767 if (sc->sc_actsrb == NULL) 768 trm_sched(sc); 769 splx(s); 770 771 if ((xs->xs_control & XS_CTL_POLL) != 0) { 772 int timeout = xs->timeout; 773 774 s = splbio(); 775 do { 776 while (--timeout) { 777 DELAY(1000); 778 if (bus_space_read_2(iot, ioh, 779 TRM_SCSI_STATUS) & SCSIINTERRUPT) 780 break; 781 } 782 if (timeout == 0) { 783 trm_timeout(srb); 784 break; 785 } else 786 trm_intr(sc); 787 } while ((xs->xs_status & XS_STS_DONE) == 0); 788 splx(s); 789 } 790 return; 791 792 case ADAPTER_REQ_GROW_RESOURCES: 793 /* XXX Not supported. */ 794 return; 795 796 case ADAPTER_REQ_SET_XFER_MODE: 797 { 798 struct trm_tinfo *ti; 799 struct scsipi_xfer_mode *xm; 800 801 xm = arg; 802 ti = &sc->sc_tinfo[xm->xm_target]; 803 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 804 805 #ifdef notyet 806 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 807 ti->flag |= USE_TAG_QUEUING; 808 else 809 #endif 810 ti->flag &= ~USE_TAG_QUEUING; 811 812 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0) { 813 ti->flag |= WIDE_NEGO_ENABLE; 814 ti->flag &= ~WIDE_NEGO_DONE; 815 } 816 817 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0) { 818 ti->flag |= SYNC_NEGO_ENABLE; 819 ti->flag &= ~SYNC_NEGO_DONE; 820 ti->period = trm_clock_period[0]; 821 } 822 823 /* 824 * If we're not going to negotiate, send the 825 * notification now, since it won't happen later. 826 */ 827 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 828 (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 829 trm_update_xfer_mode(sc, xm->xm_target); 830 831 return; 832 } 833 } 834 } 835 836 static void 837 trm_update_xfer_mode(sc, target) 838 struct trm_softc *sc; 839 int target; 840 { 841 struct scsipi_xfer_mode xm; 842 struct trm_tinfo *ti; 843 844 ti = &sc->sc_tinfo[target]; 845 xm.xm_target = target; 846 xm.xm_mode = 0; 847 xm.xm_period = 0; 848 xm.xm_offset = 0; 849 850 if ((ti->synctl & WIDE_SYNC) != 0) 851 xm.xm_mode |= PERIPH_CAP_WIDE16; 852 853 if (ti->period > 0) { 854 xm.xm_mode |= PERIPH_CAP_SYNC; 855 xm.xm_period = ti->period; 856 xm.xm_offset = ti->offset; 857 } 858 859 #ifdef notyet 860 if ((ti->flag & USE_TAG_QUEUING) != 0) 861 xm.xm_mode |= PERIPH_CAP_TQING; 862 #endif 863 864 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 865 } 866 867 static void 868 trm_sched(sc) 869 struct trm_softc *sc; 870 { 871 struct trm_srb *srb; 872 struct scsipi_periph *periph; 873 struct trm_tinfo *ti; 874 struct trm_linfo *li; 875 int s, lun, tag; 876 877 DPRINTF(("trm_sched...\n")); 878 879 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 880 periph = srb->xs->xs_periph; 881 ti = &sc->sc_tinfo[periph->periph_target]; 882 lun = periph->periph_lun; 883 884 /* select type of tag for this command */ 885 if ((ti->flag & NO_RESELECT) != 0 || 886 (ti->flag & USE_TAG_QUEUING) == 0 || 887 (srb->flag & AUTO_REQSENSE) != 0 || 888 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 889 tag = 0; 890 else 891 tag = srb->xs->xs_tag_type; 892 #if 0 893 /* XXX use tags for polled commands? */ 894 if (srb->xs->xs_control & XS_CTL_POLL) 895 tag = 0; 896 #endif 897 898 s = splbio(); 899 li = ti->linfo[lun]; 900 if (li == NULL) { 901 /* initialize lun info */ 902 if ((li = malloc(sizeof(*li), M_DEVBUF, 903 M_NOWAIT|M_ZERO)) == NULL) { 904 splx(s); 905 continue; 906 } 907 ti->linfo[lun] = li; 908 } 909 910 if (tag == 0) { 911 /* try to issue this srb as an un-tagged command */ 912 if (li->untagged == NULL) 913 li->untagged = srb; 914 } 915 if (li->untagged != NULL) { 916 tag = 0; 917 if (li->busy != 1 && li->used == 0) { 918 /* we need to issue the untagged command now */ 919 srb = li->untagged; 920 periph = srb->xs->xs_periph; 921 } else { 922 /* not ready yet */ 923 splx(s); 924 continue; 925 } 926 } 927 srb->tag[0] = tag; 928 if (tag != 0) { 929 li->queued[srb->xs->xs_tag_id] = srb; 930 srb->tag[1] = srb->xs->xs_tag_id; 931 li->used++; 932 } 933 934 if (li->untagged != NULL && li->busy != 1) { 935 li->busy = 1; 936 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 937 sc->sc_actsrb = srb; 938 trm_select(sc, srb); 939 splx(s); 940 break; 941 } 942 if (li->untagged == NULL && tag != 0) { 943 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 944 sc->sc_actsrb = srb; 945 trm_select(sc, srb); 946 splx(s); 947 break; 948 } else 949 splx(s); 950 } 951 } 952 953 static int 954 trm_select(sc, srb) 955 struct trm_softc *sc; 956 struct trm_srb *srb; 957 { 958 bus_space_tag_t iot = sc->sc_iot; 959 bus_space_handle_t ioh = sc->sc_ioh; 960 struct scsipi_periph *periph = srb->xs->xs_periph; 961 int target = periph->periph_target; 962 int lun = periph->periph_lun; 963 struct trm_tinfo *ti = &sc->sc_tinfo[target]; 964 u_int8_t scsicmd; 965 966 DPRINTF(("trm_select.....\n")); 967 968 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 969 int timeout = srb->xs->timeout; 970 timeout = (timeout > 100000) ? 971 timeout / 1000 * hz : timeout * hz / 1000; 972 callout_reset(&srb->xs->xs_callout, timeout, trm_timeout, srb); 973 } 974 975 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 976 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 977 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 978 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 979 /* Flush FIFO */ 980 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 981 DELAY(10); 982 983 sc->sc_phase = PH_BUS_FREE; /* initial phase */ 984 985 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 986 987 if (((ti->flag & WIDE_NEGO_ENABLE) && 988 (ti->flag & WIDE_NEGO_DONE) == 0) || 989 ((ti->flag & SYNC_NEGO_ENABLE) && 990 (ti->flag & SYNC_NEGO_DONE) == 0)) { 991 sc->sc_state = TRM_MSGOUT; 992 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 993 MSG_IDENTIFY(lun, 0)); 994 bus_space_write_multi_1(iot, ioh, 995 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 996 /* it's important for atn stop */ 997 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 998 DO_DATALATCH | DO_HWRESELECT); 999 /* SCSI command */ 1000 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 1001 DPRINTF(("select with SEL_ATNSTOP\n")); 1002 return (0); 1003 } 1004 1005 if (srb->tag[0] != 0) { 1006 /* Send identify message */ 1007 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1008 MSG_IDENTIFY(lun, 1)); 1009 /* Send Tag id */ 1010 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 1011 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 1012 scsicmd = SCMD_SEL_ATN3; 1013 DPRINTF(("select with SEL_ATN3\n")); 1014 } else { 1015 /* Send identify message */ 1016 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1017 MSG_IDENTIFY(lun, 1018 (ti->flag & NO_RESELECT) == 0 && 1019 (srb->flag & AUTO_REQSENSE) == 0 && 1020 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1021 scsicmd = SCMD_SEL_ATN; 1022 DPRINTF(("select with SEL_ATN\n")); 1023 } 1024 sc->sc_state = TRM_START; 1025 1026 /* 1027 * Send CDB ..command block... 1028 */ 1029 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1030 1031 /* 1032 * If trm_select returns 0: current interrupt status 1033 * is interrupt enable. It's said that SCSI processor is 1034 * unoccupied. 1035 */ 1036 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1037 /* SCSI command */ 1038 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1039 return (0); 1040 } 1041 1042 /* 1043 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1044 */ 1045 static void 1046 trm_reset(sc) 1047 struct trm_softc *sc; 1048 { 1049 bus_space_tag_t iot = sc->sc_iot; 1050 bus_space_handle_t ioh = sc->sc_ioh; 1051 int s; 1052 1053 DPRINTF(("trm_reset.........\n")); 1054 1055 s = splbio(); 1056 1057 /* disable SCSI and DMA interrupt */ 1058 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1059 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1060 1061 trm_reset_scsi_bus(sc); 1062 DELAY(100000); 1063 1064 /* Enable SCSI interrupt */ 1065 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1066 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1067 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1068 1069 /* Enable DMA interrupt */ 1070 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1071 1072 /* Clear DMA FIFO */ 1073 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1074 1075 /* Clear SCSI FIFO */ 1076 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1077 1078 sc->sc_actsrb = NULL; 1079 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1080 1081 splx(s); 1082 } 1083 1084 static void 1085 trm_timeout(arg) 1086 void *arg; 1087 { 1088 struct trm_srb *srb = (struct trm_srb *)arg; 1089 struct scsipi_xfer *xs = srb->xs; 1090 struct scsipi_periph *periph = xs->xs_periph; 1091 struct trm_softc *sc; 1092 int s; 1093 1094 if (xs == NULL) 1095 printf("trm_timeout called with xs == NULL\n"); 1096 1097 else { 1098 scsipi_printaddr(xs->xs_periph); 1099 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1100 } 1101 1102 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1103 1104 trm_reset_scsi_bus(sc); 1105 s = splbio(); 1106 srb->flag |= SRB_TIMEOUT; 1107 trm_done(sc, srb); 1108 /* XXX needs more.. */ 1109 splx(s); 1110 } 1111 1112 /* 1113 * Catch an interrupt from the adapter 1114 * Process pending device interrupts. 1115 */ 1116 static int 1117 trm_intr(arg) 1118 void *arg; 1119 { 1120 bus_space_tag_t iot; 1121 bus_space_handle_t ioh; 1122 struct trm_softc *sc; 1123 struct trm_srb *srb; 1124 int intstat, stat; 1125 1126 DPRINTF(("trm_intr......\n")); 1127 sc = (struct trm_softc *)arg; 1128 if (sc == NULL) 1129 return (0); 1130 1131 iot = sc->sc_iot; 1132 ioh = sc->sc_ioh; 1133 1134 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1135 if ((stat & SCSIINTERRUPT) == 0) 1136 return (0); 1137 1138 DPRINTF(("stat = %04x, ", stat)); 1139 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1140 1141 DPRINTF(("intstat=%02x, ", intstat)); 1142 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1143 DPRINTF(("\n")); 1144 trm_disconnect(sc); 1145 return (1); 1146 } 1147 if (intstat & INT_RESELECTED) { 1148 DPRINTF(("\n")); 1149 trm_reselect(sc); 1150 return (1); 1151 } 1152 if (intstat & INT_SCSIRESET) { 1153 DPRINTF(("\n")); 1154 trm_scsi_reset_detect(sc); 1155 return (1); 1156 } 1157 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1158 srb = sc->sc_actsrb; 1159 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1160 sc->sc_phase, sc->sc_state)); 1161 /* 1162 * software sequential machine 1163 */ 1164 1165 /* 1166 * call phase0 functions... "phase entry" handle 1167 * every phase before start transfer 1168 */ 1169 switch (sc->sc_phase) { 1170 case PH_DATA_OUT: 1171 trm_dataout_phase0(sc, stat); 1172 break; 1173 case PH_DATA_IN: 1174 trm_datain_phase0(sc, stat); 1175 break; 1176 case PH_COMMAND: 1177 break; 1178 case PH_STATUS: 1179 trm_status_phase0(sc); 1180 stat = PH_BUS_FREE; 1181 break; 1182 case PH_MSG_OUT: 1183 if (sc->sc_state == TRM_UNEXPECT_RESEL || 1184 sc->sc_state == TRM_ABORT_SENT) 1185 stat = PH_BUS_FREE; 1186 break; 1187 case PH_MSG_IN: 1188 trm_msgin_phase0(sc); 1189 stat = PH_BUS_FREE; 1190 break; 1191 case PH_BUS_FREE: 1192 break; 1193 default: 1194 printf("%s: unexpected phase in trm_intr() phase0\n", 1195 sc->sc_dev.dv_xname); 1196 break; 1197 } 1198 1199 sc->sc_phase = stat & PHASEMASK; 1200 1201 switch (sc->sc_phase) { 1202 case PH_DATA_OUT: 1203 trm_dataio_xfer(sc, XFERDATAOUT); 1204 break; 1205 case PH_DATA_IN: 1206 trm_dataio_xfer(sc, XFERDATAIN); 1207 break; 1208 case PH_COMMAND: 1209 trm_command_phase1(sc); 1210 break; 1211 case PH_STATUS: 1212 trm_status_phase1(sc); 1213 break; 1214 case PH_MSG_OUT: 1215 trm_msgout_phase1(sc); 1216 break; 1217 case PH_MSG_IN: 1218 trm_msgin_phase1(sc); 1219 break; 1220 case PH_BUS_FREE: 1221 break; 1222 default: 1223 printf("%s: unexpected phase in trm_intr() phase1\n", 1224 sc->sc_dev.dv_xname); 1225 break; 1226 } 1227 1228 return (1); 1229 } 1230 return (0); 1231 } 1232 1233 static void 1234 trm_msgout_phase1(sc) 1235 struct trm_softc *sc; 1236 { 1237 bus_space_tag_t iot = sc->sc_iot; 1238 bus_space_handle_t ioh = sc->sc_ioh; 1239 struct trm_srb *srb; 1240 struct scsipi_periph *periph; 1241 struct trm_tinfo *ti; 1242 1243 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1244 1245 srb = sc->sc_actsrb; 1246 1247 /* message out phase */ 1248 if (srb != NULL) { 1249 periph = srb->xs->xs_periph; 1250 ti = &sc->sc_tinfo[periph->periph_target]; 1251 1252 if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1253 (ti->flag & WIDE_NEGO_ENABLE)) { 1254 /* send WDTR */ 1255 ti->flag &= ~SYNC_NEGO_DONE; 1256 1257 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1258 sc->sc_msgbuf[1] = MSG_EXTENDED; 1259 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1260 sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1261 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1262 sc->sc_msgcnt = 5; 1263 1264 ti->flag |= WIDE_NEGO_DOING; 1265 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1266 (ti->flag & SYNC_NEGO_ENABLE)) { 1267 /* send SDTR */ 1268 int cnt = 0; 1269 1270 if ((ti->flag & WIDE_NEGO_DONE) == 0) 1271 sc->sc_msgbuf[cnt++] = 1272 MSG_IDENTIFY(periph->periph_lun, 0); 1273 1274 sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1275 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1276 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1277 sc->sc_msgbuf[cnt++] = ti->period; 1278 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1279 sc->sc_msgcnt = cnt; 1280 ti->flag |= SYNC_NEGO_DOING; 1281 } 1282 } 1283 if (sc->sc_msgcnt == 0) { 1284 sc->sc_msgbuf[0] = MSG_ABORT; 1285 sc->sc_msgcnt = 1; 1286 sc->sc_state = TRM_ABORT_SENT; 1287 } 1288 1289 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1290 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1291 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1292 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1293 1294 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1295 sc->sc_msgbuf, sc->sc_msgcnt); 1296 sc->sc_msgcnt = 0; 1297 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1298 1299 /* it's important for atn stop */ 1300 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1301 1302 /* 1303 * SCSI command 1304 */ 1305 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1306 } 1307 1308 static void 1309 trm_command_phase1(sc) 1310 struct trm_softc *sc; 1311 { 1312 bus_space_tag_t iot = sc->sc_iot; 1313 bus_space_handle_t ioh = sc->sc_ioh; 1314 struct trm_srb *srb; 1315 1316 srb = sc->sc_actsrb; 1317 if (srb == NULL) { 1318 DPRINTF(("trm_command_phase1: no active srb\n")); 1319 return; 1320 } 1321 1322 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1323 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1324 1325 sc->sc_state = TRM_COMMAND; 1326 /* it's important for atn stop */ 1327 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1328 1329 /* 1330 * SCSI command 1331 */ 1332 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1333 } 1334 1335 static void 1336 trm_dataout_phase0(sc, stat) 1337 struct trm_softc *sc; 1338 int stat; 1339 { 1340 bus_space_tag_t iot = sc->sc_iot; 1341 bus_space_handle_t ioh = sc->sc_ioh; 1342 struct trm_srb *srb; 1343 struct scsipi_periph *periph; 1344 struct trm_tinfo *ti; 1345 struct trm_sg_entry *sg; 1346 int sgindex; 1347 u_int32_t xferlen, leftcnt = 0; 1348 1349 if (sc->sc_state == TRM_XFERPAD) 1350 return; 1351 1352 srb = sc->sc_actsrb; 1353 if (srb == NULL) { 1354 DPRINTF(("trm_dataout_phase0: no active srb\n")); 1355 return; 1356 } 1357 periph = srb->xs->xs_periph; 1358 ti = &sc->sc_tinfo[periph->periph_target]; 1359 1360 if ((stat & PARITYERROR) != 0) 1361 srb->flag |= PARITY_ERROR; 1362 1363 if ((stat & SCSIXFERDONE) == 0) { 1364 /* 1365 * when data transfer from DMA FIFO to SCSI FIFO 1366 * if there was some data left in SCSI FIFO 1367 */ 1368 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1369 SCSI_FIFOCNT_MASK; 1370 if (ti->synctl & WIDE_SYNC) 1371 /* 1372 * if WIDE scsi SCSI FIFOCNT unit is word 1373 * so need to * 2 1374 */ 1375 leftcnt <<= 1; 1376 } 1377 /* 1378 * calculate all the residue data that was not yet transferred 1379 * SCSI transfer counter + left in SCSI FIFO data 1380 * 1381 * .....TRM_SCSI_XCNT (24bits) 1382 * The counter always decrements by one for every SCSI 1383 * byte transfer. 1384 * .....TRM_SCSI_FIFOCNT ( 5bits) 1385 * The counter is SCSI FIFO offset counter 1386 */ 1387 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1388 if (leftcnt == 1) { 1389 leftcnt = 0; 1390 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1391 } 1392 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1393 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1394 DMAXFERCOMP) == 0) 1395 ; /* XXX needs timeout */ 1396 1397 srb->buflen = 0; 1398 } else { 1399 /* Update SG list */ 1400 1401 /* 1402 * if transfer not yet complete 1403 * there were some data residue in SCSI FIFO or 1404 * SCSI transfer counter not empty 1405 */ 1406 if (srb->buflen != leftcnt) { 1407 /* data that had transferred length */ 1408 xferlen = srb->buflen - leftcnt; 1409 1410 /* next time to be transferred length */ 1411 srb->buflen = leftcnt; 1412 1413 /* 1414 * parsing from last time disconnect sgindex 1415 */ 1416 sg = srb->sgentry + srb->sgindex; 1417 for (sgindex = srb->sgindex; 1418 sgindex < srb->sgcnt; 1419 sgindex++, sg++) { 1420 /* 1421 * find last time which SG transfer 1422 * be disconnect 1423 */ 1424 if (xferlen >= le32toh(sg->length)) 1425 xferlen -= le32toh(sg->length); 1426 else { 1427 /* 1428 * update last time 1429 * disconnected SG list 1430 */ 1431 /* residue data length */ 1432 sg->length = 1433 htole32(le32toh(sg->length) 1434 - xferlen); 1435 /* residue data pointer */ 1436 sg->address = 1437 htole32(le32toh(sg->address) 1438 + xferlen); 1439 srb->sgindex = sgindex; 1440 break; 1441 } 1442 } 1443 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1444 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1445 } 1446 } 1447 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1448 } 1449 1450 static void 1451 trm_datain_phase0(sc, stat) 1452 struct trm_softc *sc; 1453 int stat; 1454 { 1455 bus_space_tag_t iot = sc->sc_iot; 1456 bus_space_handle_t ioh = sc->sc_ioh; 1457 struct trm_srb *srb; 1458 struct trm_sg_entry *sg; 1459 int sgindex; 1460 u_int32_t xferlen, leftcnt = 0; 1461 1462 if (sc->sc_state == TRM_XFERPAD) 1463 return; 1464 1465 srb = sc->sc_actsrb; 1466 if (srb == NULL) { 1467 DPRINTF(("trm_datain_phase0: no active srb\n")); 1468 return; 1469 } 1470 1471 if (stat & PARITYERROR) 1472 srb->flag |= PARITY_ERROR; 1473 1474 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1475 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1476 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1477 DMAXFERCOMP) == 0) 1478 ; /* XXX needs timeout */ 1479 1480 srb->buflen = 0; 1481 } else { /* phase changed */ 1482 /* 1483 * parsing the case: 1484 * when a transfer not yet complete 1485 * but be disconnected by upper layer 1486 * if transfer not yet complete 1487 * there were some data residue in SCSI FIFO or 1488 * SCSI transfer counter not empty 1489 */ 1490 if (srb->buflen != leftcnt) { 1491 /* 1492 * data that had transferred length 1493 */ 1494 xferlen = srb->buflen - leftcnt; 1495 1496 /* 1497 * next time to be transferred length 1498 */ 1499 srb->buflen = leftcnt; 1500 1501 /* 1502 * parsing from last time disconnect sgindex 1503 */ 1504 sg = srb->sgentry + srb->sgindex; 1505 for (sgindex = srb->sgindex; 1506 sgindex < srb->sgcnt; 1507 sgindex++, sg++) { 1508 /* 1509 * find last time which SG transfer 1510 * be disconnect 1511 */ 1512 if (xferlen >= le32toh(sg->length)) 1513 xferlen -= le32toh(sg->length); 1514 else { 1515 /* 1516 * update last time 1517 * disconnected SG list 1518 */ 1519 /* residue data length */ 1520 sg->length = 1521 htole32(le32toh(sg->length) 1522 - xferlen); 1523 /* residue data pointer */ 1524 sg->address = 1525 htole32(le32toh(sg->address) 1526 + xferlen); 1527 srb->sgindex = sgindex; 1528 break; 1529 } 1530 } 1531 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1532 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1533 } 1534 } 1535 } 1536 1537 static void 1538 trm_dataio_xfer(sc, iodir) 1539 struct trm_softc *sc; 1540 int iodir; 1541 { 1542 bus_space_tag_t iot = sc->sc_iot; 1543 bus_space_handle_t ioh = sc->sc_ioh; 1544 struct trm_srb *srb; 1545 struct scsipi_periph *periph; 1546 struct trm_tinfo *ti; 1547 1548 srb = sc->sc_actsrb; 1549 if (srb == NULL) { 1550 DPRINTF(("trm_dataio_xfer: no active srb\n")); 1551 return; 1552 } 1553 periph = srb->xs->xs_periph; 1554 ti = &sc->sc_tinfo[periph->periph_target]; 1555 1556 if (srb->sgindex < srb->sgcnt) { 1557 if (srb->buflen > 0) { 1558 /* 1559 * load what physical address of Scatter/Gather 1560 * list table want to be transfer 1561 */ 1562 sc->sc_state = TRM_DATA_XFER; 1563 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1564 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1565 srb->sgaddr + 1566 srb->sgindex * sizeof(struct trm_sg_entry)); 1567 /* 1568 * load how many bytes in the Scatter/Gather list table 1569 */ 1570 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1571 (srb->sgcnt - srb->sgindex) 1572 * sizeof(struct trm_sg_entry)); 1573 /* 1574 * load total xfer length (24bits) max value 16Mbyte 1575 */ 1576 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1577 /* Start DMA transfer */ 1578 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1579 iodir | SGXFER); 1580 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1581 STARTDMAXFER); 1582 1583 /* Start SCSI transfer */ 1584 /* it's important for atn stop */ 1585 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1586 DO_DATALATCH); 1587 1588 /* 1589 * SCSI command 1590 */ 1591 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1592 (iodir == XFERDATAOUT) ? 1593 SCMD_DMA_OUT : SCMD_DMA_IN); 1594 } else { /* xfer pad */ 1595 if (srb->sgcnt) { 1596 srb->hastat = H_OVER_UNDER_RUN; 1597 } 1598 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1599 (ti->synctl & WIDE_SYNC) ? 2 : 1); 1600 1601 if (iodir == XFERDATAOUT) 1602 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1603 else 1604 bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1605 1606 sc->sc_state = TRM_XFERPAD; 1607 /* it's important for atn stop */ 1608 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1609 DO_DATALATCH); 1610 1611 /* 1612 * SCSI command 1613 */ 1614 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1615 (iodir == XFERDATAOUT) ? 1616 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1617 } 1618 } 1619 } 1620 1621 static void 1622 trm_status_phase0(sc) 1623 struct trm_softc *sc; 1624 { 1625 bus_space_tag_t iot = sc->sc_iot; 1626 bus_space_handle_t ioh = sc->sc_ioh; 1627 struct trm_srb *srb; 1628 1629 srb = sc->sc_actsrb; 1630 if (srb == NULL) { 1631 DPRINTF(("trm_status_phase0: no active srb\n")); 1632 return; 1633 } 1634 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1635 sc->sc_state = TRM_COMPLETED; 1636 /* it's important for atn stop */ 1637 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1638 1639 /* 1640 * SCSI command 1641 */ 1642 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1643 } 1644 1645 static void 1646 trm_status_phase1(sc) 1647 struct trm_softc *sc; 1648 { 1649 bus_space_tag_t iot = sc->sc_iot; 1650 bus_space_handle_t ioh = sc->sc_ioh; 1651 1652 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1653 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1654 & SCSI_FIFO_EMPTY) == 0) 1655 bus_space_write_2(iot, ioh, 1656 TRM_SCSI_CONTROL, DO_CLRFIFO); 1657 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1658 & DMA_FIFO_EMPTY) == 0) 1659 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1660 } else { 1661 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1662 & DMA_FIFO_EMPTY) == 0) 1663 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1664 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1665 & SCSI_FIFO_EMPTY) == 0) 1666 bus_space_write_2(iot, ioh, 1667 TRM_SCSI_CONTROL, DO_CLRFIFO); 1668 } 1669 sc->sc_state = TRM_STATUS; 1670 /* it's important for atn stop */ 1671 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1672 1673 /* 1674 * SCSI command 1675 */ 1676 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1677 } 1678 1679 static void 1680 trm_msgin_phase0(sc) 1681 struct trm_softc *sc; 1682 { 1683 bus_space_tag_t iot = sc->sc_iot; 1684 bus_space_handle_t ioh = sc->sc_ioh; 1685 struct trm_srb *srb; 1686 struct scsipi_periph *periph; 1687 struct trm_tinfo *ti; 1688 int index; 1689 u_int8_t msgin_code; 1690 1691 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1692 if (sc->sc_state != TRM_EXTEND_MSGIN) { 1693 DPRINTF(("msgin: code = %02x\n", msgin_code)); 1694 switch (msgin_code) { 1695 case MSG_DISCONNECT: 1696 sc->sc_state = TRM_DISCONNECTED; 1697 break; 1698 1699 case MSG_SAVEDATAPOINTER: 1700 break; 1701 1702 case MSG_EXTENDED: 1703 case MSG_SIMPLE_Q_TAG: 1704 case MSG_HEAD_OF_Q_TAG: 1705 case MSG_ORDERED_Q_TAG: 1706 sc->sc_state = TRM_EXTEND_MSGIN; 1707 /* extended message (01h) */ 1708 sc->sc_msgbuf[0] = msgin_code; 1709 1710 sc->sc_msgcnt = 1; 1711 /* extended message length (n) */ 1712 sc->sc_msg = &sc->sc_msgbuf[1]; 1713 1714 break; 1715 case MSG_MESSAGE_REJECT: 1716 /* Reject message */ 1717 srb = sc->sc_actsrb; 1718 if (srb == NULL) { 1719 DPRINTF(("trm_msgin_phase0: " 1720 " message reject without actsrb\n")); 1721 break; 1722 } 1723 periph = srb->xs->xs_periph; 1724 ti = &sc->sc_tinfo[periph->periph_target]; 1725 1726 if (ti->flag & WIDE_NEGO_ENABLE) { 1727 /* do wide nego reject */ 1728 ti->flag |= WIDE_NEGO_DONE; 1729 ti->flag &= 1730 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1731 if ((ti->flag & SYNC_NEGO_ENABLE) && 1732 (ti->flag & SYNC_NEGO_DONE) == 0) { 1733 /* Set ATN, in case ATN was clear */ 1734 sc->sc_state = TRM_MSGOUT; 1735 bus_space_write_2(iot, ioh, 1736 TRM_SCSI_CONTROL, DO_SETATN); 1737 } else 1738 /* Clear ATN */ 1739 bus_space_write_2(iot, ioh, 1740 TRM_SCSI_CONTROL, DO_CLRATN); 1741 } else if (ti->flag & SYNC_NEGO_ENABLE) { 1742 /* do sync nego reject */ 1743 bus_space_write_2(iot, ioh, 1744 TRM_SCSI_CONTROL, DO_CLRATN); 1745 if (ti->flag & SYNC_NEGO_DOING) { 1746 ti->flag &=~(SYNC_NEGO_ENABLE | 1747 SYNC_NEGO_DONE); 1748 ti->synctl = 0; 1749 ti->offset = 0; 1750 bus_space_write_1(iot, ioh, 1751 TRM_SCSI_SYNC, ti->synctl); 1752 bus_space_write_1(iot, ioh, 1753 TRM_SCSI_OFFSET, ti->offset); 1754 } 1755 } 1756 break; 1757 1758 case MSG_IGN_WIDE_RESIDUE: 1759 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1760 bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1761 break; 1762 1763 default: 1764 /* 1765 * Restore data pointer message 1766 * Save data pointer message 1767 * Completion message 1768 * NOP message 1769 */ 1770 break; 1771 } 1772 } else { 1773 /* 1774 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1775 * Parsing incoming extented messages 1776 */ 1777 *sc->sc_msg++ = msgin_code; 1778 sc->sc_msgcnt++; 1779 1780 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1781 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1782 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1783 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1784 1785 switch (sc->sc_msgbuf[0]) { 1786 case MSG_SIMPLE_Q_TAG: 1787 case MSG_HEAD_OF_Q_TAG: 1788 case MSG_ORDERED_Q_TAG: 1789 /* 1790 * is QUEUE tag message : 1791 * 1792 * byte 0: 1793 * HEAD QUEUE TAG (20h) 1794 * ORDERED QUEUE TAG (21h) 1795 * SIMPLE QUEUE TAG (22h) 1796 * byte 1: 1797 * Queue tag (00h - FFh) 1798 */ 1799 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1800 /* XXX XXX XXX */ 1801 struct trm_linfo *li; 1802 int tagid; 1803 1804 sc->sc_flag &= ~WAIT_TAGMSG; 1805 tagid = sc->sc_msgbuf[1]; 1806 ti = &sc->sc_tinfo[sc->resel_target]; 1807 li = ti->linfo[sc->resel_lun]; 1808 srb = li->queued[tagid]; 1809 if (srb != NULL) { 1810 sc->sc_actsrb = srb; 1811 sc->sc_state = TRM_DATA_XFER; 1812 break; 1813 } else { 1814 printf("%s: invalid tag id\n", 1815 sc->sc_dev.dv_xname); 1816 } 1817 1818 sc->sc_state = TRM_UNEXPECT_RESEL; 1819 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1820 sc->sc_msgcnt = 1; 1821 bus_space_write_2(iot, ioh, 1822 TRM_SCSI_CONTROL, DO_SETATN); 1823 } else 1824 sc->sc_state = TRM_IDLE; 1825 break; 1826 1827 case MSG_EXTENDED: 1828 srb = sc->sc_actsrb; 1829 if (srb == NULL) { 1830 DPRINTF(("trm_msgin_phase0: " 1831 "extended message without actsrb\n")); 1832 break; 1833 } 1834 periph = srb->xs->xs_periph; 1835 ti = &sc->sc_tinfo[periph->periph_target]; 1836 1837 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1838 sc->sc_msgcnt == 4) { 1839 /* 1840 * is Wide data xfer Extended message : 1841 * ====================================== 1842 * WIDE DATA TRANSFER REQUEST 1843 * ====================================== 1844 * byte 0 : Extended message (01h) 1845 * byte 1 : Extended message length (02h) 1846 * byte 2 : WIDE DATA TRANSFER code (03h) 1847 * byte 3 : Transfer width exponent 1848 */ 1849 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1850 /* Length is wrong, reject it */ 1851 ti->flag &= ~(WIDE_NEGO_ENABLE | 1852 WIDE_NEGO_DONE); 1853 sc->sc_state = TRM_MSGOUT; 1854 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1855 sc->sc_msgcnt = 1; 1856 bus_space_write_2(iot, ioh, 1857 TRM_SCSI_CONTROL, DO_SETATN); 1858 break; 1859 } 1860 1861 if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1862 sc->sc_msgbuf[3] = 1863 MSG_EXT_WDTR_BUS_8_BIT; 1864 1865 if (sc->sc_msgbuf[3] > 1866 MSG_EXT_WDTR_BUS_32_BIT) { 1867 /* reject_msg: */ 1868 ti->flag &= ~(WIDE_NEGO_ENABLE | 1869 WIDE_NEGO_DONE); 1870 sc->sc_state = TRM_MSGOUT; 1871 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1872 sc->sc_msgcnt = 1; 1873 bus_space_write_2(iot, ioh, 1874 TRM_SCSI_CONTROL, DO_SETATN); 1875 break; 1876 } 1877 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1878 /* do 16 bits */ 1879 sc->sc_msgbuf[3] = 1880 MSG_EXT_WDTR_BUS_16_BIT; 1881 if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1882 ti->flag |= WIDE_NEGO_DONE; 1883 ti->flag &= ~(SYNC_NEGO_DONE | 1884 WIDE_NEGO_ENABLE); 1885 if (sc->sc_msgbuf[3] != 1886 MSG_EXT_WDTR_BUS_8_BIT) 1887 /* is Wide data xfer */ 1888 ti->synctl |= WIDE_SYNC; 1889 trm_update_xfer_mode(sc, 1890 periph->periph_target); 1891 } 1892 1893 sc->sc_state = TRM_MSGOUT; 1894 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1895 DO_SETATN); 1896 break; 1897 1898 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1899 sc->sc_msgcnt == 5) { 1900 /* 1901 * is 8bit transfer Extended message : 1902 * ================================= 1903 * SYNCHRONOUS DATA TRANSFER REQUEST 1904 * ================================= 1905 * byte 0 : Extended message (01h) 1906 * byte 1 : Extended message length (03) 1907 * byte 2 : SYNC DATA TRANSFER code (01h) 1908 * byte 3 : Transfer period factor 1909 * byte 4 : REQ/ACK offset 1910 */ 1911 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1912 /* reject_msg */ 1913 sc->sc_state = TRM_MSGOUT; 1914 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1915 sc->sc_msgcnt = 1; 1916 bus_space_write_2(iot, ioh, 1917 TRM_SCSI_CONTROL, DO_SETATN); 1918 break; 1919 } 1920 1921 if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1922 ti->flag &= 1923 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1924 ti->flag |= SYNC_NEGO_DONE; 1925 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1926 sc->sc_msgbuf[3] = 0; 1927 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1928 sc->sc_msgbuf[4] = 1929 TRM_MAX_OFFSET; 1930 1931 if (sc->sc_msgbuf[3] == 0 || 1932 sc->sc_msgbuf[4] == 0) { 1933 /* set async */ 1934 ti->synctl = 0; 1935 ti->offset = 0; 1936 } else { 1937 /* set sync */ 1938 /* Transfer period factor */ 1939 ti->period = sc->sc_msgbuf[3]; 1940 /* REQ/ACK offset */ 1941 ti->offset = sc->sc_msgbuf[4]; 1942 for (index = 0; 1943 index < NPERIOD; 1944 index++) 1945 if (ti->period <= 1946 trm_clock_period[ 1947 index]) 1948 break; 1949 1950 ti->synctl |= ALT_SYNC | index; 1951 } 1952 /* 1953 * program SCSI control register 1954 */ 1955 bus_space_write_1(iot, ioh, 1956 TRM_SCSI_SYNC, ti->synctl); 1957 bus_space_write_1(iot, ioh, 1958 TRM_SCSI_OFFSET, ti->offset); 1959 trm_update_xfer_mode(sc, 1960 periph->periph_target); 1961 } 1962 sc->sc_state = TRM_IDLE; 1963 } 1964 break; 1965 default: 1966 break; 1967 } 1968 } 1969 1970 /* it's important for atn stop */ 1971 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1972 1973 /* 1974 * SCSI command 1975 */ 1976 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1977 } 1978 1979 static void 1980 trm_msgin_phase1(sc) 1981 struct trm_softc *sc; 1982 { 1983 bus_space_tag_t iot = sc->sc_iot; 1984 bus_space_handle_t ioh = sc->sc_ioh; 1985 1986 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1987 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1988 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1989 sc->sc_state = TRM_MSGIN; 1990 } 1991 1992 /* it's important for atn stop */ 1993 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1994 1995 /* 1996 * SCSI command 1997 */ 1998 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1999 } 2000 2001 static void 2002 trm_disconnect(sc) 2003 struct trm_softc *sc; 2004 { 2005 bus_space_tag_t iot = sc->sc_iot; 2006 bus_space_handle_t ioh = sc->sc_ioh; 2007 struct trm_srb *srb; 2008 int s; 2009 2010 s = splbio(); 2011 2012 srb = sc->sc_actsrb; 2013 DPRINTF(("trm_disconnect...............\n")); 2014 2015 if (srb == NULL) { 2016 DPRINTF(("trm_disconnect: no active srb\n")); 2017 DELAY(1000); /* 1 msec */ 2018 2019 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2020 DO_CLRFIFO | DO_HWRESELECT); 2021 return; 2022 } 2023 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2024 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2025 DO_CLRFIFO | DO_HWRESELECT); 2026 DELAY(100); 2027 2028 switch (sc->sc_state) { 2029 case TRM_UNEXPECT_RESEL: 2030 sc->sc_state = TRM_IDLE; 2031 break; 2032 2033 case TRM_ABORT_SENT: 2034 goto finish; 2035 2036 case TRM_START: 2037 case TRM_MSGOUT: 2038 { 2039 /* Selection time out - discard all LUNs if empty */ 2040 struct scsipi_periph *periph; 2041 struct trm_tinfo *ti; 2042 struct trm_linfo *li; 2043 int lun; 2044 2045 DPRINTF(("selection timeout\n")); 2046 2047 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2048 2049 periph = srb->xs->xs_periph; 2050 ti = &sc->sc_tinfo[periph->periph_target]; 2051 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2052 li = ti->linfo[lun]; 2053 if (li != NULL && 2054 li->untagged == NULL && li->used == 0) { 2055 ti->linfo[lun] = NULL; 2056 free(li, M_DEVBUF); 2057 } 2058 } 2059 } 2060 goto finish; 2061 2062 case TRM_DISCONNECTED: 2063 sc->sc_actsrb = NULL; 2064 sc->sc_state = TRM_IDLE; 2065 goto sched; 2066 2067 case TRM_COMPLETED: 2068 goto finish; 2069 } 2070 2071 out: 2072 splx(s); 2073 return; 2074 2075 finish: 2076 sc->sc_state = TRM_IDLE; 2077 trm_done(sc, srb); 2078 goto out; 2079 2080 sched: 2081 trm_sched(sc); 2082 goto out; 2083 } 2084 2085 static void 2086 trm_reselect(sc) 2087 struct trm_softc *sc; 2088 { 2089 bus_space_tag_t iot = sc->sc_iot; 2090 bus_space_handle_t ioh = sc->sc_ioh; 2091 struct trm_tinfo *ti; 2092 struct trm_linfo *li; 2093 int target, lun; 2094 2095 DPRINTF(("trm_reselect.................\n")); 2096 2097 if (sc->sc_actsrb != NULL) { 2098 /* arbitration lost but reselection win */ 2099 sc->sc_state = TRM_READY; 2100 target = sc->sc_actsrb->xs->xs_periph->periph_target; 2101 ti = &sc->sc_tinfo[target]; 2102 } else { 2103 /* Read Reselected Target Id and LUN */ 2104 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2105 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2106 ti = &sc->sc_tinfo[target]; 2107 li = ti->linfo[lun]; 2108 DPRINTF(("target = %d, lun = %d\n", target, lun)); 2109 2110 /* 2111 * Check to see if we are running an un-tagged command. 2112 * Otherwise ack the IDENTIFY and wait for a tag message. 2113 */ 2114 if (li != NULL) { 2115 if (li->untagged != NULL && li->busy) { 2116 sc->sc_actsrb = li->untagged; 2117 sc->sc_state = TRM_DATA_XFER; 2118 } else { 2119 sc->resel_target = target; 2120 sc->resel_lun = lun; 2121 /* XXX XXX XXX */ 2122 sc->sc_flag |= WAIT_TAGMSG; 2123 } 2124 } 2125 2126 if ((ti->flag & USE_TAG_QUEUING) == 0 && 2127 sc->sc_actsrb == NULL) { 2128 printf("%s: reselect from target %d lun %d " 2129 "without nexus; sending abort\n", 2130 sc->sc_dev.dv_xname, target, lun); 2131 sc->sc_state = TRM_UNEXPECT_RESEL; 2132 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2133 sc->sc_msgcnt = 1; 2134 bus_space_write_2(iot, ioh, 2135 TRM_SCSI_CONTROL, DO_SETATN); 2136 } 2137 } 2138 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2139 /* 2140 * Program HA ID, target ID, period and offset 2141 */ 2142 /* target ID */ 2143 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2144 2145 /* host ID */ 2146 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2147 2148 /* period */ 2149 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2150 2151 /* offset */ 2152 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2153 2154 /* it's important for atn stop */ 2155 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2156 /* 2157 * SCSI command 2158 */ 2159 /* to rls the /ACK signal */ 2160 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2161 } 2162 2163 /* 2164 * Complete execution of a SCSI command 2165 * Signal completion to the generic SCSI driver 2166 */ 2167 static void 2168 trm_done(sc, srb) 2169 struct trm_softc *sc; 2170 struct trm_srb *srb; 2171 { 2172 struct scsipi_xfer *xs = srb->xs; 2173 2174 DPRINTF(("trm_done..................\n")); 2175 2176 if (xs == NULL) 2177 return; 2178 2179 if ((xs->xs_control & XS_CTL_POLL) == 0) 2180 callout_stop(&xs->xs_callout); 2181 2182 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2183 srb->flag & AUTO_REQSENSE) { 2184 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2185 srb->dmap->dm_mapsize, 2186 ((xs->xs_control & XS_CTL_DATA_IN) || 2187 (srb->flag & AUTO_REQSENSE)) ? 2188 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2189 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2190 } 2191 2192 /* 2193 * target status 2194 */ 2195 xs->status = srb->tastat; 2196 2197 DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2198 2199 switch (xs->status) { 2200 case SCSI_OK: 2201 /* 2202 * process initiator status...... 2203 * Adapter (initiator) status 2204 */ 2205 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2206 printf("%s: over/under run error\n", 2207 sc->sc_dev.dv_xname); 2208 srb->tastat = 0; 2209 /* Illegal length (over/under run) */ 2210 xs->error = XS_DRIVER_STUFFUP; 2211 } else if ((srb->flag & PARITY_ERROR) != 0) { 2212 printf("%s: parity error\n", 2213 sc->sc_dev.dv_xname); 2214 /* Driver failed to perform operation */ 2215 xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2216 } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2217 xs->resid = srb->buflen; 2218 xs->error = XS_TIMEOUT; 2219 } else { 2220 /* No error */ 2221 xs->resid = srb->buflen; 2222 srb->hastat = 0; 2223 if (srb->flag & AUTO_REQSENSE) { 2224 /* there is no error, (sense is invalid) */ 2225 xs->error = XS_SENSE; 2226 } else { 2227 srb->tastat = 0; 2228 xs->error = XS_NOERROR; 2229 } 2230 } 2231 break; 2232 2233 case SCSI_CHECK: 2234 if ((srb->flag & AUTO_REQSENSE) != 0 || 2235 trm_request_sense(sc, srb) != 0) { 2236 printf("%s: request sense failed\n", 2237 sc->sc_dev.dv_xname); 2238 xs->error = XS_DRIVER_STUFFUP; 2239 break; 2240 } 2241 xs->error = XS_SENSE; 2242 return; 2243 2244 case SCSI_SEL_TIMEOUT: 2245 srb->hastat = H_SEL_TIMEOUT; 2246 srb->tastat = 0; 2247 xs->error = XS_SELTIMEOUT; 2248 break; 2249 2250 case SCSI_QUEUE_FULL: 2251 case SCSI_BUSY: 2252 xs->error = XS_BUSY; 2253 break; 2254 2255 case SCSI_RESV_CONFLICT: 2256 DPRINTF(("%s: target reserved at ", sc->sc_dev.dv_xname)); 2257 DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2258 xs->error = XS_BUSY; 2259 break; 2260 2261 default: 2262 srb->hastat = 0; 2263 printf("%s: trm_done(): unknown status = %02x\n", 2264 sc->sc_dev.dv_xname, xs->status); 2265 xs->error = XS_DRIVER_STUFFUP; 2266 break; 2267 } 2268 2269 trm_dequeue(sc, srb); 2270 if (srb == sc->sc_actsrb) { 2271 sc->sc_actsrb = NULL; 2272 trm_sched(sc); 2273 } 2274 2275 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2276 2277 /* Notify cmd done */ 2278 scsipi_done(xs); 2279 } 2280 2281 static int 2282 trm_request_sense(sc, srb) 2283 struct trm_softc *sc; 2284 struct trm_srb *srb; 2285 { 2286 struct scsipi_xfer *xs; 2287 struct scsipi_periph *periph; 2288 struct trm_tinfo *ti; 2289 struct trm_linfo *li; 2290 struct scsipi_sense *ss = (struct scsipi_sense *)srb->cmd; 2291 int error; 2292 2293 DPRINTF(("trm_request_sense...\n")); 2294 2295 xs = srb->xs; 2296 periph = xs->xs_periph; 2297 2298 srb->flag |= AUTO_REQSENSE; 2299 2300 /* Status of initiator/target */ 2301 srb->hastat = 0; 2302 srb->tastat = 0; 2303 2304 ss->opcode = REQUEST_SENSE; 2305 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2306 ss->unused[0] = ss->unused[1] = 0; 2307 ss->length = sizeof(struct scsipi_sense_data); 2308 ss->control = 0; 2309 2310 srb->buflen = sizeof(struct scsipi_sense_data); 2311 srb->sgcnt = 1; 2312 srb->sgindex = 0; 2313 srb->cmdlen = sizeof(struct scsipi_sense); 2314 2315 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2316 &xs->sense.scsi_sense, srb->buflen, NULL, 2317 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2318 return error; 2319 } 2320 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2321 srb->buflen, BUS_DMASYNC_PREREAD); 2322 2323 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2324 srb->sgentry[0].length = htole32(sizeof(struct scsipi_sense_data)); 2325 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2326 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2327 2328 ti = &sc->sc_tinfo[periph->periph_target]; 2329 li = ti->linfo[periph->periph_lun]; 2330 if (li->busy > 0) 2331 li->busy = 0; 2332 trm_dequeue(sc, srb); 2333 li->untagged = srb; /* must be executed first to fix C/A */ 2334 li->busy = 2; 2335 2336 if (srb == sc->sc_actsrb) 2337 trm_select(sc, srb); 2338 else { 2339 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2340 if (sc->sc_actsrb == NULL) 2341 trm_sched(sc); 2342 } 2343 return 0; 2344 } 2345 2346 static void 2347 trm_dequeue(sc, srb) 2348 struct trm_softc *sc; 2349 struct trm_srb *srb; 2350 { 2351 struct scsipi_periph *periph; 2352 struct trm_tinfo *ti; 2353 struct trm_linfo *li; 2354 2355 periph = srb->xs->xs_periph; 2356 ti = &sc->sc_tinfo[periph->periph_target]; 2357 li = ti->linfo[periph->periph_lun]; 2358 2359 if (li->untagged == srb) { 2360 li->busy = 0; 2361 li->untagged = NULL; 2362 } 2363 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2364 li->queued[srb->tag[1]] = NULL; 2365 li->used--; 2366 } 2367 } 2368 2369 static void 2370 trm_reset_scsi_bus(sc) 2371 struct trm_softc *sc; 2372 { 2373 bus_space_tag_t iot = sc->sc_iot; 2374 bus_space_handle_t ioh = sc->sc_ioh; 2375 int timeout, s; 2376 2377 DPRINTF(("trm_reset_scsi_bus.........\n")); 2378 2379 s = splbio(); 2380 2381 sc->sc_flag |= RESET_DEV; 2382 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2383 for (timeout = 20000; timeout >= 0; timeout--) { 2384 DELAY(1); 2385 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2386 INT_SCSIRESET) == 0) 2387 break; 2388 } 2389 if (timeout == 0) 2390 printf(": scsibus reset timeout\n"); 2391 2392 splx(s); 2393 } 2394 2395 static void 2396 trm_scsi_reset_detect(sc) 2397 struct trm_softc *sc; 2398 { 2399 bus_space_tag_t iot = sc->sc_iot; 2400 bus_space_handle_t ioh = sc->sc_ioh; 2401 int s; 2402 2403 DPRINTF(("trm_scsi_reset_detect...............\n")); 2404 DELAY(1000000); /* delay 1 sec */ 2405 2406 s = splbio(); 2407 2408 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2409 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2410 2411 if (sc->sc_flag & RESET_DEV) { 2412 sc->sc_flag |= RESET_DONE; 2413 } else { 2414 sc->sc_flag |= RESET_DETECT; 2415 sc->sc_actsrb = NULL; 2416 sc->sc_flag = 0; 2417 trm_sched(sc); 2418 } 2419 splx(s); 2420 } 2421 2422 /* 2423 * read seeprom 128 bytes to struct eeprom and check checksum. 2424 * If it is wrong, update with default value. 2425 */ 2426 static void 2427 trm_check_eeprom(sc, eeprom) 2428 struct trm_softc *sc; 2429 struct trm_nvram *eeprom; 2430 { 2431 struct nvram_target *target; 2432 u_int16_t *ep; 2433 u_int16_t chksum; 2434 int i; 2435 2436 DPRINTF(("trm_check_eeprom......\n")); 2437 trm_eeprom_read_all(sc, eeprom); 2438 ep = (u_int16_t *)eeprom; 2439 chksum = 0; 2440 for (i = 0; i < 64; i++) 2441 chksum += le16toh(*ep++); 2442 2443 if (chksum != TRM_NVRAM_CKSUM) { 2444 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2445 /* 2446 * Checksum error, load default 2447 */ 2448 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2449 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2450 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2451 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2452 eeprom->subclass = 0x00; 2453 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2454 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2455 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2456 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2457 eeprom->reserved0 = 0x00; 2458 2459 for (i = 0, target = eeprom->target; 2460 i < TRM_MAX_TARGETS; 2461 i++, target++) { 2462 target->config0 = 0x77; 2463 target->period = 0x00; 2464 target->config2 = 0x00; 2465 target->config3 = 0x00; 2466 } 2467 2468 eeprom->scsi_id = 7; 2469 eeprom->channel_cfg = 0x0F; 2470 eeprom->delay_time = 0; 2471 eeprom->max_tag = 4; 2472 eeprom->reserved1 = 0x15; 2473 eeprom->boot_target = 0; 2474 eeprom->boot_lun = 0; 2475 eeprom->reserved2 = 0; 2476 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2477 2478 chksum = 0; 2479 ep = (u_int16_t *)eeprom; 2480 for (i = 0; i < 63; i++) 2481 chksum += le16toh(*ep++); 2482 2483 chksum = TRM_NVRAM_CKSUM - chksum; 2484 eeprom->checksum0 = chksum & 0xFF; 2485 eeprom->checksum1 = chksum >> 8; 2486 2487 trm_eeprom_write_all(sc, eeprom); 2488 } 2489 } 2490 2491 /* 2492 * write struct eeprom 128 bytes to seeprom 2493 */ 2494 static void 2495 trm_eeprom_write_all(sc, eeprom) 2496 struct trm_softc *sc; 2497 struct trm_nvram *eeprom; 2498 { 2499 bus_space_tag_t iot = sc->sc_iot; 2500 bus_space_handle_t ioh = sc->sc_ioh; 2501 u_int8_t *buf = (u_int8_t *)eeprom; 2502 u_int8_t addr; 2503 2504 /* Enable SEEPROM */ 2505 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2506 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2507 2508 /* 2509 * Write enable 2510 */ 2511 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2512 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2513 trm_eeprom_wait(); 2514 2515 for (addr = 0; addr < 128; addr++, buf++) 2516 trm_eeprom_set_data(sc, addr, *buf); 2517 2518 /* 2519 * Write disable 2520 */ 2521 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2522 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2523 trm_eeprom_wait(); 2524 2525 /* Disable SEEPROM */ 2526 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2527 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2528 } 2529 2530 /* 2531 * write one byte to seeprom 2532 */ 2533 static void 2534 trm_eeprom_set_data(sc, addr, data) 2535 struct trm_softc *sc; 2536 u_int8_t addr; 2537 u_int8_t data; 2538 { 2539 bus_space_tag_t iot = sc->sc_iot; 2540 bus_space_handle_t ioh = sc->sc_ioh; 2541 int i; 2542 u_int8_t send; 2543 2544 /* 2545 * Send write command & address 2546 */ 2547 trm_eeprom_write_cmd(sc, 0x05, addr); 2548 /* 2549 * Write data 2550 */ 2551 for (i = 0; i < 8; i++, data <<= 1) { 2552 send = NVR_SELECT; 2553 if (data & 0x80) /* Start from bit 7 */ 2554 send |= NVR_BITOUT; 2555 2556 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2557 trm_eeprom_wait(); 2558 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2559 trm_eeprom_wait(); 2560 } 2561 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2562 trm_eeprom_wait(); 2563 /* 2564 * Disable chip select 2565 */ 2566 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2567 trm_eeprom_wait(); 2568 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2569 trm_eeprom_wait(); 2570 /* 2571 * Wait for write ready 2572 */ 2573 for (;;) { 2574 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2575 NVR_SELECT | NVR_CLOCK); 2576 trm_eeprom_wait(); 2577 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2578 trm_eeprom_wait(); 2579 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2580 break; 2581 } 2582 /* 2583 * Disable chip select 2584 */ 2585 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2586 } 2587 2588 /* 2589 * read seeprom 128 bytes to struct eeprom 2590 */ 2591 static void 2592 trm_eeprom_read_all(sc, eeprom) 2593 struct trm_softc *sc; 2594 struct trm_nvram *eeprom; 2595 { 2596 bus_space_tag_t iot = sc->sc_iot; 2597 bus_space_handle_t ioh = sc->sc_ioh; 2598 u_int8_t *buf = (u_int8_t *)eeprom; 2599 u_int8_t addr; 2600 2601 /* 2602 * Enable SEEPROM 2603 */ 2604 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2605 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2606 2607 for (addr = 0; addr < 128; addr++) 2608 *buf++ = trm_eeprom_get_data(sc, addr); 2609 2610 /* 2611 * Disable SEEPROM 2612 */ 2613 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2614 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2615 } 2616 2617 /* 2618 * read one byte from seeprom 2619 */ 2620 static u_int8_t 2621 trm_eeprom_get_data(sc, addr) 2622 struct trm_softc *sc; 2623 u_int8_t addr; 2624 { 2625 bus_space_tag_t iot = sc->sc_iot; 2626 bus_space_handle_t ioh = sc->sc_ioh; 2627 int i; 2628 u_int8_t read, data = 0; 2629 2630 /* 2631 * Send read command & address 2632 */ 2633 trm_eeprom_write_cmd(sc, 0x06, addr); 2634 2635 for (i = 0; i < 8; i++) { /* Read data */ 2636 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2637 NVR_SELECT | NVR_CLOCK); 2638 trm_eeprom_wait(); 2639 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2640 /* 2641 * Get data bit while falling edge 2642 */ 2643 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2644 data <<= 1; 2645 if (read & NVR_BITIN) 2646 data |= 1; 2647 2648 trm_eeprom_wait(); 2649 } 2650 /* 2651 * Disable chip select 2652 */ 2653 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2654 return (data); 2655 } 2656 2657 /* 2658 * write SB and Op Code into seeprom 2659 */ 2660 static void 2661 trm_eeprom_write_cmd(sc, cmd, addr) 2662 struct trm_softc *sc; 2663 u_int8_t cmd; 2664 u_int8_t addr; 2665 { 2666 bus_space_tag_t iot = sc->sc_iot; 2667 bus_space_handle_t ioh = sc->sc_ioh; 2668 int i; 2669 u_int8_t send; 2670 2671 /* Program SB+OP code */ 2672 for (i = 0; i < 3; i++, cmd <<= 1) { 2673 send = NVR_SELECT; 2674 if (cmd & 0x04) /* Start from bit 2 */ 2675 send |= NVR_BITOUT; 2676 2677 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2678 trm_eeprom_wait(); 2679 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2680 trm_eeprom_wait(); 2681 } 2682 2683 /* Program address */ 2684 for (i = 0; i < 7; i++, addr <<= 1) { 2685 send = NVR_SELECT; 2686 if (addr & 0x40) /* Start from bit 6 */ 2687 send |= NVR_BITOUT; 2688 2689 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2690 trm_eeprom_wait(); 2691 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2692 trm_eeprom_wait(); 2693 } 2694 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2695 trm_eeprom_wait(); 2696 } 2697
Indexes created Sun Oct 12 20:09:57 GMT 2025