twareg.h revision 1.1
1 /* $wasabi: twareg.h,v 1.11 2006/04/27 17:12:39 wrstuden Exp $ */ 2 /* 3 * Copyright (c) 2005-2006 Wasabi Systems, Inc. 4 * All rights reserved. 5 * 6 * Your Wasabi Systems License Agreement specifies the terms and 7 * conditions for use and redistribution. 8 */ 9 10 11 /*- 12 * Copyright (c) 2003-04 3ware, Inc. 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $FreeBSD: src/sys/dev/twa/twa_reg.h,v 1.2 2004/08/18 16:14:44 vkashyap Exp $ 37 */ 38 39 /* 40 * 3ware driver for 9000 series storage controllers. 41 * 42 * Author: Vinod Kashyap 43 */ 44 45 #ifndef _PCI_TWAREG_H_ 46 #define _PCI_TWAREG_H_ 47 48 #if defined(_KERNEL) 49 #include <machine/bus.h> 50 51 /* 52 * The following macro has no business being in twa_reg.h. It should probably 53 * be defined in twa_includes.h, before the #include twa_reg.h.... But that 54 * causes the API to run into build errors. Will leave it here for now... 55 */ 56 #define TWA_64BIT_ADDRESSES ((sizeof(bus_addr_t) == 8) ? 1 : 0) 57 58 /* 59 * Define the following here since it relies on TWA_64BIT_ADDRESSES which 60 * depends on sizeof(bus_addr_t), which is not exported to userland. 61 * The userland API shouldn't care about the kernel's bus_addr_t. 62 * For the userland API, use the array size that we would use for 32-bit 63 * addresses since that's what we use in the sg structure definition. 64 * The userland API does not actually appear to use the array, but it 65 * does include the array in various command structures. 66 */ 67 #define TWA_MAX_SG_ELEMENTS (TWA_64BIT_ADDRESSES ? 70 : 105) 68 #else 69 #define TWA_MAX_SG_ELEMENTS 105 70 #endif 71 72 #define TWAQ_FREE 0 73 #define TWAQ_BUSY 1 74 #define TWAQ_PENDING 2 75 #define TWAQ_COMPLETE 3 76 #define TWAQ_IO_PENDING 4 77 #define TWAQ_COUNT 5 /* total number of queues */ 78 79 #define TWA_DRIVER_VERSION_STRING "1.00.00.000" 80 81 #define TWA_REQUEST_TIMEOUT_PERIOD 60 /* seconds */ 82 83 #define TWA_MESSAGE_SOURCE_CONTROLLER_ERROR 3 84 85 /* Register offsets from base address. */ 86 #define TWA_CONTROL_REGISTER_OFFSET 0x0 87 #define TWA_STATUS_REGISTER_OFFSET 0x4 88 #define TWA_COMMAND_QUEUE_OFFSET 0x8 89 #define TWA_RESPONSE_QUEUE_OFFSET 0xC 90 #define TWA_COMMAND_QUEUE_OFFSET_LOW 0x20 91 #define TWA_COMMAND_QUEUE_OFFSET_HIGH 0x24 92 93 #if defined(_KERNEL) 94 #define TWA_WRITE_REGISTER(sc, offset, val) \ 95 bus_space_write_4(sc->twa_bus_iot, sc->twa_bus_ioh, offset, (u_int32_t)val) 96 97 #define TWA_WRITE_COMMAND_QUEUE(sc, val) \ 98 do { \ 99 if (TWA_64BIT_ADDRESSES) { \ 100 /* First write the low 4 bytes, then the high 4. */ \ 101 TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_LOW, \ 102 (u_int32_t)(val)); \ 103 TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_HIGH,\ 104 (u_int32_t)(((u_int64_t)val)>>32)); \ 105 } else \ 106 TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET,\ 107 (u_int32_t)(val)); \ 108 } while (0) 109 #endif 110 111 /* Control register bit definitions. */ 112 #define TWA_CONTROL_CLEAR_SBUF_WRITE_ERROR 0x00000008 113 #define TWA_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 114 #define TWA_CONTROL_DISABLE_INTERRUPTS 0x00000040 115 #define TWA_CONTROL_ENABLE_INTERRUPTS 0x00000080 116 #define TWA_CONTROL_ISSUE_SOFT_RESET 0x00000100 117 #define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000 118 #define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000 119 #define TWA_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000 120 #define TWA_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000 121 #define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000 122 #define TWA_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000 123 #define TWA_CONTROL_CLEAR_PCI_ABORT 0x00100000 124 #define TWA_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 125 #define TWA_CONTROL_CLEAR_PARITY_ERROR 0x00800000 126 127 /* Status register bit definitions. */ 128 #define TWA_STATUS_ROM_BIOS_IN_SBUF 0x00000002 129 #define TWA_STATUS_SBUF_WRITE_ERROR 0x00000008 130 #define TWA_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 131 #define TWA_STATUS_MICROCONTROLLER_READY 0x00002000 132 #define TWA_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000 133 #define TWA_STATUS_COMMAND_QUEUE_FULL 0x00008000 134 #define TWA_STATUS_RESPONSE_INTERRUPT 0x00010000 135 #define TWA_STATUS_COMMAND_INTERRUPT 0x00020000 136 #define TWA_STATUS_ATTENTION_INTERRUPT 0x00040000 137 #define TWA_STATUS_HOST_INTERRUPT 0x00080000 138 #define TWA_STATUS_PCI_ABORT_INTERRUPT 0x00100000 139 #define TWA_STATUS_MICROCONTROLLER_ERROR 0x00200000 140 #define TWA_STATUS_QUEUE_ERROR_INTERRUPT 0x00400000 141 #define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT 0x00800000 142 #define TWA_STATUS_MINOR_VERSION_MASK 0x0F000000 143 #define TWA_STATUS_MAJOR_VERSION_MASK 0xF0000000 144 145 #define TWA_STATUS_EXPECTED_BITS 0x00002000 146 #define TWA_STATUS_UNEXPECTED_BITS 0x00F00000 147 148 /* For use with the %b printf format. */ 149 #define TWA_STATUS_BITS_DESCRIPTION \ 150 "\20\15CMD_Q_EMPTY\16MC_RDY\17RESP_Q_EMPTY\20CMD_Q_FULL\21RESP_INTR\22CMD_INTR\23ATTN_INTR\24HOST_INTR\25PCI_ABRT\26MC_ERR\27Q_ERR\30PCI_PERR\n" 151 152 /* Detect inconsistencies in the status register. */ 153 #define TWA_STATUS_ERRORS(x) \ 154 ((x & TWA_STATUS_UNEXPECTED_BITS) && \ 155 (x & TWA_STATUS_MICROCONTROLLER_READY)) 156 157 /* PCI related defines. */ 158 #define TWA_IO_CONFIG_REG 0x10 159 #define TWA_DEVICE_NAME "3ware 9000 series Storage Controller" 160 #define TWA_VENDOR_ID 0x13C1 161 #define TWA_DEVICE_ID_9K 0x1002 162 163 #define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR 0xc100 164 #define TWA_PCI_CONFIG_CLEAR_PCI_ABORT 0x2000 165 166 /* Command packet opcodes. */ 167 #define TWA_OP_NOP 0x00 168 #define TWA_OP_INIT_CONNECTION 0x01 169 #define TWA_OP_READ 0x02 170 #define TWA_OP_WRITE 0x03 171 #define TWA_OP_READVERIFY 0x04 172 #define TWA_OP_VERIFY 0x05 173 #define TWA_OP_ZEROUNIT 0x08 174 #define TWA_OP_REPLACEUNIT 0x09 175 #define TWA_OP_HOTSWAP 0x0A 176 #define TWA_OP_SELFTESTS 0x0B 177 #define TWA_OP_SYNC_PARAM 0x0C 178 #define TWA_OP_REORDER_UNITS 0x0D 179 #define TWA_OP_FLUSH 0x0E 180 #define TWA_OP_EXECUTE_SCSI_COMMAND 0x10 181 #define TWA_OP_ATA_PASSTHROUGH 0x11 182 #define TWA_OP_GET_PARAM 0x12 183 #define TWA_OP_SET_PARAM 0x13 184 #define TWA_OP_CREATEUNIT 0x14 185 #define TWA_OP_DELETEUNIT 0x15 186 #define TWA_OP_DOWNLOAD_FIRMWARE 0x16 187 #define TWA_OP_REBUILDUNIT 0x17 188 #define TWA_OP_POWER_MANAGEMENT 0x18 189 190 #define TWA_OP_REMOTE_PRINT 0x1B 191 #define TWA_OP_RESET_FIRMWARE 0x1C 192 #define TWA_OP_DEBUG 0x1D 193 194 #define TWA_OP_DIAGNOSTICS 0x1F 195 196 /* Misc defines. */ 197 #define TWA_ALIGNMENT 0x4 198 #define TWA_MAX_UNITS 16 199 #define TWA_INIT_MESSAGE_CREDITS 0x100 200 #define TWA_SHUTDOWN_MESSAGE_CREDITS 0x001 201 #define TWA_64BIT_SG_ADDRESSES 0x00000001 202 #define TWA_EXTENDED_INIT_CONNECT 0x00000002 203 #define TWA_BASE_MODE 1 204 #define TWA_BASE_FW_SRL 24 205 #define TWA_BASE_FW_BRANCH 0 206 #define TWA_BASE_FW_BUILD 1 207 #define TWA_CURRENT_FW_SRL 28 208 #define TWA_CURRENT_FW_BRANCH 4 209 #define TWA_CURRENT_FW_BUILD 9 210 #define TWA_9000_ARCH_ID 0x5 /* 9000 series controllers */ 211 #define TWA_CTLR_FW_SAME_OR_NEWER 0x00000001 212 #define TWA_CTLR_FW_COMPATIBLE 0x00000002 213 #define TWA_BUNDLED_FW_SAFE_TO_FLASH 0x00000004 214 #define TWA_CTLR_FW_RECOMMENDS_FLASH 0x00000008 215 #define NUM_FW_IMAGE_CHUNKS 5 216 #define TWA_MAX_IO_SIZE 0x20000 /* 128K */ 217 /* #define TWA_MAX_SG_ELEMENTS defined above */ 218 #define TWA_MAX_ATA_SG_ELEMENTS 60 219 #define TWA_Q_LENGTH TWA_INIT_MESSAGE_CREDITS 220 #define TWA_MAX_RESET_TRIES 3 221 #define TWA_SECTOR_SIZE 0x200 /* generic I/O bufffer */ 222 #define TWA_SENSE_DATA_LENGTH 18 223 224 #define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x010a 225 #define TWA_ERROR_UNIT_OFFLINE 0x0128 226 #define TWA_ERROR_MORE_DATA 0x0231 227 228 /* Scatter/Gather list entry. */ 229 struct twa_sg { 230 #if defined(_KERNEL) 231 bus_addr_t address; 232 #else 233 u_int32_t xx_address_xx; /* Fail if userland tries to use this */ 234 #endif 235 u_int32_t length; 236 } __attribute__ ((packed)); 237 238 239 /* 7000 structures. */ 240 struct twa_command_init_connect { 241 u_int8_t opcode:5; /* TWA_OP_INITCONNECTION */ 242 u_int8_t res1:3; 243 u_int8_t size; 244 u_int8_t request_id; 245 u_int8_t res2; 246 u_int8_t status; 247 u_int8_t flags; 248 u_int16_t message_credits; 249 u_int32_t features; 250 u_int16_t fw_srl; 251 u_int16_t fw_arch_id; 252 u_int16_t fw_branch; 253 u_int16_t fw_build; 254 u_int32_t result; 255 }__attribute__ ((packed)); 256 257 struct twa_command_download_firmware { 258 u_int8_t opcode:5; /* TWA_DOWNLOAD_FIRMWARE */ 259 u_int8_t sgl_offset:3; 260 u_int8_t size; 261 u_int8_t request_id; 262 u_int8_t unit; 263 u_int8_t status; 264 u_int8_t flags; 265 u_int16_t param; 266 struct twa_sg sgl[TWA_MAX_SG_ELEMENTS]; 267 } __attribute__ ((packed)); 268 269 270 struct twa_command_reset_firmware { 271 u_int8_t opcode:5; /* TWA_OP_RESET_FIRMWARE */ 272 u_int8_t res1:3; 273 u_int8_t size; 274 u_int8_t request_id; 275 u_int8_t unit; 276 u_int8_t status; 277 u_int8_t flags; 278 u_int8_t res2; 279 u_int8_t param; 280 } __attribute__ ((packed)); 281 282 283 struct twa_command_io { 284 u_int8_t opcode:5; /* TWA_OP_READ/TWA_OP_WRITE */ 285 u_int8_t sgl_offset:3; 286 u_int8_t size; 287 u_int8_t request_id; 288 u_int8_t unit:4; 289 u_int8_t host_id:4; 290 u_int8_t status; 291 u_int8_t flags; 292 u_int16_t block_count; 293 u_int32_t lba; 294 struct twa_sg sgl[TWA_MAX_SG_ELEMENTS]; 295 } __attribute__ ((packed)); 296 297 298 struct twa_command_hotswap { 299 u_int8_t opcode:5; /* TWA_OP_HOTSWAP */ 300 u_int8_t res1:3; 301 u_int8_t size; 302 u_int8_t request_id; 303 u_int8_t unit:4; 304 u_int8_t host_id:4; 305 u_int8_t status; 306 u_int8_t flags; 307 u_int8_t action; 308 #define TWA_OP_HOTSWAP_REMOVE 0x00 /* remove assumed-degraded unit */ 309 #define TWA_OP_HOTSWAP_ADD_CBOD 0x01 /* add CBOD to empty port */ 310 #define TWA_OP_HOTSWAP_ADD_SPARE 0x02 /* add spare to empty port */ 311 u_int8_t aport; 312 } __attribute__ ((packed)); 313 314 315 struct twa_command_param { 316 u_int8_t opcode:5; /* TWA_OP_GETPARAM, TWA_OP_SETPARAM */ 317 u_int8_t sgl_offset:3; 318 u_int8_t size; 319 u_int8_t request_id; 320 u_int8_t unit:4; 321 u_int8_t host_id:4; 322 u_int8_t status; 323 u_int8_t flags; 324 u_int16_t param_count; 325 struct twa_sg sgl[TWA_MAX_SG_ELEMENTS]; 326 } __attribute__ ((packed)); 327 328 329 struct twa_command_rebuildunit { 330 u_int8_t opcode:5; /* TWA_OP_REBUILDUNIT */ 331 u_int8_t res1:3; 332 u_int8_t size; 333 u_int8_t request_id; 334 u_int8_t src_unit:4; 335 u_int8_t host_id:4; 336 u_int8_t status; 337 u_int8_t flags; 338 u_int8_t action:7; 339 #define TWA_OP_REBUILDUNIT_NOP 0 340 #define TWA_OP_REBUILDUNIT_STOP 2 /* stop all rebuilds */ 341 #define TWA_OP_REBUILDUNIT_START 4 /* start rebuild with lowest unit */ 342 #define TWA_OP_REBUILDUNIT_STARTUNIT 5 /* rebuild src_unit (not supported) */ 343 u_int8_t cs:1; /* request state change on src_unit */ 344 u_int8_t logical_subunit; /* for RAID10 rebuild of logical subunit */ 345 } __attribute__ ((packed)); 346 347 348 struct twa_command_ata { 349 u_int8_t opcode:5; /* TWA_OP_ATA_PASSTHROUGH */ 350 u_int8_t sgl_offset:3; 351 u_int8_t size; 352 u_int8_t request_id; 353 u_int8_t unit:4; 354 u_int8_t host_id:4; 355 u_int8_t status; 356 u_int8_t flags; 357 u_int16_t param; 358 u_int16_t features; 359 u_int16_t sector_count; 360 u_int16_t sector_num; 361 u_int16_t cylinder_lo; 362 u_int16_t cylinder_hi; 363 u_int8_t drive_head; 364 u_int8_t command; 365 struct twa_sg sgl[TWA_MAX_ATA_SG_ELEMENTS]; 366 } __attribute__ ((packed)); 367 368 369 struct twa_command_generic { 370 u_int8_t opcode:5; 371 u_int8_t sgl_offset:3; 372 u_int8_t size; 373 u_int8_t request_id; 374 u_int8_t unit:4; 375 u_int8_t host_id:4; 376 u_int8_t status; 377 u_int8_t flags; 378 #define TWA_FLAGS_SUCCESS 0x00 379 #define TWA_FLAGS_INFORMATIONAL 0x01 380 #define TWA_FLAGS_WARNING 0x02 381 #define TWA_FLAGS_FATAL 0x03 382 #define TWA_FLAGS_PERCENTAGE (1<<8) /* bits 0-6 indicate completion percentage */ 383 u_int16_t count; /* block count, parameter count, message credits */ 384 } __attribute__ ((packed)); 385 386 387 /* Command packet - must be TWA_ALIGNMENT aligned. */ 388 union twa_command_7k { 389 struct twa_command_init_connect init_connect; 390 struct twa_command_download_firmware download_fw; 391 struct twa_command_reset_firmware reset_fw; 392 struct twa_command_io io; 393 struct twa_command_hotswap hotswap; 394 struct twa_command_param param; 395 struct twa_command_rebuildunit rebuildunit; 396 struct twa_command_ata ata; 397 struct twa_command_generic generic; 398 } __attribute__ ((packed)); 399 400 401 /* 9000 structures. */ 402 403 /* Command Packet. */ 404 struct twa_command_9k { 405 struct { 406 u_int8_t opcode:5; 407 u_int8_t reserved:3; 408 } command; 409 u_int8_t unit; 410 u_int16_t request_id; 411 u_int8_t status; 412 u_int8_t sgl_offset; /* offset (in bytes) to sg_list, from the end of sgl_entries */ 413 u_int16_t sgl_entries; 414 u_int8_t cdb[16]; 415 struct twa_sg sg_list[TWA_MAX_SG_ELEMENTS]; 416 u_int8_t padding[32]; 417 } __attribute__ ((packed)); 418 419 420 /* Command packet header. */ 421 struct twa_command_header { 422 u_int8_t sense_data[TWA_SENSE_DATA_LENGTH]; 423 struct { 424 int8_t reserved[4]; 425 u_int16_t error; 426 u_int8_t padding; 427 struct { 428 u_int8_t severity:3; 429 u_int8_t reserved:5; 430 } substatus_block; 431 } status_block; 432 u_int8_t err_specific_desc[98]; 433 struct { 434 u_int8_t size_header; 435 u_int16_t reserved; 436 u_int8_t size_sense; 437 } header_desc; 438 u_int8_t reserved[2]; 439 } __attribute__ ((packed)); 440 441 442 /* Full command packet. */ 443 struct twa_command_packet { 444 struct twa_command_header cmd_hdr; 445 union { 446 union twa_command_7k cmd_pkt_7k; 447 struct twa_command_9k cmd_pkt_9k; 448 } command; 449 } __attribute__ ((packed)); 450 451 452 /* Response queue entry. */ 453 union twa_response_queue { 454 struct { 455 u_int32_t undefined_1:4; 456 u_int32_t response_id:8; 457 u_int32_t undefined_2:20; 458 } u; 459 u_int32_t value; 460 } __attribute__ ((packed)); 461 462 463 #define TWA_AEN_QUEUE_EMPTY 0x00 464 #define TWA_AEN_SOFT_RESET 0x01 465 #define TWA_AEN_SYNC_TIME_WITH_HOST 0x31 466 #define TWA_AEN_SEVERITY_ERROR 0x1 467 #define TWA_AEN_SEVERITY_WARNING 0x1 468 #define TWA_AEN_SEVERITY_INFO 0x1 469 #define TWA_AEN_SEVERITY_DEBUG 0x4 470 471 #define TWA_PARAM_DRIVESUMMARY 0x0002 472 #define TWA_PARAM_DRIVESTATUS 3 473 474 #define TWA_DRIVE_DETECTED 0x80 475 476 #define TWA_PARAM_DRIVE_TABLE 0x0200 477 #define TWA_PARAM_DRIVESIZEINDEX 2 478 #define TWA_PARAM_DRIVEMODELINDEX 3 479 480 #define TWA_PARAM_DRIVESIZE_LENGTH 4 481 #define TWA_PARAM_DRIVEMODEL_LENGTH 40 482 483 484 #define TWA_PARAM_VERSION 0x0402 485 #define TWA_PARAM_VERSION_Mon 2 /* monitor version [16] */ 486 #define TWA_PARAM_VERSION_FW 3 /* firmware version [16] */ 487 #define TWA_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */ 488 #define TWA_PARAM_VERSION_PCBA 5 /* PCB version [8] */ 489 #define TWA_PARAM_VERSION_ATA 6 /* A-chip version [8] */ 490 #define TWA_PARAM_VERSION_PCI 7 /* P-chip version [8] */ 491 492 #define TWA_PARAM_CONTROLLER 0x0403 493 #define TWA_PARAM_CONTROLLER_PortCount 3 /* number of ports [1] */ 494 495 #define TWA_PARAM_TIME_TABLE 0x40A 496 #define TWA_PARAM_TIME_SchedulerTime 0x3 497 498 #define TWA_9K_PARAM_DESCRIPTOR 0x8000 499 500 501 struct twa_param_9k { 502 u_int16_t table_id; 503 u_int8_t parameter_id; 504 u_int8_t reserved; 505 u_int16_t parameter_size_bytes; 506 u_int16_t parameter_actual_size_bytes; 507 u_int8_t data[1]; 508 } __attribute__ ((packed)); 509 510 #endif /* !_PCI_TWAREG_H_ */ 511
Indexes created Wed Sep 24 15:09:51 GMT 2025