twareg.h revision 1.2.6.2
1 /* $NetBSD: twareg.h,v 1.2.6.2 2006/06/19 04:01:37 chap Exp $ */ 2 /* $wasabi: twareg.h,v 1.11 2006/04/27 17:12:39 wrstuden Exp $ */ 3 /* 4 * Copyright (c) 2005-2006 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Your Wasabi Systems License Agreement specifies the terms and 8 * conditions for use and redistribution. 9 */ 10 11 12 /*- 13 * Copyright (c) 2003-04 3ware, Inc. 14 * All rights reserved. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/twa/twa_reg.h,v 1.2 2004/08/18 16:14:44 vkashyap Exp $ 38 */ 39 40 /* 41 * 3ware driver for 9000 series storage controllers. 42 * 43 * Author: Vinod Kashyap 44 */ 45 46 #ifndef _PCI_TWAREG_H_ 47 #define _PCI_TWAREG_H_ 48 49 #if defined(_KERNEL) 50 #include <machine/bus.h> 51 52 /* 53 * The following macro has no business being in twa_reg.h. It should probably 54 * be defined in twa_includes.h, before the #include twa_reg.h.... But that 55 * causes the API to run into build errors. Will leave it here for now... 56 */ 57 #define TWA_64BIT_ADDRESSES ((sizeof(bus_addr_t) == 8) ? 1 : 0) 58 59 /* 60 * Define the following here since it relies on TWA_64BIT_ADDRESSES which 61 * depends on sizeof(bus_addr_t), which is not exported to userland. 62 * The userland API shouldn't care about the kernel's bus_addr_t. 63 * For the userland API, use the array size that we would use for 32-bit 64 * addresses since that's what we use in the sg structure definition. 65 * The userland API does not actually appear to use the array, but it 66 * does include the array in various command structures. 67 */ 68 #define TWA_MAX_SG_ELEMENTS (TWA_64BIT_ADDRESSES ? 70 : 105) 69 #else 70 #define TWA_MAX_SG_ELEMENTS 105 71 #endif 72 73 #define TWAQ_FREE 0 74 #define TWAQ_BUSY 1 75 #define TWAQ_PENDING 2 76 #define TWAQ_COMPLETE 3 77 #define TWAQ_IO_PENDING 4 78 #define TWAQ_COUNT 5 /* total number of queues */ 79 80 #define TWA_DRIVER_VERSION_STRING "1.00.00.000" 81 82 #define TWA_REQUEST_TIMEOUT_PERIOD 60 /* seconds */ 83 84 #define TWA_MESSAGE_SOURCE_CONTROLLER_ERROR 3 85 86 /* Register offsets from base address. */ 87 #define TWA_CONTROL_REGISTER_OFFSET 0x0 88 #define TWA_STATUS_REGISTER_OFFSET 0x4 89 #define TWA_COMMAND_QUEUE_OFFSET 0x8 90 #define TWA_RESPONSE_QUEUE_OFFSET 0xC 91 #define TWA_COMMAND_QUEUE_OFFSET_LOW 0x20 92 #define TWA_COMMAND_QUEUE_OFFSET_HIGH 0x24 93 94 #if defined(_KERNEL) 95 #define TWA_WRITE_REGISTER(sc, offset, val) \ 96 bus_space_write_4(sc->twa_bus_iot, sc->twa_bus_ioh, offset, (u_int32_t)val) 97 98 #define TWA_WRITE_COMMAND_QUEUE(sc, val) \ 99 do { \ 100 if (TWA_64BIT_ADDRESSES) { \ 101 /* First write the low 4 bytes, then the high 4. */ \ 102 TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_LOW, \ 103 (u_int32_t)(val)); \ 104 TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_HIGH,\ 105 (u_int32_t)(((u_int64_t)val)>>32)); \ 106 } else \ 107 TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET,\ 108 (u_int32_t)(val)); \ 109 } while (0) 110 #endif 111 112 /* Control register bit definitions. */ 113 #define TWA_CONTROL_CLEAR_SBUF_WRITE_ERROR 0x00000008 114 #define TWA_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 115 #define TWA_CONTROL_DISABLE_INTERRUPTS 0x00000040 116 #define TWA_CONTROL_ENABLE_INTERRUPTS 0x00000080 117 #define TWA_CONTROL_ISSUE_SOFT_RESET 0x00000100 118 #define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000 119 #define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000 120 #define TWA_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000 121 #define TWA_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000 122 #define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000 123 #define TWA_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000 124 #define TWA_CONTROL_CLEAR_PCI_ABORT 0x00100000 125 #define TWA_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 126 #define TWA_CONTROL_CLEAR_PARITY_ERROR 0x00800000 127 128 /* Status register bit definitions. */ 129 #define TWA_STATUS_ROM_BIOS_IN_SBUF 0x00000002 130 #define TWA_STATUS_SBUF_WRITE_ERROR 0x00000008 131 #define TWA_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 132 #define TWA_STATUS_MICROCONTROLLER_READY 0x00002000 133 #define TWA_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000 134 #define TWA_STATUS_COMMAND_QUEUE_FULL 0x00008000 135 #define TWA_STATUS_RESPONSE_INTERRUPT 0x00010000 136 #define TWA_STATUS_COMMAND_INTERRUPT 0x00020000 137 #define TWA_STATUS_ATTENTION_INTERRUPT 0x00040000 138 #define TWA_STATUS_HOST_INTERRUPT 0x00080000 139 #define TWA_STATUS_PCI_ABORT_INTERRUPT 0x00100000 140 #define TWA_STATUS_MICROCONTROLLER_ERROR 0x00200000 141 #define TWA_STATUS_QUEUE_ERROR_INTERRUPT 0x00400000 142 #define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT 0x00800000 143 #define TWA_STATUS_MINOR_VERSION_MASK 0x0F000000 144 #define TWA_STATUS_MAJOR_VERSION_MASK 0xF0000000 145 146 #define TWA_STATUS_EXPECTED_BITS 0x00002000 147 #define TWA_STATUS_UNEXPECTED_BITS 0x00F00000 148 149 /* For use with the %b printf format. */ 150 #define TWA_STATUS_BITS_DESCRIPTION \ 151 "\20\15CMD_Q_EMPTY\16MC_RDY\17RESP_Q_EMPTY\20CMD_Q_FULL\21RESP_INTR\22CMD_INTR\23ATTN_INTR\24HOST_INTR\25PCI_ABRT\26MC_ERR\27Q_ERR\30PCI_PERR\n" 152 153 /* Detect inconsistencies in the status register. */ 154 #define TWA_STATUS_ERRORS(x) \ 155 ((x & TWA_STATUS_UNEXPECTED_BITS) && \ 156 (x & TWA_STATUS_MICROCONTROLLER_READY)) 157 158 /* PCI related defines. */ 159 #define TWA_IO_CONFIG_REG 0x10 160 #define TWA_DEVICE_NAME "3ware 9000 series Storage Controller" 161 #define TWA_VENDOR_ID 0x13C1 162 #define TWA_DEVICE_ID_9K 0x1002 163 164 #define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR 0xc100 165 #define TWA_PCI_CONFIG_CLEAR_PCI_ABORT 0x2000 166 167 /* Command packet opcodes. */ 168 #define TWA_OP_NOP 0x00 169 #define TWA_OP_INIT_CONNECTION 0x01 170 #define TWA_OP_READ 0x02 171 #define TWA_OP_WRITE 0x03 172 #define TWA_OP_READVERIFY 0x04 173 #define TWA_OP_VERIFY 0x05 174 #define TWA_OP_ZEROUNIT 0x08 175 #define TWA_OP_REPLACEUNIT 0x09 176 #define TWA_OP_HOTSWAP 0x0A 177 #define TWA_OP_SELFTESTS 0x0B 178 #define TWA_OP_SYNC_PARAM 0x0C 179 #define TWA_OP_REORDER_UNITS 0x0D 180 #define TWA_OP_FLUSH 0x0E 181 #define TWA_OP_EXECUTE_SCSI_COMMAND 0x10 182 #define TWA_OP_ATA_PASSTHROUGH 0x11 183 #define TWA_OP_GET_PARAM 0x12 184 #define TWA_OP_SET_PARAM 0x13 185 #define TWA_OP_CREATEUNIT 0x14 186 #define TWA_OP_DELETEUNIT 0x15 187 #define TWA_OP_DOWNLOAD_FIRMWARE 0x16 188 #define TWA_OP_REBUILDUNIT 0x17 189 #define TWA_OP_POWER_MANAGEMENT 0x18 190 191 #define TWA_OP_REMOTE_PRINT 0x1B 192 #define TWA_OP_RESET_FIRMWARE 0x1C 193 #define TWA_OP_DEBUG 0x1D 194 195 #define TWA_OP_DIAGNOSTICS 0x1F 196 197 /* Misc defines. */ 198 #define TWA_ALIGNMENT 0x4 199 #define TWA_MAX_UNITS 16 200 #define TWA_INIT_MESSAGE_CREDITS 0x100 201 #define TWA_SHUTDOWN_MESSAGE_CREDITS 0x001 202 #define TWA_64BIT_SG_ADDRESSES 0x00000001 203 #define TWA_EXTENDED_INIT_CONNECT 0x00000002 204 #define TWA_BASE_MODE 1 205 #define TWA_BASE_FW_SRL 24 206 #define TWA_BASE_FW_BRANCH 0 207 #define TWA_BASE_FW_BUILD 1 208 #define TWA_CURRENT_FW_SRL 28 209 #define TWA_CURRENT_FW_BRANCH 4 210 #define TWA_CURRENT_FW_BUILD 9 211 #define TWA_9000_ARCH_ID 0x5 /* 9000 series controllers */ 212 #define TWA_CTLR_FW_SAME_OR_NEWER 0x00000001 213 #define TWA_CTLR_FW_COMPATIBLE 0x00000002 214 #define TWA_BUNDLED_FW_SAFE_TO_FLASH 0x00000004 215 #define TWA_CTLR_FW_RECOMMENDS_FLASH 0x00000008 216 #define NUM_FW_IMAGE_CHUNKS 5 217 #define TWA_MAX_IO_SIZE 0x20000 /* 128K */ 218 /* #define TWA_MAX_SG_ELEMENTS defined above */ 219 #define TWA_MAX_ATA_SG_ELEMENTS 60 220 #define TWA_Q_LENGTH TWA_INIT_MESSAGE_CREDITS 221 #define TWA_MAX_RESET_TRIES 3 222 #define TWA_SECTOR_SIZE 0x200 /* generic I/O bufffer */ 223 #define TWA_SENSE_DATA_LENGTH 18 224 225 #define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x010a 226 #define TWA_ERROR_UNIT_OFFLINE 0x0128 227 #define TWA_ERROR_MORE_DATA 0x0231 228 229 /* Scatter/Gather list entry. */ 230 struct twa_sg { 231 #if defined(_KERNEL) 232 bus_addr_t address; 233 #else 234 u_int32_t xx_address_xx; /* Fail if userland tries to use this */ 235 #endif 236 u_int32_t length; 237 } __attribute__ ((packed)); 238 239 240 /* 7000 structures. */ 241 struct twa_command_init_connect { 242 u_int8_t opcode:5; /* TWA_OP_INITCONNECTION */ 243 u_int8_t res1:3; 244 u_int8_t size; 245 u_int8_t request_id; 246 u_int8_t res2; 247 u_int8_t status; 248 u_int8_t flags; 249 u_int16_t message_credits; 250 u_int32_t features; 251 u_int16_t fw_srl; 252 u_int16_t fw_arch_id; 253 u_int16_t fw_branch; 254 u_int16_t fw_build; 255 u_int32_t result; 256 }__attribute__ ((packed)); 257 258 struct twa_command_download_firmware { 259 u_int8_t opcode:5; /* TWA_DOWNLOAD_FIRMWARE */ 260 u_int8_t sgl_offset:3; 261 u_int8_t size; 262 u_int8_t request_id; 263 u_int8_t unit; 264 u_int8_t status; 265 u_int8_t flags; 266 u_int16_t param; 267 struct twa_sg sgl[TWA_MAX_SG_ELEMENTS]; 268 } __attribute__ ((packed)); 269 270 271 struct twa_command_reset_firmware { 272 u_int8_t opcode:5; /* TWA_OP_RESET_FIRMWARE */ 273 u_int8_t res1:3; 274 u_int8_t size; 275 u_int8_t request_id; 276 u_int8_t unit; 277 u_int8_t status; 278 u_int8_t flags; 279 u_int8_t res2; 280 u_int8_t param; 281 } __attribute__ ((packed)); 282 283 284 struct twa_command_io { 285 u_int8_t opcode:5; /* TWA_OP_READ/TWA_OP_WRITE */ 286 u_int8_t sgl_offset:3; 287 u_int8_t size; 288 u_int8_t request_id; 289 u_int8_t unit:4; 290 u_int8_t host_id:4; 291 u_int8_t status; 292 u_int8_t flags; 293 u_int16_t block_count; 294 u_int32_t lba; 295 struct twa_sg sgl[TWA_MAX_SG_ELEMENTS]; 296 } __attribute__ ((packed)); 297 298 299 struct twa_command_hotswap { 300 u_int8_t opcode:5; /* TWA_OP_HOTSWAP */ 301 u_int8_t res1:3; 302 u_int8_t size; 303 u_int8_t request_id; 304 u_int8_t unit:4; 305 u_int8_t host_id:4; 306 u_int8_t status; 307 u_int8_t flags; 308 u_int8_t action; 309 #define TWA_OP_HOTSWAP_REMOVE 0x00 /* remove assumed-degraded unit */ 310 #define TWA_OP_HOTSWAP_ADD_CBOD 0x01 /* add CBOD to empty port */ 311 #define TWA_OP_HOTSWAP_ADD_SPARE 0x02 /* add spare to empty port */ 312 u_int8_t aport; 313 } __attribute__ ((packed)); 314 315 316 struct twa_command_param { 317 u_int8_t opcode:5; /* TWA_OP_GETPARAM, TWA_OP_SETPARAM */ 318 u_int8_t sgl_offset:3; 319 u_int8_t size; 320 u_int8_t request_id; 321 u_int8_t unit:4; 322 u_int8_t host_id:4; 323 u_int8_t status; 324 u_int8_t flags; 325 u_int16_t param_count; 326 struct twa_sg sgl[TWA_MAX_SG_ELEMENTS]; 327 } __attribute__ ((packed)); 328 329 330 struct twa_command_rebuildunit { 331 u_int8_t opcode:5; /* TWA_OP_REBUILDUNIT */ 332 u_int8_t res1:3; 333 u_int8_t size; 334 u_int8_t request_id; 335 u_int8_t src_unit:4; 336 u_int8_t host_id:4; 337 u_int8_t status; 338 u_int8_t flags; 339 u_int8_t action:7; 340 #define TWA_OP_REBUILDUNIT_NOP 0 341 #define TWA_OP_REBUILDUNIT_STOP 2 /* stop all rebuilds */ 342 #define TWA_OP_REBUILDUNIT_START 4 /* start rebuild with lowest unit */ 343 #define TWA_OP_REBUILDUNIT_STARTUNIT 5 /* rebuild src_unit (not supported) */ 344 u_int8_t cs:1; /* request state change on src_unit */ 345 u_int8_t logical_subunit; /* for RAID10 rebuild of logical subunit */ 346 } __attribute__ ((packed)); 347 348 349 struct twa_command_ata { 350 u_int8_t opcode:5; /* TWA_OP_ATA_PASSTHROUGH */ 351 u_int8_t sgl_offset:3; 352 u_int8_t size; 353 u_int8_t request_id; 354 u_int8_t unit:4; 355 u_int8_t host_id:4; 356 u_int8_t status; 357 u_int8_t flags; 358 u_int16_t param; 359 u_int16_t features; 360 u_int16_t sector_count; 361 u_int16_t sector_num; 362 u_int16_t cylinder_lo; 363 u_int16_t cylinder_hi; 364 u_int8_t drive_head; 365 u_int8_t command; 366 struct twa_sg sgl[TWA_MAX_ATA_SG_ELEMENTS]; 367 } __attribute__ ((packed)); 368 369 370 struct twa_command_generic { 371 u_int8_t opcode:5; 372 u_int8_t sgl_offset:3; 373 u_int8_t size; 374 u_int8_t request_id; 375 u_int8_t unit:4; 376 u_int8_t host_id:4; 377 u_int8_t status; 378 u_int8_t flags; 379 #define TWA_FLAGS_SUCCESS 0x00 380 #define TWA_FLAGS_INFORMATIONAL 0x01 381 #define TWA_FLAGS_WARNING 0x02 382 #define TWA_FLAGS_FATAL 0x03 383 #define TWA_FLAGS_PERCENTAGE (1<<8) /* bits 0-6 indicate completion percentage */ 384 u_int16_t count; /* block count, parameter count, message credits */ 385 } __attribute__ ((packed)); 386 387 388 /* Command packet - must be TWA_ALIGNMENT aligned. */ 389 union twa_command_7k { 390 struct twa_command_init_connect init_connect; 391 struct twa_command_download_firmware download_fw; 392 struct twa_command_reset_firmware reset_fw; 393 struct twa_command_io io; 394 struct twa_command_hotswap hotswap; 395 struct twa_command_param param; 396 struct twa_command_rebuildunit rebuildunit; 397 struct twa_command_ata ata; 398 struct twa_command_generic generic; 399 } __attribute__ ((packed)); 400 401 402 /* 9000 structures. */ 403 404 /* Command Packet. */ 405 struct twa_command_9k { 406 struct { 407 u_int8_t opcode:5; 408 u_int8_t reserved:3; 409 } command; 410 u_int8_t unit; 411 u_int16_t request_id; 412 u_int8_t status; 413 u_int8_t sgl_offset; /* offset (in bytes) to sg_list, from the end of sgl_entries */ 414 u_int16_t sgl_entries; 415 u_int8_t cdb[16]; 416 struct twa_sg sg_list[TWA_MAX_SG_ELEMENTS]; 417 u_int8_t padding[32]; 418 } __attribute__ ((packed)); 419 420 421 /* Command packet header. */ 422 struct twa_command_header { 423 u_int8_t sense_data[TWA_SENSE_DATA_LENGTH]; 424 struct { 425 int8_t reserved[4]; 426 u_int16_t error; 427 u_int8_t padding; 428 struct { 429 u_int8_t severity:3; 430 u_int8_t reserved:5; 431 } substatus_block; 432 } status_block; 433 u_int8_t err_specific_desc[98]; 434 struct { 435 u_int8_t size_header; 436 u_int16_t reserved; 437 u_int8_t size_sense; 438 } header_desc; 439 u_int8_t reserved[2]; 440 } __attribute__ ((packed)); 441 442 443 /* Full command packet. */ 444 struct twa_command_packet { 445 struct twa_command_header cmd_hdr; 446 union { 447 union twa_command_7k cmd_pkt_7k; 448 struct twa_command_9k cmd_pkt_9k; 449 } command; 450 } __attribute__ ((packed)); 451 452 453 /* Response queue entry. */ 454 union twa_response_queue { 455 struct { 456 u_int32_t undefined_1:4; 457 u_int32_t response_id:8; 458 u_int32_t undefined_2:20; 459 } u; 460 u_int32_t value; 461 } __attribute__ ((packed)); 462 463 464 #define TWA_AEN_QUEUE_EMPTY 0x00 465 #define TWA_AEN_SOFT_RESET 0x01 466 #define TWA_AEN_SYNC_TIME_WITH_HOST 0x31 467 #define TWA_AEN_SEVERITY_ERROR 0x1 468 #define TWA_AEN_SEVERITY_WARNING 0x1 469 #define TWA_AEN_SEVERITY_INFO 0x1 470 #define TWA_AEN_SEVERITY_DEBUG 0x4 471 472 #define TWA_PARAM_DRIVESUMMARY 0x0002 473 #define TWA_PARAM_DRIVESTATUS 3 474 475 #define TWA_DRIVE_DETECTED 0x80 476 477 #define TWA_PARAM_DRIVE_TABLE 0x0200 478 #define TWA_PARAM_DRIVESIZEINDEX 2 479 #define TWA_PARAM_DRIVEMODELINDEX 3 480 481 #define TWA_PARAM_DRIVESIZE_LENGTH 4 482 #define TWA_PARAM_DRIVEMODEL_LENGTH 40 483 484 485 #define TWA_PARAM_VERSION 0x0402 486 #define TWA_PARAM_VERSION_Mon 2 /* monitor version [16] */ 487 #define TWA_PARAM_VERSION_FW 3 /* firmware version [16] */ 488 #define TWA_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */ 489 #define TWA_PARAM_VERSION_PCBA 5 /* PCB version [8] */ 490 #define TWA_PARAM_VERSION_ATA 6 /* A-chip version [8] */ 491 #define TWA_PARAM_VERSION_PCI 7 /* P-chip version [8] */ 492 493 #define TWA_PARAM_CONTROLLER 0x0403 494 #define TWA_PARAM_CONTROLLER_PortCount 3 /* number of ports [1] */ 495 496 #define TWA_PARAM_TIME_TABLE 0x40A 497 #define TWA_PARAM_TIME_SchedulerTime 0x3 498 499 #define TWA_9K_PARAM_DESCRIPTOR 0x8000 500 501 502 struct twa_param_9k { 503 u_int16_t table_id; 504 u_int8_t parameter_id; 505 u_int8_t reserved; 506 u_int16_t parameter_size_bytes; 507 u_int16_t parameter_actual_size_bytes; 508 u_int8_t data[1]; 509 } __attribute__ ((packed)); 510 511 #endif /* !_PCI_TWAREG_H_ */ 512
Indexes created Thu Oct 02 14:10:14 GMT 2025