twareg.h revision 1.7
1 /* $NetBSD: twareg.h,v 1.7 2007/10/19 12:00:56 ad Exp $ */ 2 /* $wasabi: twareg.h,v 1.14 2006/07/28 18:29:51 wrstuden Exp $ */ 3 4 /*- 5 * Copyright (c) 2003-04 3ware, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/twa/twa_reg.h,v 1.2 2004/08/18 16:14:44 vkashyap Exp $ 30 */ 31 32 /* 33 * 3ware driver for 9000 series storage controllers. 34 * 35 * Author: Vinod Kashyap 36 */ 37 38 #ifndef _PCI_TWAREG_H_ 39 #define _PCI_TWAREG_H_ 40 41 #if defined(_KERNEL) 42 #include <sys/bus.h> 43 44 /* 45 * The following macro has no business being in twa_reg.h. It should probably 46 * be defined in twa_includes.h, before the #include twa_reg.h.... But that 47 * causes the API to run into build errors. Will leave it here for now... 48 */ 49 #define TWA_64BIT_ADDRESSES ((sizeof(bus_addr_t) == 8) ? 1 : 0) 50 51 /* 52 * Define the following here since it relies on TWA_64BIT_ADDRESSES which 53 * depends on sizeof(bus_addr_t), which is not exported to userland. 54 * The userland API shouldn't care about the kernel's bus_addr_t. 55 * For the userland API, use the array size that we would use for 32-bit 56 * addresses since that's what we use in the sg structure definition. 57 * The userland API does not actually appear to use the array, but it 58 * does include the array in various command structures. 59 */ 60 #define TWA_MAX_SG_ELEMENTS (TWA_64BIT_ADDRESSES ? 70 : 105) 61 #else 62 #define TWA_MAX_SG_ELEMENTS 105 63 #endif 64 65 #define TWAQ_FREE 0 66 #define TWAQ_BUSY 1 67 #define TWAQ_PENDING 2 68 #define TWAQ_COMPLETE 3 69 #define TWAQ_IO_PENDING 4 70 #define TWAQ_COUNT 5 /* total number of queues */ 71 72 #define TWA_DRIVER_VERSION_STRING "1.00.00.000" 73 74 #define TWA_REQUEST_TIMEOUT_PERIOD 60 /* seconds */ 75 76 #define TWA_MESSAGE_SOURCE_CONTROLLER_ERROR 3 77 78 /* Register offsets from base address. */ 79 #define TWA_CONTROL_REGISTER_OFFSET 0x0 80 #define TWA_STATUS_REGISTER_OFFSET 0x4 81 #define TWA_COMMAND_QUEUE_OFFSET 0x8 82 #define TWA_RESPONSE_QUEUE_OFFSET 0xC 83 #define TWA_COMMAND_QUEUE_OFFSET_LOW 0x20 84 #define TWA_COMMAND_QUEUE_OFFSET_HIGH 0x24 85 86 #if defined(_KERNEL) 87 #define TWA_WRITE_REGISTER(sc, offset, val) \ 88 bus_space_write_4(sc->twa_bus_iot, sc->twa_bus_ioh, offset, (uint32_t)val) 89 90 #define TWA_WRITE_COMMAND_QUEUE(sc, val) \ 91 do { \ 92 if (TWA_64BIT_ADDRESSES) { \ 93 /* First write the low 4 bytes, then the high 4. */ \ 94 TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_LOW, \ 95 (uint32_t)(val)); \ 96 TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_HIGH,\ 97 (uint32_t)(((uint64_t)val)>>32)); \ 98 } else \ 99 TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET,\ 100 (uint32_t)(val)); \ 101 } while (0) 102 #endif 103 104 /* Control register bit definitions. */ 105 #define TWA_CONTROL_CLEAR_SBUF_WRITE_ERROR 0x00000008 106 #define TWA_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 107 #define TWA_CONTROL_DISABLE_INTERRUPTS 0x00000040 108 #define TWA_CONTROL_ENABLE_INTERRUPTS 0x00000080 109 #define TWA_CONTROL_ISSUE_SOFT_RESET 0x00000100 110 #define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000 111 #define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000 112 #define TWA_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000 113 #define TWA_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000 114 #define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000 115 #define TWA_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000 116 #define TWA_CONTROL_CLEAR_PCI_ABORT 0x00100000 117 #define TWA_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 118 #define TWA_CONTROL_CLEAR_PARITY_ERROR 0x00800000 119 120 /* Status register bit definitions. */ 121 #define TWA_STATUS_ROM_BIOS_IN_SBUF 0x00000002 122 #define TWA_STATUS_SBUF_WRITE_ERROR 0x00000008 123 #define TWA_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 124 #define TWA_STATUS_MICROCONTROLLER_READY 0x00002000 125 #define TWA_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000 126 #define TWA_STATUS_COMMAND_QUEUE_FULL 0x00008000 127 #define TWA_STATUS_RESPONSE_INTERRUPT 0x00010000 128 #define TWA_STATUS_COMMAND_INTERRUPT 0x00020000 129 #define TWA_STATUS_ATTENTION_INTERRUPT 0x00040000 130 #define TWA_STATUS_HOST_INTERRUPT 0x00080000 131 #define TWA_STATUS_PCI_ABORT_INTERRUPT 0x00100000 132 #define TWA_STATUS_MICROCONTROLLER_ERROR 0x00200000 133 #define TWA_STATUS_QUEUE_ERROR_INTERRUPT 0x00400000 134 #define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT 0x00800000 135 #define TWA_STATUS_MINOR_VERSION_MASK 0x0F000000 136 #define TWA_STATUS_MAJOR_VERSION_MASK 0xF0000000 137 138 #define TWA_STATUS_EXPECTED_BITS 0x00002000 139 #define TWA_STATUS_UNEXPECTED_BITS 0x00F00000 140 141 /* For use with the %b printf format. */ 142 #define TWA_STATUS_BITS_DESCRIPTION \ 143 "\20\15CMD_Q_EMPTY\16MC_RDY\17RESP_Q_EMPTY\20CMD_Q_FULL\21RESP_INTR\22CMD_INTR\23ATTN_INTR\24HOST_INTR\25PCI_ABRT\26MC_ERR\27Q_ERR\30PCI_PERR\n" 144 145 /* Detect inconsistencies in the status register. */ 146 #define TWA_STATUS_ERRORS(x) \ 147 ((x & TWA_STATUS_UNEXPECTED_BITS) && \ 148 (x & TWA_STATUS_MICROCONTROLLER_READY)) 149 150 /* PCI related defines. */ 151 #define TWA_IO_CONFIG_REG 0x10 152 #define TWA_DEVICE_NAME "3ware 9000 series Storage Controller" 153 #define TWA_VENDOR_ID 0x13C1 154 #define TWA_DEVICE_ID_9K 0x1002 155 156 #define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR 0xc100 157 #define TWA_PCI_CONFIG_CLEAR_PCI_ABORT 0x2000 158 159 /* Command packet opcodes. */ 160 #define TWA_OP_NOP 0x00 161 #define TWA_OP_INIT_CONNECTION 0x01 162 #define TWA_OP_READ 0x02 163 #define TWA_OP_WRITE 0x03 164 #define TWA_OP_READVERIFY 0x04 165 #define TWA_OP_VERIFY 0x05 166 #define TWA_OP_ZEROUNIT 0x08 167 #define TWA_OP_REPLACEUNIT 0x09 168 #define TWA_OP_HOTSWAP 0x0A 169 #define TWA_OP_SELFTESTS 0x0B 170 #define TWA_OP_SYNC_PARAM 0x0C 171 #define TWA_OP_REORDER_UNITS 0x0D 172 #define TWA_OP_FLUSH 0x0E 173 #define TWA_OP_EXECUTE_SCSI_COMMAND 0x10 174 #define TWA_OP_ATA_PASSTHROUGH 0x11 175 #define TWA_OP_GET_PARAM 0x12 176 #define TWA_OP_SET_PARAM 0x13 177 #define TWA_OP_CREATEUNIT 0x14 178 #define TWA_OP_DELETEUNIT 0x15 179 #define TWA_OP_DOWNLOAD_FIRMWARE 0x16 180 #define TWA_OP_REBUILDUNIT 0x17 181 #define TWA_OP_POWER_MANAGEMENT 0x18 182 183 #define TWA_OP_REMOTE_PRINT 0x1B 184 #define TWA_OP_RESET_FIRMWARE 0x1C 185 #define TWA_OP_DEBUG 0x1D 186 187 #define TWA_OP_DIAGNOSTICS 0x1F 188 189 /* Misc defines. */ 190 #define TWA_ALIGNMENT 0x4 191 #define TWA_MAX_UNITS 16 192 #define TWA_INIT_MESSAGE_CREDITS 0x100 193 #define TWA_SHUTDOWN_MESSAGE_CREDITS 0x001 194 #define TWA_64BIT_SG_ADDRESSES 0x00000001 195 #define TWA_EXTENDED_INIT_CONNECT 0x00000002 196 #define TWA_BASE_MODE 1 197 #define TWA_BASE_FW_SRL 24 198 #define TWA_BASE_FW_BRANCH 0 199 #define TWA_BASE_FW_BUILD 1 200 #define TWA_CURRENT_FW_SRL 28 201 #define TWA_CURRENT_FW_BRANCH 4 202 #define TWA_CURRENT_FW_BUILD 9 203 #define TWA_9000_ARCH_ID 0x5 /* 9000 series controllers */ 204 #define TWA_CTLR_FW_SAME_OR_NEWER 0x00000001 205 #define TWA_CTLR_FW_COMPATIBLE 0x00000002 206 #define TWA_BUNDLED_FW_SAFE_TO_FLASH 0x00000004 207 #define TWA_CTLR_FW_RECOMMENDS_FLASH 0x00000008 208 #define NUM_FW_IMAGE_CHUNKS 5 209 #define TWA_MAX_IO_SIZE 0x20000 /* 128K */ 210 /* #define TWA_MAX_SG_ELEMENTS defined above */ 211 #define TWA_MAX_ATA_SG_ELEMENTS 60 212 #define TWA_Q_LENGTH TWA_INIT_MESSAGE_CREDITS 213 #define TWA_MAX_RESET_TRIES 3 214 #define TWA_SECTOR_SIZE 0x200 /* generic I/O bufffer */ 215 #define TWA_SENSE_DATA_LENGTH 18 216 217 #define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x010a 218 #define TWA_ERROR_UNIT_OFFLINE 0x0128 219 #define TWA_ERROR_MORE_DATA 0x0231 220 221 /* Scatter/Gather list entry. */ 222 struct twa_sg { 223 #if defined(_KERNEL) 224 bus_addr_t address; 225 #else 226 uint32_t xx_address_xx; /* Fail if userland tries to use this */ 227 #endif 228 uint32_t length; 229 } __attribute__ ((packed)); 230 231 232 /* 7000 structures. */ 233 struct twa_command_init_connect { 234 uint8_t opcode:5; /* TWA_OP_INITCONNECTION */ 235 uint8_t res1:3; 236 uint8_t size; 237 uint8_t request_id; 238 uint8_t res2; 239 uint8_t status; 240 uint8_t flags; 241 uint16_t message_credits; 242 uint32_t features; 243 uint16_t fw_srl; 244 uint16_t fw_arch_id; 245 uint16_t fw_branch; 246 uint16_t fw_build; 247 uint32_t result; 248 }__attribute__ ((packed)); 249 250 struct twa_command_download_firmware { 251 uint8_t opcode:5; /* TWA_DOWNLOAD_FIRMWARE */ 252 uint8_t sgl_offset:3; 253 uint8_t size; 254 uint8_t request_id; 255 uint8_t unit; 256 uint8_t status; 257 uint8_t flags; 258 uint16_t param; 259 uint8_t sgl[1]; 260 } __attribute__ ((packed)); 261 262 263 struct twa_command_reset_firmware { 264 uint8_t opcode:5; /* TWA_OP_RESET_FIRMWARE */ 265 uint8_t res1:3; 266 uint8_t size; 267 uint8_t request_id; 268 uint8_t unit; 269 uint8_t status; 270 uint8_t flags; 271 uint8_t res2; 272 uint8_t param; 273 } __attribute__ ((packed)); 274 275 276 struct twa_command_io { 277 uint8_t opcode:5; /* TWA_OP_READ/TWA_OP_WRITE */ 278 uint8_t sgl_offset:3; 279 uint8_t size; 280 uint8_t request_id; 281 uint8_t unit:4; 282 uint8_t host_id:4; 283 uint8_t status; 284 uint8_t flags; 285 uint16_t block_count; 286 uint32_t lba; 287 struct twa_sg sgl[TWA_MAX_SG_ELEMENTS]; 288 } __attribute__ ((packed)); 289 290 291 struct twa_command_hotswap { 292 uint8_t opcode:5; /* TWA_OP_HOTSWAP */ 293 uint8_t res1:3; 294 uint8_t size; 295 uint8_t request_id; 296 uint8_t unit:4; 297 uint8_t host_id:4; 298 uint8_t status; 299 uint8_t flags; 300 uint8_t action; 301 #define TWA_OP_HOTSWAP_REMOVE 0x00 /* remove assumed-degraded unit */ 302 #define TWA_OP_HOTSWAP_ADD_CBOD 0x01 /* add CBOD to empty port */ 303 #define TWA_OP_HOTSWAP_ADD_SPARE 0x02 /* add spare to empty port */ 304 uint8_t aport; 305 } __attribute__ ((packed)); 306 307 308 struct twa_command_param { 309 uint8_t opcode:5; /* TWA_OP_GETPARAM, TWA_OP_SETPARAM */ 310 uint8_t sgl_offset:3; 311 uint8_t size; 312 uint8_t request_id; 313 uint8_t unit:4; 314 uint8_t host_id:4; 315 uint8_t status; 316 uint8_t flags; 317 uint16_t param_count; 318 uint8_t sgl[1]; 319 } __attribute__ ((packed)); 320 321 322 struct twa_command_rebuildunit { 323 uint8_t opcode:5; /* TWA_OP_REBUILDUNIT */ 324 uint8_t res1:3; 325 uint8_t size; 326 uint8_t request_id; 327 uint8_t src_unit:4; 328 uint8_t host_id:4; 329 uint8_t status; 330 uint8_t flags; 331 uint8_t action:7; 332 #define TWA_OP_REBUILDUNIT_NOP 0 333 #define TWA_OP_REBUILDUNIT_STOP 2 /* stop all rebuilds */ 334 #define TWA_OP_REBUILDUNIT_START 4 /* start rebuild with lowest unit */ 335 #define TWA_OP_REBUILDUNIT_STARTUNIT 5 /* rebuild src_unit (not supported) */ 336 uint8_t cs:1; /* request state change on src_unit */ 337 uint8_t logical_subunit; /* for RAID10 rebuild of logical subunit */ 338 } __attribute__ ((packed)); 339 340 341 struct twa_command_ata { 342 uint8_t opcode:5; /* TWA_OP_ATA_PASSTHROUGH */ 343 uint8_t sgl_offset:3; 344 uint8_t size; 345 uint8_t request_id; 346 uint8_t unit:4; 347 uint8_t host_id:4; 348 uint8_t status; 349 uint8_t flags; 350 uint16_t param; 351 uint16_t features; 352 uint16_t sector_count; 353 uint16_t sector_num; 354 uint16_t cylinder_lo; 355 uint16_t cylinder_hi; 356 uint8_t drive_head; 357 uint8_t command; 358 struct twa_sg sgl[TWA_MAX_ATA_SG_ELEMENTS]; 359 } __attribute__ ((packed)); 360 361 362 struct twa_command_generic { 363 uint8_t opcode:5; 364 uint8_t sgl_offset:3; 365 uint8_t size; 366 uint8_t request_id; 367 uint8_t unit:4; 368 uint8_t host_id:4; 369 uint8_t status; 370 uint8_t flags; 371 #define TWA_FLAGS_SUCCESS 0x00 372 #define TWA_FLAGS_INFORMATIONAL 0x01 373 #define TWA_FLAGS_WARNING 0x02 374 #define TWA_FLAGS_FATAL 0x03 375 #define TWA_FLAGS_PERCENTAGE (1<<8) /* bits 0-6 indicate completion percentage */ 376 uint16_t count; /* block count, parameter count, message credits */ 377 } __attribute__ ((packed)); 378 379 /* Command packet header. */ 380 #pragma pack(1) 381 struct twa_command_header { 382 uint8_t sense_data[TWA_SENSE_DATA_LENGTH]; 383 struct { 384 int8_t reserved[4]; 385 uint16_t error; 386 uint8_t padding; 387 struct { 388 uint8_t severity:3; 389 uint8_t reserved:5; 390 } substatus_block; 391 } status_block; 392 uint8_t err_specific_desc[98]; 393 struct { 394 uint8_t size_header; 395 uint16_t reserved; 396 uint8_t size_sense; 397 } header_desc; 398 } __attribute__ ((packed)); 399 #pragma pack() 400 401 402 /* Command packet - must be TWA_ALIGNMENT aligned. */ 403 union twa_command_7k { 404 struct twa_command_init_connect init_connect; 405 struct twa_command_download_firmware download_fw; 406 struct twa_command_reset_firmware reset_fw; 407 struct twa_command_param param; 408 struct twa_command_generic generic; 409 uint8_t padding[1024 - sizeof(struct twa_command_header)]; 410 } __attribute__ ((packed)); 411 412 413 /* 9000 structures. */ 414 415 /* Command Packet. */ 416 struct twa_command_9k { 417 struct { 418 uint8_t opcode:5; 419 uint8_t reserved:3; 420 } command; 421 uint8_t unit; 422 uint16_t request_id; 423 uint8_t status; 424 uint8_t sgl_offset; /* offset (in bytes) to sg_list, from the end of sgl_entries */ 425 uint16_t sgl_entries; 426 uint8_t cdb[16]; 427 struct twa_sg sg_list[TWA_MAX_SG_ELEMENTS]; 428 uint8_t padding[32]; 429 } __attribute__ ((packed)); 430 431 432 433 /* Full command packet. */ 434 struct twa_command_packet { 435 struct twa_command_header cmd_hdr; 436 union { 437 union twa_command_7k cmd_pkt_7k; 438 struct twa_command_9k cmd_pkt_9k; 439 } command; 440 } __attribute__ ((packed)); 441 442 443 /* Response queue entry. */ 444 union twa_response_queue { 445 struct { 446 uint32_t undefined_1:4; 447 uint32_t response_id:8; 448 uint32_t undefined_2:20; 449 } u; 450 uint32_t value; 451 } __attribute__ ((packed)); 452 453 454 #define TWA_AEN_QUEUE_EMPTY 0x00 455 #define TWA_AEN_SOFT_RESET 0x01 456 #define TWA_AEN_SYNC_TIME_WITH_HOST 0x31 457 #define TWA_AEN_SEVERITY_ERROR 0x1 458 #define TWA_AEN_SEVERITY_WARNING 0x2 459 #define TWA_AEN_SEVERITY_INFO 0x3 460 #define TWA_AEN_SEVERITY_DEBUG 0x4 461 462 #define TWA_PARAM_DRIVESUMMARY 0x0002 463 #define TWA_PARAM_DRIVESTATUS 3 464 465 #define TWA_DRIVE_DETECTED 0x80 466 467 #define TWA_PARAM_DRIVE_TABLE 0x0200 468 #define TWA_PARAM_DRIVESIZEINDEX 2 469 #define TWA_PARAM_DRIVEMODELINDEX 3 470 471 #define TWA_PARAM_DRIVESIZE_LENGTH 4 472 #define TWA_PARAM_DRIVEMODEL_LENGTH 40 473 474 475 #define TWA_PARAM_VERSION 0x0402 476 #define TWA_PARAM_VERSION_Mon 2 /* monitor version [16] */ 477 #define TWA_PARAM_VERSION_FW 3 /* firmware version [16] */ 478 #define TWA_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */ 479 #define TWA_PARAM_VERSION_PCBA 5 /* PCB version [8] */ 480 #define TWA_PARAM_VERSION_ATA 6 /* A-chip version [8] */ 481 #define TWA_PARAM_VERSION_PCI 7 /* P-chip version [8] */ 482 483 #define TWA_PARAM_CONTROLLER 0x0403 484 #define TWA_PARAM_CONTROLLER_PortCount 3 /* number of ports [1] */ 485 486 #define TWA_PARAM_TIME_TABLE 0x40A 487 #define TWA_PARAM_TIME_SchedulerTime 0x3 488 489 #define TWA_9K_PARAM_DESCRIPTOR 0x8000 490 491 492 struct twa_param_9k { 493 uint16_t table_id; 494 uint8_t parameter_id; 495 uint8_t reserved; 496 uint16_t parameter_size_bytes; 497 uint16_t parameter_actual_size_bytes; 498 uint8_t data[1]; 499 } __attribute__ ((packed)); 500 501 #endif /* !_PCI_TWAREG_H_ */ 502
Indexes created Tue Sep 23 23:09:58 GMT 2025