twe.c revision 1.16
1 /* $NetBSD: twe.c,v 1.16 2001/07/19 16:36:16 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twe.c,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 /* 69 * Driver for the 3ware Escalade family of RAID controllers. 70 */ 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/kernel.h> 75 #include <sys/device.h> 76 #include <sys/queue.h> 77 #include <sys/proc.h> 78 #include <sys/buf.h> 79 #include <sys/endian.h> 80 #include <sys/malloc.h> 81 #include <sys/disk.h> 82 83 #include <uvm/uvm_extern.h> 84 85 #include <machine/bswap.h> 86 #include <machine/bus.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 #include <dev/pci/twereg.h> 92 #include <dev/pci/twevar.h> 93 94 #define TWE_INL(sc, port) \ 95 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, port) 96 #define TWE_OUTL(sc, port, val) \ 97 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, port, val) 98 99 #define PCI_CBIO 0x10 100 101 static void twe_aen_handler(struct twe_ccb *, int); 102 static void twe_attach(struct device *, struct device *, void *); 103 static int twe_init_connection(struct twe_softc *); 104 static int twe_intr(void *); 105 static int twe_match(struct device *, struct cfdata *, void *); 106 static int twe_param_get(struct twe_softc *, int, int, size_t, 107 void (*)(struct twe_ccb *, int), void **); 108 static void twe_poll(struct twe_softc *); 109 static int twe_print(void *, const char *); 110 static int twe_reset(struct twe_softc *); 111 static int twe_submatch(struct device *, struct cfdata *, void *); 112 static int twe_status_check(struct twe_softc *, u_int); 113 static int twe_status_wait(struct twe_softc *, u_int, int); 114 115 struct cfattach twe_ca = { 116 sizeof(struct twe_softc), twe_match, twe_attach 117 }; 118 119 struct { 120 const u_int aen; /* High byte non-zero if w/unit */ 121 const char *desc; 122 } static const twe_aen_names[] = { 123 { 0x0000, "queue empty" }, 124 { 0x0001, "soft reset" }, 125 { 0x0102, "degraded mirror" }, 126 { 0x0003, "controller error" }, 127 { 0x0104, "rebuild fail" }, 128 { 0x0105, "rebuild done" }, 129 { 0x0106, "incompatible unit" }, 130 { 0x0107, "init done" }, 131 { 0x0108, "unclean shutdown" }, 132 { 0x0109, "aport timeout" }, 133 { 0x010a, "drive error" }, 134 { 0x010b, "rebuild started" }, 135 { 0x010c, "init started" }, 136 { 0x0015, "table undefined" }, 137 { 0x00ff, "aen queue full" }, 138 }; 139 140 /* 141 * Match a supported board. 142 */ 143 static int 144 twe_match(struct device *parent, struct cfdata *cfdata, void *aux) 145 { 146 struct pci_attach_args *pa; 147 148 pa = aux; 149 150 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3WARE && 151 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE || 152 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE_ASIC)); 153 } 154 155 /* 156 * Attach a supported board. 157 * 158 * XXX This doesn't fail gracefully. 159 */ 160 static void 161 twe_attach(struct device *parent, struct device *self, void *aux) 162 { 163 struct pci_attach_args *pa; 164 struct twe_softc *sc; 165 pci_chipset_tag_t pc; 166 pci_intr_handle_t ih; 167 pcireg_t csr; 168 const char *intrstr; 169 int size, i, rv, rseg; 170 struct twe_param *dtp, *ctp; 171 bus_dma_segment_t seg; 172 struct twe_cmd *tc; 173 struct twe_attach_args twea; 174 struct twe_ccb *ccb; 175 176 sc = (struct twe_softc *)self; 177 pa = aux; 178 pc = pa->pa_pc; 179 sc->sc_dmat = pa->pa_dmat; 180 SIMPLEQ_INIT(&sc->sc_ccb_queue); 181 SLIST_INIT(&sc->sc_ccb_freelist); 182 183 printf(": 3ware Escalade\n"); 184 185 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 186 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 187 printf("%s: can't map i/o space\n", sc->sc_dv.dv_xname); 188 return; 189 } 190 191 /* Enable the device. */ 192 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 193 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 194 csr | PCI_COMMAND_MASTER_ENABLE); 195 196 /* Map and establish the interrupt. */ 197 if (pci_intr_map(pa, &ih)) { 198 printf("%s: can't map interrupt\n", sc->sc_dv.dv_xname); 199 return; 200 } 201 intrstr = pci_intr_string(pc, ih); 202 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, twe_intr, sc); 203 if (sc->sc_ih == NULL) { 204 printf("%s: can't establish interrupt", sc->sc_dv.dv_xname); 205 if (intrstr != NULL) 206 printf(" at %s", intrstr); 207 printf("\n"); 208 return; 209 } 210 if (intrstr != NULL) 211 printf("%s: interrupting at %s\n", sc->sc_dv.dv_xname, intrstr); 212 213 /* 214 * Allocate and initialise the command blocks and CCBs. 215 */ 216 size = sizeof(struct twe_cmd) * TWE_MAX_QUEUECNT; 217 218 if ((rv = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 1, 219 &rseg, BUS_DMA_NOWAIT)) != 0) { 220 printf("%s: unable to allocate commands, rv = %d\n", 221 sc->sc_dv.dv_xname, rv); 222 return; 223 } 224 225 if ((rv = bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 226 (caddr_t *)&sc->sc_cmds, 227 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 228 printf("%s: unable to map commands, rv = %d\n", 229 sc->sc_dv.dv_xname, rv); 230 return; 231 } 232 233 if ((rv = bus_dmamap_create(sc->sc_dmat, size, size, 1, 0, 234 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 235 printf("%s: unable to create command DMA map, rv = %d\n", 236 sc->sc_dv.dv_xname, rv); 237 return; 238 } 239 240 if ((rv = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cmds, 241 size, NULL, BUS_DMA_NOWAIT)) != 0) { 242 printf("%s: unable to load command DMA map, rv = %d\n", 243 sc->sc_dv.dv_xname, rv); 244 return; 245 } 246 247 sc->sc_cmds_paddr = sc->sc_dmamap->dm_segs[0].ds_addr; 248 memset(sc->sc_cmds, 0, size); 249 250 ccb = malloc(sizeof(*ccb) * TWE_MAX_QUEUECNT, M_DEVBUF, M_NOWAIT); 251 sc->sc_ccbs = ccb; 252 tc = (struct twe_cmd *)sc->sc_cmds; 253 254 for (i = 0; i < TWE_MAX_QUEUECNT; i++, tc++, ccb++) { 255 ccb->ccb_cmd = tc; 256 ccb->ccb_cmdid = i; 257 ccb->ccb_flags = 0; 258 rv = bus_dmamap_create(sc->sc_dmat, TWE_MAX_XFER, 259 TWE_MAX_SEGS, PAGE_SIZE, 0, 260 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 261 &ccb->ccb_dmamap_xfer); 262 if (rv != 0) { 263 printf("%s: can't create dmamap, rv = %d\n", 264 sc->sc_dv.dv_xname, rv); 265 return; 266 } 267 /* Save one CCB for parameter retrieval. */ 268 if (i != 0) 269 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, 270 ccb_chain.slist); 271 } 272 273 /* Wait for the controller to become ready. */ 274 if (twe_status_wait(sc, TWE_STS_MICROCONTROLLER_READY, 6)) { 275 printf("%s: microcontroller not ready\n", sc->sc_dv.dv_xname); 276 return; 277 } 278 279 TWE_OUTL(sc, TWE_REG_CTL, TWE_CTL_DISABLE_INTRS); 280 281 /* Reset the controller. */ 282 if (twe_reset(sc)) { 283 printf("%s: reset failed\n", sc->sc_dv.dv_xname); 284 return; 285 } 286 287 /* Find attached units. */ 288 rv = twe_param_get(sc, TWE_PARAM_UNITSUMMARY, 289 TWE_PARAM_UNITSUMMARY_Status, TWE_MAX_UNITS, NULL, (void **)&dtp); 290 if (rv != 0) { 291 printf("%s: can't detect attached units (%d)\n", 292 sc->sc_dv.dv_xname, rv); 293 return; 294 } 295 296 /* For each detected unit, collect size and store in an array. */ 297 for (i = 0, sc->sc_nunits = 0; i < TWE_MAX_UNITS; i++) { 298 /* Unit present? */ 299 if ((dtp->tp_data[i] & TWE_PARAM_UNITSTATUS_Online) == 0) { 300 sc->sc_dsize[i] = 0; 301 continue; 302 } 303 304 rv = twe_param_get(sc, TWE_PARAM_UNITINFO + i, 305 TWE_PARAM_UNITINFO_Capacity, 4, NULL, (void **)&ctp); 306 if (rv != 0) { 307 printf("%s: error %d fetching capacity for unit %d\n", 308 sc->sc_dv.dv_xname, rv, i); 309 continue; 310 } 311 312 sc->sc_dsize[i] = le32toh(*(u_int32_t *)ctp->tp_data); 313 free(ctp, M_DEVBUF); 314 sc->sc_nunits++; 315 } 316 free(dtp, M_DEVBUF); 317 318 /* Initialise connection with controller and enable interrupts. */ 319 twe_init_connection(sc); 320 TWE_OUTL(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR | 321 TWE_CTL_UNMASK_RESP_INTR | 322 TWE_CTL_ENABLE_INTRS); 323 324 /* Attach sub-devices. */ 325 for (i = 0; i < TWE_MAX_UNITS; i++) { 326 if (sc->sc_dsize[i] == 0) 327 continue; 328 twea.twea_unit = i; 329 config_found_sm(&sc->sc_dv, &twea, twe_print, twe_submatch); 330 } 331 } 332 333 /* 334 * Reset the controller. Currently only useful at attach time; must be 335 * called with interrupts blocked. 336 */ 337 static int 338 twe_reset(struct twe_softc *sc) 339 { 340 struct twe_param *tp; 341 u_int aen, status; 342 volatile u_int32_t junk; 343 int got, rv; 344 345 /* Issue a soft reset. */ 346 TWE_OUTL(sc, TWE_REG_CTL, TWE_CTL_ISSUE_SOFT_RESET | 347 TWE_CTL_CLEAR_HOST_INTR | 348 TWE_CTL_CLEAR_ATTN_INTR | 349 TWE_CTL_MASK_CMD_INTR | 350 TWE_CTL_MASK_RESP_INTR | 351 TWE_CTL_CLEAR_ERROR_STS | 352 TWE_CTL_DISABLE_INTRS); 353 354 if (twe_status_wait(sc, TWE_STS_ATTN_INTR, 15)) { 355 printf("%s: no attention interrupt\n", 356 sc->sc_dv.dv_xname); 357 return (-1); 358 } 359 360 /* Pull AENs out of the controller; look for a soft reset AEN. */ 361 for (got = 0;;) { 362 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 363 2, NULL, (void **)&tp); 364 if (rv != 0) 365 printf("%s: error %d while draining response queue\n", 366 sc->sc_dv.dv_xname, rv); 367 aen = TWE_AEN_CODE(le16toh(*(u_int16_t *)tp->tp_data)); 368 free(tp, M_DEVBUF); 369 if (aen == TWE_AEN_QUEUE_EMPTY) 370 break; 371 if (aen == TWE_AEN_SOFT_RESET) 372 got = 1; 373 } 374 if (!got) { 375 printf("%s: reset not reported\n", sc->sc_dv.dv_xname); 376 return (-1); 377 } 378 379 /* Check controller status. */ 380 status = TWE_INL(sc, TWE_REG_STS); 381 if (twe_status_check(sc, status)) { 382 printf("%s: controller errors detected\n", 383 sc->sc_dv.dv_xname); 384 return (-1); 385 } 386 387 /* Drain the response queue. */ 388 for (;;) { 389 status = TWE_INL(sc, TWE_REG_STS); 390 if (twe_status_check(sc, status) != 0) { 391 printf("%s: can't drain response queue\n", 392 sc->sc_dv.dv_xname); 393 return (-1); 394 } 395 if ((status & TWE_STS_RESP_QUEUE_EMPTY) != 0) 396 break; 397 junk = TWE_INL(sc, TWE_REG_RESP_QUEUE); 398 } 399 400 return (0); 401 } 402 403 /* 404 * Print autoconfiguration message for a sub-device. 405 */ 406 static int 407 twe_print(void *aux, const char *pnp) 408 { 409 struct twe_attach_args *twea; 410 411 twea = aux; 412 413 if (pnp != NULL) 414 printf("block device at %s", pnp); 415 printf(" unit %d", twea->twea_unit); 416 return (UNCONF); 417 } 418 419 /* 420 * Match a sub-device. 421 */ 422 static int 423 twe_submatch(struct device *parent, struct cfdata *cf, void *aux) 424 { 425 struct twe_attach_args *twea; 426 427 twea = aux; 428 429 if (cf->tweacf_unit != TWECF_UNIT_DEFAULT && 430 cf->tweacf_unit != twea->twea_unit) 431 return (0); 432 433 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 434 } 435 436 /* 437 * Interrupt service routine. 438 */ 439 static int 440 twe_intr(void *arg) 441 { 442 struct twe_softc *sc; 443 u_int status; 444 int caught, rv; 445 446 sc = arg; 447 caught = 0; 448 status = TWE_INL(sc, TWE_REG_STS); 449 twe_status_check(sc, status); 450 451 /* Host interrupts - purpose unknown. */ 452 if ((status & TWE_STS_HOST_INTR) != 0) { 453 #ifdef DIAGNOSTIC 454 printf("%s: host interrupt\n", sc->sc_dv.dv_xname); 455 #endif 456 TWE_OUTL(sc, TWE_REG_CTL, TWE_CTL_CLEAR_HOST_INTR); 457 caught = 1; 458 } 459 460 /* 461 * Attention interrupts, signalled when a controller or child device 462 * state change has occured. 463 */ 464 if ((status & TWE_STS_ATTN_INTR) != 0) { 465 if ((sc->sc_flags & TWEF_AEN) == 0) { 466 rv = twe_param_get(sc, TWE_PARAM_AEN, 467 TWE_PARAM_AEN_UnitCode, 2, twe_aen_handler, 468 NULL); 469 if (rv != 0) { 470 printf("%s: unable to retrieve AEN (%d)\n", 471 sc->sc_dv.dv_xname, rv); 472 TWE_OUTL(sc, TWE_REG_CTL, 473 TWE_CTL_CLEAR_ATTN_INTR); 474 } else 475 sc->sc_flags |= TWEF_AEN; 476 } 477 caught = 1; 478 } 479 480 /* 481 * Command interrupts, signalled when the controller can accept more 482 * commands. We don't use this; instead, we try to submit commands 483 * when we receive them, and when other commands have completed. 484 * Mask it so we don't get another one. 485 */ 486 if ((status & TWE_STS_CMD_INTR) != 0) { 487 #ifdef DIAGNOSTIC 488 printf("%s: command interrupt\n", sc->sc_dv.dv_xname); 489 #endif 490 TWE_OUTL(sc, TWE_REG_CTL, TWE_CTL_MASK_CMD_INTR); 491 caught = 1; 492 } 493 494 if ((status & TWE_STS_RESP_INTR) != 0) { 495 twe_poll(sc); 496 caught = 1; 497 } 498 499 return (caught); 500 } 501 502 /* 503 * Handle an AEN returned by the controller. 504 */ 505 static void 506 twe_aen_handler(struct twe_ccb *ccb, int error) 507 { 508 struct twe_softc *sc; 509 struct twe_param *tp; 510 const char *str; 511 u_int aen; 512 int i, hu, rv; 513 514 sc = (struct twe_softc *)ccb->ccb_tx.tx_dv; 515 tp = ccb->ccb_tx.tx_context; 516 twe_ccb_unmap(sc, ccb); 517 518 if (error) { 519 printf("%s: error retrieving AEN\n", sc->sc_dv.dv_xname); 520 aen = TWE_AEN_QUEUE_EMPTY; 521 } else 522 aen = le16toh(*(u_int16_t *)tp->tp_data); 523 free(tp, M_DEVBUF); 524 twe_ccb_free(sc, ccb); 525 526 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) { 527 TWE_OUTL(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 528 sc->sc_flags &= ~TWEF_AEN; 529 return; 530 } 531 532 str = "<unknown>"; 533 i = 0; 534 hu = 0; 535 536 while (i < sizeof(twe_aen_names) / sizeof(twe_aen_names[0])) { 537 if (TWE_AEN_CODE(twe_aen_names[i].aen) == TWE_AEN_CODE(aen)) { 538 str = twe_aen_names[i].desc; 539 hu = (TWE_AEN_UNIT(twe_aen_names[i].aen) != 0); 540 break; 541 } 542 i++; 543 } 544 printf("%s: AEN 0x%04x (%s) received", sc->sc_dv.dv_xname, 545 TWE_AEN_CODE(aen), str); 546 if (hu != 0) 547 printf(" for unit %d", TWE_AEN_UNIT(aen)); 548 printf("\n"); 549 550 /* 551 * Chain another retrieval in case interrupts have been 552 * coalesced. 553 */ 554 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 2, 555 twe_aen_handler, NULL); 556 if (rv != 0) 557 printf("%s: unable to retrieve AEN (%d)\n", 558 sc->sc_dv.dv_xname, rv); 559 } 560 561 /* 562 * Execute a TWE_OP_GET_PARAM command. If a callback function is provided, 563 * it will be called with generated context when the command has completed. 564 * If no callback is provided, the command will be executed synchronously 565 * and a pointer to a buffer containing the data returned. 566 * 567 * The caller or callback is responsible for freeing the buffer. 568 */ 569 static int 570 twe_param_get(struct twe_softc *sc, int table_id, int param_id, size_t size, 571 void (*func)(struct twe_ccb *, int), void **pbuf) 572 { 573 struct twe_ccb *ccb; 574 struct twe_cmd *tc; 575 struct twe_param *tp; 576 int rv, s; 577 578 rv = twe_ccb_alloc(sc, &ccb, 579 TWE_CCB_PARAM | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 580 if (rv != 0) 581 return (rv); 582 583 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 584 if (pbuf != NULL) 585 *pbuf = tp; 586 587 ccb->ccb_data = tp; 588 ccb->ccb_datasize = TWE_SECTOR_SIZE; 589 ccb->ccb_tx.tx_handler = func; 590 ccb->ccb_tx.tx_context = tp; 591 ccb->ccb_tx.tx_dv = &sc->sc_dv; 592 593 tc = ccb->ccb_cmd; 594 tc->tc_size = 2; 595 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 596 tc->tc_unit = 0; 597 tc->tc_count = htole16(1); 598 599 /* Fill in the outbound parameter data. */ 600 tp->tp_table_id = htole16(table_id); 601 tp->tp_param_id = param_id; 602 tp->tp_param_size = size; 603 604 /* Map the transfer. */ 605 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 606 twe_ccb_free(sc, ccb); 607 free(tp, M_DEVBUF); 608 return (rv); 609 } 610 611 /* Submit the command and either wait or let the callback handle it. */ 612 if (func == NULL) { 613 s = splbio(); 614 rv = twe_ccb_poll(sc, ccb, 5); 615 twe_ccb_unmap(sc, ccb); 616 twe_ccb_free(sc, ccb); 617 splx(s); 618 if (rv != 0) 619 free(tp, M_DEVBUF); 620 } else { 621 twe_ccb_enqueue(sc, ccb); 622 rv = 0; 623 } 624 625 return (rv); 626 } 627 628 /* 629 * Execute a TWE_OP_INIT_CONNECTION command. Return non-zero on error. 630 * Must be called with interrupts blocked. 631 */ 632 static int 633 twe_init_connection(struct twe_softc *sc) 634 { 635 struct twe_ccb *ccb; 636 struct twe_cmd *tc; 637 int rv; 638 639 if ((rv = twe_ccb_alloc(sc, &ccb, 0)) != 0) 640 return (rv); 641 642 /* Build the command. */ 643 tc = ccb->ccb_cmd; 644 tc->tc_size = 3; 645 tc->tc_opcode = TWE_OP_INIT_CONNECTION; 646 tc->tc_unit = 0; 647 tc->tc_count = htole16(TWE_MAX_CMDS); 648 tc->tc_args.init_connection.response_queue_pointer = 0; 649 650 /* Submit the command for immediate execution. */ 651 rv = twe_ccb_poll(sc, ccb, 5); 652 twe_ccb_free(sc, ccb); 653 return (rv); 654 } 655 656 /* 657 * Poll the controller for completed commands. Must be called with 658 * interrupts blocked. 659 */ 660 static void 661 twe_poll(struct twe_softc *sc) 662 { 663 struct twe_ccb *ccb; 664 int found; 665 u_int status, cmdid; 666 667 found = 0; 668 669 for (;;) { 670 status = TWE_INL(sc, TWE_REG_STS); 671 twe_status_check(sc, status); 672 673 if ((status & TWE_STS_RESP_QUEUE_EMPTY)) 674 break; 675 676 found = 1; 677 cmdid = TWE_INL(sc, TWE_REG_RESP_QUEUE); 678 cmdid = (cmdid & TWE_RESP_MASK) >> TWE_RESP_SHIFT; 679 if (cmdid >= TWE_MAX_QUEUECNT) { 680 printf("%s: bad completion\n", sc->sc_dv.dv_xname); 681 continue; 682 } 683 684 ccb = sc->sc_ccbs + cmdid; 685 if ((ccb->ccb_flags & TWE_CCB_ACTIVE) == 0) { 686 printf("%s: bad completion (not active)\n", 687 sc->sc_dv.dv_xname); 688 continue; 689 } 690 ccb->ccb_flags ^= TWE_CCB_COMPLETE | TWE_CCB_ACTIVE; 691 692 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 693 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, 694 sizeof(struct twe_cmd), 695 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 696 697 /* Pass notification to upper layers. */ 698 if (ccb->ccb_tx.tx_handler != NULL) 699 (*ccb->ccb_tx.tx_handler)(ccb, 700 ccb->ccb_cmd->tc_status != 0 ? EIO : 0); 701 } 702 703 /* If any commands have completed, run the software queue. */ 704 if (found) 705 twe_ccb_enqueue(sc, NULL); 706 } 707 708 /* 709 * Wait for `status' to be set in the controller status register. Return 710 * zero if found, non-zero if the operation timed out. 711 */ 712 static int 713 twe_status_wait(struct twe_softc *sc, u_int32_t status, int timo) 714 { 715 716 for (timo *= 10; timo != 0; timo--) { 717 if ((TWE_INL(sc, TWE_REG_STS) & status) == status) 718 break; 719 delay(100000); 720 } 721 722 return (timo == 0); 723 } 724 725 /* 726 * Complain if the status bits aren't what we expect. 727 */ 728 static int 729 twe_status_check(struct twe_softc *sc, u_int status) 730 { 731 int rv; 732 733 rv = 0; 734 735 if ((status & TWE_STS_EXPECTED_BITS) != TWE_STS_EXPECTED_BITS) { 736 printf("%s: missing status bits: 0x%08x\n", sc->sc_dv.dv_xname, 737 status & ~TWE_STS_EXPECTED_BITS); 738 rv = -1; 739 } 740 741 if ((status & TWE_STS_UNEXPECTED_BITS) != 0) { 742 printf("%s: unexpected status bits: 0x%08x\n", 743 sc->sc_dv.dv_xname, status & TWE_STS_UNEXPECTED_BITS); 744 rv = -1; 745 } 746 747 return (rv); 748 } 749 750 /* 751 * Allocate and initialise a CCB. 752 */ 753 int 754 twe_ccb_alloc(struct twe_softc *sc, struct twe_ccb **ccbp, int flags) 755 { 756 struct twe_cmd *tc; 757 struct twe_ccb *ccb; 758 int s; 759 760 s = splbio(); 761 if ((flags & TWE_CCB_PARAM) != 0) 762 ccb = sc->sc_ccbs; 763 else { 764 /* Allocate a CCB and command block. */ 765 if (SLIST_FIRST(&sc->sc_ccb_freelist) == NULL) { 766 splx(s); 767 return (EAGAIN); 768 } 769 ccb = SLIST_FIRST(&sc->sc_ccb_freelist); 770 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 771 } 772 #ifdef DIAGNOSTIC 773 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 774 panic("twe_ccb_alloc: CCB already allocated"); 775 flags |= TWE_CCB_ALLOCED; 776 #endif 777 splx(s); 778 779 /* Initialise some fields and return. */ 780 ccb->ccb_tx.tx_handler = NULL; 781 ccb->ccb_flags = flags; 782 tc = ccb->ccb_cmd; 783 tc->tc_status = 0; 784 tc->tc_flags = 0; 785 tc->tc_cmdid = ccb->ccb_cmdid; 786 *ccbp = ccb; 787 788 return (0); 789 } 790 791 /* 792 * Free a CCB. 793 */ 794 void 795 twe_ccb_free(struct twe_softc *sc, struct twe_ccb *ccb) 796 { 797 int s; 798 799 s = splbio(); 800 if ((ccb->ccb_flags & TWE_CCB_PARAM) == 0) 801 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, ccb_chain.slist); 802 ccb->ccb_flags = 0; 803 splx(s); 804 } 805 806 /* 807 * Map the specified CCB's command block and data buffer (if any) into 808 * controller visible space. Perform DMA synchronisation. 809 */ 810 int 811 twe_ccb_map(struct twe_softc *sc, struct twe_ccb *ccb) 812 { 813 struct twe_cmd *tc; 814 int flags, nsegs, i, s, rv; 815 void *data; 816 817 /* 818 * The data as a whole must be 512-byte aligned. 819 */ 820 if (((u_long)ccb->ccb_data & (TWE_ALIGNMENT - 1)) != 0) { 821 s = splvm(); 822 /* XXX */ 823 ccb->ccb_abuf = uvm_km_kmemalloc(kmem_map, uvmexp.kmem_object, 824 ccb->ccb_datasize, UVM_KMF_NOWAIT); 825 splx(s); 826 data = (void *)ccb->ccb_abuf; 827 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 828 memcpy(data, ccb->ccb_data, ccb->ccb_datasize); 829 } else { 830 ccb->ccb_abuf = (vaddr_t)0; 831 data = ccb->ccb_data; 832 } 833 834 /* 835 * Map the data buffer into bus space and build the S/G list. 836 */ 837 rv = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap_xfer, data, 838 ccb->ccb_datasize, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 839 ((ccb->ccb_flags & TWE_CCB_DATA_IN) ? 840 BUS_DMA_READ : BUS_DMA_WRITE)); 841 if (rv != 0) { 842 if (ccb->ccb_abuf != (vaddr_t)0) { 843 s = splvm(); 844 /* XXX */ 845 uvm_km_free(kmem_map, ccb->ccb_abuf, 846 ccb->ccb_datasize); 847 splx(s); 848 } 849 return (rv); 850 } 851 852 nsegs = ccb->ccb_dmamap_xfer->dm_nsegs; 853 tc = ccb->ccb_cmd; 854 tc->tc_size += 2 * nsegs; 855 856 /* The location of the S/G list is dependant upon command type. */ 857 switch (tc->tc_opcode >> 5) { 858 case 2: 859 for (i = 0; i < nsegs; i++) { 860 tc->tc_args.param.sgl[i].tsg_address = 861 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 862 tc->tc_args.param.sgl[i].tsg_length = 863 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 864 } 865 /* XXX Needed? */ 866 for (; i < TWE_SG_SIZE; i++) { 867 tc->tc_args.param.sgl[i].tsg_address = 0; 868 tc->tc_args.param.sgl[i].tsg_length = 0; 869 } 870 break; 871 case 3: 872 for (i = 0; i < nsegs; i++) { 873 tc->tc_args.io.sgl[i].tsg_address = 874 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 875 tc->tc_args.io.sgl[i].tsg_length = 876 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 877 } 878 /* XXX Needed? */ 879 for (; i < TWE_SG_SIZE; i++) { 880 tc->tc_args.io.sgl[i].tsg_address = 0; 881 tc->tc_args.io.sgl[i].tsg_length = 0; 882 } 883 break; 884 #ifdef DEBUG 885 default: 886 panic("twe_ccb_map: oops"); 887 #endif 888 } 889 890 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 891 flags = BUS_DMASYNC_PREREAD; 892 else 893 flags = 0; 894 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 895 flags |= BUS_DMASYNC_PREWRITE; 896 897 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 898 ccb->ccb_datasize, flags); 899 return (0); 900 } 901 902 /* 903 * Unmap the specified CCB's command block and data buffer (if any) and 904 * perform DMA synchronisation. 905 */ 906 void 907 twe_ccb_unmap(struct twe_softc *sc, struct twe_ccb *ccb) 908 { 909 int flags, s; 910 911 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 912 flags = BUS_DMASYNC_POSTREAD; 913 else 914 flags = 0; 915 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 916 flags |= BUS_DMASYNC_POSTWRITE; 917 918 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 919 ccb->ccb_datasize, flags); 920 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap_xfer); 921 922 if (ccb->ccb_abuf != (vaddr_t)0) { 923 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 924 memcpy(ccb->ccb_data, (void *)ccb->ccb_abuf, 925 ccb->ccb_datasize); 926 s = splvm(); 927 /* XXX */ 928 uvm_km_free(kmem_map, ccb->ccb_abuf, ccb->ccb_datasize); 929 splx(s); 930 } 931 } 932 933 /* 934 * Submit a command to the controller and poll on completion. Return 935 * non-zero on timeout (but don't check status, as some command types don't 936 * return status). Must be called with interrupts blocked. 937 */ 938 int 939 twe_ccb_poll(struct twe_softc *sc, struct twe_ccb *ccb, int timo) 940 { 941 int rv; 942 943 if ((rv = twe_ccb_submit(sc, ccb)) != 0) 944 return (rv); 945 946 for (timo *= 1000; timo != 0; timo--) { 947 twe_poll(sc); 948 if ((ccb->ccb_flags & TWE_CCB_COMPLETE) != 0) 949 break; 950 DELAY(100); 951 } 952 953 return (timo == 0); 954 } 955 956 /* 957 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 958 * the order that they were enqueued and try to submit their command blocks 959 * to the controller for execution. 960 */ 961 void 962 twe_ccb_enqueue(struct twe_softc *sc, struct twe_ccb *ccb) 963 { 964 int s; 965 966 s = splbio(); 967 968 if (ccb != NULL) 969 SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 970 971 while ((ccb = SIMPLEQ_FIRST(&sc->sc_ccb_queue)) != NULL) { 972 if (twe_ccb_submit(sc, ccb)) 973 break; 974 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 975 } 976 977 splx(s); 978 } 979 980 /* 981 * Submit the command block associated with the specified CCB to the 982 * controller for execution. Must be called with interrupts blocked. 983 */ 984 int 985 twe_ccb_submit(struct twe_softc *sc, struct twe_ccb *ccb) 986 { 987 bus_addr_t pa; 988 int rv; 989 u_int status; 990 991 /* Check to see if we can post a command. */ 992 status = TWE_INL(sc, TWE_REG_STS); 993 twe_status_check(sc, status); 994 995 if ((status & TWE_STS_CMD_QUEUE_FULL) == 0) { 996 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 997 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, sizeof(struct twe_cmd), 998 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 999 ccb->ccb_flags |= TWE_CCB_ACTIVE; 1000 pa = sc->sc_cmds_paddr + 1001 ccb->ccb_cmdid * sizeof(struct twe_cmd); 1002 TWE_OUTL(sc, TWE_REG_CMD_QUEUE, (u_int32_t)pa); 1003 rv = 0; 1004 } else 1005 rv = EBUSY; 1006 1007 return (rv); 1008 } 1009
Indexes created Wed Oct 01 07:09:59 GMT 2025