twe.c revision 1.20.4.3
1 /* $NetBSD: twe.c,v 1.20.4.3 2001/11/24 21:54:18 he Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twe.c,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 /* 69 * Driver for the 3ware Escalade family of RAID controllers. 70 */ 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/kernel.h> 75 #include <sys/device.h> 76 #include <sys/queue.h> 77 #include <sys/proc.h> 78 #include <sys/buf.h> 79 #include <sys/endian.h> 80 #include <sys/malloc.h> 81 #include <sys/disk.h> 82 83 #include <vm/vm.h> 84 #include <vm/vm_kern.h> 85 #include <uvm/uvm_extern.h> 86 #include <machine/bswap.h> 87 #include <machine/bus.h> 88 89 #include <dev/pci/pcireg.h> 90 #include <dev/pci/pcivar.h> 91 #include <dev/pci/pcidevs.h> 92 #include <dev/pci/twereg.h> 93 #include <dev/pci/twevar.h> 94 95 #define TWE_INL(sc, port) \ 96 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, port) 97 #define TWE_OUTL(sc, port, val) \ 98 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, port, val) 99 100 #define PCI_CBIO 0x10 101 102 static void twe_aen_handler(struct twe_ccb *, int); 103 static void twe_attach(struct device *, struct device *, void *); 104 static int twe_init_connection(struct twe_softc *); 105 static int twe_intr(void *); 106 static int twe_match(struct device *, struct cfdata *, void *); 107 static int twe_param_get(struct twe_softc *, int, int, size_t, 108 void (*)(struct twe_ccb *, int), void **); 109 static void twe_poll(struct twe_softc *); 110 static int twe_print(void *, const char *); 111 static int twe_reset(struct twe_softc *); 112 static int twe_submatch(struct device *, struct cfdata *, void *); 113 static int twe_status_check(struct twe_softc *, u_int); 114 static int twe_status_wait(struct twe_softc *, u_int, int); 115 116 struct cfattach twe_ca = { 117 sizeof(struct twe_softc), twe_match, twe_attach 118 }; 119 120 struct { 121 const u_int aen; /* High byte non-zero if w/unit */ 122 const char *desc; 123 } static const twe_aen_names[] = { 124 { 0x0000, "queue empty" }, 125 { 0x0001, "soft reset" }, 126 { 0x0102, "degraded mirror" }, 127 { 0x0003, "controller error" }, 128 { 0x0104, "rebuild fail" }, 129 { 0x0105, "rebuild done" }, 130 { 0x0106, "incompatible unit" }, 131 { 0x0107, "init done" }, 132 { 0x0108, "unclean shutdown" }, 133 { 0x0109, "aport timeout" }, 134 { 0x010a, "drive error" }, 135 { 0x010b, "rebuild started" }, 136 { 0x010c, "init started" }, 137 { 0x0015, "table undefined" }, 138 { 0x00ff, "aen queue full" }, 139 }; 140 141 /* 142 * Match a supported board. 143 */ 144 static int 145 twe_match(struct device *parent, struct cfdata *cfdata, void *aux) 146 { 147 struct pci_attach_args *pa; 148 149 pa = aux; 150 151 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3WARE && 152 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE || 153 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE_ASIC)); 154 } 155 156 /* 157 * Attach a supported board. 158 * 159 * XXX This doesn't fail gracefully. 160 */ 161 static void 162 twe_attach(struct device *parent, struct device *self, void *aux) 163 { 164 struct pci_attach_args *pa; 165 struct twe_softc *sc; 166 pci_chipset_tag_t pc; 167 pci_intr_handle_t ih; 168 pcireg_t csr; 169 const char *intrstr; 170 int size, i, rv, rseg; 171 struct twe_param *dtp, *ctp; 172 bus_dma_segment_t seg; 173 struct twe_cmd *tc; 174 struct twe_attach_args twea; 175 struct twe_ccb *ccb; 176 177 sc = (struct twe_softc *)self; 178 pa = aux; 179 pc = pa->pa_pc; 180 sc->sc_dmat = pa->pa_dmat; 181 SIMPLEQ_INIT(&sc->sc_ccb_queue); 182 SLIST_INIT(&sc->sc_ccb_freelist); 183 184 printf(": 3ware Escalade\n"); 185 186 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 187 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 188 printf("%s: can't map i/o space\n", sc->sc_dv.dv_xname); 189 return; 190 } 191 192 /* Enable the device. */ 193 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 194 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 195 csr | PCI_COMMAND_MASTER_ENABLE); 196 197 /* Map and establish the interrupt. */ 198 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, pa->pa_intrline, 199 &ih)) { 200 printf("%s: can't map interrupt\n", sc->sc_dv.dv_xname); 201 return; 202 } 203 intrstr = pci_intr_string(pc, ih); 204 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, twe_intr, sc); 205 if (sc->sc_ih == NULL) { 206 printf("%s: can't establish interrupt", sc->sc_dv.dv_xname); 207 if (intrstr != NULL) 208 printf(" at %s", intrstr); 209 printf("\n"); 210 return; 211 } 212 if (intrstr != NULL) 213 printf("%s: interrupting at %s\n", sc->sc_dv.dv_xname, intrstr); 214 215 /* 216 * Allocate and initialise the command blocks and CCBs. 217 */ 218 size = sizeof(struct twe_cmd) * TWE_MAX_QUEUECNT; 219 220 if ((rv = bus_dmamem_alloc(sc->sc_dmat, size, NBPG, 0, &seg, 1, 221 &rseg, BUS_DMA_NOWAIT)) != 0) { 222 printf("%s: unable to allocate commands, rv = %d\n", 223 sc->sc_dv.dv_xname, rv); 224 return; 225 } 226 227 if ((rv = bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 228 (caddr_t *)&sc->sc_cmds, 229 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 230 printf("%s: unable to map commands, rv = %d\n", 231 sc->sc_dv.dv_xname, rv); 232 return; 233 } 234 235 if ((rv = bus_dmamap_create(sc->sc_dmat, size, size, 1, 0, 236 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 237 printf("%s: unable to create command DMA map, rv = %d\n", 238 sc->sc_dv.dv_xname, rv); 239 return; 240 } 241 242 if ((rv = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cmds, 243 size, NULL, BUS_DMA_NOWAIT)) != 0) { 244 printf("%s: unable to load command DMA map, rv = %d\n", 245 sc->sc_dv.dv_xname, rv); 246 return; 247 } 248 249 sc->sc_cmds_paddr = sc->sc_dmamap->dm_segs[0].ds_addr; 250 memset(sc->sc_cmds, 0, size); 251 252 ccb = malloc(sizeof(*ccb) * TWE_MAX_QUEUECNT, M_DEVBUF, M_NOWAIT); 253 sc->sc_ccbs = ccb; 254 tc = (struct twe_cmd *)sc->sc_cmds; 255 256 for (i = 0; i < TWE_MAX_QUEUECNT; i++, tc++, ccb++) { 257 ccb->ccb_cmd = tc; 258 ccb->ccb_cmdid = i; 259 ccb->ccb_flags = 0; 260 rv = bus_dmamap_create(sc->sc_dmat, TWE_MAX_XFER, 261 TWE_MAX_SEGS, NBPG, 0, 262 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 263 &ccb->ccb_dmamap_xfer); 264 if (rv != 0) { 265 printf("%s: can't create dmamap, rv = %d\n", 266 sc->sc_dv.dv_xname, rv); 267 return; 268 } 269 /* Save one CCB for parameter retrieval. */ 270 if (i != 0) 271 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, 272 ccb_chain.slist); 273 } 274 275 /* Wait for the controller to become ready. */ 276 if (twe_status_wait(sc, TWE_STS_MICROCONTROLLER_READY, 6)) { 277 printf("%s: microcontroller not ready\n", sc->sc_dv.dv_xname); 278 return; 279 } 280 281 TWE_OUTL(sc, TWE_REG_CTL, TWE_CTL_DISABLE_INTRS); 282 283 /* Reset the controller. */ 284 if (twe_reset(sc)) { 285 printf("%s: reset failed\n", sc->sc_dv.dv_xname); 286 return; 287 } 288 289 /* Find attached units. */ 290 rv = twe_param_get(sc, TWE_PARAM_UNITSUMMARY, 291 TWE_PARAM_UNITSUMMARY_Status, TWE_MAX_UNITS, NULL, (void **)&dtp); 292 if (rv != 0) { 293 printf("%s: can't detect attached units (%d)\n", 294 sc->sc_dv.dv_xname, rv); 295 return; 296 } 297 298 /* For each detected unit, collect size and store in an array. */ 299 for (i = 0, sc->sc_nunits = 0; i < TWE_MAX_UNITS; i++) { 300 /* Unit present? */ 301 if ((dtp->tp_data[i] & TWE_PARAM_UNITSTATUS_Online) == 0) { 302 sc->sc_dsize[i] = 0; 303 continue; 304 } 305 306 rv = twe_param_get(sc, TWE_PARAM_UNITINFO + i, 307 TWE_PARAM_UNITINFO_Capacity, 4, NULL, (void **)&ctp); 308 if (rv != 0) { 309 printf("%s: error %d fetching capacity for unit %d\n", 310 sc->sc_dv.dv_xname, rv, i); 311 continue; 312 } 313 314 sc->sc_dsize[i] = le32toh(*(u_int32_t *)ctp->tp_data); 315 free(ctp, M_DEVBUF); 316 sc->sc_nunits++; 317 } 318 free(dtp, M_DEVBUF); 319 320 /* Initialise connection with controller and enable interrupts. */ 321 twe_init_connection(sc); 322 TWE_OUTL(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR | 323 TWE_CTL_UNMASK_RESP_INTR | 324 TWE_CTL_ENABLE_INTRS); 325 326 /* Attach sub-devices. */ 327 for (i = 0; i < TWE_MAX_UNITS; i++) { 328 if (sc->sc_dsize[i] == 0) 329 continue; 330 twea.twea_unit = i; 331 config_found_sm(&sc->sc_dv, &twea, twe_print, twe_submatch); 332 } 333 } 334 335 /* 336 * Reset the controller. Currently only useful at attach time; must be 337 * called with interrupts blocked. 338 */ 339 static int 340 twe_reset(struct twe_softc *sc) 341 { 342 struct twe_param *tp; 343 u_int aen, status; 344 volatile u_int32_t junk; 345 int got, rv; 346 347 /* Issue a soft reset. */ 348 TWE_OUTL(sc, TWE_REG_CTL, TWE_CTL_ISSUE_SOFT_RESET | 349 TWE_CTL_CLEAR_HOST_INTR | 350 TWE_CTL_CLEAR_ATTN_INTR | 351 TWE_CTL_MASK_CMD_INTR | 352 TWE_CTL_MASK_RESP_INTR | 353 TWE_CTL_CLEAR_ERROR_STS | 354 TWE_CTL_DISABLE_INTRS); 355 356 if (twe_status_wait(sc, TWE_STS_ATTN_INTR, 15)) { 357 printf("%s: no attention interrupt\n", 358 sc->sc_dv.dv_xname); 359 return (-1); 360 } 361 362 /* Pull AENs out of the controller; look for a soft reset AEN. */ 363 for (got = 0;;) { 364 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 365 2, NULL, (void **)&tp); 366 if (rv != 0) 367 printf("%s: error %d while draining response queue\n", 368 sc->sc_dv.dv_xname, rv); 369 aen = TWE_AEN_CODE(le16toh(*(u_int16_t *)tp->tp_data)); 370 free(tp, M_DEVBUF); 371 if (aen == TWE_AEN_QUEUE_EMPTY) 372 break; 373 if (aen == TWE_AEN_SOFT_RESET) 374 got = 1; 375 } 376 if (!got) { 377 printf("%s: reset not reported\n", sc->sc_dv.dv_xname); 378 return (-1); 379 } 380 381 /* Check controller status. */ 382 status = TWE_INL(sc, TWE_REG_STS); 383 if (twe_status_check(sc, status)) { 384 printf("%s: controller errors detected\n", 385 sc->sc_dv.dv_xname); 386 return (-1); 387 } 388 389 /* Drain the response queue. */ 390 for (;;) { 391 status = TWE_INL(sc, TWE_REG_STS); 392 if (twe_status_check(sc, status) != 0) { 393 printf("%s: can't drain response queue\n", 394 sc->sc_dv.dv_xname); 395 return (-1); 396 } 397 if ((status & TWE_STS_RESP_QUEUE_EMPTY) != 0) 398 break; 399 junk = TWE_INL(sc, TWE_REG_RESP_QUEUE); 400 } 401 402 return (0); 403 } 404 405 /* 406 * Print autoconfiguration message for a sub-device. 407 */ 408 static int 409 twe_print(void *aux, const char *pnp) 410 { 411 struct twe_attach_args *twea; 412 413 twea = aux; 414 415 if (pnp != NULL) 416 printf("block device at %s", pnp); 417 printf(" unit %d", twea->twea_unit); 418 return (UNCONF); 419 } 420 421 /* 422 * Match a sub-device. 423 */ 424 static int 425 twe_submatch(struct device *parent, struct cfdata *cf, void *aux) 426 { 427 struct twe_attach_args *twea; 428 429 twea = aux; 430 431 if (cf->tweacf_unit != TWECF_UNIT_DEFAULT && 432 cf->tweacf_unit != twea->twea_unit) 433 return (0); 434 435 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 436 } 437 438 /* 439 * Interrupt service routine. 440 */ 441 static int 442 twe_intr(void *arg) 443 { 444 struct twe_softc *sc; 445 u_int status; 446 int caught, rv; 447 448 sc = arg; 449 caught = 0; 450 status = TWE_INL(sc, TWE_REG_STS); 451 twe_status_check(sc, status); 452 453 /* Host interrupts - purpose unknown. */ 454 if ((status & TWE_STS_HOST_INTR) != 0) { 455 #ifdef DIAGNOSTIC 456 printf("%s: host interrupt\n", sc->sc_dv.dv_xname); 457 #endif 458 TWE_OUTL(sc, TWE_REG_CTL, TWE_CTL_CLEAR_HOST_INTR); 459 caught = 1; 460 } 461 462 /* 463 * Attention interrupts, signalled when a controller or child device 464 * state change has occurred. 465 */ 466 if ((status & TWE_STS_ATTN_INTR) != 0) { 467 if ((sc->sc_flags & TWEF_AEN) == 0) { 468 rv = twe_param_get(sc, TWE_PARAM_AEN, 469 TWE_PARAM_AEN_UnitCode, 2, twe_aen_handler, 470 NULL); 471 if (rv != 0) { 472 printf("%s: unable to retrieve AEN (%d)\n", 473 sc->sc_dv.dv_xname, rv); 474 TWE_OUTL(sc, TWE_REG_CTL, 475 TWE_CTL_CLEAR_ATTN_INTR); 476 } else 477 sc->sc_flags |= TWEF_AEN; 478 } 479 caught = 1; 480 } 481 482 /* 483 * Command interrupts, signalled when the controller can accept more 484 * commands. We don't use this; instead, we try to submit commands 485 * when we receive them, and when other commands have completed. 486 * Mask it so we don't get another one. 487 */ 488 if ((status & TWE_STS_CMD_INTR) != 0) { 489 #ifdef DIAGNOSTIC 490 printf("%s: command interrupt\n", sc->sc_dv.dv_xname); 491 #endif 492 TWE_OUTL(sc, TWE_REG_CTL, TWE_CTL_MASK_CMD_INTR); 493 caught = 1; 494 } 495 496 if ((status & TWE_STS_RESP_INTR) != 0) { 497 twe_poll(sc); 498 caught = 1; 499 } 500 501 return (caught); 502 } 503 504 /* 505 * Handle an AEN returned by the controller. 506 */ 507 static void 508 twe_aen_handler(struct twe_ccb *ccb, int error) 509 { 510 struct twe_softc *sc; 511 struct twe_param *tp; 512 const char *str; 513 u_int aen; 514 int i, hu, rv; 515 516 sc = (struct twe_softc *)ccb->ccb_tx.tx_dv; 517 tp = ccb->ccb_tx.tx_context; 518 twe_ccb_unmap(sc, ccb); 519 520 if (error) { 521 printf("%s: error retrieving AEN\n", sc->sc_dv.dv_xname); 522 aen = TWE_AEN_QUEUE_EMPTY; 523 } else 524 aen = le16toh(*(u_int16_t *)tp->tp_data); 525 free(tp, M_DEVBUF); 526 twe_ccb_free(sc, ccb); 527 528 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) { 529 TWE_OUTL(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 530 sc->sc_flags &= ~TWEF_AEN; 531 return; 532 } 533 534 str = "<unknown>"; 535 i = 0; 536 hu = 0; 537 538 while (i < sizeof(twe_aen_names) / sizeof(twe_aen_names[0])) { 539 if (TWE_AEN_CODE(twe_aen_names[i].aen) == TWE_AEN_CODE(aen)) { 540 str = twe_aen_names[i].desc; 541 hu = (TWE_AEN_UNIT(twe_aen_names[i].aen) != 0); 542 break; 543 } 544 i++; 545 } 546 printf("%s: AEN 0x%04x (%s) received", sc->sc_dv.dv_xname, 547 TWE_AEN_CODE(aen), str); 548 if (hu != 0) 549 printf(" for unit %d", TWE_AEN_UNIT(aen)); 550 printf("\n"); 551 552 /* 553 * Chain another retrieval in case interrupts have been 554 * coalesced. 555 */ 556 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 2, 557 twe_aen_handler, NULL); 558 if (rv != 0) 559 printf("%s: unable to retrieve AEN (%d)\n", 560 sc->sc_dv.dv_xname, rv); 561 } 562 563 /* 564 * Execute a TWE_OP_GET_PARAM command. If a callback function is provided, 565 * it will be called with generated context when the command has completed. 566 * If no callback is provided, the command will be executed synchronously 567 * and a pointer to a buffer containing the data returned. 568 * 569 * The caller or callback is responsible for freeing the buffer. 570 */ 571 static int 572 twe_param_get(struct twe_softc *sc, int table_id, int param_id, size_t size, 573 void (*func)(struct twe_ccb *, int), void **pbuf) 574 { 575 struct twe_ccb *ccb; 576 struct twe_cmd *tc; 577 struct twe_param *tp; 578 int rv, s; 579 580 rv = twe_ccb_alloc(sc, &ccb, 581 TWE_CCB_PARAM | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 582 if (rv != 0) 583 return (rv); 584 585 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 586 if (pbuf != NULL) 587 *pbuf = tp; 588 589 ccb->ccb_data = tp; 590 ccb->ccb_datasize = TWE_SECTOR_SIZE; 591 ccb->ccb_tx.tx_handler = func; 592 ccb->ccb_tx.tx_context = tp; 593 ccb->ccb_tx.tx_dv = &sc->sc_dv; 594 595 tc = ccb->ccb_cmd; 596 tc->tc_size = 2; 597 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 598 tc->tc_unit = 0; 599 tc->tc_count = htole16(1); 600 601 /* Fill in the outbound parameter data. */ 602 tp->tp_table_id = htole16(table_id); 603 tp->tp_param_id = param_id; 604 tp->tp_param_size = size; 605 606 /* Map the transfer. */ 607 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 608 twe_ccb_free(sc, ccb); 609 free(tp, M_DEVBUF); 610 return (rv); 611 } 612 613 /* Submit the command and either wait or let the callback handle it. */ 614 if (func == NULL) { 615 s = splbio(); 616 rv = twe_ccb_poll(sc, ccb, 5); 617 twe_ccb_unmap(sc, ccb); 618 twe_ccb_free(sc, ccb); 619 splx(s); 620 if (rv != 0) 621 free(tp, M_DEVBUF); 622 } else { 623 twe_ccb_enqueue(sc, ccb); 624 rv = 0; 625 } 626 627 return (rv); 628 } 629 630 /* 631 * Execute a TWE_OP_INIT_CONNECTION command. Return non-zero on error. 632 * Must be called with interrupts blocked. 633 */ 634 static int 635 twe_init_connection(struct twe_softc *sc) 636 { 637 struct twe_ccb *ccb; 638 struct twe_cmd *tc; 639 int rv; 640 641 if ((rv = twe_ccb_alloc(sc, &ccb, 0)) != 0) 642 return (rv); 643 644 /* Build the command. */ 645 tc = ccb->ccb_cmd; 646 tc->tc_size = 3; 647 tc->tc_opcode = TWE_OP_INIT_CONNECTION; 648 tc->tc_unit = 0; 649 tc->tc_count = htole16(TWE_MAX_CMDS); 650 tc->tc_args.init_connection.response_queue_pointer = 0; 651 652 /* Submit the command for immediate execution. */ 653 rv = twe_ccb_poll(sc, ccb, 5); 654 twe_ccb_free(sc, ccb); 655 return (rv); 656 } 657 658 /* 659 * Poll the controller for completed commands. Must be called with 660 * interrupts blocked. 661 */ 662 static void 663 twe_poll(struct twe_softc *sc) 664 { 665 struct twe_ccb *ccb; 666 int found; 667 u_int status, cmdid; 668 669 found = 0; 670 671 for (;;) { 672 status = TWE_INL(sc, TWE_REG_STS); 673 twe_status_check(sc, status); 674 675 if ((status & TWE_STS_RESP_QUEUE_EMPTY)) 676 break; 677 678 found = 1; 679 cmdid = TWE_INL(sc, TWE_REG_RESP_QUEUE); 680 cmdid = (cmdid & TWE_RESP_MASK) >> TWE_RESP_SHIFT; 681 if (cmdid >= TWE_MAX_QUEUECNT) { 682 printf("%s: bad completion\n", sc->sc_dv.dv_xname); 683 continue; 684 } 685 686 ccb = sc->sc_ccbs + cmdid; 687 if ((ccb->ccb_flags & TWE_CCB_ACTIVE) == 0) { 688 printf("%s: bad completion (not active)\n", 689 sc->sc_dv.dv_xname); 690 continue; 691 } 692 ccb->ccb_flags ^= TWE_CCB_COMPLETE | TWE_CCB_ACTIVE; 693 694 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 695 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, 696 sizeof(struct twe_cmd), 697 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 698 699 /* Pass notification to upper layers. */ 700 if (ccb->ccb_tx.tx_handler != NULL) 701 (*ccb->ccb_tx.tx_handler)(ccb, 702 ccb->ccb_cmd->tc_status != 0 ? EIO : 0); 703 } 704 705 /* If any commands have completed, run the software queue. */ 706 if (found) 707 twe_ccb_enqueue(sc, NULL); 708 } 709 710 /* 711 * Wait for `status' to be set in the controller status register. Return 712 * zero if found, non-zero if the operation timed out. 713 */ 714 static int 715 twe_status_wait(struct twe_softc *sc, u_int32_t status, int timo) 716 { 717 718 for (timo *= 10; timo != 0; timo--) { 719 if ((TWE_INL(sc, TWE_REG_STS) & status) == status) 720 break; 721 delay(100000); 722 } 723 724 return (timo == 0); 725 } 726 727 /* 728 * Complain if the status bits aren't what we expect. 729 */ 730 static int 731 twe_status_check(struct twe_softc *sc, u_int status) 732 { 733 int rv; 734 735 rv = 0; 736 737 if ((status & TWE_STS_EXPECTED_BITS) != TWE_STS_EXPECTED_BITS) { 738 printf("%s: missing status bits: 0x%08x\n", sc->sc_dv.dv_xname, 739 status & ~TWE_STS_EXPECTED_BITS); 740 rv = -1; 741 } 742 743 if ((status & TWE_STS_UNEXPECTED_BITS) != 0) { 744 printf("%s: unexpected status bits: 0x%08x\n", 745 sc->sc_dv.dv_xname, status & TWE_STS_UNEXPECTED_BITS); 746 rv = -1; 747 } 748 749 return (rv); 750 } 751 752 /* 753 * Allocate and initialise a CCB. 754 */ 755 int 756 twe_ccb_alloc(struct twe_softc *sc, struct twe_ccb **ccbp, int flags) 757 { 758 struct twe_cmd *tc; 759 struct twe_ccb *ccb; 760 int s; 761 762 s = splbio(); 763 if ((flags & TWE_CCB_PARAM) != 0) 764 ccb = sc->sc_ccbs; 765 else { 766 /* Allocate a CCB and command block. */ 767 if (SLIST_FIRST(&sc->sc_ccb_freelist) == NULL) { 768 splx(s); 769 return (EAGAIN); 770 } 771 ccb = SLIST_FIRST(&sc->sc_ccb_freelist); 772 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 773 } 774 #ifdef DIAGNOSTIC 775 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 776 panic("twe_ccb_alloc: CCB already allocated"); 777 flags |= TWE_CCB_ALLOCED; 778 #endif 779 splx(s); 780 781 /* Initialise some fields and return. */ 782 ccb->ccb_tx.tx_handler = NULL; 783 ccb->ccb_flags = flags; 784 tc = ccb->ccb_cmd; 785 tc->tc_status = 0; 786 tc->tc_flags = 0; 787 tc->tc_cmdid = ccb->ccb_cmdid; 788 *ccbp = ccb; 789 790 return (0); 791 } 792 793 /* 794 * Free a CCB. 795 */ 796 void 797 twe_ccb_free(struct twe_softc *sc, struct twe_ccb *ccb) 798 { 799 int s; 800 801 s = splbio(); 802 if ((ccb->ccb_flags & TWE_CCB_PARAM) == 0) 803 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, ccb_chain.slist); 804 ccb->ccb_flags = 0; 805 splx(s); 806 } 807 808 /* 809 * Map the specified CCB's command block and data buffer (if any) into 810 * controller visible space. Perform DMA synchronisation. 811 */ 812 int 813 twe_ccb_map(struct twe_softc *sc, struct twe_ccb *ccb) 814 { 815 struct twe_cmd *tc; 816 int flags, nsegs, i, s, rv; 817 void *data; 818 819 /* 820 * The data as a whole must be 512-byte aligned. 821 */ 822 if (((u_long)ccb->ccb_data & (TWE_ALIGNMENT - 1)) != 0) { 823 s = splimp(); 824 /* XXX */ 825 ccb->ccb_abuf = uvm_km_kmemalloc(kmem_map, uvmexp.kmem_object, 826 ccb->ccb_datasize, UVM_KMF_NOWAIT); 827 splx(s); 828 data = (void *)ccb->ccb_abuf; 829 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 830 memcpy(data, ccb->ccb_data, ccb->ccb_datasize); 831 } else { 832 ccb->ccb_abuf = (vaddr_t)0; 833 data = ccb->ccb_data; 834 } 835 836 /* 837 * Map the data buffer into bus space and build the S/G list. 838 */ 839 rv = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap_xfer, data, 840 ccb->ccb_datasize, NULL, BUS_DMA_NOWAIT); 841 if (rv != 0) { 842 if (ccb->ccb_abuf != (vaddr_t)0) { 843 s = splimp(); 844 /* XXX */ 845 uvm_km_free(kmem_map, ccb->ccb_abuf, 846 ccb->ccb_datasize); 847 splx(s); 848 } 849 return (rv); 850 } 851 852 nsegs = ccb->ccb_dmamap_xfer->dm_nsegs; 853 tc = ccb->ccb_cmd; 854 tc->tc_size += 2 * nsegs; 855 856 /* The location of the S/G list is dependant upon command type. */ 857 switch (tc->tc_opcode >> 5) { 858 case 2: 859 for (i = 0; i < nsegs; i++) { 860 tc->tc_args.param.sgl[i].tsg_address = 861 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 862 tc->tc_args.param.sgl[i].tsg_length = 863 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 864 } 865 /* XXX Needed? */ 866 for (; i < TWE_SG_SIZE; i++) { 867 tc->tc_args.param.sgl[i].tsg_address = 0; 868 tc->tc_args.param.sgl[i].tsg_length = 0; 869 } 870 break; 871 case 3: 872 for (i = 0; i < nsegs; i++) { 873 tc->tc_args.io.sgl[i].tsg_address = 874 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 875 tc->tc_args.io.sgl[i].tsg_length = 876 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 877 } 878 /* XXX Needed? */ 879 for (; i < TWE_SG_SIZE; i++) { 880 tc->tc_args.io.sgl[i].tsg_address = 0; 881 tc->tc_args.io.sgl[i].tsg_length = 0; 882 } 883 break; 884 #ifdef DEBUG 885 default: 886 panic("twe_ccb_map: oops"); 887 #endif 888 } 889 890 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 891 flags = BUS_DMASYNC_PREREAD; 892 else 893 flags = 0; 894 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 895 flags |= BUS_DMASYNC_PREWRITE; 896 897 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 898 ccb->ccb_datasize, flags); 899 return (0); 900 } 901 902 /* 903 * Unmap the specified CCB's command block and data buffer (if any) and 904 * perform DMA synchronisation. 905 */ 906 void 907 twe_ccb_unmap(struct twe_softc *sc, struct twe_ccb *ccb) 908 { 909 int flags, s; 910 911 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 912 flags = BUS_DMASYNC_POSTREAD; 913 else 914 flags = 0; 915 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 916 flags |= BUS_DMASYNC_POSTWRITE; 917 918 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 919 ccb->ccb_datasize, flags); 920 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap_xfer); 921 922 if (ccb->ccb_abuf != (vaddr_t)0) { 923 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 924 memcpy(ccb->ccb_data, (void *)ccb->ccb_abuf, 925 ccb->ccb_datasize); 926 s = splimp(); 927 /* XXX */ 928 uvm_km_free(kmem_map, ccb->ccb_abuf, ccb->ccb_datasize); 929 splx(s); 930 } 931 } 932 933 /* 934 * Submit a command to the controller and poll on completion. Return 935 * non-zero on timeout (but don't check status, as some command types don't 936 * return status). Must be called with interrupts blocked. 937 */ 938 int 939 twe_ccb_poll(struct twe_softc *sc, struct twe_ccb *ccb, int timo) 940 { 941 int rv; 942 943 if ((rv = twe_ccb_submit(sc, ccb)) != 0) 944 return (rv); 945 946 for (timo *= 1000; timo != 0; timo--) { 947 twe_poll(sc); 948 if ((ccb->ccb_flags & TWE_CCB_COMPLETE) != 0) 949 break; 950 DELAY(100); 951 } 952 953 return (timo == 0); 954 } 955 956 /* 957 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 958 * the order that they were enqueued and try to submit their command blocks 959 * to the controller for execution. 960 */ 961 void 962 twe_ccb_enqueue(struct twe_softc *sc, struct twe_ccb *ccb) 963 { 964 int s; 965 966 s = splbio(); 967 968 if (ccb != NULL) 969 SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 970 971 while ((ccb = SIMPLEQ_FIRST(&sc->sc_ccb_queue)) != NULL) { 972 if (twe_ccb_submit(sc, ccb)) 973 break; 974 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 975 } 976 977 splx(s); 978 } 979 980 /* 981 * Submit the command block associated with the specified CCB to the 982 * controller for execution. Must be called with interrupts blocked. 983 */ 984 int 985 twe_ccb_submit(struct twe_softc *sc, struct twe_ccb *ccb) 986 { 987 bus_addr_t pa; 988 int rv; 989 u_int status; 990 991 /* Check to see if we can post a command. */ 992 status = TWE_INL(sc, TWE_REG_STS); 993 twe_status_check(sc, status); 994 995 if ((status & TWE_STS_CMD_QUEUE_FULL) == 0) { 996 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 997 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, sizeof(struct twe_cmd), 998 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 999 ccb->ccb_flags |= TWE_CCB_ACTIVE; 1000 pa = sc->sc_cmds_paddr + 1001 ccb->ccb_cmdid * sizeof(struct twe_cmd); 1002 TWE_OUTL(sc, TWE_REG_CMD_QUEUE, (u_int32_t)pa); 1003 rv = 0; 1004 } else 1005 rv = EBUSY; 1006 1007 return (rv); 1008 } 1009
Indexes created Wed Oct 01 07:09:59 GMT 2025