twe.c revision 1.22
1 /* $NetBSD: twe.c,v 1.22 2002/05/18 20:59:20 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twe.c,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 /* 69 * Driver for the 3ware Escalade family of RAID controllers. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: twe.c,v 1.22 2002/05/18 20:59:20 ad Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/device.h> 79 #include <sys/queue.h> 80 #include <sys/proc.h> 81 #include <sys/buf.h> 82 #include <sys/endian.h> 83 #include <sys/malloc.h> 84 #include <sys/disk.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/bswap.h> 89 #include <machine/bus.h> 90 91 #include <dev/pci/pcireg.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcidevs.h> 94 #include <dev/pci/twereg.h> 95 #include <dev/pci/twevar.h> 96 97 #define PCI_CBIO 0x10 98 99 static void twe_aen_handler(struct twe_ccb *, int); 100 static void twe_attach(struct device *, struct device *, void *); 101 static int twe_init_connection(struct twe_softc *); 102 static int twe_intr(void *); 103 static int twe_match(struct device *, struct cfdata *, void *); 104 static int twe_param_get(struct twe_softc *, int, int, size_t, 105 void (*)(struct twe_ccb *, int), void **); 106 static void twe_poll(struct twe_softc *); 107 static int twe_print(void *, const char *); 108 static int twe_reset(struct twe_softc *); 109 static int twe_submatch(struct device *, struct cfdata *, void *); 110 static int twe_status_check(struct twe_softc *, u_int); 111 static int twe_status_wait(struct twe_softc *, u_int, int); 112 113 static inline u_int32_t twe_inl(struct twe_softc *, int); 114 static inline void twe_outl(struct twe_softc *, int, u_int32_t); 115 116 struct cfattach twe_ca = { 117 sizeof(struct twe_softc), twe_match, twe_attach 118 }; 119 120 struct { 121 const u_int aen; /* High byte non-zero if w/unit */ 122 const char *desc; 123 } static const twe_aen_names[] = { 124 { 0x0000, "queue empty" }, 125 { 0x0001, "soft reset" }, 126 { 0x0102, "degraded mirror" }, 127 { 0x0003, "controller error" }, 128 { 0x0104, "rebuild fail" }, 129 { 0x0105, "rebuild done" }, 130 { 0x0106, "incompatible unit" }, 131 { 0x0107, "init done" }, 132 { 0x0108, "unclean shutdown" }, 133 { 0x0109, "aport timeout" }, 134 { 0x010a, "drive error" }, 135 { 0x010b, "rebuild started" }, 136 { 0x010c, "init started" }, 137 { 0x0015, "table undefined" }, 138 { 0x00ff, "aen queue full" }, 139 }; 140 141 static inline u_int32_t 142 twe_inl(struct twe_softc *sc, int off) 143 { 144 145 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 146 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 147 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, off)); 148 } 149 150 static inline void 151 twe_outl(struct twe_softc *sc, int off, u_int32_t val) 152 { 153 154 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 155 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 156 BUS_SPACE_BARRIER_WRITE); 157 } 158 159 /* 160 * Match a supported board. 161 */ 162 static int 163 twe_match(struct device *parent, struct cfdata *cfdata, void *aux) 164 { 165 struct pci_attach_args *pa; 166 167 pa = aux; 168 169 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3WARE && 170 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE || 171 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE_ASIC)); 172 } 173 174 /* 175 * Attach a supported board. 176 * 177 * XXX This doesn't fail gracefully. 178 */ 179 static void 180 twe_attach(struct device *parent, struct device *self, void *aux) 181 { 182 struct pci_attach_args *pa; 183 struct twe_softc *sc; 184 pci_chipset_tag_t pc; 185 pci_intr_handle_t ih; 186 pcireg_t csr; 187 const char *intrstr; 188 int size, i, rv, rseg; 189 struct twe_param *dtp, *ctp; 190 bus_dma_segment_t seg; 191 struct twe_cmd *tc; 192 struct twe_attach_args twea; 193 struct twe_ccb *ccb; 194 195 sc = (struct twe_softc *)self; 196 pa = aux; 197 pc = pa->pa_pc; 198 sc->sc_dmat = pa->pa_dmat; 199 SIMPLEQ_INIT(&sc->sc_ccb_queue); 200 SLIST_INIT(&sc->sc_ccb_freelist); 201 202 printf(": 3ware Escalade\n"); 203 204 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 205 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 206 printf("%s: can't map i/o space\n", sc->sc_dv.dv_xname); 207 return; 208 } 209 210 /* Enable the device. */ 211 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 212 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 213 csr | PCI_COMMAND_MASTER_ENABLE); 214 215 /* Map and establish the interrupt. */ 216 if (pci_intr_map(pa, &ih)) { 217 printf("%s: can't map interrupt\n", sc->sc_dv.dv_xname); 218 return; 219 } 220 intrstr = pci_intr_string(pc, ih); 221 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, twe_intr, sc); 222 if (sc->sc_ih == NULL) { 223 printf("%s: can't establish interrupt", sc->sc_dv.dv_xname); 224 if (intrstr != NULL) 225 printf(" at %s", intrstr); 226 printf("\n"); 227 return; 228 } 229 if (intrstr != NULL) 230 printf("%s: interrupting at %s\n", sc->sc_dv.dv_xname, intrstr); 231 232 /* 233 * Allocate and initialise the command blocks and CCBs. 234 */ 235 size = sizeof(struct twe_cmd) * TWE_MAX_QUEUECNT; 236 237 if ((rv = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 1, 238 &rseg, BUS_DMA_NOWAIT)) != 0) { 239 printf("%s: unable to allocate commands, rv = %d\n", 240 sc->sc_dv.dv_xname, rv); 241 return; 242 } 243 244 if ((rv = bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 245 (caddr_t *)&sc->sc_cmds, 246 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 247 printf("%s: unable to map commands, rv = %d\n", 248 sc->sc_dv.dv_xname, rv); 249 return; 250 } 251 252 if ((rv = bus_dmamap_create(sc->sc_dmat, size, size, 1, 0, 253 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 254 printf("%s: unable to create command DMA map, rv = %d\n", 255 sc->sc_dv.dv_xname, rv); 256 return; 257 } 258 259 if ((rv = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cmds, 260 size, NULL, BUS_DMA_NOWAIT)) != 0) { 261 printf("%s: unable to load command DMA map, rv = %d\n", 262 sc->sc_dv.dv_xname, rv); 263 return; 264 } 265 266 sc->sc_cmds_paddr = sc->sc_dmamap->dm_segs[0].ds_addr; 267 memset(sc->sc_cmds, 0, size); 268 269 ccb = malloc(sizeof(*ccb) * TWE_MAX_QUEUECNT, M_DEVBUF, M_NOWAIT); 270 sc->sc_ccbs = ccb; 271 tc = (struct twe_cmd *)sc->sc_cmds; 272 273 for (i = 0; i < TWE_MAX_QUEUECNT; i++, tc++, ccb++) { 274 ccb->ccb_cmd = tc; 275 ccb->ccb_cmdid = i; 276 ccb->ccb_flags = 0; 277 rv = bus_dmamap_create(sc->sc_dmat, TWE_MAX_XFER, 278 TWE_MAX_SEGS, PAGE_SIZE, 0, 279 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 280 &ccb->ccb_dmamap_xfer); 281 if (rv != 0) { 282 printf("%s: can't create dmamap, rv = %d\n", 283 sc->sc_dv.dv_xname, rv); 284 return; 285 } 286 /* Save one CCB for parameter retrieval. */ 287 if (i != 0) 288 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, 289 ccb_chain.slist); 290 } 291 292 /* Wait for the controller to become ready. */ 293 if (twe_status_wait(sc, TWE_STS_MICROCONTROLLER_READY, 6)) { 294 printf("%s: microcontroller not ready\n", sc->sc_dv.dv_xname); 295 return; 296 } 297 298 twe_outl(sc, TWE_REG_CTL, TWE_CTL_DISABLE_INTRS); 299 300 /* Reset the controller. */ 301 if (twe_reset(sc)) { 302 printf("%s: reset failed\n", sc->sc_dv.dv_xname); 303 return; 304 } 305 306 /* Find attached units. */ 307 rv = twe_param_get(sc, TWE_PARAM_UNITSUMMARY, 308 TWE_PARAM_UNITSUMMARY_Status, TWE_MAX_UNITS, NULL, (void **)&dtp); 309 if (rv != 0) { 310 printf("%s: can't detect attached units (%d)\n", 311 sc->sc_dv.dv_xname, rv); 312 return; 313 } 314 315 /* For each detected unit, collect size and store in an array. */ 316 for (i = 0, sc->sc_nunits = 0; i < TWE_MAX_UNITS; i++) { 317 /* Unit present? */ 318 if ((dtp->tp_data[i] & TWE_PARAM_UNITSTATUS_Online) == 0) { 319 sc->sc_dsize[i] = 0; 320 continue; 321 } 322 323 rv = twe_param_get(sc, TWE_PARAM_UNITINFO + i, 324 TWE_PARAM_UNITINFO_Capacity, 4, NULL, (void **)&ctp); 325 if (rv != 0) { 326 printf("%s: error %d fetching capacity for unit %d\n", 327 sc->sc_dv.dv_xname, rv, i); 328 continue; 329 } 330 331 sc->sc_dsize[i] = le32toh(*(u_int32_t *)ctp->tp_data); 332 free(ctp, M_DEVBUF); 333 sc->sc_nunits++; 334 } 335 free(dtp, M_DEVBUF); 336 337 /* Initialise connection with controller and enable interrupts. */ 338 twe_init_connection(sc); 339 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR | 340 TWE_CTL_UNMASK_RESP_INTR | 341 TWE_CTL_ENABLE_INTRS); 342 343 /* Attach sub-devices. */ 344 for (i = 0; i < TWE_MAX_UNITS; i++) { 345 if (sc->sc_dsize[i] == 0) 346 continue; 347 twea.twea_unit = i; 348 config_found_sm(&sc->sc_dv, &twea, twe_print, twe_submatch); 349 } 350 } 351 352 /* 353 * Reset the controller. Currently only useful at attach time; must be 354 * called with interrupts blocked. 355 */ 356 static int 357 twe_reset(struct twe_softc *sc) 358 { 359 struct twe_param *tp; 360 u_int aen, status; 361 volatile u_int32_t junk; 362 int got, rv; 363 364 /* Issue a soft reset. */ 365 twe_outl(sc, TWE_REG_CTL, TWE_CTL_ISSUE_SOFT_RESET | 366 TWE_CTL_CLEAR_HOST_INTR | 367 TWE_CTL_CLEAR_ATTN_INTR | 368 TWE_CTL_MASK_CMD_INTR | 369 TWE_CTL_MASK_RESP_INTR | 370 TWE_CTL_CLEAR_ERROR_STS | 371 TWE_CTL_DISABLE_INTRS); 372 373 if (twe_status_wait(sc, TWE_STS_ATTN_INTR, 15)) { 374 printf("%s: no attention interrupt\n", 375 sc->sc_dv.dv_xname); 376 return (-1); 377 } 378 379 /* Pull AENs out of the controller; look for a soft reset AEN. */ 380 for (got = 0;;) { 381 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 382 2, NULL, (void **)&tp); 383 if (rv != 0) 384 printf("%s: error %d while draining response queue\n", 385 sc->sc_dv.dv_xname, rv); 386 aen = TWE_AEN_CODE(le16toh(*(u_int16_t *)tp->tp_data)); 387 free(tp, M_DEVBUF); 388 if (aen == TWE_AEN_QUEUE_EMPTY) 389 break; 390 if (aen == TWE_AEN_SOFT_RESET) 391 got = 1; 392 } 393 if (!got) { 394 printf("%s: reset not reported\n", sc->sc_dv.dv_xname); 395 return (-1); 396 } 397 398 /* Check controller status. */ 399 status = twe_inl(sc, TWE_REG_STS); 400 if (twe_status_check(sc, status)) { 401 printf("%s: controller errors detected\n", 402 sc->sc_dv.dv_xname); 403 return (-1); 404 } 405 406 /* Drain the response queue. */ 407 for (;;) { 408 status = twe_inl(sc, TWE_REG_STS); 409 if (twe_status_check(sc, status) != 0) { 410 printf("%s: can't drain response queue\n", 411 sc->sc_dv.dv_xname); 412 return (-1); 413 } 414 if ((status & TWE_STS_RESP_QUEUE_EMPTY) != 0) 415 break; 416 junk = twe_inl(sc, TWE_REG_RESP_QUEUE); 417 } 418 419 return (0); 420 } 421 422 /* 423 * Print autoconfiguration message for a sub-device. 424 */ 425 static int 426 twe_print(void *aux, const char *pnp) 427 { 428 struct twe_attach_args *twea; 429 430 twea = aux; 431 432 if (pnp != NULL) 433 printf("block device at %s", pnp); 434 printf(" unit %d", twea->twea_unit); 435 return (UNCONF); 436 } 437 438 /* 439 * Match a sub-device. 440 */ 441 static int 442 twe_submatch(struct device *parent, struct cfdata *cf, void *aux) 443 { 444 struct twe_attach_args *twea; 445 446 twea = aux; 447 448 if (cf->tweacf_unit != TWECF_UNIT_DEFAULT && 449 cf->tweacf_unit != twea->twea_unit) 450 return (0); 451 452 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 453 } 454 455 /* 456 * Interrupt service routine. 457 */ 458 static int 459 twe_intr(void *arg) 460 { 461 struct twe_softc *sc; 462 u_int status; 463 int caught, rv; 464 465 sc = arg; 466 caught = 0; 467 status = twe_inl(sc, TWE_REG_STS); 468 twe_status_check(sc, status); 469 470 /* Host interrupts - purpose unknown. */ 471 if ((status & TWE_STS_HOST_INTR) != 0) { 472 #ifdef DIAGNOSTIC 473 printf("%s: host interrupt\n", sc->sc_dv.dv_xname); 474 #endif 475 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_HOST_INTR); 476 caught = 1; 477 } 478 479 /* 480 * Attention interrupts, signalled when a controller or child device 481 * state change has occurred. 482 */ 483 if ((status & TWE_STS_ATTN_INTR) != 0) { 484 if ((sc->sc_flags & TWEF_AEN) == 0) { 485 rv = twe_param_get(sc, TWE_PARAM_AEN, 486 TWE_PARAM_AEN_UnitCode, 2, twe_aen_handler, 487 NULL); 488 if (rv != 0) { 489 printf("%s: unable to retrieve AEN (%d)\n", 490 sc->sc_dv.dv_xname, rv); 491 twe_outl(sc, TWE_REG_CTL, 492 TWE_CTL_CLEAR_ATTN_INTR); 493 } else 494 sc->sc_flags |= TWEF_AEN; 495 } 496 caught = 1; 497 } 498 499 /* 500 * Command interrupts, signalled when the controller can accept more 501 * commands. We don't use this; instead, we try to submit commands 502 * when we receive them, and when other commands have completed. 503 * Mask it so we don't get another one. 504 */ 505 if ((status & TWE_STS_CMD_INTR) != 0) { 506 #ifdef DIAGNOSTIC 507 printf("%s: command interrupt\n", sc->sc_dv.dv_xname); 508 #endif 509 twe_outl(sc, TWE_REG_CTL, TWE_CTL_MASK_CMD_INTR); 510 caught = 1; 511 } 512 513 if ((status & TWE_STS_RESP_INTR) != 0) { 514 twe_poll(sc); 515 caught = 1; 516 } 517 518 return (caught); 519 } 520 521 /* 522 * Handle an AEN returned by the controller. 523 */ 524 static void 525 twe_aen_handler(struct twe_ccb *ccb, int error) 526 { 527 struct twe_softc *sc; 528 struct twe_param *tp; 529 const char *str; 530 u_int aen; 531 int i, hu, rv; 532 533 sc = (struct twe_softc *)ccb->ccb_tx.tx_dv; 534 tp = ccb->ccb_tx.tx_context; 535 twe_ccb_unmap(sc, ccb); 536 537 if (error) { 538 printf("%s: error retrieving AEN\n", sc->sc_dv.dv_xname); 539 aen = TWE_AEN_QUEUE_EMPTY; 540 } else 541 aen = le16toh(*(u_int16_t *)tp->tp_data); 542 free(tp, M_DEVBUF); 543 twe_ccb_free(sc, ccb); 544 545 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) { 546 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 547 sc->sc_flags &= ~TWEF_AEN; 548 return; 549 } 550 551 str = "<unknown>"; 552 i = 0; 553 hu = 0; 554 555 while (i < sizeof(twe_aen_names) / sizeof(twe_aen_names[0])) { 556 if (TWE_AEN_CODE(twe_aen_names[i].aen) == TWE_AEN_CODE(aen)) { 557 str = twe_aen_names[i].desc; 558 hu = (TWE_AEN_UNIT(twe_aen_names[i].aen) != 0); 559 break; 560 } 561 i++; 562 } 563 printf("%s: AEN 0x%04x (%s) received", sc->sc_dv.dv_xname, 564 TWE_AEN_CODE(aen), str); 565 if (hu != 0) 566 printf(" for unit %d", TWE_AEN_UNIT(aen)); 567 printf("\n"); 568 569 /* 570 * Chain another retrieval in case interrupts have been 571 * coalesced. 572 */ 573 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 2, 574 twe_aen_handler, NULL); 575 if (rv != 0) 576 printf("%s: unable to retrieve AEN (%d)\n", 577 sc->sc_dv.dv_xname, rv); 578 } 579 580 /* 581 * Execute a TWE_OP_GET_PARAM command. If a callback function is provided, 582 * it will be called with generated context when the command has completed. 583 * If no callback is provided, the command will be executed synchronously 584 * and a pointer to a buffer containing the data returned. 585 * 586 * The caller or callback is responsible for freeing the buffer. 587 */ 588 static int 589 twe_param_get(struct twe_softc *sc, int table_id, int param_id, size_t size, 590 void (*func)(struct twe_ccb *, int), void **pbuf) 591 { 592 struct twe_ccb *ccb; 593 struct twe_cmd *tc; 594 struct twe_param *tp; 595 int rv, s; 596 597 rv = twe_ccb_alloc(sc, &ccb, 598 TWE_CCB_PARAM | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 599 if (rv != 0) 600 return (rv); 601 602 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 603 if (pbuf != NULL) 604 *pbuf = tp; 605 606 ccb->ccb_data = tp; 607 ccb->ccb_datasize = TWE_SECTOR_SIZE; 608 ccb->ccb_tx.tx_handler = func; 609 ccb->ccb_tx.tx_context = tp; 610 ccb->ccb_tx.tx_dv = &sc->sc_dv; 611 612 tc = ccb->ccb_cmd; 613 tc->tc_size = 2; 614 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 615 tc->tc_unit = 0; 616 tc->tc_count = htole16(1); 617 618 /* Fill in the outbound parameter data. */ 619 tp->tp_table_id = htole16(table_id); 620 tp->tp_param_id = param_id; 621 tp->tp_param_size = size; 622 623 /* Map the transfer. */ 624 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 625 twe_ccb_free(sc, ccb); 626 free(tp, M_DEVBUF); 627 return (rv); 628 } 629 630 /* Submit the command and either wait or let the callback handle it. */ 631 if (func == NULL) { 632 s = splbio(); 633 rv = twe_ccb_poll(sc, ccb, 5); 634 twe_ccb_unmap(sc, ccb); 635 twe_ccb_free(sc, ccb); 636 splx(s); 637 if (rv != 0) 638 free(tp, M_DEVBUF); 639 } else { 640 twe_ccb_enqueue(sc, ccb); 641 rv = 0; 642 } 643 644 return (rv); 645 } 646 647 /* 648 * Execute a TWE_OP_INIT_CONNECTION command. Return non-zero on error. 649 * Must be called with interrupts blocked. 650 */ 651 static int 652 twe_init_connection(struct twe_softc *sc) 653 { 654 struct twe_ccb *ccb; 655 struct twe_cmd *tc; 656 int rv; 657 658 if ((rv = twe_ccb_alloc(sc, &ccb, 0)) != 0) 659 return (rv); 660 661 /* Build the command. */ 662 tc = ccb->ccb_cmd; 663 tc->tc_size = 3; 664 tc->tc_opcode = TWE_OP_INIT_CONNECTION; 665 tc->tc_unit = 0; 666 tc->tc_count = htole16(TWE_MAX_CMDS); 667 tc->tc_args.init_connection.response_queue_pointer = 0; 668 669 /* Submit the command for immediate execution. */ 670 rv = twe_ccb_poll(sc, ccb, 5); 671 twe_ccb_free(sc, ccb); 672 return (rv); 673 } 674 675 /* 676 * Poll the controller for completed commands. Must be called with 677 * interrupts blocked. 678 */ 679 static void 680 twe_poll(struct twe_softc *sc) 681 { 682 struct twe_ccb *ccb; 683 int found; 684 u_int status, cmdid; 685 686 found = 0; 687 688 for (;;) { 689 status = twe_inl(sc, TWE_REG_STS); 690 twe_status_check(sc, status); 691 692 if ((status & TWE_STS_RESP_QUEUE_EMPTY)) 693 break; 694 695 found = 1; 696 cmdid = twe_inl(sc, TWE_REG_RESP_QUEUE); 697 cmdid = (cmdid & TWE_RESP_MASK) >> TWE_RESP_SHIFT; 698 if (cmdid >= TWE_MAX_QUEUECNT) { 699 printf("%s: bad completion\n", sc->sc_dv.dv_xname); 700 continue; 701 } 702 703 ccb = sc->sc_ccbs + cmdid; 704 if ((ccb->ccb_flags & TWE_CCB_ACTIVE) == 0) { 705 printf("%s: bad completion (not active)\n", 706 sc->sc_dv.dv_xname); 707 continue; 708 } 709 ccb->ccb_flags ^= TWE_CCB_COMPLETE | TWE_CCB_ACTIVE; 710 711 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 712 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, 713 sizeof(struct twe_cmd), 714 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 715 716 /* Pass notification to upper layers. */ 717 if (ccb->ccb_tx.tx_handler != NULL) 718 (*ccb->ccb_tx.tx_handler)(ccb, 719 ccb->ccb_cmd->tc_status != 0 ? EIO : 0); 720 } 721 722 /* If any commands have completed, run the software queue. */ 723 if (found) 724 twe_ccb_enqueue(sc, NULL); 725 } 726 727 /* 728 * Wait for `status' to be set in the controller status register. Return 729 * zero if found, non-zero if the operation timed out. 730 */ 731 static int 732 twe_status_wait(struct twe_softc *sc, u_int32_t status, int timo) 733 { 734 735 for (timo *= 10; timo != 0; timo--) { 736 if ((twe_inl(sc, TWE_REG_STS) & status) == status) 737 break; 738 delay(100000); 739 } 740 741 return (timo == 0); 742 } 743 744 /* 745 * Complain if the status bits aren't what we expect. 746 */ 747 static int 748 twe_status_check(struct twe_softc *sc, u_int status) 749 { 750 int rv; 751 752 rv = 0; 753 754 if ((status & TWE_STS_EXPECTED_BITS) != TWE_STS_EXPECTED_BITS) { 755 printf("%s: missing status bits: 0x%08x\n", sc->sc_dv.dv_xname, 756 status & ~TWE_STS_EXPECTED_BITS); 757 rv = -1; 758 } 759 760 if ((status & TWE_STS_UNEXPECTED_BITS) != 0) { 761 printf("%s: unexpected status bits: 0x%08x\n", 762 sc->sc_dv.dv_xname, status & TWE_STS_UNEXPECTED_BITS); 763 rv = -1; 764 } 765 766 return (rv); 767 } 768 769 /* 770 * Allocate and initialise a CCB. 771 */ 772 int 773 twe_ccb_alloc(struct twe_softc *sc, struct twe_ccb **ccbp, int flags) 774 { 775 struct twe_cmd *tc; 776 struct twe_ccb *ccb; 777 int s; 778 779 s = splbio(); 780 if ((flags & TWE_CCB_PARAM) != 0) 781 ccb = sc->sc_ccbs; 782 else { 783 /* Allocate a CCB and command block. */ 784 if (SLIST_FIRST(&sc->sc_ccb_freelist) == NULL) { 785 splx(s); 786 return (EAGAIN); 787 } 788 ccb = SLIST_FIRST(&sc->sc_ccb_freelist); 789 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 790 } 791 #ifdef DIAGNOSTIC 792 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 793 panic("twe_ccb_alloc: CCB already allocated"); 794 flags |= TWE_CCB_ALLOCED; 795 #endif 796 splx(s); 797 798 /* Initialise some fields and return. */ 799 ccb->ccb_tx.tx_handler = NULL; 800 ccb->ccb_flags = flags; 801 tc = ccb->ccb_cmd; 802 tc->tc_status = 0; 803 tc->tc_flags = 0; 804 tc->tc_cmdid = ccb->ccb_cmdid; 805 *ccbp = ccb; 806 807 return (0); 808 } 809 810 /* 811 * Free a CCB. 812 */ 813 void 814 twe_ccb_free(struct twe_softc *sc, struct twe_ccb *ccb) 815 { 816 int s; 817 818 s = splbio(); 819 if ((ccb->ccb_flags & TWE_CCB_PARAM) == 0) 820 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, ccb_chain.slist); 821 ccb->ccb_flags = 0; 822 splx(s); 823 } 824 825 /* 826 * Map the specified CCB's command block and data buffer (if any) into 827 * controller visible space. Perform DMA synchronisation. 828 */ 829 int 830 twe_ccb_map(struct twe_softc *sc, struct twe_ccb *ccb) 831 { 832 struct twe_cmd *tc; 833 int flags, nsegs, i, s, rv; 834 void *data; 835 836 /* 837 * The data as a whole must be 512-byte aligned. 838 */ 839 if (((u_long)ccb->ccb_data & (TWE_ALIGNMENT - 1)) != 0) { 840 s = splvm(); 841 /* XXX */ 842 ccb->ccb_abuf = uvm_km_kmemalloc(kmem_map, NULL, 843 ccb->ccb_datasize, UVM_KMF_NOWAIT); 844 splx(s); 845 data = (void *)ccb->ccb_abuf; 846 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 847 memcpy(data, ccb->ccb_data, ccb->ccb_datasize); 848 } else { 849 ccb->ccb_abuf = (vaddr_t)0; 850 data = ccb->ccb_data; 851 } 852 853 /* 854 * Map the data buffer into bus space and build the S/G list. 855 */ 856 rv = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap_xfer, data, 857 ccb->ccb_datasize, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 858 ((ccb->ccb_flags & TWE_CCB_DATA_IN) ? 859 BUS_DMA_READ : BUS_DMA_WRITE)); 860 if (rv != 0) { 861 if (ccb->ccb_abuf != (vaddr_t)0) { 862 s = splvm(); 863 /* XXX */ 864 uvm_km_free(kmem_map, ccb->ccb_abuf, 865 ccb->ccb_datasize); 866 splx(s); 867 } 868 return (rv); 869 } 870 871 nsegs = ccb->ccb_dmamap_xfer->dm_nsegs; 872 tc = ccb->ccb_cmd; 873 tc->tc_size += 2 * nsegs; 874 875 /* The location of the S/G list is dependant upon command type. */ 876 switch (tc->tc_opcode >> 5) { 877 case 2: 878 for (i = 0; i < nsegs; i++) { 879 tc->tc_args.param.sgl[i].tsg_address = 880 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 881 tc->tc_args.param.sgl[i].tsg_length = 882 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 883 } 884 /* XXX Needed? */ 885 for (; i < TWE_SG_SIZE; i++) { 886 tc->tc_args.param.sgl[i].tsg_address = 0; 887 tc->tc_args.param.sgl[i].tsg_length = 0; 888 } 889 break; 890 case 3: 891 for (i = 0; i < nsegs; i++) { 892 tc->tc_args.io.sgl[i].tsg_address = 893 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 894 tc->tc_args.io.sgl[i].tsg_length = 895 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 896 } 897 /* XXX Needed? */ 898 for (; i < TWE_SG_SIZE; i++) { 899 tc->tc_args.io.sgl[i].tsg_address = 0; 900 tc->tc_args.io.sgl[i].tsg_length = 0; 901 } 902 break; 903 #ifdef DEBUG 904 default: 905 panic("twe_ccb_map: oops"); 906 #endif 907 } 908 909 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 910 flags = BUS_DMASYNC_PREREAD; 911 else 912 flags = 0; 913 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 914 flags |= BUS_DMASYNC_PREWRITE; 915 916 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 917 ccb->ccb_datasize, flags); 918 return (0); 919 } 920 921 /* 922 * Unmap the specified CCB's command block and data buffer (if any) and 923 * perform DMA synchronisation. 924 */ 925 void 926 twe_ccb_unmap(struct twe_softc *sc, struct twe_ccb *ccb) 927 { 928 int flags, s; 929 930 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 931 flags = BUS_DMASYNC_POSTREAD; 932 else 933 flags = 0; 934 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 935 flags |= BUS_DMASYNC_POSTWRITE; 936 937 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 938 ccb->ccb_datasize, flags); 939 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap_xfer); 940 941 if (ccb->ccb_abuf != (vaddr_t)0) { 942 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 943 memcpy(ccb->ccb_data, (void *)ccb->ccb_abuf, 944 ccb->ccb_datasize); 945 s = splvm(); 946 /* XXX */ 947 uvm_km_free(kmem_map, ccb->ccb_abuf, ccb->ccb_datasize); 948 splx(s); 949 } 950 } 951 952 /* 953 * Submit a command to the controller and poll on completion. Return 954 * non-zero on timeout (but don't check status, as some command types don't 955 * return status). Must be called with interrupts blocked. 956 */ 957 int 958 twe_ccb_poll(struct twe_softc *sc, struct twe_ccb *ccb, int timo) 959 { 960 int rv; 961 962 if ((rv = twe_ccb_submit(sc, ccb)) != 0) 963 return (rv); 964 965 for (timo *= 1000; timo != 0; timo--) { 966 twe_poll(sc); 967 if ((ccb->ccb_flags & TWE_CCB_COMPLETE) != 0) 968 break; 969 DELAY(100); 970 } 971 972 return (timo == 0); 973 } 974 975 /* 976 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 977 * the order that they were enqueued and try to submit their command blocks 978 * to the controller for execution. 979 */ 980 void 981 twe_ccb_enqueue(struct twe_softc *sc, struct twe_ccb *ccb) 982 { 983 int s; 984 985 s = splbio(); 986 987 if (ccb != NULL) 988 SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 989 990 while ((ccb = SIMPLEQ_FIRST(&sc->sc_ccb_queue)) != NULL) { 991 if (twe_ccb_submit(sc, ccb)) 992 break; 993 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 994 } 995 996 splx(s); 997 } 998 999 /* 1000 * Submit the command block associated with the specified CCB to the 1001 * controller for execution. Must be called with interrupts blocked. 1002 */ 1003 int 1004 twe_ccb_submit(struct twe_softc *sc, struct twe_ccb *ccb) 1005 { 1006 bus_addr_t pa; 1007 int rv; 1008 u_int status; 1009 1010 /* Check to see if we can post a command. */ 1011 status = twe_inl(sc, TWE_REG_STS); 1012 twe_status_check(sc, status); 1013 1014 if ((status & TWE_STS_CMD_QUEUE_FULL) == 0) { 1015 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1016 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, sizeof(struct twe_cmd), 1017 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1018 ccb->ccb_flags |= TWE_CCB_ACTIVE; 1019 pa = sc->sc_cmds_paddr + 1020 ccb->ccb_cmdid * sizeof(struct twe_cmd); 1021 twe_outl(sc, TWE_REG_CMD_QUEUE, (u_int32_t)pa); 1022 rv = 0; 1023 } else 1024 rv = EBUSY; 1025 1026 return (rv); 1027 } 1028
Indexes created Tue Sep 23 07:09:52 GMT 2025