twe.c revision 1.23
1 /* $NetBSD: twe.c,v 1.23 2002/05/24 15:58:06 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twe.c,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 /* 69 * Driver for the 3ware Escalade family of RAID controllers. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: twe.c,v 1.23 2002/05/24 15:58:06 christos Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/device.h> 79 #include <sys/queue.h> 80 #include <sys/proc.h> 81 #include <sys/buf.h> 82 #include <sys/endian.h> 83 #include <sys/malloc.h> 84 #include <sys/disk.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/bswap.h> 89 #include <machine/bus.h> 90 91 #include <dev/pci/pcireg.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcidevs.h> 94 #include <dev/pci/twereg.h> 95 #include <dev/pci/twevar.h> 96 97 #define PCI_CBIO 0x10 98 99 static void twe_aen_handler(struct twe_ccb *, int); 100 static void twe_attach(struct device *, struct device *, void *); 101 static int twe_init_connection(struct twe_softc *); 102 static int twe_intr(void *); 103 static int twe_match(struct device *, struct cfdata *, void *); 104 static int twe_param_get(struct twe_softc *, int, int, size_t, 105 void (*)(struct twe_ccb *, int), void **); 106 static void twe_poll(struct twe_softc *); 107 static int twe_print(void *, const char *); 108 static int twe_reset(struct twe_softc *); 109 static int twe_submatch(struct device *, struct cfdata *, void *); 110 static int twe_status_check(struct twe_softc *, u_int); 111 static int twe_status_wait(struct twe_softc *, u_int, int); 112 113 static inline u_int32_t twe_inl(struct twe_softc *, int); 114 static inline void twe_outl(struct twe_softc *, int, u_int32_t); 115 116 struct cfattach twe_ca = { 117 sizeof(struct twe_softc), twe_match, twe_attach 118 }; 119 120 struct { 121 const u_int aen; /* High byte non-zero if w/unit */ 122 const char *desc; 123 } static const twe_aen_names[] = { 124 { 0x0000, "queue empty" }, 125 { 0x0001, "soft reset" }, 126 { 0x0102, "degraded mirror" }, 127 { 0x0003, "controller error" }, 128 { 0x0104, "rebuild fail" }, 129 { 0x0105, "rebuild done" }, 130 { 0x0106, "incompatible unit" }, 131 { 0x0107, "init done" }, 132 { 0x0108, "unclean shutdown" }, 133 { 0x0109, "aport timeout" }, 134 { 0x010a, "drive error" }, 135 { 0x010b, "rebuild started" }, 136 { 0x010c, "init started" }, 137 { 0x0015, "table undefined" }, 138 { 0x00ff, "aen queue full" }, 139 }; 140 141 static inline u_int32_t 142 twe_inl(struct twe_softc *sc, int off) 143 { 144 145 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 146 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 147 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, off)); 148 } 149 150 static inline void 151 twe_outl(struct twe_softc *sc, int off, u_int32_t val) 152 { 153 154 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 155 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 156 BUS_SPACE_BARRIER_WRITE); 157 } 158 159 /* 160 * Match a supported board. 161 */ 162 static int 163 twe_match(struct device *parent, struct cfdata *cfdata, void *aux) 164 { 165 struct pci_attach_args *pa; 166 167 pa = aux; 168 169 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3WARE && 170 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE || 171 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE_ASIC)); 172 } 173 174 /* 175 * Attach a supported board. 176 * 177 * XXX This doesn't fail gracefully. 178 */ 179 static void 180 twe_attach(struct device *parent, struct device *self, void *aux) 181 { 182 struct pci_attach_args *pa; 183 struct twe_softc *sc; 184 pci_chipset_tag_t pc; 185 pci_intr_handle_t ih; 186 pcireg_t csr; 187 const char *intrstr; 188 int size, i, rv, rseg; 189 size_t max_segs, max_xfer; 190 struct twe_param *dtp, *ctp; 191 bus_dma_segment_t seg; 192 struct twe_cmd *tc; 193 struct twe_attach_args twea; 194 struct twe_ccb *ccb; 195 196 sc = (struct twe_softc *)self; 197 pa = aux; 198 pc = pa->pa_pc; 199 sc->sc_dmat = pa->pa_dmat; 200 SIMPLEQ_INIT(&sc->sc_ccb_queue); 201 SLIST_INIT(&sc->sc_ccb_freelist); 202 203 printf(": 3ware Escalade\n"); 204 205 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 206 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 207 printf("%s: can't map i/o space\n", sc->sc_dv.dv_xname); 208 return; 209 } 210 211 /* Enable the device. */ 212 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 213 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 214 csr | PCI_COMMAND_MASTER_ENABLE); 215 216 /* Map and establish the interrupt. */ 217 if (pci_intr_map(pa, &ih)) { 218 printf("%s: can't map interrupt\n", sc->sc_dv.dv_xname); 219 return; 220 } 221 intrstr = pci_intr_string(pc, ih); 222 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, twe_intr, sc); 223 if (sc->sc_ih == NULL) { 224 printf("%s: can't establish interrupt", sc->sc_dv.dv_xname); 225 if (intrstr != NULL) 226 printf(" at %s", intrstr); 227 printf("\n"); 228 return; 229 } 230 if (intrstr != NULL) 231 printf("%s: interrupting at %s\n", sc->sc_dv.dv_xname, intrstr); 232 233 /* 234 * Allocate and initialise the command blocks and CCBs. 235 */ 236 size = sizeof(struct twe_cmd) * TWE_MAX_QUEUECNT; 237 238 if ((rv = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 1, 239 &rseg, BUS_DMA_NOWAIT)) != 0) { 240 printf("%s: unable to allocate commands, rv = %d\n", 241 sc->sc_dv.dv_xname, rv); 242 return; 243 } 244 245 if ((rv = bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 246 (caddr_t *)&sc->sc_cmds, 247 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 248 printf("%s: unable to map commands, rv = %d\n", 249 sc->sc_dv.dv_xname, rv); 250 return; 251 } 252 253 if ((rv = bus_dmamap_create(sc->sc_dmat, size, size, 1, 0, 254 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 255 printf("%s: unable to create command DMA map, rv = %d\n", 256 sc->sc_dv.dv_xname, rv); 257 return; 258 } 259 260 if ((rv = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cmds, 261 size, NULL, BUS_DMA_NOWAIT)) != 0) { 262 printf("%s: unable to load command DMA map, rv = %d\n", 263 sc->sc_dv.dv_xname, rv); 264 return; 265 } 266 267 sc->sc_cmds_paddr = sc->sc_dmamap->dm_segs[0].ds_addr; 268 memset(sc->sc_cmds, 0, size); 269 270 ccb = malloc(sizeof(*ccb) * TWE_MAX_QUEUECNT, M_DEVBUF, M_NOWAIT); 271 sc->sc_ccbs = ccb; 272 tc = (struct twe_cmd *)sc->sc_cmds; 273 max_segs = ((MAXPHYS + PAGE_SIZE - 1) / PAGE_SIZE) + 1; 274 #ifdef TWE_SG_SIZE 275 if (TWE_SG_SIZE < max_segs) 276 max_segs = TWE_SG_SIZE; 277 #endif 278 max_xfer = (max_segs - 1) * PAGE_SIZE; 279 280 for (i = 0; i < TWE_MAX_QUEUECNT; i++, tc++, ccb++) { 281 ccb->ccb_cmd = tc; 282 ccb->ccb_cmdid = i; 283 ccb->ccb_flags = 0; 284 rv = bus_dmamap_create(sc->sc_dmat, max_xfer, 285 max_segs, PAGE_SIZE, 0, 286 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 287 &ccb->ccb_dmamap_xfer); 288 if (rv != 0) { 289 printf("%s: can't create dmamap, rv = %d\n", 290 sc->sc_dv.dv_xname, rv); 291 return; 292 } 293 /* Save one CCB for parameter retrieval. */ 294 if (i != 0) 295 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, 296 ccb_chain.slist); 297 } 298 299 /* Wait for the controller to become ready. */ 300 if (twe_status_wait(sc, TWE_STS_MICROCONTROLLER_READY, 6)) { 301 printf("%s: microcontroller not ready\n", sc->sc_dv.dv_xname); 302 return; 303 } 304 305 twe_outl(sc, TWE_REG_CTL, TWE_CTL_DISABLE_INTRS); 306 307 /* Reset the controller. */ 308 if (twe_reset(sc)) { 309 printf("%s: reset failed\n", sc->sc_dv.dv_xname); 310 return; 311 } 312 313 /* Find attached units. */ 314 rv = twe_param_get(sc, TWE_PARAM_UNITSUMMARY, 315 TWE_PARAM_UNITSUMMARY_Status, TWE_MAX_UNITS, NULL, (void **)&dtp); 316 if (rv != 0) { 317 printf("%s: can't detect attached units (%d)\n", 318 sc->sc_dv.dv_xname, rv); 319 return; 320 } 321 322 /* For each detected unit, collect size and store in an array. */ 323 for (i = 0, sc->sc_nunits = 0; i < TWE_MAX_UNITS; i++) { 324 /* Unit present? */ 325 if ((dtp->tp_data[i] & TWE_PARAM_UNITSTATUS_Online) == 0) { 326 sc->sc_dsize[i] = 0; 327 continue; 328 } 329 330 rv = twe_param_get(sc, TWE_PARAM_UNITINFO + i, 331 TWE_PARAM_UNITINFO_Capacity, 4, NULL, (void **)&ctp); 332 if (rv != 0) { 333 printf("%s: error %d fetching capacity for unit %d\n", 334 sc->sc_dv.dv_xname, rv, i); 335 continue; 336 } 337 338 sc->sc_dsize[i] = le32toh(*(u_int32_t *)ctp->tp_data); 339 free(ctp, M_DEVBUF); 340 sc->sc_nunits++; 341 } 342 free(dtp, M_DEVBUF); 343 344 /* Initialise connection with controller and enable interrupts. */ 345 twe_init_connection(sc); 346 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR | 347 TWE_CTL_UNMASK_RESP_INTR | 348 TWE_CTL_ENABLE_INTRS); 349 350 /* Attach sub-devices. */ 351 for (i = 0; i < TWE_MAX_UNITS; i++) { 352 if (sc->sc_dsize[i] == 0) 353 continue; 354 twea.twea_unit = i; 355 config_found_sm(&sc->sc_dv, &twea, twe_print, twe_submatch); 356 } 357 } 358 359 /* 360 * Reset the controller. Currently only useful at attach time; must be 361 * called with interrupts blocked. 362 */ 363 static int 364 twe_reset(struct twe_softc *sc) 365 { 366 struct twe_param *tp; 367 u_int aen, status; 368 volatile u_int32_t junk; 369 int got, rv; 370 371 /* Issue a soft reset. */ 372 twe_outl(sc, TWE_REG_CTL, TWE_CTL_ISSUE_SOFT_RESET | 373 TWE_CTL_CLEAR_HOST_INTR | 374 TWE_CTL_CLEAR_ATTN_INTR | 375 TWE_CTL_MASK_CMD_INTR | 376 TWE_CTL_MASK_RESP_INTR | 377 TWE_CTL_CLEAR_ERROR_STS | 378 TWE_CTL_DISABLE_INTRS); 379 380 if (twe_status_wait(sc, TWE_STS_ATTN_INTR, 15)) { 381 printf("%s: no attention interrupt\n", 382 sc->sc_dv.dv_xname); 383 return (-1); 384 } 385 386 /* Pull AENs out of the controller; look for a soft reset AEN. */ 387 for (got = 0;;) { 388 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 389 2, NULL, (void **)&tp); 390 if (rv != 0) 391 printf("%s: error %d while draining response queue\n", 392 sc->sc_dv.dv_xname, rv); 393 aen = TWE_AEN_CODE(le16toh(*(u_int16_t *)tp->tp_data)); 394 free(tp, M_DEVBUF); 395 if (aen == TWE_AEN_QUEUE_EMPTY) 396 break; 397 if (aen == TWE_AEN_SOFT_RESET) 398 got = 1; 399 } 400 if (!got) { 401 printf("%s: reset not reported\n", sc->sc_dv.dv_xname); 402 return (-1); 403 } 404 405 /* Check controller status. */ 406 status = twe_inl(sc, TWE_REG_STS); 407 if (twe_status_check(sc, status)) { 408 printf("%s: controller errors detected\n", 409 sc->sc_dv.dv_xname); 410 return (-1); 411 } 412 413 /* Drain the response queue. */ 414 for (;;) { 415 status = twe_inl(sc, TWE_REG_STS); 416 if (twe_status_check(sc, status) != 0) { 417 printf("%s: can't drain response queue\n", 418 sc->sc_dv.dv_xname); 419 return (-1); 420 } 421 if ((status & TWE_STS_RESP_QUEUE_EMPTY) != 0) 422 break; 423 junk = twe_inl(sc, TWE_REG_RESP_QUEUE); 424 } 425 426 return (0); 427 } 428 429 /* 430 * Print autoconfiguration message for a sub-device. 431 */ 432 static int 433 twe_print(void *aux, const char *pnp) 434 { 435 struct twe_attach_args *twea; 436 437 twea = aux; 438 439 if (pnp != NULL) 440 printf("block device at %s", pnp); 441 printf(" unit %d", twea->twea_unit); 442 return (UNCONF); 443 } 444 445 /* 446 * Match a sub-device. 447 */ 448 static int 449 twe_submatch(struct device *parent, struct cfdata *cf, void *aux) 450 { 451 struct twe_attach_args *twea; 452 453 twea = aux; 454 455 if (cf->tweacf_unit != TWECF_UNIT_DEFAULT && 456 cf->tweacf_unit != twea->twea_unit) 457 return (0); 458 459 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 460 } 461 462 /* 463 * Interrupt service routine. 464 */ 465 static int 466 twe_intr(void *arg) 467 { 468 struct twe_softc *sc; 469 u_int status; 470 int caught, rv; 471 472 sc = arg; 473 caught = 0; 474 status = twe_inl(sc, TWE_REG_STS); 475 twe_status_check(sc, status); 476 477 /* Host interrupts - purpose unknown. */ 478 if ((status & TWE_STS_HOST_INTR) != 0) { 479 #ifdef DIAGNOSTIC 480 printf("%s: host interrupt\n", sc->sc_dv.dv_xname); 481 #endif 482 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_HOST_INTR); 483 caught = 1; 484 } 485 486 /* 487 * Attention interrupts, signalled when a controller or child device 488 * state change has occurred. 489 */ 490 if ((status & TWE_STS_ATTN_INTR) != 0) { 491 if ((sc->sc_flags & TWEF_AEN) == 0) { 492 rv = twe_param_get(sc, TWE_PARAM_AEN, 493 TWE_PARAM_AEN_UnitCode, 2, twe_aen_handler, 494 NULL); 495 if (rv != 0) { 496 printf("%s: unable to retrieve AEN (%d)\n", 497 sc->sc_dv.dv_xname, rv); 498 twe_outl(sc, TWE_REG_CTL, 499 TWE_CTL_CLEAR_ATTN_INTR); 500 } else 501 sc->sc_flags |= TWEF_AEN; 502 } 503 caught = 1; 504 } 505 506 /* 507 * Command interrupts, signalled when the controller can accept more 508 * commands. We don't use this; instead, we try to submit commands 509 * when we receive them, and when other commands have completed. 510 * Mask it so we don't get another one. 511 */ 512 if ((status & TWE_STS_CMD_INTR) != 0) { 513 #ifdef DIAGNOSTIC 514 printf("%s: command interrupt\n", sc->sc_dv.dv_xname); 515 #endif 516 twe_outl(sc, TWE_REG_CTL, TWE_CTL_MASK_CMD_INTR); 517 caught = 1; 518 } 519 520 if ((status & TWE_STS_RESP_INTR) != 0) { 521 twe_poll(sc); 522 caught = 1; 523 } 524 525 return (caught); 526 } 527 528 /* 529 * Handle an AEN returned by the controller. 530 */ 531 static void 532 twe_aen_handler(struct twe_ccb *ccb, int error) 533 { 534 struct twe_softc *sc; 535 struct twe_param *tp; 536 const char *str; 537 u_int aen; 538 int i, hu, rv; 539 540 sc = (struct twe_softc *)ccb->ccb_tx.tx_dv; 541 tp = ccb->ccb_tx.tx_context; 542 twe_ccb_unmap(sc, ccb); 543 544 if (error) { 545 printf("%s: error retrieving AEN\n", sc->sc_dv.dv_xname); 546 aen = TWE_AEN_QUEUE_EMPTY; 547 } else 548 aen = le16toh(*(u_int16_t *)tp->tp_data); 549 free(tp, M_DEVBUF); 550 twe_ccb_free(sc, ccb); 551 552 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) { 553 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 554 sc->sc_flags &= ~TWEF_AEN; 555 return; 556 } 557 558 str = "<unknown>"; 559 i = 0; 560 hu = 0; 561 562 while (i < sizeof(twe_aen_names) / sizeof(twe_aen_names[0])) { 563 if (TWE_AEN_CODE(twe_aen_names[i].aen) == TWE_AEN_CODE(aen)) { 564 str = twe_aen_names[i].desc; 565 hu = (TWE_AEN_UNIT(twe_aen_names[i].aen) != 0); 566 break; 567 } 568 i++; 569 } 570 printf("%s: AEN 0x%04x (%s) received", sc->sc_dv.dv_xname, 571 TWE_AEN_CODE(aen), str); 572 if (hu != 0) 573 printf(" for unit %d", TWE_AEN_UNIT(aen)); 574 printf("\n"); 575 576 /* 577 * Chain another retrieval in case interrupts have been 578 * coalesced. 579 */ 580 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 2, 581 twe_aen_handler, NULL); 582 if (rv != 0) 583 printf("%s: unable to retrieve AEN (%d)\n", 584 sc->sc_dv.dv_xname, rv); 585 } 586 587 /* 588 * Execute a TWE_OP_GET_PARAM command. If a callback function is provided, 589 * it will be called with generated context when the command has completed. 590 * If no callback is provided, the command will be executed synchronously 591 * and a pointer to a buffer containing the data returned. 592 * 593 * The caller or callback is responsible for freeing the buffer. 594 */ 595 static int 596 twe_param_get(struct twe_softc *sc, int table_id, int param_id, size_t size, 597 void (*func)(struct twe_ccb *, int), void **pbuf) 598 { 599 struct twe_ccb *ccb; 600 struct twe_cmd *tc; 601 struct twe_param *tp; 602 int rv, s; 603 604 rv = twe_ccb_alloc(sc, &ccb, 605 TWE_CCB_PARAM | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 606 if (rv != 0) 607 return (rv); 608 609 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 610 if (pbuf != NULL) 611 *pbuf = tp; 612 613 ccb->ccb_data = tp; 614 ccb->ccb_datasize = TWE_SECTOR_SIZE; 615 ccb->ccb_tx.tx_handler = func; 616 ccb->ccb_tx.tx_context = tp; 617 ccb->ccb_tx.tx_dv = &sc->sc_dv; 618 619 tc = ccb->ccb_cmd; 620 tc->tc_size = 2; 621 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 622 tc->tc_unit = 0; 623 tc->tc_count = htole16(1); 624 625 /* Fill in the outbound parameter data. */ 626 tp->tp_table_id = htole16(table_id); 627 tp->tp_param_id = param_id; 628 tp->tp_param_size = size; 629 630 /* Map the transfer. */ 631 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 632 twe_ccb_free(sc, ccb); 633 free(tp, M_DEVBUF); 634 return (rv); 635 } 636 637 /* Submit the command and either wait or let the callback handle it. */ 638 if (func == NULL) { 639 s = splbio(); 640 rv = twe_ccb_poll(sc, ccb, 5); 641 twe_ccb_unmap(sc, ccb); 642 twe_ccb_free(sc, ccb); 643 splx(s); 644 if (rv != 0) 645 free(tp, M_DEVBUF); 646 } else { 647 twe_ccb_enqueue(sc, ccb); 648 rv = 0; 649 } 650 651 return (rv); 652 } 653 654 /* 655 * Execute a TWE_OP_INIT_CONNECTION command. Return non-zero on error. 656 * Must be called with interrupts blocked. 657 */ 658 static int 659 twe_init_connection(struct twe_softc *sc) 660 { 661 struct twe_ccb *ccb; 662 struct twe_cmd *tc; 663 int rv; 664 665 if ((rv = twe_ccb_alloc(sc, &ccb, 0)) != 0) 666 return (rv); 667 668 /* Build the command. */ 669 tc = ccb->ccb_cmd; 670 tc->tc_size = 3; 671 tc->tc_opcode = TWE_OP_INIT_CONNECTION; 672 tc->tc_unit = 0; 673 tc->tc_count = htole16(TWE_MAX_CMDS); 674 tc->tc_args.init_connection.response_queue_pointer = 0; 675 676 /* Submit the command for immediate execution. */ 677 rv = twe_ccb_poll(sc, ccb, 5); 678 twe_ccb_free(sc, ccb); 679 return (rv); 680 } 681 682 /* 683 * Poll the controller for completed commands. Must be called with 684 * interrupts blocked. 685 */ 686 static void 687 twe_poll(struct twe_softc *sc) 688 { 689 struct twe_ccb *ccb; 690 int found; 691 u_int status, cmdid; 692 693 found = 0; 694 695 for (;;) { 696 status = twe_inl(sc, TWE_REG_STS); 697 twe_status_check(sc, status); 698 699 if ((status & TWE_STS_RESP_QUEUE_EMPTY)) 700 break; 701 702 found = 1; 703 cmdid = twe_inl(sc, TWE_REG_RESP_QUEUE); 704 cmdid = (cmdid & TWE_RESP_MASK) >> TWE_RESP_SHIFT; 705 if (cmdid >= TWE_MAX_QUEUECNT) { 706 printf("%s: bad completion\n", sc->sc_dv.dv_xname); 707 continue; 708 } 709 710 ccb = sc->sc_ccbs + cmdid; 711 if ((ccb->ccb_flags & TWE_CCB_ACTIVE) == 0) { 712 printf("%s: bad completion (not active)\n", 713 sc->sc_dv.dv_xname); 714 continue; 715 } 716 ccb->ccb_flags ^= TWE_CCB_COMPLETE | TWE_CCB_ACTIVE; 717 718 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 719 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, 720 sizeof(struct twe_cmd), 721 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 722 723 /* Pass notification to upper layers. */ 724 if (ccb->ccb_tx.tx_handler != NULL) 725 (*ccb->ccb_tx.tx_handler)(ccb, 726 ccb->ccb_cmd->tc_status != 0 ? EIO : 0); 727 } 728 729 /* If any commands have completed, run the software queue. */ 730 if (found) 731 twe_ccb_enqueue(sc, NULL); 732 } 733 734 /* 735 * Wait for `status' to be set in the controller status register. Return 736 * zero if found, non-zero if the operation timed out. 737 */ 738 static int 739 twe_status_wait(struct twe_softc *sc, u_int32_t status, int timo) 740 { 741 742 for (timo *= 10; timo != 0; timo--) { 743 if ((twe_inl(sc, TWE_REG_STS) & status) == status) 744 break; 745 delay(100000); 746 } 747 748 return (timo == 0); 749 } 750 751 /* 752 * Complain if the status bits aren't what we expect. 753 */ 754 static int 755 twe_status_check(struct twe_softc *sc, u_int status) 756 { 757 int rv; 758 759 rv = 0; 760 761 if ((status & TWE_STS_EXPECTED_BITS) != TWE_STS_EXPECTED_BITS) { 762 printf("%s: missing status bits: 0x%08x\n", sc->sc_dv.dv_xname, 763 status & ~TWE_STS_EXPECTED_BITS); 764 rv = -1; 765 } 766 767 if ((status & TWE_STS_UNEXPECTED_BITS) != 0) { 768 printf("%s: unexpected status bits: 0x%08x\n", 769 sc->sc_dv.dv_xname, status & TWE_STS_UNEXPECTED_BITS); 770 rv = -1; 771 } 772 773 return (rv); 774 } 775 776 /* 777 * Allocate and initialise a CCB. 778 */ 779 int 780 twe_ccb_alloc(struct twe_softc *sc, struct twe_ccb **ccbp, int flags) 781 { 782 struct twe_cmd *tc; 783 struct twe_ccb *ccb; 784 int s; 785 786 s = splbio(); 787 if ((flags & TWE_CCB_PARAM) != 0) 788 ccb = sc->sc_ccbs; 789 else { 790 /* Allocate a CCB and command block. */ 791 if (SLIST_FIRST(&sc->sc_ccb_freelist) == NULL) { 792 splx(s); 793 return (EAGAIN); 794 } 795 ccb = SLIST_FIRST(&sc->sc_ccb_freelist); 796 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 797 } 798 #ifdef DIAGNOSTIC 799 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 800 panic("twe_ccb_alloc: CCB already allocated"); 801 flags |= TWE_CCB_ALLOCED; 802 #endif 803 splx(s); 804 805 /* Initialise some fields and return. */ 806 ccb->ccb_tx.tx_handler = NULL; 807 ccb->ccb_flags = flags; 808 tc = ccb->ccb_cmd; 809 tc->tc_status = 0; 810 tc->tc_flags = 0; 811 tc->tc_cmdid = ccb->ccb_cmdid; 812 *ccbp = ccb; 813 814 return (0); 815 } 816 817 /* 818 * Free a CCB. 819 */ 820 void 821 twe_ccb_free(struct twe_softc *sc, struct twe_ccb *ccb) 822 { 823 int s; 824 825 s = splbio(); 826 if ((ccb->ccb_flags & TWE_CCB_PARAM) == 0) 827 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, ccb_chain.slist); 828 ccb->ccb_flags = 0; 829 splx(s); 830 } 831 832 /* 833 * Map the specified CCB's command block and data buffer (if any) into 834 * controller visible space. Perform DMA synchronisation. 835 */ 836 int 837 twe_ccb_map(struct twe_softc *sc, struct twe_ccb *ccb) 838 { 839 struct twe_cmd *tc; 840 int flags, nsegs, i, s, rv; 841 void *data; 842 843 /* 844 * The data as a whole must be 512-byte aligned. 845 */ 846 if (((u_long)ccb->ccb_data & (TWE_ALIGNMENT - 1)) != 0) { 847 s = splvm(); 848 /* XXX */ 849 ccb->ccb_abuf = uvm_km_kmemalloc(kmem_map, NULL, 850 ccb->ccb_datasize, UVM_KMF_NOWAIT); 851 splx(s); 852 data = (void *)ccb->ccb_abuf; 853 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 854 memcpy(data, ccb->ccb_data, ccb->ccb_datasize); 855 } else { 856 ccb->ccb_abuf = (vaddr_t)0; 857 data = ccb->ccb_data; 858 } 859 860 /* 861 * Map the data buffer into bus space and build the S/G list. 862 */ 863 rv = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap_xfer, data, 864 ccb->ccb_datasize, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 865 ((ccb->ccb_flags & TWE_CCB_DATA_IN) ? 866 BUS_DMA_READ : BUS_DMA_WRITE)); 867 if (rv != 0) { 868 if (ccb->ccb_abuf != (vaddr_t)0) { 869 s = splvm(); 870 /* XXX */ 871 uvm_km_free(kmem_map, ccb->ccb_abuf, 872 ccb->ccb_datasize); 873 splx(s); 874 } 875 return (rv); 876 } 877 878 nsegs = ccb->ccb_dmamap_xfer->dm_nsegs; 879 tc = ccb->ccb_cmd; 880 tc->tc_size += 2 * nsegs; 881 882 /* The location of the S/G list is dependant upon command type. */ 883 switch (tc->tc_opcode >> 5) { 884 case 2: 885 for (i = 0; i < nsegs; i++) { 886 tc->tc_args.param.sgl[i].tsg_address = 887 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 888 tc->tc_args.param.sgl[i].tsg_length = 889 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 890 } 891 /* XXX Needed? */ 892 for (; i < TWE_SG_SIZE; i++) { 893 tc->tc_args.param.sgl[i].tsg_address = 0; 894 tc->tc_args.param.sgl[i].tsg_length = 0; 895 } 896 break; 897 case 3: 898 for (i = 0; i < nsegs; i++) { 899 tc->tc_args.io.sgl[i].tsg_address = 900 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 901 tc->tc_args.io.sgl[i].tsg_length = 902 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 903 } 904 /* XXX Needed? */ 905 for (; i < TWE_SG_SIZE; i++) { 906 tc->tc_args.io.sgl[i].tsg_address = 0; 907 tc->tc_args.io.sgl[i].tsg_length = 0; 908 } 909 break; 910 #ifdef DEBUG 911 default: 912 panic("twe_ccb_map: oops"); 913 #endif 914 } 915 916 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 917 flags = BUS_DMASYNC_PREREAD; 918 else 919 flags = 0; 920 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 921 flags |= BUS_DMASYNC_PREWRITE; 922 923 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 924 ccb->ccb_datasize, flags); 925 return (0); 926 } 927 928 /* 929 * Unmap the specified CCB's command block and data buffer (if any) and 930 * perform DMA synchronisation. 931 */ 932 void 933 twe_ccb_unmap(struct twe_softc *sc, struct twe_ccb *ccb) 934 { 935 int flags, s; 936 937 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 938 flags = BUS_DMASYNC_POSTREAD; 939 else 940 flags = 0; 941 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 942 flags |= BUS_DMASYNC_POSTWRITE; 943 944 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 945 ccb->ccb_datasize, flags); 946 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap_xfer); 947 948 if (ccb->ccb_abuf != (vaddr_t)0) { 949 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 950 memcpy(ccb->ccb_data, (void *)ccb->ccb_abuf, 951 ccb->ccb_datasize); 952 s = splvm(); 953 /* XXX */ 954 uvm_km_free(kmem_map, ccb->ccb_abuf, ccb->ccb_datasize); 955 splx(s); 956 } 957 } 958 959 /* 960 * Submit a command to the controller and poll on completion. Return 961 * non-zero on timeout (but don't check status, as some command types don't 962 * return status). Must be called with interrupts blocked. 963 */ 964 int 965 twe_ccb_poll(struct twe_softc *sc, struct twe_ccb *ccb, int timo) 966 { 967 int rv; 968 969 if ((rv = twe_ccb_submit(sc, ccb)) != 0) 970 return (rv); 971 972 for (timo *= 1000; timo != 0; timo--) { 973 twe_poll(sc); 974 if ((ccb->ccb_flags & TWE_CCB_COMPLETE) != 0) 975 break; 976 DELAY(100); 977 } 978 979 return (timo == 0); 980 } 981 982 /* 983 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 984 * the order that they were enqueued and try to submit their command blocks 985 * to the controller for execution. 986 */ 987 void 988 twe_ccb_enqueue(struct twe_softc *sc, struct twe_ccb *ccb) 989 { 990 int s; 991 992 s = splbio(); 993 994 if (ccb != NULL) 995 SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 996 997 while ((ccb = SIMPLEQ_FIRST(&sc->sc_ccb_queue)) != NULL) { 998 if (twe_ccb_submit(sc, ccb)) 999 break; 1000 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 1001 } 1002 1003 splx(s); 1004 } 1005 1006 /* 1007 * Submit the command block associated with the specified CCB to the 1008 * controller for execution. Must be called with interrupts blocked. 1009 */ 1010 int 1011 twe_ccb_submit(struct twe_softc *sc, struct twe_ccb *ccb) 1012 { 1013 bus_addr_t pa; 1014 int rv; 1015 u_int status; 1016 1017 /* Check to see if we can post a command. */ 1018 status = twe_inl(sc, TWE_REG_STS); 1019 twe_status_check(sc, status); 1020 1021 if ((status & TWE_STS_CMD_QUEUE_FULL) == 0) { 1022 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1023 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, sizeof(struct twe_cmd), 1024 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1025 ccb->ccb_flags |= TWE_CCB_ACTIVE; 1026 pa = sc->sc_cmds_paddr + 1027 ccb->ccb_cmdid * sizeof(struct twe_cmd); 1028 twe_outl(sc, TWE_REG_CMD_QUEUE, (u_int32_t)pa); 1029 rv = 0; 1030 } else 1031 rv = EBUSY; 1032 1033 return (rv); 1034 } 1035
Indexes created Sun Sep 21 20:09:37 GMT 2025