twe.c revision 1.32
1 /* $NetBSD: twe.c,v 1.32 2002/11/25 07:47:53 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twe.c,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 /* 69 * Driver for the 3ware Escalade family of RAID controllers. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: twe.c,v 1.32 2002/11/25 07:47:53 thorpej Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/device.h> 79 #include <sys/queue.h> 80 #include <sys/proc.h> 81 #include <sys/buf.h> 82 #include <sys/endian.h> 83 #include <sys/malloc.h> 84 #include <sys/disk.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/bswap.h> 89 #include <machine/bus.h> 90 91 #include <dev/pci/pcireg.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcidevs.h> 94 #include <dev/pci/twereg.h> 95 #include <dev/pci/twevar.h> 96 97 #define PCI_CBIO 0x10 98 99 static void twe_aen_handler(struct twe_ccb *, int); 100 static void twe_attach(struct device *, struct device *, void *); 101 static int twe_init_connection(struct twe_softc *); 102 static int twe_intr(void *); 103 static int twe_match(struct device *, struct cfdata *, void *); 104 static int twe_param_get(struct twe_softc *, int, int, size_t, 105 void (*)(struct twe_ccb *, int), void **); 106 static void twe_poll(struct twe_softc *); 107 static int twe_print(void *, const char *); 108 static int twe_reset(struct twe_softc *); 109 static int twe_submatch(struct device *, struct cfdata *, void *); 110 static int twe_status_check(struct twe_softc *, u_int); 111 static int twe_status_wait(struct twe_softc *, u_int, int); 112 113 static inline u_int32_t twe_inl(struct twe_softc *, int); 114 static inline void twe_outl(struct twe_softc *, int, u_int32_t); 115 116 CFATTACH_DECL(twe, sizeof(struct twe_softc), 117 twe_match, twe_attach, NULL, NULL); 118 119 struct { 120 const u_int aen; /* High byte indicates type of message */ 121 const char *desc; 122 } static const twe_aen_names[] = { 123 { 0x0000, "queue empty" }, 124 { 0x0001, "soft reset" }, 125 { 0x0102, "degraded mirror" }, 126 { 0x0003, "controller error" }, 127 { 0x0104, "rebuild fail" }, 128 { 0x0105, "rebuild done" }, 129 { 0x0106, "incompatible unit" }, 130 { 0x0107, "initialisation done" }, 131 { 0x0108, "unclean shutdown detected" }, 132 { 0x0109, "drive timeout" }, 133 { 0x010a, "drive error" }, 134 { 0x010b, "rebuild started" }, 135 { 0x010c, "init started" }, 136 { 0x010d, "logical unit deleted" }, 137 { 0x020f, "SMART threshold exceeded" }, 138 { 0x0015, "table undefined" }, /* XXX: Not in FreeBSD's table */ 139 { 0x0221, "ATA UDMA downgrade" }, 140 { 0x0222, "ATA UDMA upgrade" }, 141 { 0x0222, "ATA UDMA upgrade" }, 142 { 0x0223, "Sector repair occurred" }, 143 { 0x0024, "SBUF integrity check failure" }, 144 { 0x0225, "lost cached write" }, 145 { 0x0226, "drive ECC error detected" }, 146 { 0x0227, "DCB checksum error" }, 147 { 0x0228, "DCB unsupported version" }, 148 { 0x0129, "verify started" }, 149 { 0x012a, "verify failed" }, 150 { 0x012b, "verify complete" }, 151 { 0x022c, "overwrote bad sector during rebuild" }, 152 { 0x022d, "encountered bad sector during rebuild" }, 153 { 0x00ff, "aen queue full" }, 154 }; 155 156 /* 157 * The high byte of the message above determines the format, 158 * currently we know about format 0 (no unit/port specific) 159 * format 1 (unit specific message), and format 2 (port specific message). 160 */ 161 static const char *aenfmt[] = { 162 "", /* No message */ 163 "unit %d: ", /* Unit message */ 164 "port %d: " /* Port message */ 165 }; 166 167 168 static inline u_int32_t 169 twe_inl(struct twe_softc *sc, int off) 170 { 171 172 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 173 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 174 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, off)); 175 } 176 177 static inline void 178 twe_outl(struct twe_softc *sc, int off, u_int32_t val) 179 { 180 181 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 182 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 183 BUS_SPACE_BARRIER_WRITE); 184 } 185 186 /* 187 * Match a supported board. 188 */ 189 static int 190 twe_match(struct device *parent, struct cfdata *cfdata, void *aux) 191 { 192 struct pci_attach_args *pa; 193 194 pa = aux; 195 196 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3WARE && 197 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE || 198 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE_ASIC)); 199 } 200 201 /* 202 * Attach a supported board. 203 * 204 * XXX This doesn't fail gracefully. 205 */ 206 static void 207 twe_attach(struct device *parent, struct device *self, void *aux) 208 { 209 struct pci_attach_args *pa; 210 struct twe_softc *sc; 211 pci_chipset_tag_t pc; 212 pci_intr_handle_t ih; 213 pcireg_t csr; 214 const char *intrstr; 215 int size, i, rv, rseg; 216 size_t max_segs, max_xfer; 217 struct twe_param *dtp, *ctp; 218 bus_dma_segment_t seg; 219 struct twe_cmd *tc; 220 struct twe_attach_args twea; 221 struct twe_ccb *ccb; 222 223 sc = (struct twe_softc *)self; 224 pa = aux; 225 pc = pa->pa_pc; 226 sc->sc_dmat = pa->pa_dmat; 227 SIMPLEQ_INIT(&sc->sc_ccb_queue); 228 SLIST_INIT(&sc->sc_ccb_freelist); 229 230 printf(": 3ware Escalade\n"); 231 232 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 233 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 234 printf("%s: can't map i/o space\n", sc->sc_dv.dv_xname); 235 return; 236 } 237 238 /* Enable the device. */ 239 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 240 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 241 csr | PCI_COMMAND_MASTER_ENABLE); 242 243 /* Map and establish the interrupt. */ 244 if (pci_intr_map(pa, &ih)) { 245 printf("%s: can't map interrupt\n", sc->sc_dv.dv_xname); 246 return; 247 } 248 intrstr = pci_intr_string(pc, ih); 249 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, twe_intr, sc); 250 if (sc->sc_ih == NULL) { 251 printf("%s: can't establish interrupt", sc->sc_dv.dv_xname); 252 if (intrstr != NULL) 253 printf(" at %s", intrstr); 254 printf("\n"); 255 return; 256 } 257 if (intrstr != NULL) 258 printf("%s: interrupting at %s\n", sc->sc_dv.dv_xname, intrstr); 259 260 /* 261 * Allocate and initialise the command blocks and CCBs. 262 */ 263 size = sizeof(struct twe_cmd) * TWE_MAX_QUEUECNT; 264 265 if ((rv = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 1, 266 &rseg, BUS_DMA_NOWAIT)) != 0) { 267 printf("%s: unable to allocate commands, rv = %d\n", 268 sc->sc_dv.dv_xname, rv); 269 return; 270 } 271 272 if ((rv = bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 273 (caddr_t *)&sc->sc_cmds, 274 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 275 printf("%s: unable to map commands, rv = %d\n", 276 sc->sc_dv.dv_xname, rv); 277 return; 278 } 279 280 if ((rv = bus_dmamap_create(sc->sc_dmat, size, size, 1, 0, 281 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 282 printf("%s: unable to create command DMA map, rv = %d\n", 283 sc->sc_dv.dv_xname, rv); 284 return; 285 } 286 287 if ((rv = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cmds, 288 size, NULL, BUS_DMA_NOWAIT)) != 0) { 289 printf("%s: unable to load command DMA map, rv = %d\n", 290 sc->sc_dv.dv_xname, rv); 291 return; 292 } 293 294 sc->sc_cmds_paddr = sc->sc_dmamap->dm_segs[0].ds_addr; 295 memset(sc->sc_cmds, 0, size); 296 297 ccb = malloc(sizeof(*ccb) * TWE_MAX_QUEUECNT, M_DEVBUF, M_NOWAIT); 298 sc->sc_ccbs = ccb; 299 tc = (struct twe_cmd *)sc->sc_cmds; 300 max_segs = twe_get_maxsegs(); 301 max_xfer = twe_get_maxxfer(max_segs); 302 303 for (i = 0; i < TWE_MAX_QUEUECNT; i++, tc++, ccb++) { 304 ccb->ccb_cmd = tc; 305 ccb->ccb_cmdid = i; 306 ccb->ccb_flags = 0; 307 rv = bus_dmamap_create(sc->sc_dmat, max_xfer, 308 max_segs, PAGE_SIZE, 0, 309 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 310 &ccb->ccb_dmamap_xfer); 311 if (rv != 0) { 312 printf("%s: can't create dmamap, rv = %d\n", 313 sc->sc_dv.dv_xname, rv); 314 return; 315 } 316 /* Save one CCB for parameter retrieval. */ 317 if (i != 0) 318 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, 319 ccb_chain.slist); 320 } 321 322 /* Wait for the controller to become ready. */ 323 if (twe_status_wait(sc, TWE_STS_MICROCONTROLLER_READY, 6)) { 324 printf("%s: microcontroller not ready\n", sc->sc_dv.dv_xname); 325 return; 326 } 327 328 twe_outl(sc, TWE_REG_CTL, TWE_CTL_DISABLE_INTRS); 329 330 /* Reset the controller. */ 331 if (twe_reset(sc)) { 332 printf("%s: reset failed\n", sc->sc_dv.dv_xname); 333 return; 334 } 335 336 /* Find attached units. */ 337 rv = twe_param_get(sc, TWE_PARAM_UNITSUMMARY, 338 TWE_PARAM_UNITSUMMARY_Status, TWE_MAX_UNITS, NULL, (void *)&dtp); 339 if (rv != 0) { 340 printf("%s: can't detect attached units (%d)\n", 341 sc->sc_dv.dv_xname, rv); 342 return; 343 } 344 345 /* For each detected unit, collect size and store in an array. */ 346 for (i = 0, sc->sc_nunits = 0; i < TWE_MAX_UNITS; i++) { 347 /* Unit present? */ 348 if ((dtp->tp_data[i] & TWE_PARAM_UNITSTATUS_Online) == 0) { 349 sc->sc_dsize[i] = 0; 350 continue; 351 } 352 353 rv = twe_param_get(sc, TWE_PARAM_UNITINFO + i, 354 TWE_PARAM_UNITINFO_Capacity, 4, NULL, (void *)&ctp); 355 if (rv != 0) { 356 printf("%s: error %d fetching capacity for unit %d\n", 357 sc->sc_dv.dv_xname, rv, i); 358 continue; 359 } 360 361 sc->sc_dsize[i] = le32toh(*(u_int32_t *)ctp->tp_data); 362 free(ctp, M_DEVBUF); 363 sc->sc_nunits++; 364 } 365 free(dtp, M_DEVBUF); 366 367 /* Initialise connection with controller and enable interrupts. */ 368 twe_init_connection(sc); 369 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR | 370 TWE_CTL_UNMASK_RESP_INTR | 371 TWE_CTL_ENABLE_INTRS); 372 373 /* Attach sub-devices. */ 374 for (i = 0; i < TWE_MAX_UNITS; i++) { 375 if (sc->sc_dsize[i] == 0) 376 continue; 377 twea.twea_unit = i; 378 config_found_sm(&sc->sc_dv, &twea, twe_print, twe_submatch); 379 } 380 } 381 382 /* 383 * Reset the controller. Currently only useful at attach time; must be 384 * called with interrupts blocked. 385 */ 386 static int 387 twe_reset(struct twe_softc *sc) 388 { 389 struct twe_param *tp; 390 u_int aen, status; 391 volatile u_int32_t junk; 392 int got, rv; 393 394 /* Issue a soft reset. */ 395 twe_outl(sc, TWE_REG_CTL, TWE_CTL_ISSUE_SOFT_RESET | 396 TWE_CTL_CLEAR_HOST_INTR | 397 TWE_CTL_CLEAR_ATTN_INTR | 398 TWE_CTL_MASK_CMD_INTR | 399 TWE_CTL_MASK_RESP_INTR | 400 TWE_CTL_CLEAR_ERROR_STS | 401 TWE_CTL_DISABLE_INTRS); 402 403 if (twe_status_wait(sc, TWE_STS_ATTN_INTR, 15)) { 404 printf("%s: no attention interrupt\n", 405 sc->sc_dv.dv_xname); 406 return (-1); 407 } 408 409 /* Pull AENs out of the controller; look for a soft reset AEN. */ 410 for (got = 0;;) { 411 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 412 2, NULL, (void *)&tp); 413 if (rv != 0) 414 printf("%s: error %d while draining response queue\n", 415 sc->sc_dv.dv_xname, rv); 416 aen = TWE_AEN_CODE(le16toh(*(u_int16_t *)tp->tp_data)); 417 free(tp, M_DEVBUF); 418 if (aen == TWE_AEN_QUEUE_EMPTY) 419 break; 420 if (aen == TWE_AEN_SOFT_RESET) 421 got = 1; 422 } 423 if (!got) { 424 printf("%s: reset not reported\n", sc->sc_dv.dv_xname); 425 return (-1); 426 } 427 428 /* Check controller status. */ 429 status = twe_inl(sc, TWE_REG_STS); 430 if (twe_status_check(sc, status)) { 431 printf("%s: controller errors detected\n", 432 sc->sc_dv.dv_xname); 433 return (-1); 434 } 435 436 /* Drain the response queue. */ 437 for (;;) { 438 status = twe_inl(sc, TWE_REG_STS); 439 if (twe_status_check(sc, status) != 0) { 440 printf("%s: can't drain response queue\n", 441 sc->sc_dv.dv_xname); 442 return (-1); 443 } 444 if ((status & TWE_STS_RESP_QUEUE_EMPTY) != 0) 445 break; 446 junk = twe_inl(sc, TWE_REG_RESP_QUEUE); 447 } 448 449 return (0); 450 } 451 452 /* 453 * Print autoconfiguration message for a sub-device. 454 */ 455 static int 456 twe_print(void *aux, const char *pnp) 457 { 458 struct twe_attach_args *twea; 459 460 twea = aux; 461 462 if (pnp != NULL) 463 printf("block device at %s", pnp); 464 printf(" unit %d", twea->twea_unit); 465 return (UNCONF); 466 } 467 468 /* 469 * Match a sub-device. 470 */ 471 static int 472 twe_submatch(struct device *parent, struct cfdata *cf, void *aux) 473 { 474 struct twe_attach_args *twea; 475 476 twea = aux; 477 478 if (cf->tweacf_unit != TWECF_UNIT_DEFAULT && 479 cf->tweacf_unit != twea->twea_unit) 480 return (0); 481 482 return (config_match(parent, cf, aux)); 483 } 484 485 /* 486 * Interrupt service routine. 487 */ 488 static int 489 twe_intr(void *arg) 490 { 491 struct twe_softc *sc; 492 u_int status; 493 int caught, rv; 494 495 sc = arg; 496 caught = 0; 497 status = twe_inl(sc, TWE_REG_STS); 498 twe_status_check(sc, status); 499 500 /* Host interrupts - purpose unknown. */ 501 if ((status & TWE_STS_HOST_INTR) != 0) { 502 #ifdef DIAGNOSTIC 503 printf("%s: host interrupt\n", sc->sc_dv.dv_xname); 504 #endif 505 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_HOST_INTR); 506 caught = 1; 507 } 508 509 /* 510 * Attention interrupts, signalled when a controller or child device 511 * state change has occurred. 512 */ 513 if ((status & TWE_STS_ATTN_INTR) != 0) { 514 if ((sc->sc_flags & TWEF_AEN) == 0) { 515 rv = twe_param_get(sc, TWE_PARAM_AEN, 516 TWE_PARAM_AEN_UnitCode, 2, twe_aen_handler, 517 NULL); 518 if (rv != 0) { 519 printf("%s: unable to retrieve AEN (%d)\n", 520 sc->sc_dv.dv_xname, rv); 521 twe_outl(sc, TWE_REG_CTL, 522 TWE_CTL_CLEAR_ATTN_INTR); 523 } else 524 sc->sc_flags |= TWEF_AEN; 525 } 526 caught = 1; 527 } 528 529 /* 530 * Command interrupts, signalled when the controller can accept more 531 * commands. We don't use this; instead, we try to submit commands 532 * when we receive them, and when other commands have completed. 533 * Mask it so we don't get another one. 534 */ 535 if ((status & TWE_STS_CMD_INTR) != 0) { 536 #ifdef DIAGNOSTIC 537 printf("%s: command interrupt\n", sc->sc_dv.dv_xname); 538 #endif 539 twe_outl(sc, TWE_REG_CTL, TWE_CTL_MASK_CMD_INTR); 540 caught = 1; 541 } 542 543 if ((status & TWE_STS_RESP_INTR) != 0) { 544 twe_poll(sc); 545 caught = 1; 546 } 547 548 return (caught); 549 } 550 551 /* 552 * Handle an AEN returned by the controller. 553 */ 554 static void 555 twe_aen_handler(struct twe_ccb *ccb, int error) 556 { 557 struct twe_softc *sc; 558 struct twe_param *tp; 559 const char *str; 560 u_int aen; 561 int i, hu, rv; 562 563 sc = (struct twe_softc *)ccb->ccb_tx.tx_dv; 564 tp = ccb->ccb_tx.tx_context; 565 twe_ccb_unmap(sc, ccb); 566 567 if (error) { 568 printf("%s: error retrieving AEN\n", sc->sc_dv.dv_xname); 569 aen = TWE_AEN_QUEUE_EMPTY; 570 } else 571 aen = le16toh(*(u_int16_t *)tp->tp_data); 572 free(tp, M_DEVBUF); 573 twe_ccb_free(sc, ccb); 574 575 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) { 576 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 577 sc->sc_flags &= ~TWEF_AEN; 578 return; 579 } 580 581 str = "<unknown>"; 582 i = 0; 583 hu = 0; 584 585 while (i < sizeof(twe_aen_names) / sizeof(twe_aen_names[0])) { 586 if (TWE_AEN_CODE(twe_aen_names[i].aen) == TWE_AEN_CODE(aen)) { 587 str = twe_aen_names[i].desc; 588 hu = TWE_AEN_UNIT(twe_aen_names[i].aen); 589 break; 590 } 591 i++; 592 } 593 printf("%s: ", sc->sc_dv.dv_xname); 594 printf(aenfmt[hu], TWE_AEN_UNIT(aen)); 595 printf("AEN 0x%04x (%s) received\n", TWE_AEN_CODE(aen), str); 596 597 /* 598 * Chain another retrieval in case interrupts have been 599 * coalesced. 600 */ 601 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 2, 602 twe_aen_handler, NULL); 603 if (rv != 0) 604 printf("%s: unable to retrieve AEN (%d)\n", 605 sc->sc_dv.dv_xname, rv); 606 } 607 608 /* 609 * Execute a TWE_OP_GET_PARAM command. If a callback function is provided, 610 * it will be called with generated context when the command has completed. 611 * If no callback is provided, the command will be executed synchronously 612 * and a pointer to a buffer containing the data returned. 613 * 614 * The caller or callback is responsible for freeing the buffer. 615 */ 616 static int 617 twe_param_get(struct twe_softc *sc, int table_id, int param_id, size_t size, 618 void (*func)(struct twe_ccb *, int), void **pbuf) 619 { 620 struct twe_ccb *ccb; 621 struct twe_cmd *tc; 622 struct twe_param *tp; 623 int rv, s; 624 625 rv = twe_ccb_alloc(sc, &ccb, 626 TWE_CCB_PARAM | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 627 if (rv != 0) 628 return (rv); 629 630 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 631 if (pbuf != NULL) 632 *pbuf = tp; 633 634 ccb->ccb_data = tp; 635 ccb->ccb_datasize = TWE_SECTOR_SIZE; 636 ccb->ccb_tx.tx_handler = func; 637 ccb->ccb_tx.tx_context = tp; 638 ccb->ccb_tx.tx_dv = &sc->sc_dv; 639 640 tc = ccb->ccb_cmd; 641 tc->tc_size = 2; 642 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 643 tc->tc_unit = 0; 644 tc->tc_count = htole16(1); 645 646 /* Fill in the outbound parameter data. */ 647 tp->tp_table_id = htole16(table_id); 648 tp->tp_param_id = param_id; 649 tp->tp_param_size = size; 650 651 /* Map the transfer. */ 652 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 653 twe_ccb_free(sc, ccb); 654 free(tp, M_DEVBUF); 655 return (rv); 656 } 657 658 /* Submit the command and either wait or let the callback handle it. */ 659 if (func == NULL) { 660 s = splbio(); 661 rv = twe_ccb_poll(sc, ccb, 5); 662 twe_ccb_unmap(sc, ccb); 663 twe_ccb_free(sc, ccb); 664 splx(s); 665 if (rv != 0) 666 free(tp, M_DEVBUF); 667 } else { 668 twe_ccb_enqueue(sc, ccb); 669 rv = 0; 670 } 671 672 return (rv); 673 } 674 675 /* 676 * Execute a TWE_OP_INIT_CONNECTION command. Return non-zero on error. 677 * Must be called with interrupts blocked. 678 */ 679 static int 680 twe_init_connection(struct twe_softc *sc) 681 { 682 struct twe_ccb *ccb; 683 struct twe_cmd *tc; 684 int rv; 685 686 if ((rv = twe_ccb_alloc(sc, &ccb, 0)) != 0) 687 return (rv); 688 689 /* Build the command. */ 690 tc = ccb->ccb_cmd; 691 tc->tc_size = 3; 692 tc->tc_opcode = TWE_OP_INIT_CONNECTION; 693 tc->tc_unit = 0; 694 tc->tc_count = htole16(TWE_MAX_CMDS); 695 tc->tc_args.init_connection.response_queue_pointer = 0; 696 697 /* Submit the command for immediate execution. */ 698 rv = twe_ccb_poll(sc, ccb, 5); 699 twe_ccb_free(sc, ccb); 700 return (rv); 701 } 702 703 /* 704 * Poll the controller for completed commands. Must be called with 705 * interrupts blocked. 706 */ 707 static void 708 twe_poll(struct twe_softc *sc) 709 { 710 struct twe_ccb *ccb; 711 int found; 712 u_int status, cmdid; 713 714 found = 0; 715 716 for (;;) { 717 status = twe_inl(sc, TWE_REG_STS); 718 twe_status_check(sc, status); 719 720 if ((status & TWE_STS_RESP_QUEUE_EMPTY)) 721 break; 722 723 found = 1; 724 cmdid = twe_inl(sc, TWE_REG_RESP_QUEUE); 725 cmdid = (cmdid & TWE_RESP_MASK) >> TWE_RESP_SHIFT; 726 if (cmdid >= TWE_MAX_QUEUECNT) { 727 printf("%s: bad completion\n", sc->sc_dv.dv_xname); 728 continue; 729 } 730 731 ccb = sc->sc_ccbs + cmdid; 732 if ((ccb->ccb_flags & TWE_CCB_ACTIVE) == 0) { 733 printf("%s: bad completion (not active)\n", 734 sc->sc_dv.dv_xname); 735 continue; 736 } 737 ccb->ccb_flags ^= TWE_CCB_COMPLETE | TWE_CCB_ACTIVE; 738 739 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 740 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, 741 sizeof(struct twe_cmd), 742 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 743 744 /* Pass notification to upper layers. */ 745 if (ccb->ccb_tx.tx_handler != NULL) 746 (*ccb->ccb_tx.tx_handler)(ccb, 747 ccb->ccb_cmd->tc_status != 0 ? EIO : 0); 748 } 749 750 /* If any commands have completed, run the software queue. */ 751 if (found) 752 twe_ccb_enqueue(sc, NULL); 753 } 754 755 /* 756 * Wait for `status' to be set in the controller status register. Return 757 * zero if found, non-zero if the operation timed out. 758 */ 759 static int 760 twe_status_wait(struct twe_softc *sc, u_int32_t status, int timo) 761 { 762 763 for (timo *= 10; timo != 0; timo--) { 764 if ((twe_inl(sc, TWE_REG_STS) & status) == status) 765 break; 766 delay(100000); 767 } 768 769 return (timo == 0); 770 } 771 772 /* 773 * Complain if the status bits aren't what we expect. 774 */ 775 static int 776 twe_status_check(struct twe_softc *sc, u_int status) 777 { 778 int rv; 779 780 rv = 0; 781 782 if ((status & TWE_STS_EXPECTED_BITS) != TWE_STS_EXPECTED_BITS) { 783 printf("%s: missing status bits: 0x%08x\n", sc->sc_dv.dv_xname, 784 status & ~TWE_STS_EXPECTED_BITS); 785 rv = -1; 786 } 787 788 if ((status & TWE_STS_UNEXPECTED_BITS) != 0) { 789 printf("%s: unexpected status bits: 0x%08x\n", 790 sc->sc_dv.dv_xname, status & TWE_STS_UNEXPECTED_BITS); 791 rv = -1; 792 } 793 794 return (rv); 795 } 796 797 /* 798 * Allocate and initialise a CCB. 799 */ 800 int 801 twe_ccb_alloc(struct twe_softc *sc, struct twe_ccb **ccbp, int flags) 802 { 803 struct twe_cmd *tc; 804 struct twe_ccb *ccb; 805 int s; 806 807 s = splbio(); 808 if ((flags & TWE_CCB_PARAM) != 0) 809 ccb = sc->sc_ccbs; 810 else { 811 /* Allocate a CCB and command block. */ 812 if (SLIST_FIRST(&sc->sc_ccb_freelist) == NULL) { 813 splx(s); 814 return (EAGAIN); 815 } 816 ccb = SLIST_FIRST(&sc->sc_ccb_freelist); 817 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 818 } 819 #ifdef DIAGNOSTIC 820 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 821 panic("twe_ccb_alloc: CCB already allocated"); 822 flags |= TWE_CCB_ALLOCED; 823 #endif 824 splx(s); 825 826 /* Initialise some fields and return. */ 827 ccb->ccb_tx.tx_handler = NULL; 828 ccb->ccb_flags = flags; 829 tc = ccb->ccb_cmd; 830 tc->tc_status = 0; 831 tc->tc_flags = 0; 832 tc->tc_cmdid = ccb->ccb_cmdid; 833 *ccbp = ccb; 834 835 return (0); 836 } 837 838 /* 839 * Free a CCB. 840 */ 841 void 842 twe_ccb_free(struct twe_softc *sc, struct twe_ccb *ccb) 843 { 844 int s; 845 846 s = splbio(); 847 if ((ccb->ccb_flags & TWE_CCB_PARAM) == 0) 848 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, ccb_chain.slist); 849 ccb->ccb_flags = 0; 850 splx(s); 851 } 852 853 /* 854 * Map the specified CCB's command block and data buffer (if any) into 855 * controller visible space. Perform DMA synchronisation. 856 */ 857 int 858 twe_ccb_map(struct twe_softc *sc, struct twe_ccb *ccb) 859 { 860 struct twe_cmd *tc; 861 int flags, nsegs, i, s, rv; 862 void *data; 863 864 /* 865 * The data as a whole must be 512-byte aligned. 866 */ 867 if (((u_long)ccb->ccb_data & (TWE_ALIGNMENT - 1)) != 0) { 868 s = splvm(); 869 /* XXX */ 870 ccb->ccb_abuf = uvm_km_kmemalloc(kmem_map, NULL, 871 ccb->ccb_datasize, UVM_KMF_NOWAIT); 872 splx(s); 873 data = (void *)ccb->ccb_abuf; 874 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 875 memcpy(data, ccb->ccb_data, ccb->ccb_datasize); 876 } else { 877 ccb->ccb_abuf = (vaddr_t)0; 878 data = ccb->ccb_data; 879 } 880 881 /* 882 * Map the data buffer into bus space and build the S/G list. 883 */ 884 rv = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap_xfer, data, 885 ccb->ccb_datasize, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 886 ((ccb->ccb_flags & TWE_CCB_DATA_IN) ? 887 BUS_DMA_READ : BUS_DMA_WRITE)); 888 if (rv != 0) { 889 if (ccb->ccb_abuf != (vaddr_t)0) { 890 s = splvm(); 891 /* XXX */ 892 uvm_km_free(kmem_map, ccb->ccb_abuf, 893 ccb->ccb_datasize); 894 splx(s); 895 } 896 return (rv); 897 } 898 899 nsegs = ccb->ccb_dmamap_xfer->dm_nsegs; 900 tc = ccb->ccb_cmd; 901 tc->tc_size += 2 * nsegs; 902 903 /* The location of the S/G list is dependant upon command type. */ 904 switch (tc->tc_opcode >> 5) { 905 case 2: 906 for (i = 0; i < nsegs; i++) { 907 tc->tc_args.param.sgl[i].tsg_address = 908 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 909 tc->tc_args.param.sgl[i].tsg_length = 910 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 911 } 912 /* XXX Needed? */ 913 for (; i < TWE_SG_SIZE; i++) { 914 tc->tc_args.param.sgl[i].tsg_address = 0; 915 tc->tc_args.param.sgl[i].tsg_length = 0; 916 } 917 break; 918 case 3: 919 for (i = 0; i < nsegs; i++) { 920 tc->tc_args.io.sgl[i].tsg_address = 921 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 922 tc->tc_args.io.sgl[i].tsg_length = 923 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 924 } 925 /* XXX Needed? */ 926 for (; i < TWE_SG_SIZE; i++) { 927 tc->tc_args.io.sgl[i].tsg_address = 0; 928 tc->tc_args.io.sgl[i].tsg_length = 0; 929 } 930 break; 931 #ifdef DEBUG 932 default: 933 panic("twe_ccb_map: oops"); 934 #endif 935 } 936 937 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 938 flags = BUS_DMASYNC_PREREAD; 939 else 940 flags = 0; 941 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 942 flags |= BUS_DMASYNC_PREWRITE; 943 944 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 945 ccb->ccb_datasize, flags); 946 return (0); 947 } 948 949 /* 950 * Unmap the specified CCB's command block and data buffer (if any) and 951 * perform DMA synchronisation. 952 */ 953 void 954 twe_ccb_unmap(struct twe_softc *sc, struct twe_ccb *ccb) 955 { 956 int flags, s; 957 958 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 959 flags = BUS_DMASYNC_POSTREAD; 960 else 961 flags = 0; 962 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 963 flags |= BUS_DMASYNC_POSTWRITE; 964 965 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 966 ccb->ccb_datasize, flags); 967 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap_xfer); 968 969 if (ccb->ccb_abuf != (vaddr_t)0) { 970 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 971 memcpy(ccb->ccb_data, (void *)ccb->ccb_abuf, 972 ccb->ccb_datasize); 973 s = splvm(); 974 /* XXX */ 975 uvm_km_free(kmem_map, ccb->ccb_abuf, ccb->ccb_datasize); 976 splx(s); 977 } 978 } 979 980 /* 981 * Submit a command to the controller and poll on completion. Return 982 * non-zero on timeout (but don't check status, as some command types don't 983 * return status). Must be called with interrupts blocked. 984 */ 985 int 986 twe_ccb_poll(struct twe_softc *sc, struct twe_ccb *ccb, int timo) 987 { 988 int rv; 989 990 if ((rv = twe_ccb_submit(sc, ccb)) != 0) 991 return (rv); 992 993 for (timo *= 1000; timo != 0; timo--) { 994 twe_poll(sc); 995 if ((ccb->ccb_flags & TWE_CCB_COMPLETE) != 0) 996 break; 997 DELAY(100); 998 } 999 1000 return (timo == 0); 1001 } 1002 1003 /* 1004 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1005 * the order that they were enqueued and try to submit their command blocks 1006 * to the controller for execution. 1007 */ 1008 void 1009 twe_ccb_enqueue(struct twe_softc *sc, struct twe_ccb *ccb) 1010 { 1011 int s; 1012 1013 s = splbio(); 1014 1015 if (ccb != NULL) 1016 SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 1017 1018 while ((ccb = SIMPLEQ_FIRST(&sc->sc_ccb_queue)) != NULL) { 1019 if (twe_ccb_submit(sc, ccb)) 1020 break; 1021 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_queue, ccb_chain.simpleq); 1022 } 1023 1024 splx(s); 1025 } 1026 1027 /* 1028 * Submit the command block associated with the specified CCB to the 1029 * controller for execution. Must be called with interrupts blocked. 1030 */ 1031 int 1032 twe_ccb_submit(struct twe_softc *sc, struct twe_ccb *ccb) 1033 { 1034 bus_addr_t pa; 1035 int rv; 1036 u_int status; 1037 1038 /* Check to see if we can post a command. */ 1039 status = twe_inl(sc, TWE_REG_STS); 1040 twe_status_check(sc, status); 1041 1042 if ((status & TWE_STS_CMD_QUEUE_FULL) == 0) { 1043 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1044 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, sizeof(struct twe_cmd), 1045 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1046 ccb->ccb_flags |= TWE_CCB_ACTIVE; 1047 pa = sc->sc_cmds_paddr + 1048 ccb->ccb_cmdid * sizeof(struct twe_cmd); 1049 twe_outl(sc, TWE_REG_CMD_QUEUE, (u_int32_t)pa); 1050 rv = 0; 1051 } else 1052 rv = EBUSY; 1053 1054 return (rv); 1055 } 1056
Indexes created Tue Sep 23 02:09:52 GMT 2025