twe.c revision 1.37.2.6
1 /* $NetBSD: twe.c,v 1.37.2.6 2005/02/15 21:33:13 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran; and by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twe.c,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 /* 69 * Driver for the 3ware Escalade family of RAID controllers. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: twe.c,v 1.37.2.6 2005/02/15 21:33:13 skrll Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/device.h> 79 #include <sys/queue.h> 80 #include <sys/proc.h> 81 #include <sys/buf.h> 82 #include <sys/endian.h> 83 #include <sys/malloc.h> 84 #include <sys/conf.h> 85 #include <sys/disk.h> 86 #include <sys/syslog.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/bswap.h> 91 #include <machine/bus.h> 92 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcivar.h> 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/twereg.h> 97 #include <dev/pci/twevar.h> 98 #include <dev/pci/tweio.h> 99 100 #include "locators.h" 101 102 #define PCI_CBIO 0x10 103 104 static int twe_aen_get(struct twe_softc *, uint16_t *); 105 static void twe_aen_handler(struct twe_ccb *, int); 106 static void twe_aen_enqueue(struct twe_softc *sc, uint16_t, int); 107 static uint16_t twe_aen_dequeue(struct twe_softc *); 108 109 static void twe_attach(struct device *, struct device *, void *); 110 static int twe_init_connection(struct twe_softc *); 111 static int twe_intr(void *); 112 static int twe_match(struct device *, struct cfdata *, void *); 113 static int twe_param_set(struct twe_softc *, int, int, size_t, void *); 114 static void twe_poll(struct twe_softc *); 115 static int twe_print(void *, const char *); 116 static int twe_reset(struct twe_softc *); 117 static int twe_submatch(struct device *, struct cfdata *, 118 const locdesc_t *, void *); 119 static int twe_status_check(struct twe_softc *, u_int); 120 static int twe_status_wait(struct twe_softc *, u_int, int); 121 static void twe_describe_controller(struct twe_softc *); 122 123 static int twe_add_unit(struct twe_softc *, int); 124 static int twe_del_unit(struct twe_softc *, int); 125 126 static inline u_int32_t twe_inl(struct twe_softc *, int); 127 static inline void twe_outl(struct twe_softc *, int, u_int32_t); 128 129 dev_type_open(tweopen); 130 dev_type_close(tweclose); 131 dev_type_ioctl(tweioctl); 132 133 const struct cdevsw twe_cdevsw = { 134 tweopen, tweclose, noread, nowrite, tweioctl, 135 nostop, notty, nopoll, nommap, 136 }; 137 138 extern struct cfdriver twe_cd; 139 140 CFATTACH_DECL(twe, sizeof(struct twe_softc), 141 twe_match, twe_attach, NULL, NULL); 142 143 /* 144 * Tables to convert numeric codes to strings. 145 */ 146 const struct twe_code_table twe_table_status[] = { 147 { 0x00, "successful completion" }, 148 149 /* info */ 150 { 0x42, "command in progress" }, 151 { 0x6c, "retrying interface CRC error from UDMA command" }, 152 153 /* warning */ 154 { 0x81, "redundant/inconsequential request ignored" }, 155 { 0x8e, "failed to write zeroes to LBA 0" }, 156 { 0x8f, "failed to profile TwinStor zones" }, 157 158 /* fatal */ 159 { 0xc1, "aborted due to system command or reconfiguration" }, 160 { 0xc4, "aborted" }, 161 { 0xc5, "access error" }, 162 { 0xc6, "access violation" }, 163 { 0xc7, "device failure" }, /* high byte may be port # */ 164 { 0xc8, "controller error" }, 165 { 0xc9, "timed out" }, 166 { 0xcb, "invalid unit number" }, 167 { 0xcf, "unit not available" }, 168 { 0xd2, "undefined opcode" }, 169 { 0xdb, "request incompatible with unit" }, 170 { 0xdc, "invalid request" }, 171 { 0xff, "firmware error, reset requested" }, 172 173 { 0, NULL } 174 }; 175 176 const struct twe_code_table twe_table_unitstate[] = { 177 { TWE_PARAM_UNITSTATUS_Normal, "Normal" }, 178 { TWE_PARAM_UNITSTATUS_Initialising, "Initializing" }, 179 { TWE_PARAM_UNITSTATUS_Degraded, "Degraded" }, 180 { TWE_PARAM_UNITSTATUS_Rebuilding, "Rebuilding" }, 181 { TWE_PARAM_UNITSTATUS_Verifying, "Verifying" }, 182 { TWE_PARAM_UNITSTATUS_Corrupt, "Corrupt" }, 183 { TWE_PARAM_UNITSTATUS_Missing, "Missing" }, 184 185 { 0, NULL } 186 }; 187 188 const struct twe_code_table twe_table_unittype[] = { 189 /* array descriptor configuration */ 190 { TWE_AD_CONFIG_RAID0, "RAID0" }, 191 { TWE_AD_CONFIG_RAID1, "RAID1" }, 192 { TWE_AD_CONFIG_TwinStor, "TwinStor" }, 193 { TWE_AD_CONFIG_RAID5, "RAID5" }, 194 { TWE_AD_CONFIG_RAID10, "RAID10" }, 195 { TWE_UD_CONFIG_JBOD, "JBOD" }, 196 197 { 0, NULL } 198 }; 199 200 const struct twe_code_table twe_table_stripedepth[] = { 201 { TWE_AD_STRIPE_4k, "4K" }, 202 { TWE_AD_STRIPE_8k, "8K" }, 203 { TWE_AD_STRIPE_16k, "16K" }, 204 { TWE_AD_STRIPE_32k, "32K" }, 205 { TWE_AD_STRIPE_64k, "64K" }, 206 { TWE_AD_STRIPE_128k, "128K" }, 207 { TWE_AD_STRIPE_256k, "256K" }, 208 { TWE_AD_STRIPE_512k, "512K" }, 209 { TWE_AD_STRIPE_1024k, "1024K" }, 210 211 { 0, NULL } 212 }; 213 214 /* 215 * Asynchronous event notification messages are qualified: 216 * a - not unit/port specific 217 * u - unit specific 218 * p - port specific 219 * 220 * They are further qualified with a severity: 221 * E - LOG_EMERG 222 * a - LOG_ALERT 223 * c - LOG_CRIT 224 * e - LOG_ERR 225 * w - LOG_WARNING 226 * n - LOG_NOTICE 227 * i - LOG_INFO 228 * d - LOG_DEBUG 229 * blank - just use printf 230 */ 231 const struct twe_code_table twe_table_aen[] = { 232 { 0x00, "a queue empty" }, 233 { 0x01, "a soft reset" }, 234 { 0x02, "uc degraded mode" }, 235 { 0x03, "aa controller error" }, 236 { 0x04, "uE rebuild fail" }, 237 { 0x05, "un rebuild done" }, 238 { 0x06, "ue incomplete unit" }, 239 { 0x07, "un initialization done" }, 240 { 0x08, "uw unclean shutdown detected" }, 241 { 0x09, "pe drive timeout" }, 242 { 0x0a, "pc drive error" }, 243 { 0x0b, "un rebuild started" }, 244 { 0x0c, "un initialization started" }, 245 { 0x0d, "ui logical unit deleted" }, 246 { 0x0f, "pc SMART threshold exceeded" }, 247 { 0x15, "a table undefined" }, /* XXX: Not in FreeBSD's table */ 248 { 0x21, "pe ATA UDMA downgrade" }, 249 { 0x22, "pi ATA UDMA upgrade" }, 250 { 0x23, "pw sector repair occurred" }, 251 { 0x24, "aa SBUF integrity check failure" }, 252 { 0x25, "pa lost cached write" }, 253 { 0x26, "pa drive ECC error detected" }, 254 { 0x27, "pe DCB checksum error" }, 255 { 0x28, "pn DCB unsupported version" }, 256 { 0x29, "ui verify started" }, 257 { 0x2a, "ua verify failed" }, 258 { 0x2b, "ui verify complete" }, 259 { 0x2c, "pw overwrote bad sector during rebuild" }, 260 { 0x2d, "pa encountered bad sector during rebuild" }, 261 { 0x2e, "pe replacement drive too small" }, 262 { 0x2f, "ue array not previously initialized" }, 263 { 0x30, "p drive not supported" }, 264 { 0xff, "a aen queue full" }, 265 266 { 0, NULL }, 267 }; 268 269 const char * 270 twe_describe_code(const struct twe_code_table *table, uint32_t code) 271 { 272 273 for (; table->string != NULL; table++) { 274 if (table->code == code) 275 return (table->string); 276 } 277 return (NULL); 278 } 279 280 static inline u_int32_t 281 twe_inl(struct twe_softc *sc, int off) 282 { 283 284 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 285 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 286 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, off)); 287 } 288 289 static inline void 290 twe_outl(struct twe_softc *sc, int off, u_int32_t val) 291 { 292 293 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 294 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 295 BUS_SPACE_BARRIER_WRITE); 296 } 297 298 /* 299 * Match a supported board. 300 */ 301 static int 302 twe_match(struct device *parent, struct cfdata *cfdata, void *aux) 303 { 304 struct pci_attach_args *pa; 305 306 pa = aux; 307 308 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3WARE && 309 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE || 310 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE_ASIC)); 311 } 312 313 /* 314 * Attach a supported board. 315 * 316 * XXX This doesn't fail gracefully. 317 */ 318 static void 319 twe_attach(struct device *parent, struct device *self, void *aux) 320 { 321 struct pci_attach_args *pa; 322 struct twe_softc *sc; 323 pci_chipset_tag_t pc; 324 pci_intr_handle_t ih; 325 pcireg_t csr; 326 const char *intrstr; 327 int s, size, i, rv, rseg; 328 size_t max_segs, max_xfer; 329 bus_dma_segment_t seg; 330 struct twe_cmd *tc; 331 struct twe_ccb *ccb; 332 333 sc = (struct twe_softc *)self; 334 pa = aux; 335 pc = pa->pa_pc; 336 sc->sc_dmat = pa->pa_dmat; 337 SIMPLEQ_INIT(&sc->sc_ccb_queue); 338 SLIST_INIT(&sc->sc_ccb_freelist); 339 340 aprint_naive(": RAID controller\n"); 341 aprint_normal(": 3ware Escalade\n"); 342 343 ccb = malloc(sizeof(*ccb) * TWE_MAX_QUEUECNT, M_DEVBUF, M_NOWAIT); 344 if (ccb == NULL) { 345 aprint_error("%s: unable to allocate memory for ccbs\n", 346 sc->sc_dv.dv_xname); 347 return; 348 } 349 350 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 351 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 352 aprint_error("%s: can't map i/o space\n", sc->sc_dv.dv_xname); 353 return; 354 } 355 356 /* Enable the device. */ 357 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 358 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 359 csr | PCI_COMMAND_MASTER_ENABLE); 360 361 /* Map and establish the interrupt. */ 362 if (pci_intr_map(pa, &ih)) { 363 aprint_error("%s: can't map interrupt\n", sc->sc_dv.dv_xname); 364 return; 365 } 366 367 intrstr = pci_intr_string(pc, ih); 368 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, twe_intr, sc); 369 if (sc->sc_ih == NULL) { 370 aprint_error("%s: can't establish interrupt%s%s\n", 371 sc->sc_dv.dv_xname, 372 (intrstr) ? " at " : "", 373 (intrstr) ? intrstr : ""); 374 return; 375 } 376 377 if (intrstr != NULL) 378 aprint_normal("%s: interrupting at %s\n", 379 sc->sc_dv.dv_xname, intrstr); 380 381 /* 382 * Allocate and initialise the command blocks and CCBs. 383 */ 384 size = sizeof(struct twe_cmd) * TWE_MAX_QUEUECNT; 385 386 if ((rv = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 1, 387 &rseg, BUS_DMA_NOWAIT)) != 0) { 388 aprint_error("%s: unable to allocate commands, rv = %d\n", 389 sc->sc_dv.dv_xname, rv); 390 return; 391 } 392 393 if ((rv = bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 394 (caddr_t *)&sc->sc_cmds, 395 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 396 aprint_error("%s: unable to map commands, rv = %d\n", 397 sc->sc_dv.dv_xname, rv); 398 return; 399 } 400 401 if ((rv = bus_dmamap_create(sc->sc_dmat, size, size, 1, 0, 402 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 403 aprint_error("%s: unable to create command DMA map, rv = %d\n", 404 sc->sc_dv.dv_xname, rv); 405 return; 406 } 407 408 if ((rv = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cmds, 409 size, NULL, BUS_DMA_NOWAIT)) != 0) { 410 aprint_error("%s: unable to load command DMA map, rv = %d\n", 411 sc->sc_dv.dv_xname, rv); 412 return; 413 } 414 415 sc->sc_cmds_paddr = sc->sc_dmamap->dm_segs[0].ds_addr; 416 memset(sc->sc_cmds, 0, size); 417 418 sc->sc_ccbs = ccb; 419 tc = (struct twe_cmd *)sc->sc_cmds; 420 max_segs = twe_get_maxsegs(); 421 max_xfer = twe_get_maxxfer(max_segs); 422 423 for (i = 0; i < TWE_MAX_QUEUECNT; i++, tc++, ccb++) { 424 ccb->ccb_cmd = tc; 425 ccb->ccb_cmdid = i; 426 ccb->ccb_flags = 0; 427 rv = bus_dmamap_create(sc->sc_dmat, max_xfer, 428 max_segs, PAGE_SIZE, 0, 429 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 430 &ccb->ccb_dmamap_xfer); 431 if (rv != 0) { 432 aprint_error("%s: can't create dmamap, rv = %d\n", 433 sc->sc_dv.dv_xname, rv); 434 return; 435 } 436 437 /* Save the first CCB for AEN retrieval. */ 438 if (i != 0) 439 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, 440 ccb_chain.slist); 441 } 442 443 /* Wait for the controller to become ready. */ 444 if (twe_status_wait(sc, TWE_STS_MICROCONTROLLER_READY, 6)) { 445 aprint_error("%s: microcontroller not ready\n", 446 sc->sc_dv.dv_xname); 447 return; 448 } 449 450 twe_outl(sc, TWE_REG_CTL, TWE_CTL_DISABLE_INTRS); 451 452 /* Reset the controller. */ 453 s = splbio(); 454 rv = twe_reset(sc); 455 splx(s); 456 if (rv) { 457 aprint_error("%s: reset failed\n", sc->sc_dv.dv_xname); 458 return; 459 } 460 461 /* Initialise connection with controller. */ 462 twe_init_connection(sc); 463 464 twe_describe_controller(sc); 465 466 /* Find and attach RAID array units. */ 467 sc->sc_nunits = 0; 468 for (i = 0; i < TWE_MAX_UNITS; i++) 469 (void) twe_add_unit(sc, i); 470 471 /* ...and finally, enable interrupts. */ 472 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR | 473 TWE_CTL_UNMASK_RESP_INTR | 474 TWE_CTL_ENABLE_INTRS); 475 } 476 477 void 478 twe_register_callbacks(struct twe_softc *sc, int unit, 479 const struct twe_callbacks *tcb) 480 { 481 482 sc->sc_units[unit].td_callbacks = tcb; 483 } 484 485 static void 486 twe_recompute_openings(struct twe_softc *sc) 487 { 488 struct twe_drive *td; 489 int unit, openings; 490 491 if (sc->sc_nunits != 0) 492 openings = (TWE_MAX_QUEUECNT - 1) / sc->sc_nunits; 493 else 494 openings = 0; 495 if (openings == sc->sc_openings) 496 return; 497 sc->sc_openings = openings; 498 499 #ifdef TWE_DEBUG 500 printf("%s: %d array%s, %d openings per array\n", 501 sc->sc_dv.dv_xname, sc->sc_nunits, 502 sc->sc_nunits == 1 ? "" : "s", sc->sc_openings); 503 #endif 504 505 for (unit = 0; unit < TWE_MAX_UNITS; unit++) { 506 td = &sc->sc_units[unit]; 507 if (td->td_dev != NULL) 508 (*td->td_callbacks->tcb_openings)(td->td_dev, 509 sc->sc_openings); 510 } 511 } 512 513 static int 514 twe_add_unit(struct twe_softc *sc, int unit) 515 { 516 struct twe_param *dtp, *atp; 517 struct twe_array_descriptor *ad; 518 struct twe_drive *td; 519 struct twe_attach_args twea; 520 uint32_t newsize; 521 int rv; 522 uint16_t dsize; 523 uint8_t newtype, newstripe; 524 int help[2]; 525 locdesc_t *ldesc = (void *)help; /* XXX */ 526 527 if (unit < 0 || unit >= TWE_MAX_UNITS) 528 return (EINVAL); 529 530 /* Find attached units. */ 531 rv = twe_param_get(sc, TWE_PARAM_UNITSUMMARY, 532 TWE_PARAM_UNITSUMMARY_Status, TWE_MAX_UNITS, NULL, &dtp); 533 if (rv != 0) { 534 aprint_error("%s: error %d fetching unit summary\n", 535 sc->sc_dv.dv_xname, rv); 536 return (rv); 537 } 538 539 /* For each detected unit, collect size and store in an array. */ 540 td = &sc->sc_units[unit]; 541 542 /* Unit present? */ 543 if ((dtp->tp_data[unit] & TWE_PARAM_UNITSTATUS_Online) == 0) { 544 /* 545 * XXX Should we check to see if a device has been 546 * XXX attached at this index and detach it if it 547 * XXX has? ("rescan" semantics) 548 */ 549 rv = 0; 550 goto out; 551 } 552 553 rv = twe_param_get_2(sc, TWE_PARAM_UNITINFO + unit, 554 TWE_PARAM_UNITINFO_DescriptorSize, &dsize); 555 if (rv != 0) { 556 aprint_error("%s: error %d fetching descriptor size " 557 "for unit %d\n", sc->sc_dv.dv_xname, rv, unit); 558 goto out; 559 } 560 561 rv = twe_param_get(sc, TWE_PARAM_UNITINFO + unit, 562 TWE_PARAM_UNITINFO_Descriptor, dsize - 3, NULL, &atp); 563 if (rv != 0) { 564 aprint_error("%s: error %d fetching array descriptor " 565 "for unit %d\n", sc->sc_dv.dv_xname, rv, unit); 566 goto out; 567 } 568 569 ad = (struct twe_array_descriptor *)atp->tp_data; 570 newtype = ad->configuration; 571 newstripe = ad->stripe_size; 572 free(atp, M_DEVBUF); 573 574 rv = twe_param_get_4(sc, TWE_PARAM_UNITINFO + unit, 575 TWE_PARAM_UNITINFO_Capacity, &newsize); 576 if (rv != 0) { 577 aprint_error( 578 "%s: error %d fetching capacity for unit %d\n", 579 sc->sc_dv.dv_xname, rv, unit); 580 goto out; 581 } 582 583 /* 584 * Have a device, so we need to attach it. If there is currently 585 * something sitting at the slot, and the parameters are different, 586 * then we detach the old device before attaching the new one. 587 */ 588 if (td->td_dev != NULL && 589 td->td_size == newsize && 590 td->td_type == newtype && 591 td->td_stripe == newstripe) { 592 /* Same as the old device; just keep using it. */ 593 rv = 0; 594 goto out; 595 } else if (td->td_dev != NULL) { 596 /* Detach the old device first. */ 597 (void) config_detach(td->td_dev, DETACH_FORCE); 598 td->td_dev = NULL; 599 } else if (td->td_size == 0) 600 sc->sc_nunits++; 601 602 /* 603 * Committed to the new array unit; assign its parameters and 604 * recompute the number of available command openings. 605 */ 606 td->td_size = newsize; 607 td->td_type = newtype; 608 td->td_stripe = newstripe; 609 twe_recompute_openings(sc); 610 611 twea.twea_unit = unit; 612 613 ldesc->len = 1; 614 ldesc->locs[TWECF_UNIT] = unit; 615 616 td->td_dev = config_found_sm_loc(&sc->sc_dv, "twe", NULL, &twea, 617 twe_print, twe_submatch); 618 619 rv = 0; 620 out: 621 free(dtp, M_DEVBUF); 622 return (rv); 623 } 624 625 static int 626 twe_del_unit(struct twe_softc *sc, int unit) 627 { 628 struct twe_drive *td; 629 630 if (unit < 0 || unit >= TWE_MAX_UNITS) 631 return (EINVAL); 632 633 td = &sc->sc_units[unit]; 634 if (td->td_size != 0) 635 sc->sc_nunits--; 636 td->td_size = 0; 637 td->td_type = 0; 638 td->td_stripe = 0; 639 if (td->td_dev != NULL) { 640 (void) config_detach(td->td_dev, DETACH_FORCE); 641 td->td_dev = NULL; 642 } 643 twe_recompute_openings(sc); 644 return (0); 645 } 646 647 /* 648 * Reset the controller. 649 * MUST BE CALLED AT splbio()! 650 */ 651 static int 652 twe_reset(struct twe_softc *sc) 653 { 654 uint16_t aen; 655 u_int status; 656 volatile u_int32_t junk; 657 int got, rv; 658 659 /* Issue a soft reset. */ 660 twe_outl(sc, TWE_REG_CTL, TWE_CTL_ISSUE_SOFT_RESET | 661 TWE_CTL_CLEAR_HOST_INTR | 662 TWE_CTL_CLEAR_ATTN_INTR | 663 TWE_CTL_MASK_CMD_INTR | 664 TWE_CTL_MASK_RESP_INTR | 665 TWE_CTL_CLEAR_ERROR_STS | 666 TWE_CTL_DISABLE_INTRS); 667 668 /* Wait for attention... */ 669 if (twe_status_wait(sc, TWE_STS_ATTN_INTR, 30)) { 670 printf("%s: timeout waiting for attention interrupt\n", 671 sc->sc_dv.dv_xname); 672 return (-1); 673 } 674 675 /* ...and ACK it. */ 676 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 677 678 /* 679 * Pull AENs out of the controller; look for a soft reset AEN. 680 * Open code this, since we want to detect reset even if the 681 * queue for management tools is full. 682 * 683 * Note that since: 684 * - interrupts are blocked 685 * - we have reset the controller 686 * - acknowledged the pending ATTENTION 687 * that there is no way a pending asynchronous AEN fetch would 688 * finish, so clear the flag. 689 */ 690 sc->sc_flags &= ~TWEF_AEN; 691 for (got = 0;;) { 692 rv = twe_aen_get(sc, &aen); 693 if (rv != 0) 694 printf("%s: error %d while draining event queue\n", 695 sc->sc_dv.dv_xname, rv); 696 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) 697 break; 698 if (TWE_AEN_CODE(aen) == TWE_AEN_SOFT_RESET) 699 got = 1; 700 twe_aen_enqueue(sc, aen, 1); 701 } 702 703 if (!got) { 704 printf("%s: reset not reported\n", sc->sc_dv.dv_xname); 705 return (-1); 706 } 707 708 /* Check controller status. */ 709 status = twe_inl(sc, TWE_REG_STS); 710 if (twe_status_check(sc, status)) { 711 printf("%s: controller errors detected\n", 712 sc->sc_dv.dv_xname); 713 return (-1); 714 } 715 716 /* Drain the response queue. */ 717 for (;;) { 718 status = twe_inl(sc, TWE_REG_STS); 719 if (twe_status_check(sc, status) != 0) { 720 printf("%s: can't drain response queue\n", 721 sc->sc_dv.dv_xname); 722 return (-1); 723 } 724 if ((status & TWE_STS_RESP_QUEUE_EMPTY) != 0) 725 break; 726 junk = twe_inl(sc, TWE_REG_RESP_QUEUE); 727 } 728 729 return (0); 730 } 731 732 /* 733 * Print autoconfiguration message for a sub-device. 734 */ 735 static int 736 twe_print(void *aux, const char *pnp) 737 { 738 struct twe_attach_args *twea; 739 740 twea = aux; 741 742 if (pnp != NULL) 743 aprint_normal("block device at %s", pnp); 744 aprint_normal(" unit %d", twea->twea_unit); 745 return (UNCONF); 746 } 747 748 /* 749 * Match a sub-device. 750 */ 751 static int 752 twe_submatch(struct device *parent, struct cfdata *cf, 753 const locdesc_t *ldesc, void *aux) 754 { 755 756 if (cf->cf_loc[TWECF_UNIT] != TWECF_UNIT_DEFAULT && 757 cf->cf_loc[TWECF_UNIT] != ldesc->locs[TWECF_UNIT]) 758 return (0); 759 760 return (config_match(parent, cf, aux)); 761 } 762 763 /* 764 * Interrupt service routine. 765 */ 766 static int 767 twe_intr(void *arg) 768 { 769 struct twe_softc *sc; 770 u_int status; 771 int caught, rv; 772 773 sc = arg; 774 caught = 0; 775 status = twe_inl(sc, TWE_REG_STS); 776 twe_status_check(sc, status); 777 778 /* Host interrupts - purpose unknown. */ 779 if ((status & TWE_STS_HOST_INTR) != 0) { 780 #ifdef DEBUG 781 printf("%s: host interrupt\n", sc->sc_dv.dv_xname); 782 #endif 783 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_HOST_INTR); 784 caught = 1; 785 } 786 787 /* 788 * Attention interrupts, signalled when a controller or child device 789 * state change has occurred. 790 */ 791 if ((status & TWE_STS_ATTN_INTR) != 0) { 792 rv = twe_aen_get(sc, NULL); 793 if (rv != 0) 794 printf("%s: unable to retrieve AEN (%d)\n", 795 sc->sc_dv.dv_xname, rv); 796 else 797 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 798 caught = 1; 799 } 800 801 /* 802 * Command interrupts, signalled when the controller can accept more 803 * commands. We don't use this; instead, we try to submit commands 804 * when we receive them, and when other commands have completed. 805 * Mask it so we don't get another one. 806 */ 807 if ((status & TWE_STS_CMD_INTR) != 0) { 808 #ifdef DEBUG 809 printf("%s: command interrupt\n", sc->sc_dv.dv_xname); 810 #endif 811 twe_outl(sc, TWE_REG_CTL, TWE_CTL_MASK_CMD_INTR); 812 caught = 1; 813 } 814 815 if ((status & TWE_STS_RESP_INTR) != 0) { 816 twe_poll(sc); 817 caught = 1; 818 } 819 820 return (caught); 821 } 822 823 /* 824 * Fetch an AEN. Even though this is really like parameter 825 * retrieval, we handle this specially, because we issue this 826 * AEN retrieval command from interrupt context, and thus 827 * reserve a CCB for it to avoid resource shortage. 828 * 829 * XXX There are still potential resource shortages we could 830 * XXX encounter. Consider pre-allocating all AEN-related 831 * XXX resources. 832 * 833 * MUST BE CALLED AT splbio()! 834 */ 835 static int 836 twe_aen_get(struct twe_softc *sc, uint16_t *aenp) 837 { 838 struct twe_ccb *ccb; 839 struct twe_cmd *tc; 840 struct twe_param *tp; 841 int rv; 842 843 /* 844 * If we're already retrieving an AEN, just wait; another 845 * retrieval will be chained after the current one completes. 846 */ 847 if (sc->sc_flags & TWEF_AEN) { 848 /* 849 * It is a fatal software programming error to attempt 850 * to fetch an AEN synchronously when an AEN fetch is 851 * already pending. 852 */ 853 KASSERT(aenp == NULL); 854 return (0); 855 } 856 857 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 858 if (tp == NULL) 859 return (ENOMEM); 860 861 ccb = twe_ccb_alloc(sc, 862 TWE_CCB_AEN | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 863 KASSERT(ccb != NULL); 864 865 ccb->ccb_data = tp; 866 ccb->ccb_datasize = TWE_SECTOR_SIZE; 867 ccb->ccb_tx.tx_handler = (aenp == NULL) ? twe_aen_handler : NULL; 868 ccb->ccb_tx.tx_context = tp; 869 ccb->ccb_tx.tx_dv = &sc->sc_dv; 870 871 tc = ccb->ccb_cmd; 872 tc->tc_size = 2; 873 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 874 tc->tc_unit = 0; 875 tc->tc_count = htole16(1); 876 877 /* Fill in the outbound parameter data. */ 878 tp->tp_table_id = htole16(TWE_PARAM_AEN); 879 tp->tp_param_id = TWE_PARAM_AEN_UnitCode; 880 tp->tp_param_size = 2; 881 882 /* Map the transfer. */ 883 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 884 twe_ccb_free(sc, ccb); 885 goto done; 886 } 887 888 /* Enqueue the command and wait. */ 889 if (aenp != NULL) { 890 rv = twe_ccb_poll(sc, ccb, 5); 891 twe_ccb_unmap(sc, ccb); 892 twe_ccb_free(sc, ccb); 893 if (rv == 0) 894 *aenp = le16toh(*(uint16_t *)tp->tp_data); 895 free(tp, M_DEVBUF); 896 } else { 897 sc->sc_flags |= TWEF_AEN; 898 twe_ccb_enqueue(sc, ccb); 899 rv = 0; 900 } 901 902 done: 903 return (rv); 904 } 905 906 /* 907 * Handle an AEN returned by the controller. 908 * MUST BE CALLED AT splbio()! 909 */ 910 static void 911 twe_aen_handler(struct twe_ccb *ccb, int error) 912 { 913 struct twe_softc *sc; 914 struct twe_param *tp; 915 uint16_t aen; 916 int rv; 917 918 sc = (struct twe_softc *)ccb->ccb_tx.tx_dv; 919 tp = ccb->ccb_tx.tx_context; 920 twe_ccb_unmap(sc, ccb); 921 922 sc->sc_flags &= ~TWEF_AEN; 923 924 if (error) { 925 printf("%s: error retrieving AEN\n", sc->sc_dv.dv_xname); 926 aen = TWE_AEN_QUEUE_EMPTY; 927 } else 928 aen = le16toh(*(u_int16_t *)tp->tp_data); 929 free(tp, M_DEVBUF); 930 twe_ccb_free(sc, ccb); 931 932 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) { 933 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 934 return; 935 } 936 937 twe_aen_enqueue(sc, aen, 0); 938 939 /* 940 * Chain another retrieval in case interrupts have been 941 * coalesced. 942 */ 943 rv = twe_aen_get(sc, NULL); 944 if (rv != 0) 945 printf("%s: unable to retrieve AEN (%d)\n", 946 sc->sc_dv.dv_xname, rv); 947 } 948 949 static void 950 twe_aen_enqueue(struct twe_softc *sc, uint16_t aen, int quiet) 951 { 952 const char *str, *msg; 953 int s, next, nextnext, level; 954 955 /* 956 * First report the AEN on the console. Maybe. 957 */ 958 if (! quiet) { 959 str = twe_describe_code(twe_table_aen, TWE_AEN_CODE(aen)); 960 if (str == NULL) { 961 printf("%s: unknown AEN 0x%04x\n", 962 sc->sc_dv.dv_xname, aen); 963 } else { 964 msg = str + 3; 965 switch (str[1]) { 966 case 'E': level = LOG_EMERG; break; 967 case 'a': level = LOG_ALERT; break; 968 case 'c': level = LOG_CRIT; break; 969 case 'e': level = LOG_ERR; break; 970 case 'w': level = LOG_WARNING; break; 971 case 'n': level = LOG_NOTICE; break; 972 case 'i': level = LOG_INFO; break; 973 case 'd': level = LOG_DEBUG; break; 974 default: 975 /* Don't use syslog. */ 976 level = -1; 977 } 978 979 if (level < 0) { 980 switch (str[0]) { 981 case 'u': 982 case 'p': 983 printf("%s: %s %d: %s\n", 984 sc->sc_dv.dv_xname, 985 str[0] == 'u' ? "unit" : "port", 986 TWE_AEN_UNIT(aen), msg); 987 break; 988 989 default: 990 printf("%s: %s\n", 991 sc->sc_dv.dv_xname, msg); 992 } 993 } else { 994 switch (str[0]) { 995 case 'u': 996 case 'p': 997 log(level, "%s: %s %d: %s\n", 998 sc->sc_dv.dv_xname, 999 str[0] == 'u' ? "unit" : "port", 1000 TWE_AEN_UNIT(aen), msg); 1001 break; 1002 1003 default: 1004 log(level, "%s: %s\n", 1005 sc->sc_dv.dv_xname, msg); 1006 } 1007 } 1008 } 1009 } 1010 1011 /* Now enqueue the AEN for mangement tools. */ 1012 s = splbio(); 1013 1014 next = (sc->sc_aen_head + 1) % TWE_AEN_Q_LENGTH; 1015 nextnext = (sc->sc_aen_head + 2) % TWE_AEN_Q_LENGTH; 1016 1017 /* 1018 * If this is the last free slot, then queue up a "queue 1019 * full" message. 1020 */ 1021 if (nextnext == sc->sc_aen_tail) 1022 aen = TWE_AEN_QUEUE_FULL; 1023 1024 if (next != sc->sc_aen_tail) { 1025 sc->sc_aen_queue[sc->sc_aen_head] = aen; 1026 sc->sc_aen_head = next; 1027 } 1028 1029 if (sc->sc_flags & TWEF_AENQ_WAIT) { 1030 sc->sc_flags &= ~TWEF_AENQ_WAIT; 1031 wakeup(&sc->sc_aen_queue); 1032 } 1033 1034 splx(s); 1035 } 1036 1037 /* NOTE: Must be called at splbio(). */ 1038 static uint16_t 1039 twe_aen_dequeue(struct twe_softc *sc) 1040 { 1041 uint16_t aen; 1042 1043 if (sc->sc_aen_tail == sc->sc_aen_head) 1044 aen = TWE_AEN_QUEUE_EMPTY; 1045 else { 1046 aen = sc->sc_aen_queue[sc->sc_aen_tail]; 1047 sc->sc_aen_tail = (sc->sc_aen_tail + 1) % TWE_AEN_Q_LENGTH; 1048 } 1049 1050 return (aen); 1051 } 1052 1053 /* 1054 * These are short-hand functions that execute TWE_OP_GET_PARAM to 1055 * fetch 1, 2, and 4 byte parameter values, respectively. 1056 */ 1057 int 1058 twe_param_get_1(struct twe_softc *sc, int table_id, int param_id, 1059 uint8_t *valp) 1060 { 1061 struct twe_param *tp; 1062 int rv; 1063 1064 rv = twe_param_get(sc, table_id, param_id, 1, NULL, &tp); 1065 if (rv != 0) 1066 return (rv); 1067 *valp = *(uint8_t *)tp->tp_data; 1068 free(tp, M_DEVBUF); 1069 return (0); 1070 } 1071 1072 int 1073 twe_param_get_2(struct twe_softc *sc, int table_id, int param_id, 1074 uint16_t *valp) 1075 { 1076 struct twe_param *tp; 1077 int rv; 1078 1079 rv = twe_param_get(sc, table_id, param_id, 2, NULL, &tp); 1080 if (rv != 0) 1081 return (rv); 1082 *valp = le16toh(*(uint16_t *)tp->tp_data); 1083 free(tp, M_DEVBUF); 1084 return (0); 1085 } 1086 1087 int 1088 twe_param_get_4(struct twe_softc *sc, int table_id, int param_id, 1089 uint32_t *valp) 1090 { 1091 struct twe_param *tp; 1092 int rv; 1093 1094 rv = twe_param_get(sc, table_id, param_id, 4, NULL, &tp); 1095 if (rv != 0) 1096 return (rv); 1097 *valp = le32toh(*(uint32_t *)tp->tp_data); 1098 free(tp, M_DEVBUF); 1099 return (0); 1100 } 1101 1102 /* 1103 * Execute a TWE_OP_GET_PARAM command. If a callback function is provided, 1104 * it will be called with generated context when the command has completed. 1105 * If no callback is provided, the command will be executed synchronously 1106 * and a pointer to a buffer containing the data returned. 1107 * 1108 * The caller or callback is responsible for freeing the buffer. 1109 * 1110 * NOTE: We assume we can sleep here to wait for a CCB to become available. 1111 */ 1112 int 1113 twe_param_get(struct twe_softc *sc, int table_id, int param_id, size_t size, 1114 void (*func)(struct twe_ccb *, int), struct twe_param **pbuf) 1115 { 1116 struct twe_ccb *ccb; 1117 struct twe_cmd *tc; 1118 struct twe_param *tp; 1119 int rv, s; 1120 1121 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 1122 if (tp == NULL) 1123 return ENOMEM; 1124 1125 ccb = twe_ccb_alloc_wait(sc, TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1126 KASSERT(ccb != NULL); 1127 1128 ccb->ccb_data = tp; 1129 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1130 ccb->ccb_tx.tx_handler = func; 1131 ccb->ccb_tx.tx_context = tp; 1132 ccb->ccb_tx.tx_dv = &sc->sc_dv; 1133 1134 tc = ccb->ccb_cmd; 1135 tc->tc_size = 2; 1136 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 1137 tc->tc_unit = 0; 1138 tc->tc_count = htole16(1); 1139 1140 /* Fill in the outbound parameter data. */ 1141 tp->tp_table_id = htole16(table_id); 1142 tp->tp_param_id = param_id; 1143 tp->tp_param_size = size; 1144 1145 /* Map the transfer. */ 1146 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 1147 twe_ccb_free(sc, ccb); 1148 goto done; 1149 } 1150 1151 /* Submit the command and either wait or let the callback handle it. */ 1152 if (func == NULL) { 1153 s = splbio(); 1154 rv = twe_ccb_poll(sc, ccb, 5); 1155 twe_ccb_unmap(sc, ccb); 1156 twe_ccb_free(sc, ccb); 1157 splx(s); 1158 } else { 1159 #ifdef DEBUG 1160 if (pbuf != NULL) 1161 panic("both func and pbuf defined"); 1162 #endif 1163 twe_ccb_enqueue(sc, ccb); 1164 return 0; 1165 } 1166 1167 done: 1168 if (pbuf == NULL || rv != 0) 1169 free(tp, M_DEVBUF); 1170 else if (pbuf != NULL && rv == 0) 1171 *pbuf = tp; 1172 return rv; 1173 } 1174 1175 /* 1176 * Execute a TWE_OP_SET_PARAM command. 1177 * 1178 * NOTE: We assume we can sleep here to wait for a CCB to become available. 1179 */ 1180 static int 1181 twe_param_set(struct twe_softc *sc, int table_id, int param_id, size_t size, 1182 void *buf) 1183 { 1184 struct twe_ccb *ccb; 1185 struct twe_cmd *tc; 1186 struct twe_param *tp; 1187 int rv, s; 1188 1189 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 1190 if (tp == NULL) 1191 return ENOMEM; 1192 1193 ccb = twe_ccb_alloc_wait(sc, TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1194 KASSERT(ccb != NULL); 1195 1196 ccb->ccb_data = tp; 1197 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1198 ccb->ccb_tx.tx_handler = 0; 1199 ccb->ccb_tx.tx_context = tp; 1200 ccb->ccb_tx.tx_dv = &sc->sc_dv; 1201 1202 tc = ccb->ccb_cmd; 1203 tc->tc_size = 2; 1204 tc->tc_opcode = TWE_OP_SET_PARAM | (tc->tc_size << 5); 1205 tc->tc_unit = 0; 1206 tc->tc_count = htole16(1); 1207 1208 /* Fill in the outbound parameter data. */ 1209 tp->tp_table_id = htole16(table_id); 1210 tp->tp_param_id = param_id; 1211 tp->tp_param_size = size; 1212 memcpy(tp->tp_data, buf, size); 1213 1214 /* Map the transfer. */ 1215 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 1216 twe_ccb_free(sc, ccb); 1217 goto done; 1218 } 1219 1220 /* Submit the command and wait. */ 1221 s = splbio(); 1222 rv = twe_ccb_poll(sc, ccb, 5); 1223 twe_ccb_unmap(sc, ccb); 1224 twe_ccb_free(sc, ccb); 1225 splx(s); 1226 done: 1227 free(tp, M_DEVBUF); 1228 return (rv); 1229 } 1230 1231 /* 1232 * Execute a TWE_OP_INIT_CONNECTION command. Return non-zero on error. 1233 * Must be called with interrupts blocked. 1234 */ 1235 static int 1236 twe_init_connection(struct twe_softc *sc) 1237 /*###762 [cc] warning: `twe_init_connection' was used with no prototype before its definition%%%*/ 1238 /*###762 [cc] warning: `twe_init_connection' was declared implicitly `extern' and later `static'%%%*/ 1239 { 1240 struct twe_ccb *ccb; 1241 struct twe_cmd *tc; 1242 int rv; 1243 1244 if ((ccb = twe_ccb_alloc(sc, 0)) == NULL) 1245 return (EAGAIN); 1246 1247 /* Build the command. */ 1248 tc = ccb->ccb_cmd; 1249 tc->tc_size = 3; 1250 tc->tc_opcode = TWE_OP_INIT_CONNECTION; 1251 tc->tc_unit = 0; 1252 tc->tc_count = htole16(TWE_MAX_CMDS); 1253 tc->tc_args.init_connection.response_queue_pointer = 0; 1254 1255 /* Submit the command for immediate execution. */ 1256 rv = twe_ccb_poll(sc, ccb, 5); 1257 twe_ccb_free(sc, ccb); 1258 return (rv); 1259 } 1260 1261 /* 1262 * Poll the controller for completed commands. Must be called with 1263 * interrupts blocked. 1264 */ 1265 static void 1266 twe_poll(struct twe_softc *sc) 1267 { 1268 struct twe_ccb *ccb; 1269 int found; 1270 u_int status, cmdid; 1271 1272 found = 0; 1273 1274 for (;;) { 1275 status = twe_inl(sc, TWE_REG_STS); 1276 twe_status_check(sc, status); 1277 1278 if ((status & TWE_STS_RESP_QUEUE_EMPTY)) 1279 break; 1280 1281 found = 1; 1282 cmdid = twe_inl(sc, TWE_REG_RESP_QUEUE); 1283 cmdid = (cmdid & TWE_RESP_MASK) >> TWE_RESP_SHIFT; 1284 if (cmdid >= TWE_MAX_QUEUECNT) { 1285 printf("%s: bad cmdid %d\n", sc->sc_dv.dv_xname, cmdid); 1286 continue; 1287 } 1288 1289 ccb = sc->sc_ccbs + cmdid; 1290 if ((ccb->ccb_flags & TWE_CCB_ACTIVE) == 0) { 1291 printf("%s: CCB for cmdid %d not active\n", 1292 sc->sc_dv.dv_xname, cmdid); 1293 continue; 1294 } 1295 ccb->ccb_flags ^= TWE_CCB_COMPLETE | TWE_CCB_ACTIVE; 1296 1297 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1298 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, 1299 sizeof(struct twe_cmd), 1300 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1301 1302 /* Pass notification to upper layers. */ 1303 if (ccb->ccb_tx.tx_handler != NULL) 1304 (*ccb->ccb_tx.tx_handler)(ccb, 1305 ccb->ccb_cmd->tc_status != 0 ? EIO : 0); 1306 } 1307 1308 /* If any commands have completed, run the software queue. */ 1309 if (found) 1310 twe_ccb_enqueue(sc, NULL); 1311 } 1312 1313 /* 1314 * Wait for `status' to be set in the controller status register. Return 1315 * zero if found, non-zero if the operation timed out. 1316 */ 1317 static int 1318 twe_status_wait(struct twe_softc *sc, u_int32_t status, int timo) 1319 { 1320 1321 for (timo *= 10; timo != 0; timo--) { 1322 if ((twe_inl(sc, TWE_REG_STS) & status) == status) 1323 break; 1324 delay(100000); 1325 } 1326 1327 return (timo == 0); 1328 } 1329 1330 /* 1331 * Complain if the status bits aren't what we expect. 1332 */ 1333 static int 1334 twe_status_check(struct twe_softc *sc, u_int status) 1335 { 1336 int rv; 1337 1338 rv = 0; 1339 1340 if ((status & TWE_STS_EXPECTED_BITS) != TWE_STS_EXPECTED_BITS) { 1341 printf("%s: missing status bits: 0x%08x\n", sc->sc_dv.dv_xname, 1342 status & ~TWE_STS_EXPECTED_BITS); 1343 rv = -1; 1344 } 1345 1346 if ((status & TWE_STS_UNEXPECTED_BITS) != 0) { 1347 printf("%s: unexpected status bits: 0x%08x\n", 1348 sc->sc_dv.dv_xname, status & TWE_STS_UNEXPECTED_BITS); 1349 rv = -1; 1350 } 1351 1352 return (rv); 1353 } 1354 1355 /* 1356 * Allocate and initialise a CCB. 1357 */ 1358 static __inline void 1359 twe_ccb_init(struct twe_softc *sc, struct twe_ccb *ccb, int flags) 1360 { 1361 struct twe_cmd *tc; 1362 1363 ccb->ccb_tx.tx_handler = NULL; 1364 ccb->ccb_flags = flags; 1365 tc = ccb->ccb_cmd; 1366 tc->tc_status = 0; 1367 tc->tc_flags = 0; 1368 tc->tc_cmdid = ccb->ccb_cmdid; 1369 } 1370 1371 struct twe_ccb * 1372 twe_ccb_alloc(struct twe_softc *sc, int flags) 1373 { 1374 struct twe_ccb *ccb; 1375 int s; 1376 1377 s = splbio(); 1378 if (__predict_false((flags & TWE_CCB_AEN) != 0)) { 1379 /* Use the reserved CCB. */ 1380 ccb = sc->sc_ccbs; 1381 } else { 1382 /* Allocate a CCB and command block. */ 1383 if (__predict_false((ccb = 1384 SLIST_FIRST(&sc->sc_ccb_freelist)) == NULL)) { 1385 splx(s); 1386 return (NULL); 1387 } 1388 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 1389 } 1390 #ifdef DIAGNOSTIC 1391 if ((long)(ccb - sc->sc_ccbs) == 0 && (flags & TWE_CCB_AEN) == 0) 1392 panic("twe_ccb_alloc: got reserved CCB for non-AEN"); 1393 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 1394 panic("twe_ccb_alloc: CCB %ld already allocated", 1395 (long)(ccb - sc->sc_ccbs)); 1396 flags |= TWE_CCB_ALLOCED; 1397 #endif 1398 splx(s); 1399 1400 twe_ccb_init(sc, ccb, flags); 1401 return (ccb); 1402 } 1403 1404 struct twe_ccb * 1405 twe_ccb_alloc_wait(struct twe_softc *sc, int flags) 1406 { 1407 struct twe_ccb *ccb; 1408 int s; 1409 1410 KASSERT((flags & TWE_CCB_AEN) == 0); 1411 1412 s = splbio(); 1413 while (__predict_false((ccb = 1414 SLIST_FIRST(&sc->sc_ccb_freelist)) == NULL)) { 1415 sc->sc_flags |= TWEF_WAIT_CCB; 1416 (void) tsleep(&sc->sc_ccb_freelist, PRIBIO, "tweccb", 0); 1417 } 1418 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 1419 #ifdef DIAGNOSTIC 1420 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 1421 panic("twe_ccb_alloc_wait: CCB %ld already allocated", 1422 (long)(ccb - sc->sc_ccbs)); 1423 flags |= TWE_CCB_ALLOCED; 1424 #endif 1425 splx(s); 1426 1427 twe_ccb_init(sc, ccb, flags); 1428 return (ccb); 1429 } 1430 1431 /* 1432 * Free a CCB. 1433 */ 1434 void 1435 twe_ccb_free(struct twe_softc *sc, struct twe_ccb *ccb) 1436 { 1437 int s; 1438 1439 s = splbio(); 1440 if ((ccb->ccb_flags & TWE_CCB_AEN) == 0) { 1441 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, ccb_chain.slist); 1442 if (__predict_false((sc->sc_flags & TWEF_WAIT_CCB) != 0)) { 1443 sc->sc_flags &= ~TWEF_WAIT_CCB; 1444 wakeup(&sc->sc_ccb_freelist); 1445 } 1446 } 1447 ccb->ccb_flags = 0; 1448 splx(s); 1449 } 1450 1451 /* 1452 * Map the specified CCB's command block and data buffer (if any) into 1453 * controller visible space. Perform DMA synchronisation. 1454 */ 1455 int 1456 twe_ccb_map(struct twe_softc *sc, struct twe_ccb *ccb) 1457 { 1458 struct twe_cmd *tc; 1459 int flags, nsegs, i, s, rv; 1460 void *data; 1461 1462 /* 1463 * The data as a whole must be 512-byte aligned. 1464 */ 1465 if (((u_long)ccb->ccb_data & (TWE_ALIGNMENT - 1)) != 0) { 1466 s = splvm(); 1467 /* XXX */ 1468 ccb->ccb_abuf = uvm_km_kmemalloc(kmem_map, NULL, 1469 ccb->ccb_datasize, UVM_KMF_NOWAIT); 1470 splx(s); 1471 data = (void *)ccb->ccb_abuf; 1472 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1473 memcpy(data, ccb->ccb_data, ccb->ccb_datasize); 1474 } else { 1475 ccb->ccb_abuf = (vaddr_t)0; 1476 data = ccb->ccb_data; 1477 } 1478 1479 /* 1480 * Map the data buffer into bus space and build the S/G list. 1481 */ 1482 rv = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap_xfer, data, 1483 ccb->ccb_datasize, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1484 ((ccb->ccb_flags & TWE_CCB_DATA_IN) ? 1485 BUS_DMA_READ : BUS_DMA_WRITE)); 1486 if (rv != 0) { 1487 if (ccb->ccb_abuf != (vaddr_t)0) { 1488 s = splvm(); 1489 /* XXX */ 1490 uvm_km_free(kmem_map, ccb->ccb_abuf, 1491 ccb->ccb_datasize); 1492 splx(s); 1493 } 1494 return (rv); 1495 } 1496 1497 nsegs = ccb->ccb_dmamap_xfer->dm_nsegs; 1498 tc = ccb->ccb_cmd; 1499 tc->tc_size += 2 * nsegs; 1500 1501 /* The location of the S/G list is dependant upon command type. */ 1502 switch (tc->tc_opcode >> 5) { 1503 case 2: 1504 for (i = 0; i < nsegs; i++) { 1505 tc->tc_args.param.sgl[i].tsg_address = 1506 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 1507 tc->tc_args.param.sgl[i].tsg_length = 1508 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 1509 } 1510 /* XXX Needed? */ 1511 for (; i < TWE_SG_SIZE; i++) { 1512 tc->tc_args.param.sgl[i].tsg_address = 0; 1513 tc->tc_args.param.sgl[i].tsg_length = 0; 1514 } 1515 break; 1516 case 3: 1517 for (i = 0; i < nsegs; i++) { 1518 tc->tc_args.io.sgl[i].tsg_address = 1519 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 1520 tc->tc_args.io.sgl[i].tsg_length = 1521 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 1522 } 1523 /* XXX Needed? */ 1524 for (; i < TWE_SG_SIZE; i++) { 1525 tc->tc_args.io.sgl[i].tsg_address = 0; 1526 tc->tc_args.io.sgl[i].tsg_length = 0; 1527 } 1528 break; 1529 default: 1530 /* 1531 * In all likelihood, this is a command passed from 1532 * management tools in userspace where no S/G list is 1533 * necessary because no data is being passed. 1534 */ 1535 break; 1536 } 1537 1538 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1539 flags = BUS_DMASYNC_PREREAD; 1540 else 1541 flags = 0; 1542 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1543 flags |= BUS_DMASYNC_PREWRITE; 1544 1545 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 1546 ccb->ccb_datasize, flags); 1547 return (0); 1548 } 1549 1550 /* 1551 * Unmap the specified CCB's command block and data buffer (if any) and 1552 * perform DMA synchronisation. 1553 */ 1554 void 1555 twe_ccb_unmap(struct twe_softc *sc, struct twe_ccb *ccb) 1556 { 1557 int flags, s; 1558 1559 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1560 flags = BUS_DMASYNC_POSTREAD; 1561 else 1562 flags = 0; 1563 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1564 flags |= BUS_DMASYNC_POSTWRITE; 1565 1566 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 1567 ccb->ccb_datasize, flags); 1568 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap_xfer); 1569 1570 if (ccb->ccb_abuf != (vaddr_t)0) { 1571 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1572 memcpy(ccb->ccb_data, (void *)ccb->ccb_abuf, 1573 ccb->ccb_datasize); 1574 s = splvm(); 1575 /* XXX */ 1576 uvm_km_free(kmem_map, ccb->ccb_abuf, ccb->ccb_datasize); 1577 splx(s); 1578 } 1579 } 1580 1581 /* 1582 * Submit a command to the controller and poll on completion. Return 1583 * non-zero on timeout (but don't check status, as some command types don't 1584 * return status). Must be called with interrupts blocked. 1585 */ 1586 int 1587 twe_ccb_poll(struct twe_softc *sc, struct twe_ccb *ccb, int timo) 1588 { 1589 int rv; 1590 1591 if ((rv = twe_ccb_submit(sc, ccb)) != 0) 1592 return (rv); 1593 1594 for (timo *= 1000; timo != 0; timo--) { 1595 twe_poll(sc); 1596 if ((ccb->ccb_flags & TWE_CCB_COMPLETE) != 0) 1597 break; 1598 DELAY(100); 1599 } 1600 1601 return (timo == 0); 1602 } 1603 1604 /* 1605 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1606 * the order that they were enqueued and try to submit their command blocks 1607 * to the controller for execution. 1608 */ 1609 void 1610 twe_ccb_enqueue(struct twe_softc *sc, struct twe_ccb *ccb) 1611 { 1612 int s; 1613 1614 s = splbio(); 1615 1616 if (ccb != NULL) 1617 SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 1618 1619 while ((ccb = SIMPLEQ_FIRST(&sc->sc_ccb_queue)) != NULL) { 1620 if (twe_ccb_submit(sc, ccb)) 1621 break; 1622 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_queue, ccb_chain.simpleq); 1623 } 1624 1625 splx(s); 1626 } 1627 1628 /* 1629 * Submit the command block associated with the specified CCB to the 1630 * controller for execution. Must be called with interrupts blocked. 1631 */ 1632 int 1633 twe_ccb_submit(struct twe_softc *sc, struct twe_ccb *ccb) 1634 { 1635 bus_addr_t pa; 1636 int rv; 1637 u_int status; 1638 1639 /* Check to see if we can post a command. */ 1640 status = twe_inl(sc, TWE_REG_STS); 1641 twe_status_check(sc, status); 1642 1643 if ((status & TWE_STS_CMD_QUEUE_FULL) == 0) { 1644 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1645 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, sizeof(struct twe_cmd), 1646 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1647 #ifdef DIAGNOSTIC 1648 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) == 0) 1649 panic("%s: CCB %ld not ALLOCED\n", 1650 sc->sc_dv.dv_xname, (long)(ccb - sc->sc_ccbs)); 1651 #endif 1652 ccb->ccb_flags |= TWE_CCB_ACTIVE; 1653 pa = sc->sc_cmds_paddr + 1654 ccb->ccb_cmdid * sizeof(struct twe_cmd); 1655 twe_outl(sc, TWE_REG_CMD_QUEUE, (u_int32_t)pa); 1656 rv = 0; 1657 } else 1658 rv = EBUSY; 1659 1660 return (rv); 1661 } 1662 1663 1664 /* 1665 * Accept an open operation on the control device. 1666 */ 1667 int 1668 tweopen(dev_t dev, int flag, int mode, struct lwp *l) 1669 { 1670 struct twe_softc *twe; 1671 1672 if ((twe = device_lookup(&twe_cd, minor(dev))) == NULL) 1673 return (ENXIO); 1674 if ((twe->sc_flags & TWEF_OPEN) != 0) 1675 return (EBUSY); 1676 1677 twe->sc_flags |= TWEF_OPEN; 1678 return (0); 1679 } 1680 1681 /* 1682 * Accept the last close on the control device. 1683 */ 1684 int 1685 tweclose(dev_t dev, int flag, int mode, struct lwp *l) 1686 { 1687 struct twe_softc *twe; 1688 1689 twe = device_lookup(&twe_cd, minor(dev)); 1690 twe->sc_flags &= ~TWEF_OPEN; 1691 return (0); 1692 } 1693 1694 void 1695 twe_ccb_wait_handler(struct twe_ccb *ccb, int error) 1696 { 1697 1698 /* Just wake up the sleeper. */ 1699 wakeup(ccb); 1700 } 1701 1702 /* 1703 * Handle control operations. 1704 */ 1705 int 1706 tweioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct lwp *l) 1707 { 1708 struct twe_softc *twe; 1709 struct twe_ccb *ccb; 1710 struct twe_param *param; 1711 struct twe_usercommand *tu; 1712 struct twe_paramcommand *tp; 1713 struct twe_drivecommand *td; 1714 void *pdata = NULL; 1715 int s, error = 0; 1716 u_int8_t cmdid; 1717 1718 if (securelevel >= 2) 1719 return (EPERM); 1720 1721 twe = device_lookup(&twe_cd, minor(dev)); 1722 tu = (struct twe_usercommand *)data; 1723 tp = (struct twe_paramcommand *)data; 1724 td = (struct twe_drivecommand *)data; 1725 1726 /* This is intended to be compatible with the FreeBSD interface. */ 1727 switch (cmd) { 1728 case TWEIO_COMMAND: 1729 /* XXX mutex */ 1730 if (tu->tu_size > 0) { 1731 /* 1732 * XXX Handle > TWE_SECTOR_SIZE? Let's see if 1733 * it's really necessary, first. 1734 */ 1735 if (tu->tu_size > TWE_SECTOR_SIZE) { 1736 #ifdef TWE_DEBUG 1737 printf("%s: TWEIO_COMMAND: tu_size = %d\n", 1738 twe->sc_dv.dv_xname, tu->tu_size); 1739 #endif 1740 return EINVAL; 1741 } 1742 pdata = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_WAITOK); 1743 error = copyin(tu->tu_data, pdata, tu->tu_size); 1744 if (error != 0) 1745 goto done; 1746 ccb = twe_ccb_alloc_wait(twe, 1747 TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1748 KASSERT(ccb != NULL); 1749 ccb->ccb_data = pdata; 1750 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1751 } else { 1752 ccb = twe_ccb_alloc_wait(twe, 0); 1753 KASSERT(ccb != NULL); 1754 } 1755 1756 ccb->ccb_tx.tx_handler = twe_ccb_wait_handler; 1757 ccb->ccb_tx.tx_context = NULL; 1758 ccb->ccb_tx.tx_dv = &twe->sc_dv; 1759 1760 cmdid = ccb->ccb_cmdid; 1761 memcpy(ccb->ccb_cmd, &tu->tu_cmd, sizeof(struct twe_cmd)); 1762 ccb->ccb_cmd->tc_cmdid = cmdid; 1763 1764 /* Map the transfer. */ 1765 if ((error = twe_ccb_map(twe, ccb)) != 0) { 1766 twe_ccb_free(twe, ccb); 1767 goto done; 1768 } 1769 1770 /* Submit the command and wait up to 1 minute. */ 1771 error = 0; 1772 twe_ccb_enqueue(twe, ccb); 1773 s = splbio(); 1774 while ((ccb->ccb_flags & TWE_CCB_COMPLETE) == 0) 1775 if ((error = tsleep(ccb, PRIBIO, "tweioctl", 1776 60 * hz)) != 0) 1777 break; 1778 splx(s); 1779 1780 /* Copy the command back to the ioctl argument. */ 1781 memcpy(&tu->tu_cmd, ccb->ccb_cmd, sizeof(struct twe_cmd)); 1782 #ifdef TWE_DEBUG 1783 printf("%s: TWEIO_COMMAND: tc_opcode = 0x%02x, " 1784 "tc_status = 0x%02x\n", twe->sc_dv.dv_xname, 1785 tu->tu_cmd.tc_opcode, tu->tu_cmd.tc_status); 1786 #endif 1787 1788 s = splbio(); 1789 twe_ccb_free(twe, ccb); 1790 splx(s); 1791 1792 if (tu->tu_size > 0) 1793 error = copyout(pdata, tu->tu_data, tu->tu_size); 1794 goto done; 1795 1796 case TWEIO_STATS: 1797 return (ENOENT); 1798 1799 case TWEIO_AEN_POLL: 1800 s = splbio(); 1801 *(u_int *)data = twe_aen_dequeue(twe); 1802 splx(s); 1803 return (0); 1804 1805 case TWEIO_AEN_WAIT: 1806 s = splbio(); 1807 while ((*(u_int *)data = 1808 twe_aen_dequeue(twe)) == TWE_AEN_QUEUE_EMPTY) { 1809 twe->sc_flags |= TWEF_AENQ_WAIT; 1810 error = tsleep(&twe->sc_aen_queue, PRIBIO | PCATCH, 1811 "tweaen", 0); 1812 if (error == EINTR) { 1813 splx(s); 1814 return (error); 1815 } 1816 } 1817 splx(s); 1818 return (0); 1819 1820 case TWEIO_GET_PARAM: 1821 error = twe_param_get(twe, tp->tp_table_id, tp->tp_param_id, 1822 tp->tp_size, 0, ¶m); 1823 if (error != 0) 1824 return (error); 1825 if (param->tp_param_size > tp->tp_size) { 1826 error = EFAULT; 1827 goto done; 1828 } 1829 error = copyout(param->tp_data, tp->tp_data, 1830 param->tp_param_size); 1831 goto done; 1832 1833 case TWEIO_SET_PARAM: 1834 pdata = malloc(tp->tp_size, M_DEVBUF, M_WAITOK); 1835 if ((error = copyin(tp->tp_data, pdata, tp->tp_size)) != 0) 1836 goto done; 1837 error = twe_param_set(twe, tp->tp_table_id, tp->tp_param_id, 1838 tp->tp_size, pdata); 1839 goto done; 1840 1841 case TWEIO_RESET: 1842 s = splbio(); 1843 twe_reset(twe); 1844 splx(s); 1845 return (0); 1846 1847 case TWEIO_ADD_UNIT: 1848 /* XXX mutex */ 1849 return (twe_add_unit(twe, td->td_unit)); 1850 1851 case TWEIO_DEL_UNIT: 1852 /* XXX mutex */ 1853 return (twe_del_unit(twe, td->td_unit)); 1854 1855 default: 1856 return EINVAL; 1857 } 1858 done: 1859 if (pdata) 1860 free(pdata, M_DEVBUF); 1861 return error; 1862 } 1863 1864 /* 1865 * Print some information about the controller 1866 */ 1867 static void 1868 twe_describe_controller(struct twe_softc *sc) 1869 { 1870 struct twe_param *p[6]; 1871 int i, rv = 0; 1872 uint32_t dsize; 1873 uint8_t ports; 1874 1875 /* get the port count */ 1876 rv |= twe_param_get_1(sc, TWE_PARAM_CONTROLLER, 1877 TWE_PARAM_CONTROLLER_PortCount, &ports); 1878 1879 /* get version strings */ 1880 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_Mon, 1881 16, NULL, &p[0]); 1882 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_FW, 1883 16, NULL, &p[1]); 1884 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_BIOS, 1885 16, NULL, &p[2]); 1886 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_PCB, 1887 8, NULL, &p[3]); 1888 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_ATA, 1889 8, NULL, &p[4]); 1890 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_PCI, 1891 8, NULL, &p[5]); 1892 1893 if (rv) { 1894 /* some error occurred */ 1895 aprint_error("%s: failed to fetch version information\n", 1896 sc->sc_dv.dv_xname); 1897 return; 1898 } 1899 1900 aprint_normal("%s: %d ports, Firmware %.16s, BIOS %.16s\n", 1901 sc->sc_dv.dv_xname, ports, 1902 p[1]->tp_data, p[2]->tp_data); 1903 1904 aprint_verbose("%s: Monitor %.16s, PCB %.8s, Achip %.8s, Pchip %.8s\n", 1905 sc->sc_dv.dv_xname, 1906 p[0]->tp_data, p[3]->tp_data, 1907 p[4]->tp_data, p[5]->tp_data); 1908 1909 free(p[0], M_DEVBUF); 1910 free(p[1], M_DEVBUF); 1911 free(p[2], M_DEVBUF); 1912 free(p[3], M_DEVBUF); 1913 free(p[4], M_DEVBUF); 1914 free(p[5], M_DEVBUF); 1915 1916 rv = twe_param_get(sc, TWE_PARAM_DRIVESUMMARY, 1917 TWE_PARAM_DRIVESUMMARY_Status, 16, NULL, &p[0]); 1918 if (rv) { 1919 aprint_error("%s: failed to get drive status summary\n", 1920 sc->sc_dv.dv_xname); 1921 return; 1922 } 1923 for (i = 0; i < ports; i++) { 1924 if (p[0]->tp_data[i] != TWE_PARAM_DRIVESTATUS_Present) 1925 continue; 1926 rv = twe_param_get_4(sc, TWE_PARAM_DRIVEINFO + i, 1927 TWE_PARAM_DRIVEINFO_Size, &dsize); 1928 if (rv) { 1929 aprint_error( 1930 "%s: unable to get drive size for port %d\n", 1931 sc->sc_dv.dv_xname, i); 1932 continue; 1933 } 1934 rv = twe_param_get(sc, TWE_PARAM_DRIVEINFO + i, 1935 TWE_PARAM_DRIVEINFO_Model, 40, NULL, &p[1]); 1936 if (rv) { 1937 aprint_error( 1938 "%s: unable to get drive model for port %d\n", 1939 sc->sc_dv.dv_xname, i); 1940 continue; 1941 } 1942 aprint_verbose("%s: port %d: %.40s %d MB\n", sc->sc_dv.dv_xname, 1943 i, p[1]->tp_data, dsize / 2048); 1944 free(p[1], M_DEVBUF); 1945 } 1946 free(p[0], M_DEVBUF); 1947 } 1948
Indexes created Wed Oct 01 07:09:59 GMT 2025