twe.c revision 1.43
1 /* $NetBSD: twe.c,v 1.43 2003/09/21 19:27:27 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran; and by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twe.c,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 /* 69 * Driver for the 3ware Escalade family of RAID controllers. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: twe.c,v 1.43 2003/09/21 19:27:27 thorpej Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/device.h> 79 #include <sys/queue.h> 80 #include <sys/proc.h> 81 #include <sys/buf.h> 82 #include <sys/endian.h> 83 #include <sys/malloc.h> 84 #include <sys/conf.h> 85 #include <sys/disk.h> 86 87 #include <uvm/uvm_extern.h> 88 89 #include <machine/bswap.h> 90 #include <machine/bus.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/twereg.h> 96 #include <dev/pci/twevar.h> 97 #include <dev/pci/tweio.h> 98 99 #define PCI_CBIO 0x10 100 101 static void twe_aen_handler(struct twe_ccb *, int); 102 static void twe_attach(struct device *, struct device *, void *); 103 static int twe_init_connection(struct twe_softc *); 104 static int twe_intr(void *); 105 static int twe_match(struct device *, struct cfdata *, void *); 106 static int twe_param_set(struct twe_softc *, int, int, size_t, void *); 107 static void twe_poll(struct twe_softc *); 108 static int twe_print(void *, const char *); 109 static int twe_reset(struct twe_softc *); 110 static int twe_submatch(struct device *, struct cfdata *, void *); 111 static int twe_status_check(struct twe_softc *, u_int); 112 static int twe_status_wait(struct twe_softc *, u_int, int); 113 static void twe_describe_controller(struct twe_softc *); 114 115 static inline u_int32_t twe_inl(struct twe_softc *, int); 116 static inline void twe_outl(struct twe_softc *, int, u_int32_t); 117 118 dev_type_open(tweopen); 119 dev_type_close(tweclose); 120 dev_type_ioctl(tweioctl); 121 122 const struct cdevsw twe_cdevsw = { 123 tweopen, tweclose, noread, nowrite, tweioctl, 124 nostop, notty, nopoll, nommap, 125 }; 126 127 extern struct cfdriver twe_cd; 128 129 CFATTACH_DECL(twe, sizeof(struct twe_softc), 130 twe_match, twe_attach, NULL, NULL); 131 132 /* 133 * Tables to convert numeric codes to strings. 134 */ 135 const struct twe_code_table twe_table_status[] = { 136 { 0x00, "successful completion" }, 137 138 /* info */ 139 { 0x42, "command in progress" }, 140 { 0x6c, "retrying interface CRC error from UDMA command" }, 141 142 /* warning */ 143 { 0x81, "redundant/inconsequential request ignored" }, 144 { 0x8e, "failed to write zeroes to LBA 0" }, 145 { 0x8f, "failed to profile TwinStor zones" }, 146 147 /* fatal */ 148 { 0xc1, "aborted due to system command or reconfiguration" }, 149 { 0xc4, "aborted" }, 150 { 0xc5, "access error" }, 151 { 0xc6, "access violation" }, 152 { 0xc7, "device failure" }, /* high byte may be port # */ 153 { 0xc8, "controller error" }, 154 { 0xc9, "timed out" }, 155 { 0xcb, "invalid unit number" }, 156 { 0xcf, "unit not available" }, 157 { 0xd2, "undefined opcode" }, 158 { 0xdb, "request incompatible with unit" }, 159 { 0xdc, "invalid request" }, 160 { 0xff, "firmware error, reset requested" }, 161 162 { 0, NULL } 163 }; 164 165 const struct twe_code_table twe_table_unitstate[] = { 166 { TWE_PARAM_UNITSTATUS_Normal, "Normal" }, 167 { TWE_PARAM_UNITSTATUS_Initialising, "Initializing" }, 168 { TWE_PARAM_UNITSTATUS_Degraded, "Degraded" }, 169 { TWE_PARAM_UNITSTATUS_Rebuilding, "Rebuilding" }, 170 { TWE_PARAM_UNITSTATUS_Verifying, "Verifying" }, 171 { TWE_PARAM_UNITSTATUS_Corrupt, "Corrupt" }, 172 { TWE_PARAM_UNITSTATUS_Missing, "Missing" }, 173 174 { 0, NULL } 175 }; 176 177 const struct twe_code_table twe_table_unittype[] = { 178 /* array descriptor configuration */ 179 { TWE_AD_CONFIG_RAID0, "RAID0" }, 180 { TWE_AD_CONFIG_RAID1, "RAID1" }, 181 { TWE_AD_CONFIG_TwinStor, "TwinStor" }, 182 { TWE_AD_CONFIG_RAID5, "RAID5" }, 183 { TWE_AD_CONFIG_RAID10, "RAID10" }, 184 185 { 0, NULL } 186 }; 187 188 const struct twe_code_table twe_table_stripedepth[] = { 189 { TWE_AD_STRIPE_4k, "4K" }, 190 { TWE_AD_STRIPE_8k, "8K" }, 191 { TWE_AD_STRIPE_16k, "16K" }, 192 { TWE_AD_STRIPE_32k, "32K" }, 193 { TWE_AD_STRIPE_64k, "64K" }, 194 195 { 0, NULL } 196 }; 197 198 const char * 199 twe_describe_code(const struct twe_code_table *table, uint32_t code) 200 { 201 202 for (; table->string != NULL; table++) { 203 if (table->code == code) 204 return (table->string); 205 } 206 return (NULL); 207 } 208 209 struct { 210 const u_int aen; /* High byte indicates type of message */ 211 const char *desc; 212 } static const twe_aen_names[] = { 213 { 0x0000, "queue empty" }, 214 { 0x0001, "soft reset" }, 215 { 0x0102, "degraded mirror" }, 216 { 0x0003, "controller error" }, 217 { 0x0104, "rebuild fail" }, 218 { 0x0105, "rebuild done" }, 219 { 0x0106, "incompatible unit" }, 220 { 0x0107, "initialisation done" }, 221 { 0x0108, "unclean shutdown detected" }, 222 { 0x0109, "drive timeout" }, 223 { 0x010a, "drive error" }, 224 { 0x010b, "rebuild started" }, 225 { 0x010c, "init started" }, 226 { 0x010d, "logical unit deleted" }, 227 { 0x020f, "SMART threshold exceeded" }, 228 { 0x0015, "table undefined" }, /* XXX: Not in FreeBSD's table */ 229 { 0x0221, "ATA UDMA downgrade" }, 230 { 0x0222, "ATA UDMA upgrade" }, 231 { 0x0222, "ATA UDMA upgrade" }, 232 { 0x0223, "Sector repair occurred" }, 233 { 0x0024, "SBUF integrity check failure" }, 234 { 0x0225, "lost cached write" }, 235 { 0x0226, "drive ECC error detected" }, 236 { 0x0227, "DCB checksum error" }, 237 { 0x0228, "DCB unsupported version" }, 238 { 0x0129, "verify started" }, 239 { 0x012a, "verify failed" }, 240 { 0x012b, "verify complete" }, 241 { 0x022c, "overwrote bad sector during rebuild" }, 242 { 0x022d, "encountered bad sector during rebuild" }, 243 { 0x00ff, "aen queue full" }, 244 }; 245 246 /* 247 * The high byte of the message above determines the format, 248 * currently we know about format 0 (no unit/port specific) 249 * format 1 (unit specific message), and format 2 (port specific message). 250 */ 251 static const char * const aenfmt[] = { 252 "", /* No message */ 253 "unit %d: ", /* Unit message */ 254 "port %d: " /* Port message */ 255 }; 256 257 258 static inline u_int32_t 259 twe_inl(struct twe_softc *sc, int off) 260 { 261 262 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 263 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 264 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, off)); 265 } 266 267 static inline void 268 twe_outl(struct twe_softc *sc, int off, u_int32_t val) 269 { 270 271 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 272 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 273 BUS_SPACE_BARRIER_WRITE); 274 } 275 276 /* 277 * Match a supported board. 278 */ 279 static int 280 twe_match(struct device *parent, struct cfdata *cfdata, void *aux) 281 { 282 struct pci_attach_args *pa; 283 284 pa = aux; 285 286 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3WARE && 287 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE || 288 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE_ASIC)); 289 } 290 291 /* 292 * Attach a supported board. 293 * 294 * XXX This doesn't fail gracefully. 295 */ 296 static void 297 twe_attach(struct device *parent, struct device *self, void *aux) 298 { 299 struct pci_attach_args *pa; 300 struct twe_softc *sc; 301 pci_chipset_tag_t pc; 302 pci_intr_handle_t ih; 303 pcireg_t csr; 304 const char *intrstr; 305 int size, i, rv, rseg; 306 size_t max_segs, max_xfer; 307 struct twe_param *dtp, *atp; 308 struct twe_array_descriptor *ad; 309 struct twe_drive *td; 310 bus_dma_segment_t seg; 311 struct twe_cmd *tc; 312 struct twe_attach_args twea; 313 struct twe_ccb *ccb; 314 uint16_t dsize; 315 316 sc = (struct twe_softc *)self; 317 pa = aux; 318 pc = pa->pa_pc; 319 sc->sc_dmat = pa->pa_dmat; 320 SIMPLEQ_INIT(&sc->sc_ccb_queue); 321 SLIST_INIT(&sc->sc_ccb_freelist); 322 323 aprint_naive(": RAID controller\n"); 324 aprint_normal(": 3ware Escalade\n"); 325 326 ccb = malloc(sizeof(*ccb) * TWE_MAX_QUEUECNT, M_DEVBUF, M_NOWAIT); 327 if (ccb == NULL) { 328 aprint_error("%s: unable to allocate memory for ccbs\n", 329 sc->sc_dv.dv_xname); 330 return; 331 } 332 333 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 334 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 335 aprint_error("%s: can't map i/o space\n", sc->sc_dv.dv_xname); 336 return; 337 } 338 339 /* Enable the device. */ 340 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 341 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 342 csr | PCI_COMMAND_MASTER_ENABLE); 343 344 /* Map and establish the interrupt. */ 345 if (pci_intr_map(pa, &ih)) { 346 aprint_error("%s: can't map interrupt\n", sc->sc_dv.dv_xname); 347 return; 348 } 349 350 intrstr = pci_intr_string(pc, ih); 351 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, twe_intr, sc); 352 if (sc->sc_ih == NULL) { 353 aprint_error("%s: can't establish interrupt%s%s\n", 354 sc->sc_dv.dv_xname, 355 (intrstr) ? " at " : "", 356 (intrstr) ? intrstr : ""); 357 return; 358 } 359 360 if (intrstr != NULL) 361 aprint_normal("%s: interrupting at %s\n", 362 sc->sc_dv.dv_xname, intrstr); 363 364 /* 365 * Allocate and initialise the command blocks and CCBs. 366 */ 367 size = sizeof(struct twe_cmd) * TWE_MAX_QUEUECNT; 368 369 if ((rv = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 1, 370 &rseg, BUS_DMA_NOWAIT)) != 0) { 371 aprint_error("%s: unable to allocate commands, rv = %d\n", 372 sc->sc_dv.dv_xname, rv); 373 return; 374 } 375 376 if ((rv = bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 377 (caddr_t *)&sc->sc_cmds, 378 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 379 aprint_error("%s: unable to map commands, rv = %d\n", 380 sc->sc_dv.dv_xname, rv); 381 return; 382 } 383 384 if ((rv = bus_dmamap_create(sc->sc_dmat, size, size, 1, 0, 385 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 386 aprint_error("%s: unable to create command DMA map, rv = %d\n", 387 sc->sc_dv.dv_xname, rv); 388 return; 389 } 390 391 if ((rv = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cmds, 392 size, NULL, BUS_DMA_NOWAIT)) != 0) { 393 aprint_error("%s: unable to load command DMA map, rv = %d\n", 394 sc->sc_dv.dv_xname, rv); 395 return; 396 } 397 398 sc->sc_cmds_paddr = sc->sc_dmamap->dm_segs[0].ds_addr; 399 memset(sc->sc_cmds, 0, size); 400 401 sc->sc_ccbs = ccb; 402 tc = (struct twe_cmd *)sc->sc_cmds; 403 max_segs = twe_get_maxsegs(); 404 max_xfer = twe_get_maxxfer(max_segs); 405 406 for (i = 0; i < TWE_MAX_QUEUECNT; i++, tc++, ccb++) { 407 ccb->ccb_cmd = tc; 408 ccb->ccb_cmdid = i; 409 ccb->ccb_flags = 0; 410 rv = bus_dmamap_create(sc->sc_dmat, max_xfer, 411 max_segs, PAGE_SIZE, 0, 412 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 413 &ccb->ccb_dmamap_xfer); 414 if (rv != 0) { 415 aprint_error("%s: can't create dmamap, rv = %d\n", 416 sc->sc_dv.dv_xname, rv); 417 return; 418 } 419 /* Save one CCB for parameter retrieval. */ 420 if (i != 0) 421 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, 422 ccb_chain.slist); 423 } 424 425 /* Wait for the controller to become ready. */ 426 if (twe_status_wait(sc, TWE_STS_MICROCONTROLLER_READY, 6)) { 427 aprint_error("%s: microcontroller not ready\n", 428 sc->sc_dv.dv_xname); 429 return; 430 } 431 432 twe_outl(sc, TWE_REG_CTL, TWE_CTL_DISABLE_INTRS); 433 434 /* Reset the controller. */ 435 if (twe_reset(sc)) { 436 aprint_error("%s: reset failed\n", sc->sc_dv.dv_xname); 437 return; 438 } 439 440 /* Find attached units. */ 441 rv = twe_param_get(sc, TWE_PARAM_UNITSUMMARY, 442 TWE_PARAM_UNITSUMMARY_Status, TWE_MAX_UNITS, NULL, &dtp); 443 if (rv != 0) { 444 aprint_error("%s: can't detect attached units (%d)\n", 445 sc->sc_dv.dv_xname, rv); 446 return; 447 } 448 449 /* For each detected unit, collect size and store in an array. */ 450 for (i = 0, sc->sc_nunits = 0; i < TWE_MAX_UNITS; i++) { 451 td = &sc->sc_units[i]; 452 453 /* Unit present? */ 454 if ((dtp->tp_data[i] & TWE_PARAM_UNITSTATUS_Online) == 0) { 455 td->td_size = 0; 456 td->td_type = 0; 457 td->td_stripe = 0; 458 continue; 459 } 460 461 rv = twe_param_get_2(sc, TWE_PARAM_UNITINFO + i, 462 TWE_PARAM_UNITINFO_DescriptorSize, &dsize); 463 if (rv != 0) { 464 aprint_error("%s: error %d fetching descriptor size " 465 "for unit %d\n", sc->sc_dv.dv_xname, rv, i); 466 td->td_size = 0; 467 td->td_type = 0; 468 td->td_stripe = 0; 469 continue; 470 } 471 472 rv = twe_param_get(sc, TWE_PARAM_UNITINFO + i, 473 TWE_PARAM_UNITINFO_Descriptor, dsize - 3, NULL, &atp); 474 if (rv != 0) { 475 aprint_error("%s: error %d fetching array descriptor " 476 "for unit %d\n", sc->sc_dv.dv_xname, rv, i); 477 td->td_size = 0; 478 td->td_type = 0; 479 td->td_stripe = 0; 480 continue; 481 } 482 ad = (struct twe_array_descriptor *)atp->tp_data; 483 td->td_type = ad->configuration; 484 td->td_stripe = ad->stripe_size; 485 free(atp, M_DEVBUF); 486 487 rv = twe_param_get_4(sc, TWE_PARAM_UNITINFO + i, 488 TWE_PARAM_UNITINFO_Capacity, &td->td_size); 489 if (rv != 0) { 490 aprint_error( 491 "%s: error %d fetching capacity for unit %d\n", 492 sc->sc_dv.dv_xname, rv, i); 493 td->td_size = 0; 494 td->td_type = 0; 495 td->td_stripe = 0; 496 continue; 497 } 498 499 sc->sc_nunits++; 500 } 501 free(dtp, M_DEVBUF); 502 503 /* Initialise connection with controller and enable interrupts. */ 504 twe_init_connection(sc); 505 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR | 506 TWE_CTL_UNMASK_RESP_INTR | 507 TWE_CTL_ENABLE_INTRS); 508 509 twe_describe_controller(sc); 510 511 /* Attach sub-devices. */ 512 for (i = 0; i < TWE_MAX_UNITS; i++) { 513 td = &sc->sc_units[i]; 514 if (td->td_size == 0) 515 continue; 516 twea.twea_unit = i; 517 td->td_dev = config_found_sm(&sc->sc_dv, &twea, twe_print, 518 twe_submatch); 519 } 520 } 521 522 /* 523 * Reset the controller. Currently only useful at attach time; must be 524 * called with interrupts blocked. 525 */ 526 static int 527 twe_reset(struct twe_softc *sc) 528 { 529 uint16_t aen; 530 u_int status; 531 volatile u_int32_t junk; 532 int got, rv; 533 534 /* Issue a soft reset. */ 535 twe_outl(sc, TWE_REG_CTL, TWE_CTL_ISSUE_SOFT_RESET | 536 TWE_CTL_CLEAR_HOST_INTR | 537 TWE_CTL_CLEAR_ATTN_INTR | 538 TWE_CTL_MASK_CMD_INTR | 539 TWE_CTL_MASK_RESP_INTR | 540 TWE_CTL_CLEAR_ERROR_STS | 541 TWE_CTL_DISABLE_INTRS); 542 543 if (twe_status_wait(sc, TWE_STS_ATTN_INTR, 15)) { 544 printf("%s: no attention interrupt\n", 545 sc->sc_dv.dv_xname); 546 return (-1); 547 } 548 549 /* Pull AENs out of the controller; look for a soft reset AEN. */ 550 for (got = 0;;) { 551 rv = twe_param_get_2(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 552 &aen); 553 if (rv != 0) 554 printf("%s: error %d while draining response queue\n", 555 sc->sc_dv.dv_xname, rv); 556 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) 557 break; 558 if (TWE_AEN_CODE(aen) == TWE_AEN_SOFT_RESET) 559 got = 1; 560 } 561 if (!got) { 562 printf("%s: reset not reported\n", sc->sc_dv.dv_xname); 563 return (-1); 564 } 565 566 /* Check controller status. */ 567 status = twe_inl(sc, TWE_REG_STS); 568 if (twe_status_check(sc, status)) { 569 printf("%s: controller errors detected\n", 570 sc->sc_dv.dv_xname); 571 return (-1); 572 } 573 574 /* Drain the response queue. */ 575 for (;;) { 576 status = twe_inl(sc, TWE_REG_STS); 577 if (twe_status_check(sc, status) != 0) { 578 printf("%s: can't drain response queue\n", 579 sc->sc_dv.dv_xname); 580 return (-1); 581 } 582 if ((status & TWE_STS_RESP_QUEUE_EMPTY) != 0) 583 break; 584 junk = twe_inl(sc, TWE_REG_RESP_QUEUE); 585 } 586 587 return (0); 588 } 589 590 /* 591 * Print autoconfiguration message for a sub-device. 592 */ 593 static int 594 twe_print(void *aux, const char *pnp) 595 { 596 struct twe_attach_args *twea; 597 598 twea = aux; 599 600 if (pnp != NULL) 601 aprint_normal("block device at %s", pnp); 602 aprint_normal(" unit %d", twea->twea_unit); 603 return (UNCONF); 604 } 605 606 /* 607 * Match a sub-device. 608 */ 609 static int 610 twe_submatch(struct device *parent, struct cfdata *cf, void *aux) 611 { 612 struct twe_attach_args *twea; 613 614 twea = aux; 615 616 if (cf->tweacf_unit != TWECF_UNIT_DEFAULT && 617 cf->tweacf_unit != twea->twea_unit) 618 return (0); 619 620 return (config_match(parent, cf, aux)); 621 } 622 623 /* 624 * Interrupt service routine. 625 */ 626 static int 627 twe_intr(void *arg) 628 { 629 struct twe_softc *sc; 630 u_int status; 631 int caught, rv; 632 633 sc = arg; 634 caught = 0; 635 status = twe_inl(sc, TWE_REG_STS); 636 twe_status_check(sc, status); 637 638 /* Host interrupts - purpose unknown. */ 639 if ((status & TWE_STS_HOST_INTR) != 0) { 640 #ifdef DEBUG 641 printf("%s: host interrupt\n", sc->sc_dv.dv_xname); 642 #endif 643 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_HOST_INTR); 644 caught = 1; 645 } 646 647 /* 648 * Attention interrupts, signalled when a controller or child device 649 * state change has occurred. 650 */ 651 if ((status & TWE_STS_ATTN_INTR) != 0) { 652 if ((sc->sc_flags & TWEF_AEN) == 0) { 653 rv = twe_param_get(sc, TWE_PARAM_AEN, 654 TWE_PARAM_AEN_UnitCode, 2, twe_aen_handler, 655 NULL); 656 if (rv != 0) { 657 printf("%s: unable to retrieve AEN (%d)\n", 658 sc->sc_dv.dv_xname, rv); 659 twe_outl(sc, TWE_REG_CTL, 660 TWE_CTL_CLEAR_ATTN_INTR); 661 } else 662 sc->sc_flags |= TWEF_AEN; 663 } 664 caught = 1; 665 } 666 667 /* 668 * Command interrupts, signalled when the controller can accept more 669 * commands. We don't use this; instead, we try to submit commands 670 * when we receive them, and when other commands have completed. 671 * Mask it so we don't get another one. 672 */ 673 if ((status & TWE_STS_CMD_INTR) != 0) { 674 #ifdef DEBUG 675 printf("%s: command interrupt\n", sc->sc_dv.dv_xname); 676 #endif 677 twe_outl(sc, TWE_REG_CTL, TWE_CTL_MASK_CMD_INTR); 678 caught = 1; 679 } 680 681 if ((status & TWE_STS_RESP_INTR) != 0) { 682 twe_poll(sc); 683 caught = 1; 684 } 685 686 return (caught); 687 } 688 689 /* 690 * Handle an AEN returned by the controller. 691 */ 692 static void 693 twe_aen_handler(struct twe_ccb *ccb, int error) 694 { 695 struct twe_softc *sc; 696 struct twe_param *tp; 697 const char *str; 698 u_int aen; 699 int i, hu, rv; 700 701 sc = (struct twe_softc *)ccb->ccb_tx.tx_dv; 702 tp = ccb->ccb_tx.tx_context; 703 twe_ccb_unmap(sc, ccb); 704 705 if (error) { 706 printf("%s: error retrieving AEN\n", sc->sc_dv.dv_xname); 707 aen = TWE_AEN_QUEUE_EMPTY; 708 } else 709 aen = le16toh(*(u_int16_t *)tp->tp_data); 710 free(tp, M_DEVBUF); 711 twe_ccb_free(sc, ccb); 712 713 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) { 714 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 715 sc->sc_flags &= ~TWEF_AEN; 716 return; 717 } 718 719 str = "<unknown>"; 720 i = 0; 721 hu = 0; 722 723 while (i < sizeof(twe_aen_names) / sizeof(twe_aen_names[0])) { 724 if (TWE_AEN_CODE(twe_aen_names[i].aen) == TWE_AEN_CODE(aen)) { 725 str = twe_aen_names[i].desc; 726 hu = TWE_AEN_UNIT(twe_aen_names[i].aen); 727 break; 728 } 729 i++; 730 } 731 printf("%s: ", sc->sc_dv.dv_xname); 732 printf(aenfmt[hu], TWE_AEN_UNIT(aen)); 733 printf("AEN 0x%04x (%s) received\n", TWE_AEN_CODE(aen), str); 734 735 /* 736 * Chain another retrieval in case interrupts have been 737 * coalesced. 738 */ 739 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 2, 740 twe_aen_handler, NULL); 741 if (rv != 0) 742 printf("%s: unable to retrieve AEN (%d)\n", 743 sc->sc_dv.dv_xname, rv); 744 } 745 746 /* 747 * These are short-hand functions that execute TWE_OP_GET_PARAM to 748 * fetch 1, 2, and 4 byte parameter values, respectively. 749 */ 750 int 751 twe_param_get_1(struct twe_softc *sc, int table_id, int param_id, 752 uint8_t *valp) 753 { 754 struct twe_param *tp; 755 int rv; 756 757 rv = twe_param_get(sc, table_id, param_id, 1, NULL, &tp); 758 if (rv != 0) 759 return (rv); 760 *valp = *(uint8_t *)tp->tp_data; 761 free(tp, M_DEVBUF); 762 return (0); 763 } 764 765 int 766 twe_param_get_2(struct twe_softc *sc, int table_id, int param_id, 767 uint16_t *valp) 768 { 769 struct twe_param *tp; 770 int rv; 771 772 rv = twe_param_get(sc, table_id, param_id, 2, NULL, &tp); 773 if (rv != 0) 774 return (rv); 775 *valp = le16toh(*(uint16_t *)tp->tp_data); 776 free(tp, M_DEVBUF); 777 return (0); 778 } 779 780 int 781 twe_param_get_4(struct twe_softc *sc, int table_id, int param_id, 782 uint32_t *valp) 783 { 784 struct twe_param *tp; 785 int rv; 786 787 rv = twe_param_get(sc, table_id, param_id, 4, NULL, &tp); 788 if (rv != 0) 789 return (rv); 790 *valp = le32toh(*(uint32_t *)tp->tp_data); 791 free(tp, M_DEVBUF); 792 return (0); 793 } 794 795 /* 796 * Execute a TWE_OP_GET_PARAM command. If a callback function is provided, 797 * it will be called with generated context when the command has completed. 798 * If no callback is provided, the command will be executed synchronously 799 * and a pointer to a buffer containing the data returned. 800 * 801 * The caller or callback is responsible for freeing the buffer. 802 */ 803 int 804 twe_param_get(struct twe_softc *sc, int table_id, int param_id, size_t size, 805 void (*func)(struct twe_ccb *, int), struct twe_param **pbuf) 806 { 807 struct twe_ccb *ccb; 808 struct twe_cmd *tc; 809 struct twe_param *tp; 810 int rv, s; 811 812 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 813 if (tp == NULL) 814 return ENOMEM; 815 816 rv = twe_ccb_alloc(sc, &ccb, 817 TWE_CCB_PARAM | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 818 if (rv != 0) 819 goto done; 820 821 ccb->ccb_data = tp; 822 ccb->ccb_datasize = TWE_SECTOR_SIZE; 823 ccb->ccb_tx.tx_handler = func; 824 ccb->ccb_tx.tx_context = tp; 825 ccb->ccb_tx.tx_dv = &sc->sc_dv; 826 827 tc = ccb->ccb_cmd; 828 tc->tc_size = 2; 829 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 830 tc->tc_unit = 0; 831 tc->tc_count = htole16(1); 832 833 /* Fill in the outbound parameter data. */ 834 tp->tp_table_id = htole16(table_id); 835 tp->tp_param_id = param_id; 836 tp->tp_param_size = size; 837 838 /* Map the transfer. */ 839 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 840 twe_ccb_free(sc, ccb); 841 goto done; 842 } 843 844 /* Submit the command and either wait or let the callback handle it. */ 845 if (func == NULL) { 846 s = splbio(); 847 rv = twe_ccb_poll(sc, ccb, 5); 848 twe_ccb_unmap(sc, ccb); 849 twe_ccb_free(sc, ccb); 850 splx(s); 851 } else { 852 #ifdef DEBUG 853 if (pbuf != NULL) 854 panic("both func and pbuf defined"); 855 #endif 856 twe_ccb_enqueue(sc, ccb); 857 return 0; 858 } 859 860 done: 861 if (pbuf == NULL || rv != 0) 862 free(tp, M_DEVBUF); 863 else if (pbuf != NULL && rv == 0) 864 *pbuf = tp; 865 return rv; 866 } 867 868 /* 869 * Execute a TWE_OP_SET_PARAM command. 870 */ 871 static int 872 twe_param_set(struct twe_softc *sc, int table_id, int param_id, size_t size, 873 void *buf) 874 { 875 struct twe_ccb *ccb; 876 struct twe_cmd *tc; 877 struct twe_param *tp; 878 int rv, s; 879 880 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 881 if (tp == NULL) 882 return ENOMEM; 883 884 rv = twe_ccb_alloc(sc, &ccb, 885 TWE_CCB_PARAM | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 886 if (rv != 0) 887 goto done; 888 889 ccb->ccb_data = tp; 890 ccb->ccb_datasize = TWE_SECTOR_SIZE; 891 ccb->ccb_tx.tx_handler = 0; 892 ccb->ccb_tx.tx_context = tp; 893 ccb->ccb_tx.tx_dv = &sc->sc_dv; 894 895 tc = ccb->ccb_cmd; 896 tc->tc_size = 2; 897 tc->tc_opcode = TWE_OP_SET_PARAM | (tc->tc_size << 5); 898 tc->tc_unit = 0; 899 tc->tc_count = htole16(1); 900 901 /* Fill in the outbound parameter data. */ 902 tp->tp_table_id = htole16(table_id); 903 tp->tp_param_id = param_id; 904 tp->tp_param_size = size; 905 memcpy(tp->tp_data, buf, size); 906 907 /* Map the transfer. */ 908 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 909 twe_ccb_free(sc, ccb); 910 goto done; 911 } 912 913 /* Submit the command and wait. */ 914 s = splbio(); 915 rv = twe_ccb_poll(sc, ccb, 5); 916 twe_ccb_unmap(sc, ccb); 917 twe_ccb_free(sc, ccb); 918 splx(s); 919 done: 920 free(tp, M_DEVBUF); 921 return (rv); 922 } 923 924 /* 925 * Execute a TWE_OP_INIT_CONNECTION command. Return non-zero on error. 926 * Must be called with interrupts blocked. 927 */ 928 static int 929 twe_init_connection(struct twe_softc *sc) 930 /*###762 [cc] warning: `twe_init_connection' was used with no prototype before its definition%%%*/ 931 /*###762 [cc] warning: `twe_init_connection' was declared implicitly `extern' and later `static'%%%*/ 932 { 933 struct twe_ccb *ccb; 934 struct twe_cmd *tc; 935 int rv; 936 937 if ((rv = twe_ccb_alloc(sc, &ccb, 0)) != 0) 938 return (rv); 939 940 /* Build the command. */ 941 tc = ccb->ccb_cmd; 942 tc->tc_size = 3; 943 tc->tc_opcode = TWE_OP_INIT_CONNECTION; 944 tc->tc_unit = 0; 945 tc->tc_count = htole16(TWE_MAX_CMDS); 946 tc->tc_args.init_connection.response_queue_pointer = 0; 947 948 /* Submit the command for immediate execution. */ 949 rv = twe_ccb_poll(sc, ccb, 5); 950 twe_ccb_free(sc, ccb); 951 return (rv); 952 } 953 954 /* 955 * Poll the controller for completed commands. Must be called with 956 * interrupts blocked. 957 */ 958 static void 959 twe_poll(struct twe_softc *sc) 960 { 961 struct twe_ccb *ccb; 962 int found; 963 u_int status, cmdid; 964 965 found = 0; 966 967 for (;;) { 968 status = twe_inl(sc, TWE_REG_STS); 969 twe_status_check(sc, status); 970 971 if ((status & TWE_STS_RESP_QUEUE_EMPTY)) 972 break; 973 974 found = 1; 975 cmdid = twe_inl(sc, TWE_REG_RESP_QUEUE); 976 cmdid = (cmdid & TWE_RESP_MASK) >> TWE_RESP_SHIFT; 977 if (cmdid >= TWE_MAX_QUEUECNT) { 978 printf("%s: bad completion\n", sc->sc_dv.dv_xname); 979 continue; 980 } 981 982 ccb = sc->sc_ccbs + cmdid; 983 if ((ccb->ccb_flags & TWE_CCB_ACTIVE) == 0) { 984 printf("%s: bad completion (not active)\n", 985 sc->sc_dv.dv_xname); 986 continue; 987 } 988 ccb->ccb_flags ^= TWE_CCB_COMPLETE | TWE_CCB_ACTIVE; 989 990 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 991 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, 992 sizeof(struct twe_cmd), 993 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 994 995 /* Pass notification to upper layers. */ 996 if (ccb->ccb_tx.tx_handler != NULL) 997 (*ccb->ccb_tx.tx_handler)(ccb, 998 ccb->ccb_cmd->tc_status != 0 ? EIO : 0); 999 } 1000 1001 /* If any commands have completed, run the software queue. */ 1002 if (found) 1003 twe_ccb_enqueue(sc, NULL); 1004 } 1005 1006 /* 1007 * Wait for `status' to be set in the controller status register. Return 1008 * zero if found, non-zero if the operation timed out. 1009 */ 1010 static int 1011 twe_status_wait(struct twe_softc *sc, u_int32_t status, int timo) 1012 { 1013 1014 for (timo *= 10; timo != 0; timo--) { 1015 if ((twe_inl(sc, TWE_REG_STS) & status) == status) 1016 break; 1017 delay(100000); 1018 } 1019 1020 return (timo == 0); 1021 } 1022 1023 /* 1024 * Complain if the status bits aren't what we expect. 1025 */ 1026 static int 1027 twe_status_check(struct twe_softc *sc, u_int status) 1028 { 1029 int rv; 1030 1031 rv = 0; 1032 1033 if ((status & TWE_STS_EXPECTED_BITS) != TWE_STS_EXPECTED_BITS) { 1034 printf("%s: missing status bits: 0x%08x\n", sc->sc_dv.dv_xname, 1035 status & ~TWE_STS_EXPECTED_BITS); 1036 rv = -1; 1037 } 1038 1039 if ((status & TWE_STS_UNEXPECTED_BITS) != 0) { 1040 printf("%s: unexpected status bits: 0x%08x\n", 1041 sc->sc_dv.dv_xname, status & TWE_STS_UNEXPECTED_BITS); 1042 rv = -1; 1043 } 1044 1045 return (rv); 1046 } 1047 1048 /* 1049 * Allocate and initialise a CCB. 1050 */ 1051 int 1052 twe_ccb_alloc(struct twe_softc *sc, struct twe_ccb **ccbp, int flags) 1053 { 1054 struct twe_cmd *tc; 1055 struct twe_ccb *ccb; 1056 int s; 1057 1058 s = splbio(); 1059 if ((flags & TWE_CCB_PARAM) != 0) 1060 ccb = sc->sc_ccbs; 1061 else { 1062 /* Allocate a CCB and command block. */ 1063 if (SLIST_FIRST(&sc->sc_ccb_freelist) == NULL) { 1064 splx(s); 1065 return (EAGAIN); 1066 } 1067 ccb = SLIST_FIRST(&sc->sc_ccb_freelist); 1068 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 1069 } 1070 #ifdef DIAGNOSTIC 1071 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 1072 panic("twe_ccb_alloc: CCB already allocated"); 1073 flags |= TWE_CCB_ALLOCED; 1074 #endif 1075 splx(s); 1076 1077 /* Initialise some fields and return. */ 1078 ccb->ccb_tx.tx_handler = NULL; 1079 ccb->ccb_flags = flags; 1080 tc = ccb->ccb_cmd; 1081 tc->tc_status = 0; 1082 tc->tc_flags = 0; 1083 tc->tc_cmdid = ccb->ccb_cmdid; 1084 *ccbp = ccb; 1085 1086 return (0); 1087 } 1088 1089 /* 1090 * Free a CCB. 1091 */ 1092 void 1093 twe_ccb_free(struct twe_softc *sc, struct twe_ccb *ccb) 1094 { 1095 int s; 1096 1097 s = splbio(); 1098 if ((ccb->ccb_flags & TWE_CCB_PARAM) == 0) 1099 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, ccb_chain.slist); 1100 ccb->ccb_flags = 0; 1101 splx(s); 1102 } 1103 1104 /* 1105 * Map the specified CCB's command block and data buffer (if any) into 1106 * controller visible space. Perform DMA synchronisation. 1107 */ 1108 int 1109 twe_ccb_map(struct twe_softc *sc, struct twe_ccb *ccb) 1110 { 1111 struct twe_cmd *tc; 1112 int flags, nsegs, i, s, rv; 1113 void *data; 1114 1115 /* 1116 * The data as a whole must be 512-byte aligned. 1117 */ 1118 if (((u_long)ccb->ccb_data & (TWE_ALIGNMENT - 1)) != 0) { 1119 s = splvm(); 1120 /* XXX */ 1121 ccb->ccb_abuf = uvm_km_kmemalloc(kmem_map, NULL, 1122 ccb->ccb_datasize, UVM_KMF_NOWAIT); 1123 splx(s); 1124 data = (void *)ccb->ccb_abuf; 1125 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1126 memcpy(data, ccb->ccb_data, ccb->ccb_datasize); 1127 } else { 1128 ccb->ccb_abuf = (vaddr_t)0; 1129 data = ccb->ccb_data; 1130 } 1131 1132 /* 1133 * Map the data buffer into bus space and build the S/G list. 1134 */ 1135 rv = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap_xfer, data, 1136 ccb->ccb_datasize, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1137 ((ccb->ccb_flags & TWE_CCB_DATA_IN) ? 1138 BUS_DMA_READ : BUS_DMA_WRITE)); 1139 if (rv != 0) { 1140 if (ccb->ccb_abuf != (vaddr_t)0) { 1141 s = splvm(); 1142 /* XXX */ 1143 uvm_km_free(kmem_map, ccb->ccb_abuf, 1144 ccb->ccb_datasize); 1145 splx(s); 1146 } 1147 return (rv); 1148 } 1149 1150 nsegs = ccb->ccb_dmamap_xfer->dm_nsegs; 1151 tc = ccb->ccb_cmd; 1152 tc->tc_size += 2 * nsegs; 1153 1154 /* The location of the S/G list is dependant upon command type. */ 1155 switch (tc->tc_opcode >> 5) { 1156 case 2: 1157 for (i = 0; i < nsegs; i++) { 1158 tc->tc_args.param.sgl[i].tsg_address = 1159 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 1160 tc->tc_args.param.sgl[i].tsg_length = 1161 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 1162 } 1163 /* XXX Needed? */ 1164 for (; i < TWE_SG_SIZE; i++) { 1165 tc->tc_args.param.sgl[i].tsg_address = 0; 1166 tc->tc_args.param.sgl[i].tsg_length = 0; 1167 } 1168 break; 1169 case 3: 1170 for (i = 0; i < nsegs; i++) { 1171 tc->tc_args.io.sgl[i].tsg_address = 1172 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 1173 tc->tc_args.io.sgl[i].tsg_length = 1174 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 1175 } 1176 /* XXX Needed? */ 1177 for (; i < TWE_SG_SIZE; i++) { 1178 tc->tc_args.io.sgl[i].tsg_address = 0; 1179 tc->tc_args.io.sgl[i].tsg_length = 0; 1180 } 1181 break; 1182 #ifdef DEBUG 1183 default: 1184 panic("twe_ccb_map: oops"); 1185 #endif 1186 } 1187 1188 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1189 flags = BUS_DMASYNC_PREREAD; 1190 else 1191 flags = 0; 1192 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1193 flags |= BUS_DMASYNC_PREWRITE; 1194 1195 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 1196 ccb->ccb_datasize, flags); 1197 return (0); 1198 } 1199 1200 /* 1201 * Unmap the specified CCB's command block and data buffer (if any) and 1202 * perform DMA synchronisation. 1203 */ 1204 void 1205 twe_ccb_unmap(struct twe_softc *sc, struct twe_ccb *ccb) 1206 { 1207 int flags, s; 1208 1209 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1210 flags = BUS_DMASYNC_POSTREAD; 1211 else 1212 flags = 0; 1213 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1214 flags |= BUS_DMASYNC_POSTWRITE; 1215 1216 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 1217 ccb->ccb_datasize, flags); 1218 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap_xfer); 1219 1220 if (ccb->ccb_abuf != (vaddr_t)0) { 1221 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1222 memcpy(ccb->ccb_data, (void *)ccb->ccb_abuf, 1223 ccb->ccb_datasize); 1224 s = splvm(); 1225 /* XXX */ 1226 uvm_km_free(kmem_map, ccb->ccb_abuf, ccb->ccb_datasize); 1227 splx(s); 1228 } 1229 } 1230 1231 /* 1232 * Submit a command to the controller and poll on completion. Return 1233 * non-zero on timeout (but don't check status, as some command types don't 1234 * return status). Must be called with interrupts blocked. 1235 */ 1236 int 1237 twe_ccb_poll(struct twe_softc *sc, struct twe_ccb *ccb, int timo) 1238 { 1239 int rv; 1240 1241 if ((rv = twe_ccb_submit(sc, ccb)) != 0) 1242 return (rv); 1243 1244 for (timo *= 1000; timo != 0; timo--) { 1245 twe_poll(sc); 1246 if ((ccb->ccb_flags & TWE_CCB_COMPLETE) != 0) 1247 break; 1248 DELAY(100); 1249 } 1250 1251 return (timo == 0); 1252 } 1253 1254 /* 1255 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1256 * the order that they were enqueued and try to submit their command blocks 1257 * to the controller for execution. 1258 */ 1259 void 1260 twe_ccb_enqueue(struct twe_softc *sc, struct twe_ccb *ccb) 1261 { 1262 int s; 1263 1264 s = splbio(); 1265 1266 if (ccb != NULL) 1267 SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 1268 1269 while ((ccb = SIMPLEQ_FIRST(&sc->sc_ccb_queue)) != NULL) { 1270 if (twe_ccb_submit(sc, ccb)) 1271 break; 1272 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_queue, ccb_chain.simpleq); 1273 } 1274 1275 splx(s); 1276 } 1277 1278 /* 1279 * Submit the command block associated with the specified CCB to the 1280 * controller for execution. Must be called with interrupts blocked. 1281 */ 1282 int 1283 twe_ccb_submit(struct twe_softc *sc, struct twe_ccb *ccb) 1284 { 1285 bus_addr_t pa; 1286 int rv; 1287 u_int status; 1288 1289 /* Check to see if we can post a command. */ 1290 status = twe_inl(sc, TWE_REG_STS); 1291 twe_status_check(sc, status); 1292 1293 if ((status & TWE_STS_CMD_QUEUE_FULL) == 0) { 1294 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1295 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, sizeof(struct twe_cmd), 1296 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1297 ccb->ccb_flags |= TWE_CCB_ACTIVE; 1298 pa = sc->sc_cmds_paddr + 1299 ccb->ccb_cmdid * sizeof(struct twe_cmd); 1300 twe_outl(sc, TWE_REG_CMD_QUEUE, (u_int32_t)pa); 1301 rv = 0; 1302 } else 1303 rv = EBUSY; 1304 1305 return (rv); 1306 } 1307 1308 1309 /* 1310 * Accept an open operation on the control device. 1311 */ 1312 int 1313 tweopen(dev_t dev, int flag, int mode, struct proc *p) 1314 { 1315 struct twe_softc *twe; 1316 1317 if ((twe = device_lookup(&twe_cd, minor(dev))) == NULL) 1318 return (ENXIO); 1319 if ((twe->sc_flags & TWEF_OPEN) != 0) 1320 return (EBUSY); 1321 1322 twe->sc_flags |= TWEF_OPEN; 1323 return (0); 1324 } 1325 1326 /* 1327 * Accept the last close on the control device. 1328 */ 1329 int 1330 tweclose(dev_t dev, int flag, int mode, struct proc *p) 1331 { 1332 struct twe_softc *twe; 1333 1334 twe = device_lookup(&twe_cd, minor(dev)); 1335 twe->sc_flags &= ~TWEF_OPEN; 1336 return (0); 1337 } 1338 1339 /* 1340 * Handle control operations. 1341 */ 1342 int 1343 tweioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1344 { 1345 struct twe_softc *twe; 1346 struct twe_ccb *ccb; 1347 struct twe_param *param; 1348 struct twe_usercommand *tu; 1349 struct twe_paramcommand *tp; 1350 union twe_statrequest *ts; 1351 void *pdata = NULL; 1352 int rv, s, error = 0; 1353 u_int8_t cmdid; 1354 1355 if (securelevel >= 2) 1356 return (EPERM); 1357 1358 twe = device_lookup(&twe_cd, minor(dev)); 1359 tu = (struct twe_usercommand *)data; 1360 tp = (struct twe_paramcommand *)data; 1361 ts = (union twe_statrequest *)data; 1362 1363 /* Hmm, compatible with FreeBSD */ 1364 switch (cmd) { 1365 case TWEIO_COMMAND: 1366 if (tu->tu_size > 0) { 1367 if (tu->tu_size > TWE_SECTOR_SIZE) 1368 return EINVAL; 1369 pdata = malloc(tu->tu_size, M_DEVBUF, M_WAITOK); 1370 error = copyin(tu->tu_data, pdata, tu->tu_size); 1371 if (error != 0) 1372 goto done; 1373 error = twe_ccb_alloc(twe, &ccb, TWE_CCB_PARAM | 1374 TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1375 } else { 1376 error = twe_ccb_alloc(twe, &ccb, 0); 1377 } 1378 if (rv != 0) 1379 goto done; 1380 cmdid = ccb->ccb_cmdid; 1381 memcpy(ccb->ccb_cmd, &tu->tu_cmd, sizeof(struct twe_cmd)); 1382 ccb->ccb_cmdid = cmdid; 1383 if (ccb->ccb_flags & TWE_CCB_PARAM) { 1384 ccb->ccb_data = pdata; 1385 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1386 ccb->ccb_tx.tx_handler = 0; 1387 ccb->ccb_tx.tx_context = pdata; 1388 ccb->ccb_tx.tx_dv = &twe->sc_dv; 1389 } 1390 /* Map the transfer. */ 1391 if ((error = twe_ccb_map(twe, ccb)) != 0) { 1392 twe_ccb_free(twe, ccb); 1393 goto done; 1394 } 1395 1396 /* Submit the command and wait. */ 1397 s = splbio(); 1398 rv = twe_ccb_poll(twe, ccb, 5); 1399 twe_ccb_unmap(twe, ccb); 1400 twe_ccb_free(twe, ccb); 1401 splx(s); 1402 1403 if (tu->tu_size > 0) 1404 error = copyout(pdata, tu->tu_data, tu->tu_size); 1405 goto done; 1406 1407 case TWEIO_STATS: 1408 return (ENOENT); 1409 1410 case TWEIO_AEN_POLL: 1411 if ((twe->sc_flags & TWEF_AEN) == 0) 1412 return (ENOENT); 1413 return (0); 1414 1415 case TWEIO_AEN_WAIT: 1416 s = splbio(); 1417 while ((twe->sc_flags & TWEF_AEN) == 0) { 1418 /* tsleep(); */ 1419 } 1420 splx(s); 1421 return (0); 1422 1423 case TWEIO_GET_PARAM: 1424 error = twe_param_get(twe, tp->tp_table_id, tp->tp_param_id, 1425 tp->tp_size, 0, ¶m); 1426 if (error != 0) 1427 return (error); 1428 if (param->tp_param_size > tp->tp_size) { 1429 error = EFAULT; 1430 goto done; 1431 } 1432 error = copyout(param->tp_data, tp->tp_data, 1433 param->tp_param_size); 1434 goto done; 1435 1436 case TWEIO_SET_PARAM: 1437 pdata = malloc(tp->tp_size, M_DEVBUF, M_WAITOK); 1438 if ((error = copyin(tp->tp_data, pdata, tp->tp_size)) != 0) 1439 goto done; 1440 error = twe_param_set(twe, tp->tp_table_id, tp->tp_param_id, 1441 tp->tp_size, pdata); 1442 goto done; 1443 1444 case TWEIO_RESET: 1445 twe_reset(twe); 1446 return (0); 1447 1448 default: 1449 return EINVAL; 1450 } 1451 done: 1452 if (pdata) 1453 free(pdata, M_DEVBUF); 1454 return error; 1455 } 1456 1457 /* 1458 * Print some information about the controller 1459 */ 1460 static void 1461 twe_describe_controller(struct twe_softc *sc) 1462 { 1463 struct twe_param *p[6]; 1464 int rv = 0; 1465 uint8_t ports; 1466 1467 /* get the port count */ 1468 rv |= twe_param_get_1(sc, TWE_PARAM_CONTROLLER, 1469 TWE_PARAM_CONTROLLER_PortCount, &ports); 1470 1471 /* get version strings */ 1472 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_Mon, 1473 16, NULL, &p[0]); 1474 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_FW, 1475 16, NULL, &p[1]); 1476 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_BIOS, 1477 16, NULL, &p[2]); 1478 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_PCB, 1479 8, NULL, &p[3]); 1480 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_ATA, 1481 8, NULL, &p[4]); 1482 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_PCI, 1483 8, NULL, &p[5]); 1484 1485 if (rv) { 1486 /* some error occurred */ 1487 aprint_error("%s: failed to fetch version information\n", 1488 sc->sc_dv.dv_xname); 1489 return; 1490 } 1491 1492 aprint_normal("%s: %d ports, Firmware %.16s, BIOS %.16s\n", 1493 sc->sc_dv.dv_xname, ports, 1494 p[1]->tp_data, p[2]->tp_data); 1495 1496 aprint_verbose("%s: Monitor %.16s, PCB %.8s, Achip %.8s, Pchip %.8s\n", 1497 sc->sc_dv.dv_xname, 1498 p[0]->tp_data, p[3]->tp_data, 1499 p[4]->tp_data, p[5]->tp_data); 1500 1501 free(p[0], M_DEVBUF); 1502 free(p[1], M_DEVBUF); 1503 free(p[2], M_DEVBUF); 1504 free(p[3], M_DEVBUF); 1505 free(p[4], M_DEVBUF); 1506 free(p[5], M_DEVBUF); 1507 } 1508
Indexes created Wed Oct 01 07:09:59 GMT 2025