twe.c revision 1.45
1 /* $NetBSD: twe.c,v 1.45 2003/09/22 01:13:02 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran; and by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twe.c,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 /* 69 * Driver for the 3ware Escalade family of RAID controllers. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: twe.c,v 1.45 2003/09/22 01:13:02 thorpej Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/device.h> 79 #include <sys/queue.h> 80 #include <sys/proc.h> 81 #include <sys/buf.h> 82 #include <sys/endian.h> 83 #include <sys/malloc.h> 84 #include <sys/conf.h> 85 #include <sys/disk.h> 86 87 #include <uvm/uvm_extern.h> 88 89 #include <machine/bswap.h> 90 #include <machine/bus.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/twereg.h> 96 #include <dev/pci/twevar.h> 97 #include <dev/pci/tweio.h> 98 99 #define PCI_CBIO 0x10 100 101 static void twe_aen_handler(struct twe_ccb *, int); 102 static void twe_aen_enqueue(struct twe_softc *sc, uint16_t, int); 103 static uint16_t twe_aen_dequeue(struct twe_softc *); 104 105 static void twe_attach(struct device *, struct device *, void *); 106 static int twe_init_connection(struct twe_softc *); 107 static int twe_intr(void *); 108 static int twe_match(struct device *, struct cfdata *, void *); 109 static int twe_param_set(struct twe_softc *, int, int, size_t, void *); 110 static void twe_poll(struct twe_softc *); 111 static int twe_print(void *, const char *); 112 static int twe_reset(struct twe_softc *); 113 static int twe_submatch(struct device *, struct cfdata *, void *); 114 static int twe_status_check(struct twe_softc *, u_int); 115 static int twe_status_wait(struct twe_softc *, u_int, int); 116 static void twe_describe_controller(struct twe_softc *); 117 118 static inline u_int32_t twe_inl(struct twe_softc *, int); 119 static inline void twe_outl(struct twe_softc *, int, u_int32_t); 120 121 dev_type_open(tweopen); 122 dev_type_close(tweclose); 123 dev_type_ioctl(tweioctl); 124 125 const struct cdevsw twe_cdevsw = { 126 tweopen, tweclose, noread, nowrite, tweioctl, 127 nostop, notty, nopoll, nommap, 128 }; 129 130 extern struct cfdriver twe_cd; 131 132 CFATTACH_DECL(twe, sizeof(struct twe_softc), 133 twe_match, twe_attach, NULL, NULL); 134 135 /* 136 * Tables to convert numeric codes to strings. 137 */ 138 const struct twe_code_table twe_table_status[] = { 139 { 0x00, "successful completion" }, 140 141 /* info */ 142 { 0x42, "command in progress" }, 143 { 0x6c, "retrying interface CRC error from UDMA command" }, 144 145 /* warning */ 146 { 0x81, "redundant/inconsequential request ignored" }, 147 { 0x8e, "failed to write zeroes to LBA 0" }, 148 { 0x8f, "failed to profile TwinStor zones" }, 149 150 /* fatal */ 151 { 0xc1, "aborted due to system command or reconfiguration" }, 152 { 0xc4, "aborted" }, 153 { 0xc5, "access error" }, 154 { 0xc6, "access violation" }, 155 { 0xc7, "device failure" }, /* high byte may be port # */ 156 { 0xc8, "controller error" }, 157 { 0xc9, "timed out" }, 158 { 0xcb, "invalid unit number" }, 159 { 0xcf, "unit not available" }, 160 { 0xd2, "undefined opcode" }, 161 { 0xdb, "request incompatible with unit" }, 162 { 0xdc, "invalid request" }, 163 { 0xff, "firmware error, reset requested" }, 164 165 { 0, NULL } 166 }; 167 168 const struct twe_code_table twe_table_unitstate[] = { 169 { TWE_PARAM_UNITSTATUS_Normal, "Normal" }, 170 { TWE_PARAM_UNITSTATUS_Initialising, "Initializing" }, 171 { TWE_PARAM_UNITSTATUS_Degraded, "Degraded" }, 172 { TWE_PARAM_UNITSTATUS_Rebuilding, "Rebuilding" }, 173 { TWE_PARAM_UNITSTATUS_Verifying, "Verifying" }, 174 { TWE_PARAM_UNITSTATUS_Corrupt, "Corrupt" }, 175 { TWE_PARAM_UNITSTATUS_Missing, "Missing" }, 176 177 { 0, NULL } 178 }; 179 180 const struct twe_code_table twe_table_unittype[] = { 181 /* array descriptor configuration */ 182 { TWE_AD_CONFIG_RAID0, "RAID0" }, 183 { TWE_AD_CONFIG_RAID1, "RAID1" }, 184 { TWE_AD_CONFIG_TwinStor, "TwinStor" }, 185 { TWE_AD_CONFIG_RAID5, "RAID5" }, 186 { TWE_AD_CONFIG_RAID10, "RAID10" }, 187 188 { 0, NULL } 189 }; 190 191 const struct twe_code_table twe_table_stripedepth[] = { 192 { TWE_AD_STRIPE_4k, "4K" }, 193 { TWE_AD_STRIPE_8k, "8K" }, 194 { TWE_AD_STRIPE_16k, "16K" }, 195 { TWE_AD_STRIPE_32k, "32K" }, 196 { TWE_AD_STRIPE_64k, "64K" }, 197 198 { 0, NULL } 199 }; 200 201 /* 202 * Asynchronous event notification messages are qualified: 203 * a - not unit/port specific 204 * u - unit specific 205 * p - port specific 206 */ 207 const struct twe_code_table twe_table_aen[] = { 208 { 0x00, "a queue empty" }, 209 { 0x01, "a soft reset" }, 210 { 0x02, "u degraded mode" }, 211 { 0x03, "a controller error" }, 212 { 0x04, "u rebuild fail" }, 213 { 0x05, "u rebuild done" }, 214 { 0x06, "u incomplete unit" }, 215 { 0x07, "u initialization done" }, 216 { 0x08, "u unclean shutdown detected" }, 217 { 0x09, "p drive timeout" }, 218 { 0x0a, "p drive error" }, 219 { 0x0b, "u rebuild started" }, 220 { 0x0c, "u initialization started" }, 221 { 0x0d, "u logical unit deleted" }, 222 { 0x0f, "p SMART threshold exceeded" }, 223 { 0x15, "a table undefined" }, /* XXX: Not in FreeBSD's table */ 224 { 0x21, "p ATA UDMA downgrade" }, 225 { 0x22, "p ATA UDMA upgrade" }, 226 { 0x23, "p sector repair occurred" }, 227 { 0x24, "a SBUF integrity check failure" }, 228 { 0x25, "p lost cached write" }, 229 { 0x26, "p drive ECC error detected" }, 230 { 0x27, "p DCB checksum error" }, 231 { 0x28, "p DCB unsupported version" }, 232 { 0x29, "u verify started" }, 233 { 0x2a, "u verify failed" }, 234 { 0x2b, "u verify complete" }, 235 { 0x2c, "p overwrote bad sector during rebuild" }, 236 { 0x2d, "p encountered bad sector during rebuild" }, 237 { 0x2e, "p replacement drive too small" }, 238 { 0x2f, "u array not previously initialized" }, 239 { 0x30, "p drive not supported" }, 240 { 0xff, "a aen queue full" }, 241 242 { 0, NULL }, 243 }; 244 245 const char * 246 twe_describe_code(const struct twe_code_table *table, uint32_t code) 247 { 248 249 for (; table->string != NULL; table++) { 250 if (table->code == code) 251 return (table->string); 252 } 253 return (NULL); 254 } 255 256 static inline u_int32_t 257 twe_inl(struct twe_softc *sc, int off) 258 { 259 260 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 261 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 262 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, off)); 263 } 264 265 static inline void 266 twe_outl(struct twe_softc *sc, int off, u_int32_t val) 267 { 268 269 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 270 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 271 BUS_SPACE_BARRIER_WRITE); 272 } 273 274 /* 275 * Match a supported board. 276 */ 277 static int 278 twe_match(struct device *parent, struct cfdata *cfdata, void *aux) 279 { 280 struct pci_attach_args *pa; 281 282 pa = aux; 283 284 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3WARE && 285 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE || 286 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE_ASIC)); 287 } 288 289 /* 290 * Attach a supported board. 291 * 292 * XXX This doesn't fail gracefully. 293 */ 294 static void 295 twe_attach(struct device *parent, struct device *self, void *aux) 296 { 297 struct pci_attach_args *pa; 298 struct twe_softc *sc; 299 pci_chipset_tag_t pc; 300 pci_intr_handle_t ih; 301 pcireg_t csr; 302 const char *intrstr; 303 int size, i, rv, rseg; 304 size_t max_segs, max_xfer; 305 struct twe_param *dtp, *atp; 306 struct twe_array_descriptor *ad; 307 struct twe_drive *td; 308 bus_dma_segment_t seg; 309 struct twe_cmd *tc; 310 struct twe_attach_args twea; 311 struct twe_ccb *ccb; 312 uint16_t dsize; 313 314 sc = (struct twe_softc *)self; 315 pa = aux; 316 pc = pa->pa_pc; 317 sc->sc_dmat = pa->pa_dmat; 318 SIMPLEQ_INIT(&sc->sc_ccb_queue); 319 SLIST_INIT(&sc->sc_ccb_freelist); 320 321 aprint_naive(": RAID controller\n"); 322 aprint_normal(": 3ware Escalade\n"); 323 324 ccb = malloc(sizeof(*ccb) * TWE_MAX_QUEUECNT, M_DEVBUF, M_NOWAIT); 325 if (ccb == NULL) { 326 aprint_error("%s: unable to allocate memory for ccbs\n", 327 sc->sc_dv.dv_xname); 328 return; 329 } 330 331 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 332 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 333 aprint_error("%s: can't map i/o space\n", sc->sc_dv.dv_xname); 334 return; 335 } 336 337 /* Enable the device. */ 338 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 339 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 340 csr | PCI_COMMAND_MASTER_ENABLE); 341 342 /* Map and establish the interrupt. */ 343 if (pci_intr_map(pa, &ih)) { 344 aprint_error("%s: can't map interrupt\n", sc->sc_dv.dv_xname); 345 return; 346 } 347 348 intrstr = pci_intr_string(pc, ih); 349 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, twe_intr, sc); 350 if (sc->sc_ih == NULL) { 351 aprint_error("%s: can't establish interrupt%s%s\n", 352 sc->sc_dv.dv_xname, 353 (intrstr) ? " at " : "", 354 (intrstr) ? intrstr : ""); 355 return; 356 } 357 358 if (intrstr != NULL) 359 aprint_normal("%s: interrupting at %s\n", 360 sc->sc_dv.dv_xname, intrstr); 361 362 /* 363 * Allocate and initialise the command blocks and CCBs. 364 */ 365 size = sizeof(struct twe_cmd) * TWE_MAX_QUEUECNT; 366 367 if ((rv = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 1, 368 &rseg, BUS_DMA_NOWAIT)) != 0) { 369 aprint_error("%s: unable to allocate commands, rv = %d\n", 370 sc->sc_dv.dv_xname, rv); 371 return; 372 } 373 374 if ((rv = bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 375 (caddr_t *)&sc->sc_cmds, 376 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 377 aprint_error("%s: unable to map commands, rv = %d\n", 378 sc->sc_dv.dv_xname, rv); 379 return; 380 } 381 382 if ((rv = bus_dmamap_create(sc->sc_dmat, size, size, 1, 0, 383 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 384 aprint_error("%s: unable to create command DMA map, rv = %d\n", 385 sc->sc_dv.dv_xname, rv); 386 return; 387 } 388 389 if ((rv = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cmds, 390 size, NULL, BUS_DMA_NOWAIT)) != 0) { 391 aprint_error("%s: unable to load command DMA map, rv = %d\n", 392 sc->sc_dv.dv_xname, rv); 393 return; 394 } 395 396 sc->sc_cmds_paddr = sc->sc_dmamap->dm_segs[0].ds_addr; 397 memset(sc->sc_cmds, 0, size); 398 399 sc->sc_ccbs = ccb; 400 tc = (struct twe_cmd *)sc->sc_cmds; 401 max_segs = twe_get_maxsegs(); 402 max_xfer = twe_get_maxxfer(max_segs); 403 404 for (i = 0; i < TWE_MAX_QUEUECNT; i++, tc++, ccb++) { 405 ccb->ccb_cmd = tc; 406 ccb->ccb_cmdid = i; 407 ccb->ccb_flags = 0; 408 rv = bus_dmamap_create(sc->sc_dmat, max_xfer, 409 max_segs, PAGE_SIZE, 0, 410 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 411 &ccb->ccb_dmamap_xfer); 412 if (rv != 0) { 413 aprint_error("%s: can't create dmamap, rv = %d\n", 414 sc->sc_dv.dv_xname, rv); 415 return; 416 } 417 /* Save one CCB for parameter retrieval. */ 418 if (i != 0) 419 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, 420 ccb_chain.slist); 421 } 422 423 /* Wait for the controller to become ready. */ 424 if (twe_status_wait(sc, TWE_STS_MICROCONTROLLER_READY, 6)) { 425 aprint_error("%s: microcontroller not ready\n", 426 sc->sc_dv.dv_xname); 427 return; 428 } 429 430 twe_outl(sc, TWE_REG_CTL, TWE_CTL_DISABLE_INTRS); 431 432 /* Reset the controller. */ 433 if (twe_reset(sc)) { 434 aprint_error("%s: reset failed\n", sc->sc_dv.dv_xname); 435 return; 436 } 437 438 /* Find attached units. */ 439 rv = twe_param_get(sc, TWE_PARAM_UNITSUMMARY, 440 TWE_PARAM_UNITSUMMARY_Status, TWE_MAX_UNITS, NULL, &dtp); 441 if (rv != 0) { 442 aprint_error("%s: can't detect attached units (%d)\n", 443 sc->sc_dv.dv_xname, rv); 444 return; 445 } 446 447 /* For each detected unit, collect size and store in an array. */ 448 for (i = 0, sc->sc_nunits = 0; i < TWE_MAX_UNITS; i++) { 449 td = &sc->sc_units[i]; 450 451 /* Unit present? */ 452 if ((dtp->tp_data[i] & TWE_PARAM_UNITSTATUS_Online) == 0) { 453 td->td_size = 0; 454 td->td_type = 0; 455 td->td_stripe = 0; 456 continue; 457 } 458 459 rv = twe_param_get_2(sc, TWE_PARAM_UNITINFO + i, 460 TWE_PARAM_UNITINFO_DescriptorSize, &dsize); 461 if (rv != 0) { 462 aprint_error("%s: error %d fetching descriptor size " 463 "for unit %d\n", sc->sc_dv.dv_xname, rv, i); 464 td->td_size = 0; 465 td->td_type = 0; 466 td->td_stripe = 0; 467 continue; 468 } 469 470 rv = twe_param_get(sc, TWE_PARAM_UNITINFO + i, 471 TWE_PARAM_UNITINFO_Descriptor, dsize - 3, NULL, &atp); 472 if (rv != 0) { 473 aprint_error("%s: error %d fetching array descriptor " 474 "for unit %d\n", sc->sc_dv.dv_xname, rv, i); 475 td->td_size = 0; 476 td->td_type = 0; 477 td->td_stripe = 0; 478 continue; 479 } 480 ad = (struct twe_array_descriptor *)atp->tp_data; 481 td->td_type = ad->configuration; 482 td->td_stripe = ad->stripe_size; 483 free(atp, M_DEVBUF); 484 485 rv = twe_param_get_4(sc, TWE_PARAM_UNITINFO + i, 486 TWE_PARAM_UNITINFO_Capacity, &td->td_size); 487 if (rv != 0) { 488 aprint_error( 489 "%s: error %d fetching capacity for unit %d\n", 490 sc->sc_dv.dv_xname, rv, i); 491 td->td_size = 0; 492 td->td_type = 0; 493 td->td_stripe = 0; 494 continue; 495 } 496 497 sc->sc_nunits++; 498 } 499 free(dtp, M_DEVBUF); 500 501 /* Initialise connection with controller and enable interrupts. */ 502 twe_init_connection(sc); 503 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR | 504 TWE_CTL_UNMASK_RESP_INTR | 505 TWE_CTL_ENABLE_INTRS); 506 507 twe_describe_controller(sc); 508 509 /* Attach sub-devices. */ 510 for (i = 0; i < TWE_MAX_UNITS; i++) { 511 td = &sc->sc_units[i]; 512 if (td->td_size == 0) 513 continue; 514 twea.twea_unit = i; 515 td->td_dev = config_found_sm(&sc->sc_dv, &twea, twe_print, 516 twe_submatch); 517 } 518 } 519 520 /* 521 * Reset the controller. Currently only useful at attach time; must be 522 * called with interrupts blocked. 523 */ 524 static int 525 twe_reset(struct twe_softc *sc) 526 { 527 uint16_t aen; 528 u_int status; 529 volatile u_int32_t junk; 530 int got, rv; 531 532 /* Issue a soft reset. */ 533 twe_outl(sc, TWE_REG_CTL, TWE_CTL_ISSUE_SOFT_RESET | 534 TWE_CTL_CLEAR_HOST_INTR | 535 TWE_CTL_CLEAR_ATTN_INTR | 536 TWE_CTL_MASK_CMD_INTR | 537 TWE_CTL_MASK_RESP_INTR | 538 TWE_CTL_CLEAR_ERROR_STS | 539 TWE_CTL_DISABLE_INTRS); 540 541 /* Wait for attention... */ 542 if (twe_status_wait(sc, TWE_STS_ATTN_INTR, 15)) { 543 printf("%s: no attention interrupt\n", 544 sc->sc_dv.dv_xname); 545 return (-1); 546 } 547 548 /* ...and ACK it. */ 549 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 550 551 /* 552 * Pull AENs out of the controller; look for a soft reset AEN. 553 * Open code this, since we want to detect reset even if the 554 * queue for management tools is full. 555 */ 556 for (got = 0;;) { 557 rv = twe_param_get_2(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 558 &aen); 559 if (rv != 0) 560 printf("%s: error %d while draining event queue\n", 561 sc->sc_dv.dv_xname, rv); 562 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) 563 break; 564 if (TWE_AEN_CODE(aen) == TWE_AEN_SOFT_RESET) 565 got = 1; 566 twe_aen_enqueue(sc, aen, 1); 567 } 568 569 if (!got) { 570 printf("%s: reset not reported\n", sc->sc_dv.dv_xname); 571 return (-1); 572 } 573 574 /* Check controller status. */ 575 status = twe_inl(sc, TWE_REG_STS); 576 if (twe_status_check(sc, status)) { 577 printf("%s: controller errors detected\n", 578 sc->sc_dv.dv_xname); 579 return (-1); 580 } 581 582 /* Drain the response queue. */ 583 for (;;) { 584 status = twe_inl(sc, TWE_REG_STS); 585 if (twe_status_check(sc, status) != 0) { 586 printf("%s: can't drain response queue\n", 587 sc->sc_dv.dv_xname); 588 return (-1); 589 } 590 if ((status & TWE_STS_RESP_QUEUE_EMPTY) != 0) 591 break; 592 junk = twe_inl(sc, TWE_REG_RESP_QUEUE); 593 } 594 595 return (0); 596 } 597 598 /* 599 * Print autoconfiguration message for a sub-device. 600 */ 601 static int 602 twe_print(void *aux, const char *pnp) 603 { 604 struct twe_attach_args *twea; 605 606 twea = aux; 607 608 if (pnp != NULL) 609 aprint_normal("block device at %s", pnp); 610 aprint_normal(" unit %d", twea->twea_unit); 611 return (UNCONF); 612 } 613 614 /* 615 * Match a sub-device. 616 */ 617 static int 618 twe_submatch(struct device *parent, struct cfdata *cf, void *aux) 619 { 620 struct twe_attach_args *twea; 621 622 twea = aux; 623 624 if (cf->tweacf_unit != TWECF_UNIT_DEFAULT && 625 cf->tweacf_unit != twea->twea_unit) 626 return (0); 627 628 return (config_match(parent, cf, aux)); 629 } 630 631 /* 632 * Interrupt service routine. 633 */ 634 static int 635 twe_intr(void *arg) 636 { 637 struct twe_softc *sc; 638 u_int status; 639 int caught, rv; 640 641 sc = arg; 642 caught = 0; 643 status = twe_inl(sc, TWE_REG_STS); 644 twe_status_check(sc, status); 645 646 /* Host interrupts - purpose unknown. */ 647 if ((status & TWE_STS_HOST_INTR) != 0) { 648 #ifdef DEBUG 649 printf("%s: host interrupt\n", sc->sc_dv.dv_xname); 650 #endif 651 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_HOST_INTR); 652 caught = 1; 653 } 654 655 /* 656 * Attention interrupts, signalled when a controller or child device 657 * state change has occurred. 658 */ 659 if ((status & TWE_STS_ATTN_INTR) != 0) { 660 rv = twe_param_get(sc, TWE_PARAM_AEN, 661 TWE_PARAM_AEN_UnitCode, 2, twe_aen_handler, 662 NULL); 663 if (rv != 0) 664 printf("%s: unable to retrieve AEN (%d)\n", 665 sc->sc_dv.dv_xname, rv); 666 else 667 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 668 caught = 1; 669 } 670 671 /* 672 * Command interrupts, signalled when the controller can accept more 673 * commands. We don't use this; instead, we try to submit commands 674 * when we receive them, and when other commands have completed. 675 * Mask it so we don't get another one. 676 */ 677 if ((status & TWE_STS_CMD_INTR) != 0) { 678 #ifdef DEBUG 679 printf("%s: command interrupt\n", sc->sc_dv.dv_xname); 680 #endif 681 twe_outl(sc, TWE_REG_CTL, TWE_CTL_MASK_CMD_INTR); 682 caught = 1; 683 } 684 685 if ((status & TWE_STS_RESP_INTR) != 0) { 686 twe_poll(sc); 687 caught = 1; 688 } 689 690 return (caught); 691 } 692 693 /* 694 * Handle an AEN returned by the controller. 695 */ 696 static void 697 twe_aen_handler(struct twe_ccb *ccb, int error) 698 { 699 struct twe_softc *sc; 700 struct twe_param *tp; 701 uint16_t aen; 702 int rv; 703 704 sc = (struct twe_softc *)ccb->ccb_tx.tx_dv; 705 tp = ccb->ccb_tx.tx_context; 706 twe_ccb_unmap(sc, ccb); 707 708 if (error) { 709 printf("%s: error retrieving AEN\n", sc->sc_dv.dv_xname); 710 aen = TWE_AEN_QUEUE_EMPTY; 711 } else 712 aen = le16toh(*(u_int16_t *)tp->tp_data); 713 free(tp, M_DEVBUF); 714 twe_ccb_free(sc, ccb); 715 716 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) { 717 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 718 return; 719 } 720 721 twe_aen_enqueue(sc, aen, 0); 722 723 /* 724 * Chain another retrieval in case interrupts have been 725 * coalesced. 726 */ 727 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 2, 728 twe_aen_handler, NULL); 729 if (rv != 0) 730 printf("%s: unable to retrieve AEN (%d)\n", 731 sc->sc_dv.dv_xname, rv); 732 } 733 734 static void 735 twe_aen_enqueue(struct twe_softc *sc, uint16_t aen, int quiet) 736 { 737 const char *str, *msg; 738 int s, next, nextnext; 739 740 /* 741 * First report the AEN on the console. Maybe. 742 */ 743 if (! quiet) { 744 str = twe_describe_code(twe_table_aen, TWE_AEN_CODE(aen)); 745 if (str == NULL) { 746 printf("%s: unknown AEN 0x%04x\n", 747 sc->sc_dv.dv_xname, aen); 748 } else { 749 msg = str + 2; 750 switch (*str) { 751 case 'u': 752 printf("%s: unit %d: %s\n", 753 sc->sc_dv.dv_xname, TWE_AEN_UNIT(aen), msg); 754 break; 755 756 case 'p': 757 printf("%s: port %d: %s\n", 758 sc->sc_dv.dv_xname, TWE_AEN_UNIT(aen), msg); 759 break; 760 761 default: 762 printf("%s: %s\n", sc->sc_dv.dv_xname, msg); 763 } 764 } 765 } 766 767 /* Now enqueue the AEN for mangement tools. */ 768 s = splbio(); 769 770 next = (sc->sc_aen_head + 1) % TWE_AEN_Q_LENGTH; 771 nextnext = (sc->sc_aen_head + 2) % TWE_AEN_Q_LENGTH; 772 773 /* 774 * If this is the last free slot, then queue up a "queue 775 * full" message. 776 */ 777 if (nextnext == sc->sc_aen_tail) 778 aen = TWE_AEN_QUEUE_FULL; 779 780 if (next != sc->sc_aen_tail) { 781 sc->sc_aen_queue[sc->sc_aen_head] = aen; 782 sc->sc_aen_head = next; 783 } 784 785 if (sc->sc_flags & TWEF_AENQ_WAIT) { 786 sc->sc_flags &= ~TWEF_AENQ_WAIT; 787 wakeup(&sc->sc_aen_queue); 788 } 789 790 splx(s); 791 } 792 793 /* NOTE: Must be called at splbio(). */ 794 static uint16_t 795 twe_aen_dequeue(struct twe_softc *sc) 796 { 797 uint16_t aen; 798 799 if (sc->sc_aen_tail == sc->sc_aen_head) 800 aen = TWE_AEN_QUEUE_EMPTY; 801 else { 802 aen = sc->sc_aen_queue[sc->sc_aen_tail]; 803 sc->sc_aen_tail = (sc->sc_aen_tail + 1) & TWE_AEN_Q_LENGTH; 804 } 805 806 return (aen); 807 } 808 809 /* 810 * These are short-hand functions that execute TWE_OP_GET_PARAM to 811 * fetch 1, 2, and 4 byte parameter values, respectively. 812 */ 813 int 814 twe_param_get_1(struct twe_softc *sc, int table_id, int param_id, 815 uint8_t *valp) 816 { 817 struct twe_param *tp; 818 int rv; 819 820 rv = twe_param_get(sc, table_id, param_id, 1, NULL, &tp); 821 if (rv != 0) 822 return (rv); 823 *valp = *(uint8_t *)tp->tp_data; 824 free(tp, M_DEVBUF); 825 return (0); 826 } 827 828 int 829 twe_param_get_2(struct twe_softc *sc, int table_id, int param_id, 830 uint16_t *valp) 831 { 832 struct twe_param *tp; 833 int rv; 834 835 rv = twe_param_get(sc, table_id, param_id, 2, NULL, &tp); 836 if (rv != 0) 837 return (rv); 838 *valp = le16toh(*(uint16_t *)tp->tp_data); 839 free(tp, M_DEVBUF); 840 return (0); 841 } 842 843 int 844 twe_param_get_4(struct twe_softc *sc, int table_id, int param_id, 845 uint32_t *valp) 846 { 847 struct twe_param *tp; 848 int rv; 849 850 rv = twe_param_get(sc, table_id, param_id, 4, NULL, &tp); 851 if (rv != 0) 852 return (rv); 853 *valp = le32toh(*(uint32_t *)tp->tp_data); 854 free(tp, M_DEVBUF); 855 return (0); 856 } 857 858 /* 859 * Execute a TWE_OP_GET_PARAM command. If a callback function is provided, 860 * it will be called with generated context when the command has completed. 861 * If no callback is provided, the command will be executed synchronously 862 * and a pointer to a buffer containing the data returned. 863 * 864 * The caller or callback is responsible for freeing the buffer. 865 */ 866 int 867 twe_param_get(struct twe_softc *sc, int table_id, int param_id, size_t size, 868 void (*func)(struct twe_ccb *, int), struct twe_param **pbuf) 869 { 870 struct twe_ccb *ccb; 871 struct twe_cmd *tc; 872 struct twe_param *tp; 873 int rv, s; 874 875 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 876 if (tp == NULL) 877 return ENOMEM; 878 879 rv = twe_ccb_alloc(sc, &ccb, 880 TWE_CCB_PARAM | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 881 if (rv != 0) 882 goto done; 883 884 ccb->ccb_data = tp; 885 ccb->ccb_datasize = TWE_SECTOR_SIZE; 886 ccb->ccb_tx.tx_handler = func; 887 ccb->ccb_tx.tx_context = tp; 888 ccb->ccb_tx.tx_dv = &sc->sc_dv; 889 890 tc = ccb->ccb_cmd; 891 tc->tc_size = 2; 892 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 893 tc->tc_unit = 0; 894 tc->tc_count = htole16(1); 895 896 /* Fill in the outbound parameter data. */ 897 tp->tp_table_id = htole16(table_id); 898 tp->tp_param_id = param_id; 899 tp->tp_param_size = size; 900 901 /* Map the transfer. */ 902 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 903 twe_ccb_free(sc, ccb); 904 goto done; 905 } 906 907 /* Submit the command and either wait or let the callback handle it. */ 908 if (func == NULL) { 909 s = splbio(); 910 rv = twe_ccb_poll(sc, ccb, 5); 911 twe_ccb_unmap(sc, ccb); 912 twe_ccb_free(sc, ccb); 913 splx(s); 914 } else { 915 #ifdef DEBUG 916 if (pbuf != NULL) 917 panic("both func and pbuf defined"); 918 #endif 919 twe_ccb_enqueue(sc, ccb); 920 return 0; 921 } 922 923 done: 924 if (pbuf == NULL || rv != 0) 925 free(tp, M_DEVBUF); 926 else if (pbuf != NULL && rv == 0) 927 *pbuf = tp; 928 return rv; 929 } 930 931 /* 932 * Execute a TWE_OP_SET_PARAM command. 933 */ 934 static int 935 twe_param_set(struct twe_softc *sc, int table_id, int param_id, size_t size, 936 void *buf) 937 { 938 struct twe_ccb *ccb; 939 struct twe_cmd *tc; 940 struct twe_param *tp; 941 int rv, s; 942 943 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 944 if (tp == NULL) 945 return ENOMEM; 946 947 rv = twe_ccb_alloc(sc, &ccb, 948 TWE_CCB_PARAM | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 949 if (rv != 0) 950 goto done; 951 952 ccb->ccb_data = tp; 953 ccb->ccb_datasize = TWE_SECTOR_SIZE; 954 ccb->ccb_tx.tx_handler = 0; 955 ccb->ccb_tx.tx_context = tp; 956 ccb->ccb_tx.tx_dv = &sc->sc_dv; 957 958 tc = ccb->ccb_cmd; 959 tc->tc_size = 2; 960 tc->tc_opcode = TWE_OP_SET_PARAM | (tc->tc_size << 5); 961 tc->tc_unit = 0; 962 tc->tc_count = htole16(1); 963 964 /* Fill in the outbound parameter data. */ 965 tp->tp_table_id = htole16(table_id); 966 tp->tp_param_id = param_id; 967 tp->tp_param_size = size; 968 memcpy(tp->tp_data, buf, size); 969 970 /* Map the transfer. */ 971 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 972 twe_ccb_free(sc, ccb); 973 goto done; 974 } 975 976 /* Submit the command and wait. */ 977 s = splbio(); 978 rv = twe_ccb_poll(sc, ccb, 5); 979 twe_ccb_unmap(sc, ccb); 980 twe_ccb_free(sc, ccb); 981 splx(s); 982 done: 983 free(tp, M_DEVBUF); 984 return (rv); 985 } 986 987 /* 988 * Execute a TWE_OP_INIT_CONNECTION command. Return non-zero on error. 989 * Must be called with interrupts blocked. 990 */ 991 static int 992 twe_init_connection(struct twe_softc *sc) 993 /*###762 [cc] warning: `twe_init_connection' was used with no prototype before its definition%%%*/ 994 /*###762 [cc] warning: `twe_init_connection' was declared implicitly `extern' and later `static'%%%*/ 995 { 996 struct twe_ccb *ccb; 997 struct twe_cmd *tc; 998 int rv; 999 1000 if ((rv = twe_ccb_alloc(sc, &ccb, 0)) != 0) 1001 return (rv); 1002 1003 /* Build the command. */ 1004 tc = ccb->ccb_cmd; 1005 tc->tc_size = 3; 1006 tc->tc_opcode = TWE_OP_INIT_CONNECTION; 1007 tc->tc_unit = 0; 1008 tc->tc_count = htole16(TWE_MAX_CMDS); 1009 tc->tc_args.init_connection.response_queue_pointer = 0; 1010 1011 /* Submit the command for immediate execution. */ 1012 rv = twe_ccb_poll(sc, ccb, 5); 1013 twe_ccb_free(sc, ccb); 1014 return (rv); 1015 } 1016 1017 /* 1018 * Poll the controller for completed commands. Must be called with 1019 * interrupts blocked. 1020 */ 1021 static void 1022 twe_poll(struct twe_softc *sc) 1023 { 1024 struct twe_ccb *ccb; 1025 int found; 1026 u_int status, cmdid; 1027 1028 found = 0; 1029 1030 for (;;) { 1031 status = twe_inl(sc, TWE_REG_STS); 1032 twe_status_check(sc, status); 1033 1034 if ((status & TWE_STS_RESP_QUEUE_EMPTY)) 1035 break; 1036 1037 found = 1; 1038 cmdid = twe_inl(sc, TWE_REG_RESP_QUEUE); 1039 cmdid = (cmdid & TWE_RESP_MASK) >> TWE_RESP_SHIFT; 1040 if (cmdid >= TWE_MAX_QUEUECNT) { 1041 printf("%s: bad completion\n", sc->sc_dv.dv_xname); 1042 continue; 1043 } 1044 1045 ccb = sc->sc_ccbs + cmdid; 1046 if ((ccb->ccb_flags & TWE_CCB_ACTIVE) == 0) { 1047 printf("%s: bad completion (not active)\n", 1048 sc->sc_dv.dv_xname); 1049 continue; 1050 } 1051 ccb->ccb_flags ^= TWE_CCB_COMPLETE | TWE_CCB_ACTIVE; 1052 1053 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1054 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, 1055 sizeof(struct twe_cmd), 1056 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1057 1058 /* Pass notification to upper layers. */ 1059 if (ccb->ccb_tx.tx_handler != NULL) 1060 (*ccb->ccb_tx.tx_handler)(ccb, 1061 ccb->ccb_cmd->tc_status != 0 ? EIO : 0); 1062 } 1063 1064 /* If any commands have completed, run the software queue. */ 1065 if (found) 1066 twe_ccb_enqueue(sc, NULL); 1067 } 1068 1069 /* 1070 * Wait for `status' to be set in the controller status register. Return 1071 * zero if found, non-zero if the operation timed out. 1072 */ 1073 static int 1074 twe_status_wait(struct twe_softc *sc, u_int32_t status, int timo) 1075 { 1076 1077 for (timo *= 10; timo != 0; timo--) { 1078 if ((twe_inl(sc, TWE_REG_STS) & status) == status) 1079 break; 1080 delay(100000); 1081 } 1082 1083 return (timo == 0); 1084 } 1085 1086 /* 1087 * Complain if the status bits aren't what we expect. 1088 */ 1089 static int 1090 twe_status_check(struct twe_softc *sc, u_int status) 1091 { 1092 int rv; 1093 1094 rv = 0; 1095 1096 if ((status & TWE_STS_EXPECTED_BITS) != TWE_STS_EXPECTED_BITS) { 1097 printf("%s: missing status bits: 0x%08x\n", sc->sc_dv.dv_xname, 1098 status & ~TWE_STS_EXPECTED_BITS); 1099 rv = -1; 1100 } 1101 1102 if ((status & TWE_STS_UNEXPECTED_BITS) != 0) { 1103 printf("%s: unexpected status bits: 0x%08x\n", 1104 sc->sc_dv.dv_xname, status & TWE_STS_UNEXPECTED_BITS); 1105 rv = -1; 1106 } 1107 1108 return (rv); 1109 } 1110 1111 /* 1112 * Allocate and initialise a CCB. 1113 */ 1114 int 1115 twe_ccb_alloc(struct twe_softc *sc, struct twe_ccb **ccbp, int flags) 1116 { 1117 struct twe_cmd *tc; 1118 struct twe_ccb *ccb; 1119 int s; 1120 1121 s = splbio(); 1122 if ((flags & TWE_CCB_PARAM) != 0) 1123 ccb = sc->sc_ccbs; 1124 else { 1125 /* Allocate a CCB and command block. */ 1126 if (SLIST_FIRST(&sc->sc_ccb_freelist) == NULL) { 1127 splx(s); 1128 return (EAGAIN); 1129 } 1130 ccb = SLIST_FIRST(&sc->sc_ccb_freelist); 1131 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 1132 } 1133 #ifdef DIAGNOSTIC 1134 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 1135 panic("twe_ccb_alloc: CCB already allocated"); 1136 flags |= TWE_CCB_ALLOCED; 1137 #endif 1138 splx(s); 1139 1140 /* Initialise some fields and return. */ 1141 ccb->ccb_tx.tx_handler = NULL; 1142 ccb->ccb_flags = flags; 1143 tc = ccb->ccb_cmd; 1144 tc->tc_status = 0; 1145 tc->tc_flags = 0; 1146 tc->tc_cmdid = ccb->ccb_cmdid; 1147 *ccbp = ccb; 1148 1149 return (0); 1150 } 1151 1152 /* 1153 * Free a CCB. 1154 */ 1155 void 1156 twe_ccb_free(struct twe_softc *sc, struct twe_ccb *ccb) 1157 { 1158 int s; 1159 1160 s = splbio(); 1161 if ((ccb->ccb_flags & TWE_CCB_PARAM) == 0) 1162 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, ccb_chain.slist); 1163 ccb->ccb_flags = 0; 1164 splx(s); 1165 } 1166 1167 /* 1168 * Map the specified CCB's command block and data buffer (if any) into 1169 * controller visible space. Perform DMA synchronisation. 1170 */ 1171 int 1172 twe_ccb_map(struct twe_softc *sc, struct twe_ccb *ccb) 1173 { 1174 struct twe_cmd *tc; 1175 int flags, nsegs, i, s, rv; 1176 void *data; 1177 1178 /* 1179 * The data as a whole must be 512-byte aligned. 1180 */ 1181 if (((u_long)ccb->ccb_data & (TWE_ALIGNMENT - 1)) != 0) { 1182 s = splvm(); 1183 /* XXX */ 1184 ccb->ccb_abuf = uvm_km_kmemalloc(kmem_map, NULL, 1185 ccb->ccb_datasize, UVM_KMF_NOWAIT); 1186 splx(s); 1187 data = (void *)ccb->ccb_abuf; 1188 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1189 memcpy(data, ccb->ccb_data, ccb->ccb_datasize); 1190 } else { 1191 ccb->ccb_abuf = (vaddr_t)0; 1192 data = ccb->ccb_data; 1193 } 1194 1195 /* 1196 * Map the data buffer into bus space and build the S/G list. 1197 */ 1198 rv = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap_xfer, data, 1199 ccb->ccb_datasize, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1200 ((ccb->ccb_flags & TWE_CCB_DATA_IN) ? 1201 BUS_DMA_READ : BUS_DMA_WRITE)); 1202 if (rv != 0) { 1203 if (ccb->ccb_abuf != (vaddr_t)0) { 1204 s = splvm(); 1205 /* XXX */ 1206 uvm_km_free(kmem_map, ccb->ccb_abuf, 1207 ccb->ccb_datasize); 1208 splx(s); 1209 } 1210 return (rv); 1211 } 1212 1213 nsegs = ccb->ccb_dmamap_xfer->dm_nsegs; 1214 tc = ccb->ccb_cmd; 1215 tc->tc_size += 2 * nsegs; 1216 1217 /* The location of the S/G list is dependant upon command type. */ 1218 switch (tc->tc_opcode >> 5) { 1219 case 2: 1220 for (i = 0; i < nsegs; i++) { 1221 tc->tc_args.param.sgl[i].tsg_address = 1222 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 1223 tc->tc_args.param.sgl[i].tsg_length = 1224 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 1225 } 1226 /* XXX Needed? */ 1227 for (; i < TWE_SG_SIZE; i++) { 1228 tc->tc_args.param.sgl[i].tsg_address = 0; 1229 tc->tc_args.param.sgl[i].tsg_length = 0; 1230 } 1231 break; 1232 case 3: 1233 for (i = 0; i < nsegs; i++) { 1234 tc->tc_args.io.sgl[i].tsg_address = 1235 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 1236 tc->tc_args.io.sgl[i].tsg_length = 1237 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 1238 } 1239 /* XXX Needed? */ 1240 for (; i < TWE_SG_SIZE; i++) { 1241 tc->tc_args.io.sgl[i].tsg_address = 0; 1242 tc->tc_args.io.sgl[i].tsg_length = 0; 1243 } 1244 break; 1245 #ifdef DEBUG 1246 default: 1247 panic("twe_ccb_map: oops"); 1248 #endif 1249 } 1250 1251 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1252 flags = BUS_DMASYNC_PREREAD; 1253 else 1254 flags = 0; 1255 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1256 flags |= BUS_DMASYNC_PREWRITE; 1257 1258 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 1259 ccb->ccb_datasize, flags); 1260 return (0); 1261 } 1262 1263 /* 1264 * Unmap the specified CCB's command block and data buffer (if any) and 1265 * perform DMA synchronisation. 1266 */ 1267 void 1268 twe_ccb_unmap(struct twe_softc *sc, struct twe_ccb *ccb) 1269 { 1270 int flags, s; 1271 1272 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1273 flags = BUS_DMASYNC_POSTREAD; 1274 else 1275 flags = 0; 1276 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1277 flags |= BUS_DMASYNC_POSTWRITE; 1278 1279 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 1280 ccb->ccb_datasize, flags); 1281 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap_xfer); 1282 1283 if (ccb->ccb_abuf != (vaddr_t)0) { 1284 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1285 memcpy(ccb->ccb_data, (void *)ccb->ccb_abuf, 1286 ccb->ccb_datasize); 1287 s = splvm(); 1288 /* XXX */ 1289 uvm_km_free(kmem_map, ccb->ccb_abuf, ccb->ccb_datasize); 1290 splx(s); 1291 } 1292 } 1293 1294 /* 1295 * Submit a command to the controller and poll on completion. Return 1296 * non-zero on timeout (but don't check status, as some command types don't 1297 * return status). Must be called with interrupts blocked. 1298 */ 1299 int 1300 twe_ccb_poll(struct twe_softc *sc, struct twe_ccb *ccb, int timo) 1301 { 1302 int rv; 1303 1304 if ((rv = twe_ccb_submit(sc, ccb)) != 0) 1305 return (rv); 1306 1307 for (timo *= 1000; timo != 0; timo--) { 1308 twe_poll(sc); 1309 if ((ccb->ccb_flags & TWE_CCB_COMPLETE) != 0) 1310 break; 1311 DELAY(100); 1312 } 1313 1314 return (timo == 0); 1315 } 1316 1317 /* 1318 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1319 * the order that they were enqueued and try to submit their command blocks 1320 * to the controller for execution. 1321 */ 1322 void 1323 twe_ccb_enqueue(struct twe_softc *sc, struct twe_ccb *ccb) 1324 { 1325 int s; 1326 1327 s = splbio(); 1328 1329 if (ccb != NULL) 1330 SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 1331 1332 while ((ccb = SIMPLEQ_FIRST(&sc->sc_ccb_queue)) != NULL) { 1333 if (twe_ccb_submit(sc, ccb)) 1334 break; 1335 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_queue, ccb_chain.simpleq); 1336 } 1337 1338 splx(s); 1339 } 1340 1341 /* 1342 * Submit the command block associated with the specified CCB to the 1343 * controller for execution. Must be called with interrupts blocked. 1344 */ 1345 int 1346 twe_ccb_submit(struct twe_softc *sc, struct twe_ccb *ccb) 1347 { 1348 bus_addr_t pa; 1349 int rv; 1350 u_int status; 1351 1352 /* Check to see if we can post a command. */ 1353 status = twe_inl(sc, TWE_REG_STS); 1354 twe_status_check(sc, status); 1355 1356 if ((status & TWE_STS_CMD_QUEUE_FULL) == 0) { 1357 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1358 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, sizeof(struct twe_cmd), 1359 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1360 ccb->ccb_flags |= TWE_CCB_ACTIVE; 1361 pa = sc->sc_cmds_paddr + 1362 ccb->ccb_cmdid * sizeof(struct twe_cmd); 1363 twe_outl(sc, TWE_REG_CMD_QUEUE, (u_int32_t)pa); 1364 rv = 0; 1365 } else 1366 rv = EBUSY; 1367 1368 return (rv); 1369 } 1370 1371 1372 /* 1373 * Accept an open operation on the control device. 1374 */ 1375 int 1376 tweopen(dev_t dev, int flag, int mode, struct proc *p) 1377 { 1378 struct twe_softc *twe; 1379 1380 if ((twe = device_lookup(&twe_cd, minor(dev))) == NULL) 1381 return (ENXIO); 1382 if ((twe->sc_flags & TWEF_OPEN) != 0) 1383 return (EBUSY); 1384 1385 twe->sc_flags |= TWEF_OPEN; 1386 return (0); 1387 } 1388 1389 /* 1390 * Accept the last close on the control device. 1391 */ 1392 int 1393 tweclose(dev_t dev, int flag, int mode, struct proc *p) 1394 { 1395 struct twe_softc *twe; 1396 1397 twe = device_lookup(&twe_cd, minor(dev)); 1398 twe->sc_flags &= ~TWEF_OPEN; 1399 return (0); 1400 } 1401 1402 /* 1403 * Handle control operations. 1404 */ 1405 int 1406 tweioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1407 { 1408 struct twe_softc *twe; 1409 struct twe_ccb *ccb; 1410 struct twe_param *param; 1411 struct twe_usercommand *tu; 1412 struct twe_paramcommand *tp; 1413 union twe_statrequest *ts; 1414 void *pdata = NULL; 1415 int rv, s, error = 0; 1416 u_int8_t cmdid; 1417 1418 if (securelevel >= 2) 1419 return (EPERM); 1420 1421 twe = device_lookup(&twe_cd, minor(dev)); 1422 tu = (struct twe_usercommand *)data; 1423 tp = (struct twe_paramcommand *)data; 1424 ts = (union twe_statrequest *)data; 1425 1426 /* Hmm, compatible with FreeBSD */ 1427 switch (cmd) { 1428 case TWEIO_COMMAND: 1429 if (tu->tu_size > 0) { 1430 if (tu->tu_size > TWE_SECTOR_SIZE) 1431 return EINVAL; 1432 pdata = malloc(tu->tu_size, M_DEVBUF, M_WAITOK); 1433 error = copyin(tu->tu_data, pdata, tu->tu_size); 1434 if (error != 0) 1435 goto done; 1436 error = twe_ccb_alloc(twe, &ccb, TWE_CCB_PARAM | 1437 TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1438 } else { 1439 error = twe_ccb_alloc(twe, &ccb, 0); 1440 } 1441 if (rv != 0) 1442 goto done; 1443 cmdid = ccb->ccb_cmdid; 1444 memcpy(ccb->ccb_cmd, &tu->tu_cmd, sizeof(struct twe_cmd)); 1445 ccb->ccb_cmdid = cmdid; 1446 if (ccb->ccb_flags & TWE_CCB_PARAM) { 1447 ccb->ccb_data = pdata; 1448 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1449 ccb->ccb_tx.tx_handler = 0; 1450 ccb->ccb_tx.tx_context = pdata; 1451 ccb->ccb_tx.tx_dv = &twe->sc_dv; 1452 } 1453 /* Map the transfer. */ 1454 if ((error = twe_ccb_map(twe, ccb)) != 0) { 1455 twe_ccb_free(twe, ccb); 1456 goto done; 1457 } 1458 1459 /* Submit the command and wait. */ 1460 s = splbio(); 1461 rv = twe_ccb_poll(twe, ccb, 5); 1462 twe_ccb_unmap(twe, ccb); 1463 twe_ccb_free(twe, ccb); 1464 splx(s); 1465 1466 if (tu->tu_size > 0) 1467 error = copyout(pdata, tu->tu_data, tu->tu_size); 1468 goto done; 1469 1470 case TWEIO_STATS: 1471 return (ENOENT); 1472 1473 case TWEIO_AEN_POLL: 1474 s = splbio(); 1475 *(u_int *)data = twe_aen_dequeue(twe); 1476 splx(s); 1477 return (0); 1478 1479 case TWEIO_AEN_WAIT: 1480 s = splbio(); 1481 while ((*(u_int *)data = 1482 twe_aen_dequeue(twe)) == TWE_AEN_QUEUE_EMPTY) { 1483 twe->sc_flags |= TWEF_AENQ_WAIT; 1484 error = tsleep(&twe->sc_aen_queue, PRIBIO | PCATCH, 1485 "tweaen", 0); 1486 if (error == EINTR) { 1487 splx(s); 1488 return (error); 1489 } 1490 } 1491 splx(s); 1492 return (0); 1493 1494 case TWEIO_GET_PARAM: 1495 error = twe_param_get(twe, tp->tp_table_id, tp->tp_param_id, 1496 tp->tp_size, 0, ¶m); 1497 if (error != 0) 1498 return (error); 1499 if (param->tp_param_size > tp->tp_size) { 1500 error = EFAULT; 1501 goto done; 1502 } 1503 error = copyout(param->tp_data, tp->tp_data, 1504 param->tp_param_size); 1505 goto done; 1506 1507 case TWEIO_SET_PARAM: 1508 pdata = malloc(tp->tp_size, M_DEVBUF, M_WAITOK); 1509 if ((error = copyin(tp->tp_data, pdata, tp->tp_size)) != 0) 1510 goto done; 1511 error = twe_param_set(twe, tp->tp_table_id, tp->tp_param_id, 1512 tp->tp_size, pdata); 1513 goto done; 1514 1515 case TWEIO_RESET: 1516 twe_reset(twe); 1517 return (0); 1518 1519 default: 1520 return EINVAL; 1521 } 1522 done: 1523 if (pdata) 1524 free(pdata, M_DEVBUF); 1525 return error; 1526 } 1527 1528 /* 1529 * Print some information about the controller 1530 */ 1531 static void 1532 twe_describe_controller(struct twe_softc *sc) 1533 { 1534 struct twe_param *p[6]; 1535 int i, rv = 0; 1536 uint32_t dsize; 1537 uint8_t ports; 1538 1539 /* get the port count */ 1540 rv |= twe_param_get_1(sc, TWE_PARAM_CONTROLLER, 1541 TWE_PARAM_CONTROLLER_PortCount, &ports); 1542 1543 /* get version strings */ 1544 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_Mon, 1545 16, NULL, &p[0]); 1546 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_FW, 1547 16, NULL, &p[1]); 1548 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_BIOS, 1549 16, NULL, &p[2]); 1550 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_PCB, 1551 8, NULL, &p[3]); 1552 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_ATA, 1553 8, NULL, &p[4]); 1554 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_PCI, 1555 8, NULL, &p[5]); 1556 1557 if (rv) { 1558 /* some error occurred */ 1559 aprint_error("%s: failed to fetch version information\n", 1560 sc->sc_dv.dv_xname); 1561 return; 1562 } 1563 1564 aprint_normal("%s: %d ports, Firmware %.16s, BIOS %.16s\n", 1565 sc->sc_dv.dv_xname, ports, 1566 p[1]->tp_data, p[2]->tp_data); 1567 1568 aprint_verbose("%s: Monitor %.16s, PCB %.8s, Achip %.8s, Pchip %.8s\n", 1569 sc->sc_dv.dv_xname, 1570 p[0]->tp_data, p[3]->tp_data, 1571 p[4]->tp_data, p[5]->tp_data); 1572 1573 free(p[0], M_DEVBUF); 1574 free(p[1], M_DEVBUF); 1575 free(p[2], M_DEVBUF); 1576 free(p[3], M_DEVBUF); 1577 free(p[4], M_DEVBUF); 1578 free(p[5], M_DEVBUF); 1579 1580 rv = twe_param_get(sc, TWE_PARAM_DRIVESUMMARY, 1581 TWE_PARAM_DRIVESUMMARY_Status, 16, NULL, &p[0]); 1582 if (rv) { 1583 aprint_error("%s: failed to get drive status summary\n", 1584 sc->sc_dv.dv_xname); 1585 return; 1586 } 1587 for (i = 0; i < ports; i++) { 1588 if (p[0]->tp_data[i] != TWE_PARAM_DRIVESTATUS_Present) 1589 continue; 1590 rv = twe_param_get_4(sc, TWE_PARAM_DRIVEINFO + i, 1591 TWE_PARAM_DRIVEINFO_Size, &dsize); 1592 if (rv) { 1593 aprint_error( 1594 "%s: unable to get drive size for port %d\n", 1595 sc->sc_dv.dv_xname, i); 1596 continue; 1597 } 1598 rv = twe_param_get(sc, TWE_PARAM_DRIVEINFO + i, 1599 TWE_PARAM_DRIVEINFO_Model, 40, NULL, &p[1]); 1600 if (rv) { 1601 aprint_error( 1602 "%s: unable to get drive model for port %d\n", 1603 sc->sc_dv.dv_xname, i); 1604 continue; 1605 } 1606 aprint_verbose("%s: port %d: %.40s %d MB\n", sc->sc_dv.dv_xname, 1607 i, p[1]->tp_data, dsize / 2048); 1608 free(p[1], M_DEVBUF); 1609 } 1610 free(p[0], M_DEVBUF); 1611 } 1612
Indexes created Sun Sep 21 20:09:37 GMT 2025