twe.c revision 1.46
1 /* $NetBSD: twe.c,v 1.46 2003/09/22 18:31:11 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran; and by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twe.c,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 /* 69 * Driver for the 3ware Escalade family of RAID controllers. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: twe.c,v 1.46 2003/09/22 18:31:11 thorpej Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/device.h> 79 #include <sys/queue.h> 80 #include <sys/proc.h> 81 #include <sys/buf.h> 82 #include <sys/endian.h> 83 #include <sys/malloc.h> 84 #include <sys/conf.h> 85 #include <sys/disk.h> 86 87 #include <uvm/uvm_extern.h> 88 89 #include <machine/bswap.h> 90 #include <machine/bus.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/twereg.h> 96 #include <dev/pci/twevar.h> 97 #include <dev/pci/tweio.h> 98 99 #define PCI_CBIO 0x10 100 101 static void twe_aen_handler(struct twe_ccb *, int); 102 static void twe_aen_enqueue(struct twe_softc *sc, uint16_t, int); 103 static uint16_t twe_aen_dequeue(struct twe_softc *); 104 105 static void twe_attach(struct device *, struct device *, void *); 106 static int twe_init_connection(struct twe_softc *); 107 static int twe_intr(void *); 108 static int twe_match(struct device *, struct cfdata *, void *); 109 static int twe_param_set(struct twe_softc *, int, int, size_t, void *); 110 static void twe_poll(struct twe_softc *); 111 static int twe_print(void *, const char *); 112 static int twe_reset(struct twe_softc *); 113 static int twe_submatch(struct device *, struct cfdata *, void *); 114 static int twe_status_check(struct twe_softc *, u_int); 115 static int twe_status_wait(struct twe_softc *, u_int, int); 116 static void twe_describe_controller(struct twe_softc *); 117 118 static int twe_add_unit(struct twe_softc *, int); 119 static int twe_del_unit(struct twe_softc *, int); 120 121 static inline u_int32_t twe_inl(struct twe_softc *, int); 122 static inline void twe_outl(struct twe_softc *, int, u_int32_t); 123 124 dev_type_open(tweopen); 125 dev_type_close(tweclose); 126 dev_type_ioctl(tweioctl); 127 128 const struct cdevsw twe_cdevsw = { 129 tweopen, tweclose, noread, nowrite, tweioctl, 130 nostop, notty, nopoll, nommap, 131 }; 132 133 extern struct cfdriver twe_cd; 134 135 CFATTACH_DECL(twe, sizeof(struct twe_softc), 136 twe_match, twe_attach, NULL, NULL); 137 138 /* 139 * Tables to convert numeric codes to strings. 140 */ 141 const struct twe_code_table twe_table_status[] = { 142 { 0x00, "successful completion" }, 143 144 /* info */ 145 { 0x42, "command in progress" }, 146 { 0x6c, "retrying interface CRC error from UDMA command" }, 147 148 /* warning */ 149 { 0x81, "redundant/inconsequential request ignored" }, 150 { 0x8e, "failed to write zeroes to LBA 0" }, 151 { 0x8f, "failed to profile TwinStor zones" }, 152 153 /* fatal */ 154 { 0xc1, "aborted due to system command or reconfiguration" }, 155 { 0xc4, "aborted" }, 156 { 0xc5, "access error" }, 157 { 0xc6, "access violation" }, 158 { 0xc7, "device failure" }, /* high byte may be port # */ 159 { 0xc8, "controller error" }, 160 { 0xc9, "timed out" }, 161 { 0xcb, "invalid unit number" }, 162 { 0xcf, "unit not available" }, 163 { 0xd2, "undefined opcode" }, 164 { 0xdb, "request incompatible with unit" }, 165 { 0xdc, "invalid request" }, 166 { 0xff, "firmware error, reset requested" }, 167 168 { 0, NULL } 169 }; 170 171 const struct twe_code_table twe_table_unitstate[] = { 172 { TWE_PARAM_UNITSTATUS_Normal, "Normal" }, 173 { TWE_PARAM_UNITSTATUS_Initialising, "Initializing" }, 174 { TWE_PARAM_UNITSTATUS_Degraded, "Degraded" }, 175 { TWE_PARAM_UNITSTATUS_Rebuilding, "Rebuilding" }, 176 { TWE_PARAM_UNITSTATUS_Verifying, "Verifying" }, 177 { TWE_PARAM_UNITSTATUS_Corrupt, "Corrupt" }, 178 { TWE_PARAM_UNITSTATUS_Missing, "Missing" }, 179 180 { 0, NULL } 181 }; 182 183 const struct twe_code_table twe_table_unittype[] = { 184 /* array descriptor configuration */ 185 { TWE_AD_CONFIG_RAID0, "RAID0" }, 186 { TWE_AD_CONFIG_RAID1, "RAID1" }, 187 { TWE_AD_CONFIG_TwinStor, "TwinStor" }, 188 { TWE_AD_CONFIG_RAID5, "RAID5" }, 189 { TWE_AD_CONFIG_RAID10, "RAID10" }, 190 191 { 0, NULL } 192 }; 193 194 const struct twe_code_table twe_table_stripedepth[] = { 195 { TWE_AD_STRIPE_4k, "4K" }, 196 { TWE_AD_STRIPE_8k, "8K" }, 197 { TWE_AD_STRIPE_16k, "16K" }, 198 { TWE_AD_STRIPE_32k, "32K" }, 199 { TWE_AD_STRIPE_64k, "64K" }, 200 201 { 0, NULL } 202 }; 203 204 /* 205 * Asynchronous event notification messages are qualified: 206 * a - not unit/port specific 207 * u - unit specific 208 * p - port specific 209 */ 210 const struct twe_code_table twe_table_aen[] = { 211 { 0x00, "a queue empty" }, 212 { 0x01, "a soft reset" }, 213 { 0x02, "u degraded mode" }, 214 { 0x03, "a controller error" }, 215 { 0x04, "u rebuild fail" }, 216 { 0x05, "u rebuild done" }, 217 { 0x06, "u incomplete unit" }, 218 { 0x07, "u initialization done" }, 219 { 0x08, "u unclean shutdown detected" }, 220 { 0x09, "p drive timeout" }, 221 { 0x0a, "p drive error" }, 222 { 0x0b, "u rebuild started" }, 223 { 0x0c, "u initialization started" }, 224 { 0x0d, "u logical unit deleted" }, 225 { 0x0f, "p SMART threshold exceeded" }, 226 { 0x15, "a table undefined" }, /* XXX: Not in FreeBSD's table */ 227 { 0x21, "p ATA UDMA downgrade" }, 228 { 0x22, "p ATA UDMA upgrade" }, 229 { 0x23, "p sector repair occurred" }, 230 { 0x24, "a SBUF integrity check failure" }, 231 { 0x25, "p lost cached write" }, 232 { 0x26, "p drive ECC error detected" }, 233 { 0x27, "p DCB checksum error" }, 234 { 0x28, "p DCB unsupported version" }, 235 { 0x29, "u verify started" }, 236 { 0x2a, "u verify failed" }, 237 { 0x2b, "u verify complete" }, 238 { 0x2c, "p overwrote bad sector during rebuild" }, 239 { 0x2d, "p encountered bad sector during rebuild" }, 240 { 0x2e, "p replacement drive too small" }, 241 { 0x2f, "u array not previously initialized" }, 242 { 0x30, "p drive not supported" }, 243 { 0xff, "a aen queue full" }, 244 245 { 0, NULL }, 246 }; 247 248 const char * 249 twe_describe_code(const struct twe_code_table *table, uint32_t code) 250 { 251 252 for (; table->string != NULL; table++) { 253 if (table->code == code) 254 return (table->string); 255 } 256 return (NULL); 257 } 258 259 static inline u_int32_t 260 twe_inl(struct twe_softc *sc, int off) 261 { 262 263 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 264 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 265 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, off)); 266 } 267 268 static inline void 269 twe_outl(struct twe_softc *sc, int off, u_int32_t val) 270 { 271 272 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 273 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 274 BUS_SPACE_BARRIER_WRITE); 275 } 276 277 /* 278 * Match a supported board. 279 */ 280 static int 281 twe_match(struct device *parent, struct cfdata *cfdata, void *aux) 282 { 283 struct pci_attach_args *pa; 284 285 pa = aux; 286 287 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3WARE && 288 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE || 289 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE_ASIC)); 290 } 291 292 /* 293 * Attach a supported board. 294 * 295 * XXX This doesn't fail gracefully. 296 */ 297 static void 298 twe_attach(struct device *parent, struct device *self, void *aux) 299 { 300 struct pci_attach_args *pa; 301 struct twe_softc *sc; 302 pci_chipset_tag_t pc; 303 pci_intr_handle_t ih; 304 pcireg_t csr; 305 const char *intrstr; 306 int size, i, rv, rseg; 307 size_t max_segs, max_xfer; 308 bus_dma_segment_t seg; 309 struct twe_cmd *tc; 310 struct twe_ccb *ccb; 311 312 sc = (struct twe_softc *)self; 313 pa = aux; 314 pc = pa->pa_pc; 315 sc->sc_dmat = pa->pa_dmat; 316 SIMPLEQ_INIT(&sc->sc_ccb_queue); 317 SLIST_INIT(&sc->sc_ccb_freelist); 318 319 aprint_naive(": RAID controller\n"); 320 aprint_normal(": 3ware Escalade\n"); 321 322 ccb = malloc(sizeof(*ccb) * TWE_MAX_QUEUECNT, M_DEVBUF, M_NOWAIT); 323 if (ccb == NULL) { 324 aprint_error("%s: unable to allocate memory for ccbs\n", 325 sc->sc_dv.dv_xname); 326 return; 327 } 328 329 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 330 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 331 aprint_error("%s: can't map i/o space\n", sc->sc_dv.dv_xname); 332 return; 333 } 334 335 /* Enable the device. */ 336 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 337 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 338 csr | PCI_COMMAND_MASTER_ENABLE); 339 340 /* Map and establish the interrupt. */ 341 if (pci_intr_map(pa, &ih)) { 342 aprint_error("%s: can't map interrupt\n", sc->sc_dv.dv_xname); 343 return; 344 } 345 346 intrstr = pci_intr_string(pc, ih); 347 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, twe_intr, sc); 348 if (sc->sc_ih == NULL) { 349 aprint_error("%s: can't establish interrupt%s%s\n", 350 sc->sc_dv.dv_xname, 351 (intrstr) ? " at " : "", 352 (intrstr) ? intrstr : ""); 353 return; 354 } 355 356 if (intrstr != NULL) 357 aprint_normal("%s: interrupting at %s\n", 358 sc->sc_dv.dv_xname, intrstr); 359 360 /* 361 * Allocate and initialise the command blocks and CCBs. 362 */ 363 size = sizeof(struct twe_cmd) * TWE_MAX_QUEUECNT; 364 365 if ((rv = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 1, 366 &rseg, BUS_DMA_NOWAIT)) != 0) { 367 aprint_error("%s: unable to allocate commands, rv = %d\n", 368 sc->sc_dv.dv_xname, rv); 369 return; 370 } 371 372 if ((rv = bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 373 (caddr_t *)&sc->sc_cmds, 374 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 375 aprint_error("%s: unable to map commands, rv = %d\n", 376 sc->sc_dv.dv_xname, rv); 377 return; 378 } 379 380 if ((rv = bus_dmamap_create(sc->sc_dmat, size, size, 1, 0, 381 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 382 aprint_error("%s: unable to create command DMA map, rv = %d\n", 383 sc->sc_dv.dv_xname, rv); 384 return; 385 } 386 387 if ((rv = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cmds, 388 size, NULL, BUS_DMA_NOWAIT)) != 0) { 389 aprint_error("%s: unable to load command DMA map, rv = %d\n", 390 sc->sc_dv.dv_xname, rv); 391 return; 392 } 393 394 sc->sc_cmds_paddr = sc->sc_dmamap->dm_segs[0].ds_addr; 395 memset(sc->sc_cmds, 0, size); 396 397 sc->sc_ccbs = ccb; 398 tc = (struct twe_cmd *)sc->sc_cmds; 399 max_segs = twe_get_maxsegs(); 400 max_xfer = twe_get_maxxfer(max_segs); 401 402 for (i = 0; i < TWE_MAX_QUEUECNT; i++, tc++, ccb++) { 403 ccb->ccb_cmd = tc; 404 ccb->ccb_cmdid = i; 405 ccb->ccb_flags = 0; 406 rv = bus_dmamap_create(sc->sc_dmat, max_xfer, 407 max_segs, PAGE_SIZE, 0, 408 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 409 &ccb->ccb_dmamap_xfer); 410 if (rv != 0) { 411 aprint_error("%s: can't create dmamap, rv = %d\n", 412 sc->sc_dv.dv_xname, rv); 413 return; 414 } 415 /* Save one CCB for parameter retrieval. */ 416 if (i != 0) 417 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, 418 ccb_chain.slist); 419 } 420 421 /* Wait for the controller to become ready. */ 422 if (twe_status_wait(sc, TWE_STS_MICROCONTROLLER_READY, 6)) { 423 aprint_error("%s: microcontroller not ready\n", 424 sc->sc_dv.dv_xname); 425 return; 426 } 427 428 twe_outl(sc, TWE_REG_CTL, TWE_CTL_DISABLE_INTRS); 429 430 /* Reset the controller. */ 431 if (twe_reset(sc)) { 432 aprint_error("%s: reset failed\n", sc->sc_dv.dv_xname); 433 return; 434 } 435 436 /* Initialise connection with controller. */ 437 twe_init_connection(sc); 438 439 twe_describe_controller(sc); 440 441 /* Find and attach RAID array units. */ 442 sc->sc_nunits = 0; 443 for (i = 0; i < TWE_MAX_UNITS; i++) 444 (void) twe_add_unit(sc, i); 445 446 /* ...and finally, enable interrupts. */ 447 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR | 448 TWE_CTL_UNMASK_RESP_INTR | 449 TWE_CTL_ENABLE_INTRS); 450 } 451 452 void 453 twe_register_callbacks(struct twe_softc *sc, int unit, 454 const struct twe_callbacks *tcb) 455 { 456 457 sc->sc_units[unit].td_callbacks = tcb; 458 } 459 460 static void 461 twe_recompute_openings(struct twe_softc *sc) 462 { 463 struct twe_drive *td; 464 int unit, openings; 465 466 if (sc->sc_nunits != 0) 467 openings = (TWE_MAX_QUEUECNT - 1) / sc->sc_nunits; 468 else 469 openings = 0; 470 if (openings == sc->sc_openings) 471 return; 472 sc->sc_openings = openings; 473 474 #ifdef TWE_DEBUG 475 printf("%s: %d array%s, %d openings per array\n", 476 sc->sc_dv.dv_xname, sc->sc_nunits, 477 sc->sc_nunits == 1 ? "" : "s", sc->sc_openings); 478 #endif 479 480 for (unit = 0; unit < TWE_MAX_UNITS; unit++) { 481 td = &sc->sc_units[unit]; 482 if (td->td_dev != NULL) 483 (*td->td_callbacks->tcb_openings)(td->td_dev, 484 sc->sc_openings); 485 } 486 } 487 488 static int 489 twe_add_unit(struct twe_softc *sc, int unit) 490 { 491 struct twe_param *dtp, *atp; 492 struct twe_array_descriptor *ad; 493 struct twe_drive *td; 494 struct twe_attach_args twea; 495 uint32_t newsize; 496 int rv; 497 uint16_t dsize; 498 uint8_t newtype, newstripe; 499 500 if (unit < 0 || unit >= TWE_MAX_UNITS) 501 return (EINVAL); 502 503 /* Find attached units. */ 504 rv = twe_param_get(sc, TWE_PARAM_UNITSUMMARY, 505 TWE_PARAM_UNITSUMMARY_Status, TWE_MAX_UNITS, NULL, &dtp); 506 if (rv != 0) { 507 aprint_error("%s: error %d fetching unit summary\n", 508 sc->sc_dv.dv_xname, rv); 509 return (rv); 510 } 511 512 /* For each detected unit, collect size and store in an array. */ 513 td = &sc->sc_units[unit]; 514 515 /* Unit present? */ 516 if ((dtp->tp_data[unit] & TWE_PARAM_UNITSTATUS_Online) == 0) { 517 /* 518 * XXX Should we check to see if a device has been 519 * XXX attached at this index and detach it if it 520 * XXX has? ("rescan" semantics) 521 */ 522 rv = 0; 523 goto out; 524 } 525 526 rv = twe_param_get_2(sc, TWE_PARAM_UNITINFO + unit, 527 TWE_PARAM_UNITINFO_DescriptorSize, &dsize); 528 if (rv != 0) { 529 aprint_error("%s: error %d fetching descriptor size " 530 "for unit %d\n", sc->sc_dv.dv_xname, rv, unit); 531 goto out; 532 } 533 534 rv = twe_param_get(sc, TWE_PARAM_UNITINFO + unit, 535 TWE_PARAM_UNITINFO_Descriptor, dsize - 3, NULL, &atp); 536 if (rv != 0) { 537 aprint_error("%s: error %d fetching array descriptor " 538 "for unit %d\n", sc->sc_dv.dv_xname, rv, unit); 539 goto out; 540 } 541 542 ad = (struct twe_array_descriptor *)atp->tp_data; 543 newtype = ad->configuration; 544 newstripe = ad->stripe_size; 545 free(atp, M_DEVBUF); 546 547 rv = twe_param_get_4(sc, TWE_PARAM_UNITINFO + unit, 548 TWE_PARAM_UNITINFO_Capacity, &newsize); 549 if (rv != 0) { 550 aprint_error( 551 "%s: error %d fetching capacity for unit %d\n", 552 sc->sc_dv.dv_xname, rv, unit); 553 goto out; 554 } 555 556 /* 557 * Have a device, so we need to attach it. If there is currently 558 * something sitting at the slot, and the parameters are different, 559 * then we detach the old device before attaching the new one. 560 */ 561 if (td->td_dev != NULL && 562 td->td_size == newsize && 563 td->td_type == newtype && 564 td->td_stripe == newstripe) { 565 /* Same as the old device; just keep using it. */ 566 rv = 0; 567 goto out; 568 } else if (td->td_dev != NULL) { 569 /* Detach the old device first. */ 570 (void) config_detach(td->td_dev, DETACH_FORCE); 571 td->td_dev = NULL; 572 } else if (td->td_size == 0) 573 sc->sc_nunits++; 574 575 /* 576 * Committed to the new array unit; assign its parameters and 577 * recompute the number of available command openings. 578 */ 579 td->td_size = newsize; 580 td->td_type = newtype; 581 td->td_stripe = newstripe; 582 twe_recompute_openings(sc); 583 584 twea.twea_unit = unit; 585 td->td_dev = config_found_sm(&sc->sc_dv, &twea, twe_print, 586 twe_submatch); 587 588 rv = 0; 589 out: 590 free(dtp, M_DEVBUF); 591 return (rv); 592 } 593 594 static int 595 twe_del_unit(struct twe_softc *sc, int unit) 596 { 597 struct twe_drive *td; 598 599 if (unit < 0 || unit >= TWE_MAX_UNITS) 600 return (EINVAL); 601 602 td = &sc->sc_units[unit]; 603 if (td->td_size != 0) 604 sc->sc_nunits--; 605 td->td_size = 0; 606 td->td_type = 0; 607 td->td_stripe = 0; 608 if (td->td_dev != NULL) { 609 (void) config_detach(td->td_dev, DETACH_FORCE); 610 td->td_dev = NULL; 611 } 612 twe_recompute_openings(sc); 613 return (0); 614 } 615 616 /* 617 * Reset the controller. Currently only useful at attach time; must be 618 * called with interrupts blocked. 619 */ 620 static int 621 twe_reset(struct twe_softc *sc) 622 { 623 uint16_t aen; 624 u_int status; 625 volatile u_int32_t junk; 626 int got, rv; 627 628 /* Issue a soft reset. */ 629 twe_outl(sc, TWE_REG_CTL, TWE_CTL_ISSUE_SOFT_RESET | 630 TWE_CTL_CLEAR_HOST_INTR | 631 TWE_CTL_CLEAR_ATTN_INTR | 632 TWE_CTL_MASK_CMD_INTR | 633 TWE_CTL_MASK_RESP_INTR | 634 TWE_CTL_CLEAR_ERROR_STS | 635 TWE_CTL_DISABLE_INTRS); 636 637 /* Wait for attention... */ 638 if (twe_status_wait(sc, TWE_STS_ATTN_INTR, 15)) { 639 printf("%s: no attention interrupt\n", 640 sc->sc_dv.dv_xname); 641 return (-1); 642 } 643 644 /* ...and ACK it. */ 645 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 646 647 /* 648 * Pull AENs out of the controller; look for a soft reset AEN. 649 * Open code this, since we want to detect reset even if the 650 * queue for management tools is full. 651 */ 652 for (got = 0;;) { 653 rv = twe_param_get_2(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 654 &aen); 655 if (rv != 0) 656 printf("%s: error %d while draining event queue\n", 657 sc->sc_dv.dv_xname, rv); 658 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) 659 break; 660 if (TWE_AEN_CODE(aen) == TWE_AEN_SOFT_RESET) 661 got = 1; 662 twe_aen_enqueue(sc, aen, 1); 663 } 664 665 if (!got) { 666 printf("%s: reset not reported\n", sc->sc_dv.dv_xname); 667 return (-1); 668 } 669 670 /* Check controller status. */ 671 status = twe_inl(sc, TWE_REG_STS); 672 if (twe_status_check(sc, status)) { 673 printf("%s: controller errors detected\n", 674 sc->sc_dv.dv_xname); 675 return (-1); 676 } 677 678 /* Drain the response queue. */ 679 for (;;) { 680 status = twe_inl(sc, TWE_REG_STS); 681 if (twe_status_check(sc, status) != 0) { 682 printf("%s: can't drain response queue\n", 683 sc->sc_dv.dv_xname); 684 return (-1); 685 } 686 if ((status & TWE_STS_RESP_QUEUE_EMPTY) != 0) 687 break; 688 junk = twe_inl(sc, TWE_REG_RESP_QUEUE); 689 } 690 691 return (0); 692 } 693 694 /* 695 * Print autoconfiguration message for a sub-device. 696 */ 697 static int 698 twe_print(void *aux, const char *pnp) 699 { 700 struct twe_attach_args *twea; 701 702 twea = aux; 703 704 if (pnp != NULL) 705 aprint_normal("block device at %s", pnp); 706 aprint_normal(" unit %d", twea->twea_unit); 707 return (UNCONF); 708 } 709 710 /* 711 * Match a sub-device. 712 */ 713 static int 714 twe_submatch(struct device *parent, struct cfdata *cf, void *aux) 715 { 716 struct twe_attach_args *twea; 717 718 twea = aux; 719 720 if (cf->tweacf_unit != TWECF_UNIT_DEFAULT && 721 cf->tweacf_unit != twea->twea_unit) 722 return (0); 723 724 return (config_match(parent, cf, aux)); 725 } 726 727 /* 728 * Interrupt service routine. 729 */ 730 static int 731 twe_intr(void *arg) 732 { 733 struct twe_softc *sc; 734 u_int status; 735 int caught, rv; 736 737 sc = arg; 738 caught = 0; 739 status = twe_inl(sc, TWE_REG_STS); 740 twe_status_check(sc, status); 741 742 /* Host interrupts - purpose unknown. */ 743 if ((status & TWE_STS_HOST_INTR) != 0) { 744 #ifdef DEBUG 745 printf("%s: host interrupt\n", sc->sc_dv.dv_xname); 746 #endif 747 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_HOST_INTR); 748 caught = 1; 749 } 750 751 /* 752 * Attention interrupts, signalled when a controller or child device 753 * state change has occurred. 754 */ 755 if ((status & TWE_STS_ATTN_INTR) != 0) { 756 rv = twe_param_get(sc, TWE_PARAM_AEN, 757 TWE_PARAM_AEN_UnitCode, 2, twe_aen_handler, 758 NULL); 759 if (rv != 0) 760 printf("%s: unable to retrieve AEN (%d)\n", 761 sc->sc_dv.dv_xname, rv); 762 else 763 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 764 caught = 1; 765 } 766 767 /* 768 * Command interrupts, signalled when the controller can accept more 769 * commands. We don't use this; instead, we try to submit commands 770 * when we receive them, and when other commands have completed. 771 * Mask it so we don't get another one. 772 */ 773 if ((status & TWE_STS_CMD_INTR) != 0) { 774 #ifdef DEBUG 775 printf("%s: command interrupt\n", sc->sc_dv.dv_xname); 776 #endif 777 twe_outl(sc, TWE_REG_CTL, TWE_CTL_MASK_CMD_INTR); 778 caught = 1; 779 } 780 781 if ((status & TWE_STS_RESP_INTR) != 0) { 782 twe_poll(sc); 783 caught = 1; 784 } 785 786 return (caught); 787 } 788 789 /* 790 * Handle an AEN returned by the controller. 791 */ 792 static void 793 twe_aen_handler(struct twe_ccb *ccb, int error) 794 { 795 struct twe_softc *sc; 796 struct twe_param *tp; 797 uint16_t aen; 798 int rv; 799 800 sc = (struct twe_softc *)ccb->ccb_tx.tx_dv; 801 tp = ccb->ccb_tx.tx_context; 802 twe_ccb_unmap(sc, ccb); 803 804 if (error) { 805 printf("%s: error retrieving AEN\n", sc->sc_dv.dv_xname); 806 aen = TWE_AEN_QUEUE_EMPTY; 807 } else 808 aen = le16toh(*(u_int16_t *)tp->tp_data); 809 free(tp, M_DEVBUF); 810 twe_ccb_free(sc, ccb); 811 812 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) { 813 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 814 return; 815 } 816 817 twe_aen_enqueue(sc, aen, 0); 818 819 /* 820 * Chain another retrieval in case interrupts have been 821 * coalesced. 822 */ 823 rv = twe_param_get(sc, TWE_PARAM_AEN, TWE_PARAM_AEN_UnitCode, 2, 824 twe_aen_handler, NULL); 825 if (rv != 0) 826 printf("%s: unable to retrieve AEN (%d)\n", 827 sc->sc_dv.dv_xname, rv); 828 } 829 830 static void 831 twe_aen_enqueue(struct twe_softc *sc, uint16_t aen, int quiet) 832 { 833 const char *str, *msg; 834 int s, next, nextnext; 835 836 /* 837 * First report the AEN on the console. Maybe. 838 */ 839 if (! quiet) { 840 str = twe_describe_code(twe_table_aen, TWE_AEN_CODE(aen)); 841 if (str == NULL) { 842 printf("%s: unknown AEN 0x%04x\n", 843 sc->sc_dv.dv_xname, aen); 844 } else { 845 msg = str + 2; 846 switch (*str) { 847 case 'u': 848 printf("%s: unit %d: %s\n", 849 sc->sc_dv.dv_xname, TWE_AEN_UNIT(aen), msg); 850 break; 851 852 case 'p': 853 printf("%s: port %d: %s\n", 854 sc->sc_dv.dv_xname, TWE_AEN_UNIT(aen), msg); 855 break; 856 857 default: 858 printf("%s: %s\n", sc->sc_dv.dv_xname, msg); 859 } 860 } 861 } 862 863 /* Now enqueue the AEN for mangement tools. */ 864 s = splbio(); 865 866 next = (sc->sc_aen_head + 1) % TWE_AEN_Q_LENGTH; 867 nextnext = (sc->sc_aen_head + 2) % TWE_AEN_Q_LENGTH; 868 869 /* 870 * If this is the last free slot, then queue up a "queue 871 * full" message. 872 */ 873 if (nextnext == sc->sc_aen_tail) 874 aen = TWE_AEN_QUEUE_FULL; 875 876 if (next != sc->sc_aen_tail) { 877 sc->sc_aen_queue[sc->sc_aen_head] = aen; 878 sc->sc_aen_head = next; 879 } 880 881 if (sc->sc_flags & TWEF_AENQ_WAIT) { 882 sc->sc_flags &= ~TWEF_AENQ_WAIT; 883 wakeup(&sc->sc_aen_queue); 884 } 885 886 splx(s); 887 } 888 889 /* NOTE: Must be called at splbio(). */ 890 static uint16_t 891 twe_aen_dequeue(struct twe_softc *sc) 892 { 893 uint16_t aen; 894 895 if (sc->sc_aen_tail == sc->sc_aen_head) 896 aen = TWE_AEN_QUEUE_EMPTY; 897 else { 898 aen = sc->sc_aen_queue[sc->sc_aen_tail]; 899 sc->sc_aen_tail = (sc->sc_aen_tail + 1) & TWE_AEN_Q_LENGTH; 900 } 901 902 return (aen); 903 } 904 905 /* 906 * These are short-hand functions that execute TWE_OP_GET_PARAM to 907 * fetch 1, 2, and 4 byte parameter values, respectively. 908 */ 909 int 910 twe_param_get_1(struct twe_softc *sc, int table_id, int param_id, 911 uint8_t *valp) 912 { 913 struct twe_param *tp; 914 int rv; 915 916 rv = twe_param_get(sc, table_id, param_id, 1, NULL, &tp); 917 if (rv != 0) 918 return (rv); 919 *valp = *(uint8_t *)tp->tp_data; 920 free(tp, M_DEVBUF); 921 return (0); 922 } 923 924 int 925 twe_param_get_2(struct twe_softc *sc, int table_id, int param_id, 926 uint16_t *valp) 927 { 928 struct twe_param *tp; 929 int rv; 930 931 rv = twe_param_get(sc, table_id, param_id, 2, NULL, &tp); 932 if (rv != 0) 933 return (rv); 934 *valp = le16toh(*(uint16_t *)tp->tp_data); 935 free(tp, M_DEVBUF); 936 return (0); 937 } 938 939 int 940 twe_param_get_4(struct twe_softc *sc, int table_id, int param_id, 941 uint32_t *valp) 942 { 943 struct twe_param *tp; 944 int rv; 945 946 rv = twe_param_get(sc, table_id, param_id, 4, NULL, &tp); 947 if (rv != 0) 948 return (rv); 949 *valp = le32toh(*(uint32_t *)tp->tp_data); 950 free(tp, M_DEVBUF); 951 return (0); 952 } 953 954 /* 955 * Execute a TWE_OP_GET_PARAM command. If a callback function is provided, 956 * it will be called with generated context when the command has completed. 957 * If no callback is provided, the command will be executed synchronously 958 * and a pointer to a buffer containing the data returned. 959 * 960 * The caller or callback is responsible for freeing the buffer. 961 */ 962 int 963 twe_param_get(struct twe_softc *sc, int table_id, int param_id, size_t size, 964 void (*func)(struct twe_ccb *, int), struct twe_param **pbuf) 965 { 966 struct twe_ccb *ccb; 967 struct twe_cmd *tc; 968 struct twe_param *tp; 969 int rv, s; 970 971 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 972 if (tp == NULL) 973 return ENOMEM; 974 975 rv = twe_ccb_alloc(sc, &ccb, 976 TWE_CCB_PARAM | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 977 if (rv != 0) 978 goto done; 979 980 ccb->ccb_data = tp; 981 ccb->ccb_datasize = TWE_SECTOR_SIZE; 982 ccb->ccb_tx.tx_handler = func; 983 ccb->ccb_tx.tx_context = tp; 984 ccb->ccb_tx.tx_dv = &sc->sc_dv; 985 986 tc = ccb->ccb_cmd; 987 tc->tc_size = 2; 988 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 989 tc->tc_unit = 0; 990 tc->tc_count = htole16(1); 991 992 /* Fill in the outbound parameter data. */ 993 tp->tp_table_id = htole16(table_id); 994 tp->tp_param_id = param_id; 995 tp->tp_param_size = size; 996 997 /* Map the transfer. */ 998 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 999 twe_ccb_free(sc, ccb); 1000 goto done; 1001 } 1002 1003 /* Submit the command and either wait or let the callback handle it. */ 1004 if (func == NULL) { 1005 s = splbio(); 1006 rv = twe_ccb_poll(sc, ccb, 5); 1007 twe_ccb_unmap(sc, ccb); 1008 twe_ccb_free(sc, ccb); 1009 splx(s); 1010 } else { 1011 #ifdef DEBUG 1012 if (pbuf != NULL) 1013 panic("both func and pbuf defined"); 1014 #endif 1015 twe_ccb_enqueue(sc, ccb); 1016 return 0; 1017 } 1018 1019 done: 1020 if (pbuf == NULL || rv != 0) 1021 free(tp, M_DEVBUF); 1022 else if (pbuf != NULL && rv == 0) 1023 *pbuf = tp; 1024 return rv; 1025 } 1026 1027 /* 1028 * Execute a TWE_OP_SET_PARAM command. 1029 */ 1030 static int 1031 twe_param_set(struct twe_softc *sc, int table_id, int param_id, size_t size, 1032 void *buf) 1033 { 1034 struct twe_ccb *ccb; 1035 struct twe_cmd *tc; 1036 struct twe_param *tp; 1037 int rv, s; 1038 1039 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 1040 if (tp == NULL) 1041 return ENOMEM; 1042 1043 rv = twe_ccb_alloc(sc, &ccb, 1044 TWE_CCB_PARAM | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1045 if (rv != 0) 1046 goto done; 1047 1048 ccb->ccb_data = tp; 1049 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1050 ccb->ccb_tx.tx_handler = 0; 1051 ccb->ccb_tx.tx_context = tp; 1052 ccb->ccb_tx.tx_dv = &sc->sc_dv; 1053 1054 tc = ccb->ccb_cmd; 1055 tc->tc_size = 2; 1056 tc->tc_opcode = TWE_OP_SET_PARAM | (tc->tc_size << 5); 1057 tc->tc_unit = 0; 1058 tc->tc_count = htole16(1); 1059 1060 /* Fill in the outbound parameter data. */ 1061 tp->tp_table_id = htole16(table_id); 1062 tp->tp_param_id = param_id; 1063 tp->tp_param_size = size; 1064 memcpy(tp->tp_data, buf, size); 1065 1066 /* Map the transfer. */ 1067 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 1068 twe_ccb_free(sc, ccb); 1069 goto done; 1070 } 1071 1072 /* Submit the command and wait. */ 1073 s = splbio(); 1074 rv = twe_ccb_poll(sc, ccb, 5); 1075 twe_ccb_unmap(sc, ccb); 1076 twe_ccb_free(sc, ccb); 1077 splx(s); 1078 done: 1079 free(tp, M_DEVBUF); 1080 return (rv); 1081 } 1082 1083 /* 1084 * Execute a TWE_OP_INIT_CONNECTION command. Return non-zero on error. 1085 * Must be called with interrupts blocked. 1086 */ 1087 static int 1088 twe_init_connection(struct twe_softc *sc) 1089 /*###762 [cc] warning: `twe_init_connection' was used with no prototype before its definition%%%*/ 1090 /*###762 [cc] warning: `twe_init_connection' was declared implicitly `extern' and later `static'%%%*/ 1091 { 1092 struct twe_ccb *ccb; 1093 struct twe_cmd *tc; 1094 int rv; 1095 1096 if ((rv = twe_ccb_alloc(sc, &ccb, 0)) != 0) 1097 return (rv); 1098 1099 /* Build the command. */ 1100 tc = ccb->ccb_cmd; 1101 tc->tc_size = 3; 1102 tc->tc_opcode = TWE_OP_INIT_CONNECTION; 1103 tc->tc_unit = 0; 1104 tc->tc_count = htole16(TWE_MAX_CMDS); 1105 tc->tc_args.init_connection.response_queue_pointer = 0; 1106 1107 /* Submit the command for immediate execution. */ 1108 rv = twe_ccb_poll(sc, ccb, 5); 1109 twe_ccb_free(sc, ccb); 1110 return (rv); 1111 } 1112 1113 /* 1114 * Poll the controller for completed commands. Must be called with 1115 * interrupts blocked. 1116 */ 1117 static void 1118 twe_poll(struct twe_softc *sc) 1119 { 1120 struct twe_ccb *ccb; 1121 int found; 1122 u_int status, cmdid; 1123 1124 found = 0; 1125 1126 for (;;) { 1127 status = twe_inl(sc, TWE_REG_STS); 1128 twe_status_check(sc, status); 1129 1130 if ((status & TWE_STS_RESP_QUEUE_EMPTY)) 1131 break; 1132 1133 found = 1; 1134 cmdid = twe_inl(sc, TWE_REG_RESP_QUEUE); 1135 cmdid = (cmdid & TWE_RESP_MASK) >> TWE_RESP_SHIFT; 1136 if (cmdid >= TWE_MAX_QUEUECNT) { 1137 printf("%s: bad completion\n", sc->sc_dv.dv_xname); 1138 continue; 1139 } 1140 1141 ccb = sc->sc_ccbs + cmdid; 1142 if ((ccb->ccb_flags & TWE_CCB_ACTIVE) == 0) { 1143 printf("%s: bad completion (not active)\n", 1144 sc->sc_dv.dv_xname); 1145 continue; 1146 } 1147 ccb->ccb_flags ^= TWE_CCB_COMPLETE | TWE_CCB_ACTIVE; 1148 1149 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1150 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, 1151 sizeof(struct twe_cmd), 1152 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1153 1154 /* Pass notification to upper layers. */ 1155 if (ccb->ccb_tx.tx_handler != NULL) 1156 (*ccb->ccb_tx.tx_handler)(ccb, 1157 ccb->ccb_cmd->tc_status != 0 ? EIO : 0); 1158 } 1159 1160 /* If any commands have completed, run the software queue. */ 1161 if (found) 1162 twe_ccb_enqueue(sc, NULL); 1163 } 1164 1165 /* 1166 * Wait for `status' to be set in the controller status register. Return 1167 * zero if found, non-zero if the operation timed out. 1168 */ 1169 static int 1170 twe_status_wait(struct twe_softc *sc, u_int32_t status, int timo) 1171 { 1172 1173 for (timo *= 10; timo != 0; timo--) { 1174 if ((twe_inl(sc, TWE_REG_STS) & status) == status) 1175 break; 1176 delay(100000); 1177 } 1178 1179 return (timo == 0); 1180 } 1181 1182 /* 1183 * Complain if the status bits aren't what we expect. 1184 */ 1185 static int 1186 twe_status_check(struct twe_softc *sc, u_int status) 1187 { 1188 int rv; 1189 1190 rv = 0; 1191 1192 if ((status & TWE_STS_EXPECTED_BITS) != TWE_STS_EXPECTED_BITS) { 1193 printf("%s: missing status bits: 0x%08x\n", sc->sc_dv.dv_xname, 1194 status & ~TWE_STS_EXPECTED_BITS); 1195 rv = -1; 1196 } 1197 1198 if ((status & TWE_STS_UNEXPECTED_BITS) != 0) { 1199 printf("%s: unexpected status bits: 0x%08x\n", 1200 sc->sc_dv.dv_xname, status & TWE_STS_UNEXPECTED_BITS); 1201 rv = -1; 1202 } 1203 1204 return (rv); 1205 } 1206 1207 /* 1208 * Allocate and initialise a CCB. 1209 */ 1210 int 1211 twe_ccb_alloc(struct twe_softc *sc, struct twe_ccb **ccbp, int flags) 1212 { 1213 struct twe_cmd *tc; 1214 struct twe_ccb *ccb; 1215 int s; 1216 1217 s = splbio(); 1218 if ((flags & TWE_CCB_PARAM) != 0) 1219 ccb = sc->sc_ccbs; 1220 else { 1221 /* Allocate a CCB and command block. */ 1222 if (SLIST_FIRST(&sc->sc_ccb_freelist) == NULL) { 1223 splx(s); 1224 return (EAGAIN); 1225 } 1226 ccb = SLIST_FIRST(&sc->sc_ccb_freelist); 1227 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 1228 } 1229 #ifdef DIAGNOSTIC 1230 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 1231 panic("twe_ccb_alloc: CCB already allocated"); 1232 flags |= TWE_CCB_ALLOCED; 1233 #endif 1234 splx(s); 1235 1236 /* Initialise some fields and return. */ 1237 ccb->ccb_tx.tx_handler = NULL; 1238 ccb->ccb_flags = flags; 1239 tc = ccb->ccb_cmd; 1240 tc->tc_status = 0; 1241 tc->tc_flags = 0; 1242 tc->tc_cmdid = ccb->ccb_cmdid; 1243 *ccbp = ccb; 1244 1245 return (0); 1246 } 1247 1248 /* 1249 * Free a CCB. 1250 */ 1251 void 1252 twe_ccb_free(struct twe_softc *sc, struct twe_ccb *ccb) 1253 { 1254 int s; 1255 1256 s = splbio(); 1257 if ((ccb->ccb_flags & TWE_CCB_PARAM) == 0) 1258 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, ccb_chain.slist); 1259 ccb->ccb_flags = 0; 1260 splx(s); 1261 } 1262 1263 /* 1264 * Map the specified CCB's command block and data buffer (if any) into 1265 * controller visible space. Perform DMA synchronisation. 1266 */ 1267 int 1268 twe_ccb_map(struct twe_softc *sc, struct twe_ccb *ccb) 1269 { 1270 struct twe_cmd *tc; 1271 int flags, nsegs, i, s, rv; 1272 void *data; 1273 1274 /* 1275 * The data as a whole must be 512-byte aligned. 1276 */ 1277 if (((u_long)ccb->ccb_data & (TWE_ALIGNMENT - 1)) != 0) { 1278 s = splvm(); 1279 /* XXX */ 1280 ccb->ccb_abuf = uvm_km_kmemalloc(kmem_map, NULL, 1281 ccb->ccb_datasize, UVM_KMF_NOWAIT); 1282 splx(s); 1283 data = (void *)ccb->ccb_abuf; 1284 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1285 memcpy(data, ccb->ccb_data, ccb->ccb_datasize); 1286 } else { 1287 ccb->ccb_abuf = (vaddr_t)0; 1288 data = ccb->ccb_data; 1289 } 1290 1291 /* 1292 * Map the data buffer into bus space and build the S/G list. 1293 */ 1294 rv = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap_xfer, data, 1295 ccb->ccb_datasize, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1296 ((ccb->ccb_flags & TWE_CCB_DATA_IN) ? 1297 BUS_DMA_READ : BUS_DMA_WRITE)); 1298 if (rv != 0) { 1299 if (ccb->ccb_abuf != (vaddr_t)0) { 1300 s = splvm(); 1301 /* XXX */ 1302 uvm_km_free(kmem_map, ccb->ccb_abuf, 1303 ccb->ccb_datasize); 1304 splx(s); 1305 } 1306 return (rv); 1307 } 1308 1309 nsegs = ccb->ccb_dmamap_xfer->dm_nsegs; 1310 tc = ccb->ccb_cmd; 1311 tc->tc_size += 2 * nsegs; 1312 1313 /* The location of the S/G list is dependant upon command type. */ 1314 switch (tc->tc_opcode >> 5) { 1315 case 2: 1316 for (i = 0; i < nsegs; i++) { 1317 tc->tc_args.param.sgl[i].tsg_address = 1318 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 1319 tc->tc_args.param.sgl[i].tsg_length = 1320 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 1321 } 1322 /* XXX Needed? */ 1323 for (; i < TWE_SG_SIZE; i++) { 1324 tc->tc_args.param.sgl[i].tsg_address = 0; 1325 tc->tc_args.param.sgl[i].tsg_length = 0; 1326 } 1327 break; 1328 case 3: 1329 for (i = 0; i < nsegs; i++) { 1330 tc->tc_args.io.sgl[i].tsg_address = 1331 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 1332 tc->tc_args.io.sgl[i].tsg_length = 1333 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 1334 } 1335 /* XXX Needed? */ 1336 for (; i < TWE_SG_SIZE; i++) { 1337 tc->tc_args.io.sgl[i].tsg_address = 0; 1338 tc->tc_args.io.sgl[i].tsg_length = 0; 1339 } 1340 break; 1341 #ifdef DEBUG 1342 default: 1343 panic("twe_ccb_map: oops"); 1344 #endif 1345 } 1346 1347 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1348 flags = BUS_DMASYNC_PREREAD; 1349 else 1350 flags = 0; 1351 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1352 flags |= BUS_DMASYNC_PREWRITE; 1353 1354 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 1355 ccb->ccb_datasize, flags); 1356 return (0); 1357 } 1358 1359 /* 1360 * Unmap the specified CCB's command block and data buffer (if any) and 1361 * perform DMA synchronisation. 1362 */ 1363 void 1364 twe_ccb_unmap(struct twe_softc *sc, struct twe_ccb *ccb) 1365 { 1366 int flags, s; 1367 1368 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1369 flags = BUS_DMASYNC_POSTREAD; 1370 else 1371 flags = 0; 1372 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1373 flags |= BUS_DMASYNC_POSTWRITE; 1374 1375 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 1376 ccb->ccb_datasize, flags); 1377 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap_xfer); 1378 1379 if (ccb->ccb_abuf != (vaddr_t)0) { 1380 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1381 memcpy(ccb->ccb_data, (void *)ccb->ccb_abuf, 1382 ccb->ccb_datasize); 1383 s = splvm(); 1384 /* XXX */ 1385 uvm_km_free(kmem_map, ccb->ccb_abuf, ccb->ccb_datasize); 1386 splx(s); 1387 } 1388 } 1389 1390 /* 1391 * Submit a command to the controller and poll on completion. Return 1392 * non-zero on timeout (but don't check status, as some command types don't 1393 * return status). Must be called with interrupts blocked. 1394 */ 1395 int 1396 twe_ccb_poll(struct twe_softc *sc, struct twe_ccb *ccb, int timo) 1397 { 1398 int rv; 1399 1400 if ((rv = twe_ccb_submit(sc, ccb)) != 0) 1401 return (rv); 1402 1403 for (timo *= 1000; timo != 0; timo--) { 1404 twe_poll(sc); 1405 if ((ccb->ccb_flags & TWE_CCB_COMPLETE) != 0) 1406 break; 1407 DELAY(100); 1408 } 1409 1410 return (timo == 0); 1411 } 1412 1413 /* 1414 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1415 * the order that they were enqueued and try to submit their command blocks 1416 * to the controller for execution. 1417 */ 1418 void 1419 twe_ccb_enqueue(struct twe_softc *sc, struct twe_ccb *ccb) 1420 { 1421 int s; 1422 1423 s = splbio(); 1424 1425 if (ccb != NULL) 1426 SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 1427 1428 while ((ccb = SIMPLEQ_FIRST(&sc->sc_ccb_queue)) != NULL) { 1429 if (twe_ccb_submit(sc, ccb)) 1430 break; 1431 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_queue, ccb_chain.simpleq); 1432 } 1433 1434 splx(s); 1435 } 1436 1437 /* 1438 * Submit the command block associated with the specified CCB to the 1439 * controller for execution. Must be called with interrupts blocked. 1440 */ 1441 int 1442 twe_ccb_submit(struct twe_softc *sc, struct twe_ccb *ccb) 1443 { 1444 bus_addr_t pa; 1445 int rv; 1446 u_int status; 1447 1448 /* Check to see if we can post a command. */ 1449 status = twe_inl(sc, TWE_REG_STS); 1450 twe_status_check(sc, status); 1451 1452 if ((status & TWE_STS_CMD_QUEUE_FULL) == 0) { 1453 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1454 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, sizeof(struct twe_cmd), 1455 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1456 ccb->ccb_flags |= TWE_CCB_ACTIVE; 1457 pa = sc->sc_cmds_paddr + 1458 ccb->ccb_cmdid * sizeof(struct twe_cmd); 1459 twe_outl(sc, TWE_REG_CMD_QUEUE, (u_int32_t)pa); 1460 rv = 0; 1461 } else 1462 rv = EBUSY; 1463 1464 return (rv); 1465 } 1466 1467 1468 /* 1469 * Accept an open operation on the control device. 1470 */ 1471 int 1472 tweopen(dev_t dev, int flag, int mode, struct proc *p) 1473 { 1474 struct twe_softc *twe; 1475 1476 if ((twe = device_lookup(&twe_cd, minor(dev))) == NULL) 1477 return (ENXIO); 1478 if ((twe->sc_flags & TWEF_OPEN) != 0) 1479 return (EBUSY); 1480 1481 twe->sc_flags |= TWEF_OPEN; 1482 return (0); 1483 } 1484 1485 /* 1486 * Accept the last close on the control device. 1487 */ 1488 int 1489 tweclose(dev_t dev, int flag, int mode, struct proc *p) 1490 { 1491 struct twe_softc *twe; 1492 1493 twe = device_lookup(&twe_cd, minor(dev)); 1494 twe->sc_flags &= ~TWEF_OPEN; 1495 return (0); 1496 } 1497 1498 /* 1499 * Handle control operations. 1500 */ 1501 int 1502 tweioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1503 { 1504 struct twe_softc *twe; 1505 struct twe_ccb *ccb; 1506 struct twe_param *param; 1507 struct twe_usercommand *tu; 1508 struct twe_paramcommand *tp; 1509 union twe_statrequest *ts; 1510 void *pdata = NULL; 1511 int rv, s, error = 0; 1512 u_int8_t cmdid; 1513 1514 if (securelevel >= 2) 1515 return (EPERM); 1516 1517 twe = device_lookup(&twe_cd, minor(dev)); 1518 tu = (struct twe_usercommand *)data; 1519 tp = (struct twe_paramcommand *)data; 1520 ts = (union twe_statrequest *)data; 1521 1522 /* Hmm, compatible with FreeBSD */ 1523 switch (cmd) { 1524 case TWEIO_COMMAND: 1525 if (tu->tu_size > 0) { 1526 if (tu->tu_size > TWE_SECTOR_SIZE) 1527 return EINVAL; 1528 pdata = malloc(tu->tu_size, M_DEVBUF, M_WAITOK); 1529 error = copyin(tu->tu_data, pdata, tu->tu_size); 1530 if (error != 0) 1531 goto done; 1532 error = twe_ccb_alloc(twe, &ccb, TWE_CCB_PARAM | 1533 TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1534 } else { 1535 error = twe_ccb_alloc(twe, &ccb, 0); 1536 } 1537 if (rv != 0) 1538 goto done; 1539 cmdid = ccb->ccb_cmdid; 1540 memcpy(ccb->ccb_cmd, &tu->tu_cmd, sizeof(struct twe_cmd)); 1541 ccb->ccb_cmdid = cmdid; 1542 if (ccb->ccb_flags & TWE_CCB_PARAM) { 1543 ccb->ccb_data = pdata; 1544 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1545 ccb->ccb_tx.tx_handler = 0; 1546 ccb->ccb_tx.tx_context = pdata; 1547 ccb->ccb_tx.tx_dv = &twe->sc_dv; 1548 } 1549 /* Map the transfer. */ 1550 if ((error = twe_ccb_map(twe, ccb)) != 0) { 1551 twe_ccb_free(twe, ccb); 1552 goto done; 1553 } 1554 1555 /* Submit the command and wait. */ 1556 s = splbio(); 1557 rv = twe_ccb_poll(twe, ccb, 5); 1558 twe_ccb_unmap(twe, ccb); 1559 twe_ccb_free(twe, ccb); 1560 splx(s); 1561 1562 if (tu->tu_size > 0) 1563 error = copyout(pdata, tu->tu_data, tu->tu_size); 1564 goto done; 1565 1566 case TWEIO_STATS: 1567 return (ENOENT); 1568 1569 case TWEIO_AEN_POLL: 1570 s = splbio(); 1571 *(u_int *)data = twe_aen_dequeue(twe); 1572 splx(s); 1573 return (0); 1574 1575 case TWEIO_AEN_WAIT: 1576 s = splbio(); 1577 while ((*(u_int *)data = 1578 twe_aen_dequeue(twe)) == TWE_AEN_QUEUE_EMPTY) { 1579 twe->sc_flags |= TWEF_AENQ_WAIT; 1580 error = tsleep(&twe->sc_aen_queue, PRIBIO | PCATCH, 1581 "tweaen", 0); 1582 if (error == EINTR) { 1583 splx(s); 1584 return (error); 1585 } 1586 } 1587 splx(s); 1588 return (0); 1589 1590 case TWEIO_GET_PARAM: 1591 error = twe_param_get(twe, tp->tp_table_id, tp->tp_param_id, 1592 tp->tp_size, 0, ¶m); 1593 if (error != 0) 1594 return (error); 1595 if (param->tp_param_size > tp->tp_size) { 1596 error = EFAULT; 1597 goto done; 1598 } 1599 error = copyout(param->tp_data, tp->tp_data, 1600 param->tp_param_size); 1601 goto done; 1602 1603 case TWEIO_SET_PARAM: 1604 pdata = malloc(tp->tp_size, M_DEVBUF, M_WAITOK); 1605 if ((error = copyin(tp->tp_data, pdata, tp->tp_size)) != 0) 1606 goto done; 1607 error = twe_param_set(twe, tp->tp_table_id, tp->tp_param_id, 1608 tp->tp_size, pdata); 1609 goto done; 1610 1611 case TWEIO_RESET: 1612 twe_reset(twe); 1613 return (0); 1614 1615 case TWEIO_ADD_UNIT: 1616 /* XXX mutex */ 1617 return (twe_add_unit(twe, *(int *)data)); 1618 1619 case TWEIO_DEL_UNIT: 1620 /* XXX mutex */ 1621 return (twe_del_unit(twe, *(int *)data)); 1622 1623 default: 1624 return EINVAL; 1625 } 1626 done: 1627 if (pdata) 1628 free(pdata, M_DEVBUF); 1629 return error; 1630 } 1631 1632 /* 1633 * Print some information about the controller 1634 */ 1635 static void 1636 twe_describe_controller(struct twe_softc *sc) 1637 { 1638 struct twe_param *p[6]; 1639 int i, rv = 0; 1640 uint32_t dsize; 1641 uint8_t ports; 1642 1643 /* get the port count */ 1644 rv |= twe_param_get_1(sc, TWE_PARAM_CONTROLLER, 1645 TWE_PARAM_CONTROLLER_PortCount, &ports); 1646 1647 /* get version strings */ 1648 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_Mon, 1649 16, NULL, &p[0]); 1650 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_FW, 1651 16, NULL, &p[1]); 1652 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_BIOS, 1653 16, NULL, &p[2]); 1654 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_PCB, 1655 8, NULL, &p[3]); 1656 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_ATA, 1657 8, NULL, &p[4]); 1658 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_PCI, 1659 8, NULL, &p[5]); 1660 1661 if (rv) { 1662 /* some error occurred */ 1663 aprint_error("%s: failed to fetch version information\n", 1664 sc->sc_dv.dv_xname); 1665 return; 1666 } 1667 1668 aprint_normal("%s: %d ports, Firmware %.16s, BIOS %.16s\n", 1669 sc->sc_dv.dv_xname, ports, 1670 p[1]->tp_data, p[2]->tp_data); 1671 1672 aprint_verbose("%s: Monitor %.16s, PCB %.8s, Achip %.8s, Pchip %.8s\n", 1673 sc->sc_dv.dv_xname, 1674 p[0]->tp_data, p[3]->tp_data, 1675 p[4]->tp_data, p[5]->tp_data); 1676 1677 free(p[0], M_DEVBUF); 1678 free(p[1], M_DEVBUF); 1679 free(p[2], M_DEVBUF); 1680 free(p[3], M_DEVBUF); 1681 free(p[4], M_DEVBUF); 1682 free(p[5], M_DEVBUF); 1683 1684 rv = twe_param_get(sc, TWE_PARAM_DRIVESUMMARY, 1685 TWE_PARAM_DRIVESUMMARY_Status, 16, NULL, &p[0]); 1686 if (rv) { 1687 aprint_error("%s: failed to get drive status summary\n", 1688 sc->sc_dv.dv_xname); 1689 return; 1690 } 1691 for (i = 0; i < ports; i++) { 1692 if (p[0]->tp_data[i] != TWE_PARAM_DRIVESTATUS_Present) 1693 continue; 1694 rv = twe_param_get_4(sc, TWE_PARAM_DRIVEINFO + i, 1695 TWE_PARAM_DRIVEINFO_Size, &dsize); 1696 if (rv) { 1697 aprint_error( 1698 "%s: unable to get drive size for port %d\n", 1699 sc->sc_dv.dv_xname, i); 1700 continue; 1701 } 1702 rv = twe_param_get(sc, TWE_PARAM_DRIVEINFO + i, 1703 TWE_PARAM_DRIVEINFO_Model, 40, NULL, &p[1]); 1704 if (rv) { 1705 aprint_error( 1706 "%s: unable to get drive model for port %d\n", 1707 sc->sc_dv.dv_xname, i); 1708 continue; 1709 } 1710 aprint_verbose("%s: port %d: %.40s %d MB\n", sc->sc_dv.dv_xname, 1711 i, p[1]->tp_data, dsize / 2048); 1712 free(p[1], M_DEVBUF); 1713 } 1714 free(p[0], M_DEVBUF); 1715 } 1716
Indexes created Sun Sep 21 20:09:37 GMT 2025