twe.c revision 1.47
1 /* $NetBSD: twe.c,v 1.47 2003/09/23 23:08:54 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran; and by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twe.c,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 /* 69 * Driver for the 3ware Escalade family of RAID controllers. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: twe.c,v 1.47 2003/09/23 23:08:54 thorpej Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/device.h> 79 #include <sys/queue.h> 80 #include <sys/proc.h> 81 #include <sys/buf.h> 82 #include <sys/endian.h> 83 #include <sys/malloc.h> 84 #include <sys/conf.h> 85 #include <sys/disk.h> 86 87 #include <uvm/uvm_extern.h> 88 89 #include <machine/bswap.h> 90 #include <machine/bus.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/twereg.h> 96 #include <dev/pci/twevar.h> 97 #include <dev/pci/tweio.h> 98 99 #define PCI_CBIO 0x10 100 101 static int twe_aen_get(struct twe_softc *, uint16_t *); 102 static void twe_aen_handler(struct twe_ccb *, int); 103 static void twe_aen_enqueue(struct twe_softc *sc, uint16_t, int); 104 static uint16_t twe_aen_dequeue(struct twe_softc *); 105 106 static void twe_attach(struct device *, struct device *, void *); 107 static int twe_init_connection(struct twe_softc *); 108 static int twe_intr(void *); 109 static int twe_match(struct device *, struct cfdata *, void *); 110 static int twe_param_set(struct twe_softc *, int, int, size_t, void *); 111 static void twe_poll(struct twe_softc *); 112 static int twe_print(void *, const char *); 113 static int twe_reset(struct twe_softc *); 114 static int twe_submatch(struct device *, struct cfdata *, void *); 115 static int twe_status_check(struct twe_softc *, u_int); 116 static int twe_status_wait(struct twe_softc *, u_int, int); 117 static void twe_describe_controller(struct twe_softc *); 118 119 static int twe_add_unit(struct twe_softc *, int); 120 static int twe_del_unit(struct twe_softc *, int); 121 122 static inline u_int32_t twe_inl(struct twe_softc *, int); 123 static inline void twe_outl(struct twe_softc *, int, u_int32_t); 124 125 dev_type_open(tweopen); 126 dev_type_close(tweclose); 127 dev_type_ioctl(tweioctl); 128 129 const struct cdevsw twe_cdevsw = { 130 tweopen, tweclose, noread, nowrite, tweioctl, 131 nostop, notty, nopoll, nommap, 132 }; 133 134 extern struct cfdriver twe_cd; 135 136 CFATTACH_DECL(twe, sizeof(struct twe_softc), 137 twe_match, twe_attach, NULL, NULL); 138 139 /* 140 * Tables to convert numeric codes to strings. 141 */ 142 const struct twe_code_table twe_table_status[] = { 143 { 0x00, "successful completion" }, 144 145 /* info */ 146 { 0x42, "command in progress" }, 147 { 0x6c, "retrying interface CRC error from UDMA command" }, 148 149 /* warning */ 150 { 0x81, "redundant/inconsequential request ignored" }, 151 { 0x8e, "failed to write zeroes to LBA 0" }, 152 { 0x8f, "failed to profile TwinStor zones" }, 153 154 /* fatal */ 155 { 0xc1, "aborted due to system command or reconfiguration" }, 156 { 0xc4, "aborted" }, 157 { 0xc5, "access error" }, 158 { 0xc6, "access violation" }, 159 { 0xc7, "device failure" }, /* high byte may be port # */ 160 { 0xc8, "controller error" }, 161 { 0xc9, "timed out" }, 162 { 0xcb, "invalid unit number" }, 163 { 0xcf, "unit not available" }, 164 { 0xd2, "undefined opcode" }, 165 { 0xdb, "request incompatible with unit" }, 166 { 0xdc, "invalid request" }, 167 { 0xff, "firmware error, reset requested" }, 168 169 { 0, NULL } 170 }; 171 172 const struct twe_code_table twe_table_unitstate[] = { 173 { TWE_PARAM_UNITSTATUS_Normal, "Normal" }, 174 { TWE_PARAM_UNITSTATUS_Initialising, "Initializing" }, 175 { TWE_PARAM_UNITSTATUS_Degraded, "Degraded" }, 176 { TWE_PARAM_UNITSTATUS_Rebuilding, "Rebuilding" }, 177 { TWE_PARAM_UNITSTATUS_Verifying, "Verifying" }, 178 { TWE_PARAM_UNITSTATUS_Corrupt, "Corrupt" }, 179 { TWE_PARAM_UNITSTATUS_Missing, "Missing" }, 180 181 { 0, NULL } 182 }; 183 184 const struct twe_code_table twe_table_unittype[] = { 185 /* array descriptor configuration */ 186 { TWE_AD_CONFIG_RAID0, "RAID0" }, 187 { TWE_AD_CONFIG_RAID1, "RAID1" }, 188 { TWE_AD_CONFIG_TwinStor, "TwinStor" }, 189 { TWE_AD_CONFIG_RAID5, "RAID5" }, 190 { TWE_AD_CONFIG_RAID10, "RAID10" }, 191 192 { 0, NULL } 193 }; 194 195 const struct twe_code_table twe_table_stripedepth[] = { 196 { TWE_AD_STRIPE_4k, "4K" }, 197 { TWE_AD_STRIPE_8k, "8K" }, 198 { TWE_AD_STRIPE_16k, "16K" }, 199 { TWE_AD_STRIPE_32k, "32K" }, 200 { TWE_AD_STRIPE_64k, "64K" }, 201 202 { 0, NULL } 203 }; 204 205 /* 206 * Asynchronous event notification messages are qualified: 207 * a - not unit/port specific 208 * u - unit specific 209 * p - port specific 210 */ 211 const struct twe_code_table twe_table_aen[] = { 212 { 0x00, "a queue empty" }, 213 { 0x01, "a soft reset" }, 214 { 0x02, "u degraded mode" }, 215 { 0x03, "a controller error" }, 216 { 0x04, "u rebuild fail" }, 217 { 0x05, "u rebuild done" }, 218 { 0x06, "u incomplete unit" }, 219 { 0x07, "u initialization done" }, 220 { 0x08, "u unclean shutdown detected" }, 221 { 0x09, "p drive timeout" }, 222 { 0x0a, "p drive error" }, 223 { 0x0b, "u rebuild started" }, 224 { 0x0c, "u initialization started" }, 225 { 0x0d, "u logical unit deleted" }, 226 { 0x0f, "p SMART threshold exceeded" }, 227 { 0x15, "a table undefined" }, /* XXX: Not in FreeBSD's table */ 228 { 0x21, "p ATA UDMA downgrade" }, 229 { 0x22, "p ATA UDMA upgrade" }, 230 { 0x23, "p sector repair occurred" }, 231 { 0x24, "a SBUF integrity check failure" }, 232 { 0x25, "p lost cached write" }, 233 { 0x26, "p drive ECC error detected" }, 234 { 0x27, "p DCB checksum error" }, 235 { 0x28, "p DCB unsupported version" }, 236 { 0x29, "u verify started" }, 237 { 0x2a, "u verify failed" }, 238 { 0x2b, "u verify complete" }, 239 { 0x2c, "p overwrote bad sector during rebuild" }, 240 { 0x2d, "p encountered bad sector during rebuild" }, 241 { 0x2e, "p replacement drive too small" }, 242 { 0x2f, "u array not previously initialized" }, 243 { 0x30, "p drive not supported" }, 244 { 0xff, "a aen queue full" }, 245 246 { 0, NULL }, 247 }; 248 249 const char * 250 twe_describe_code(const struct twe_code_table *table, uint32_t code) 251 { 252 253 for (; table->string != NULL; table++) { 254 if (table->code == code) 255 return (table->string); 256 } 257 return (NULL); 258 } 259 260 static inline u_int32_t 261 twe_inl(struct twe_softc *sc, int off) 262 { 263 264 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 265 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 266 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, off)); 267 } 268 269 static inline void 270 twe_outl(struct twe_softc *sc, int off, u_int32_t val) 271 { 272 273 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 274 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 275 BUS_SPACE_BARRIER_WRITE); 276 } 277 278 /* 279 * Match a supported board. 280 */ 281 static int 282 twe_match(struct device *parent, struct cfdata *cfdata, void *aux) 283 { 284 struct pci_attach_args *pa; 285 286 pa = aux; 287 288 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3WARE && 289 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE || 290 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE_ASIC)); 291 } 292 293 /* 294 * Attach a supported board. 295 * 296 * XXX This doesn't fail gracefully. 297 */ 298 static void 299 twe_attach(struct device *parent, struct device *self, void *aux) 300 { 301 struct pci_attach_args *pa; 302 struct twe_softc *sc; 303 pci_chipset_tag_t pc; 304 pci_intr_handle_t ih; 305 pcireg_t csr; 306 const char *intrstr; 307 int s, size, i, rv, rseg; 308 size_t max_segs, max_xfer; 309 bus_dma_segment_t seg; 310 struct twe_cmd *tc; 311 struct twe_ccb *ccb; 312 313 sc = (struct twe_softc *)self; 314 pa = aux; 315 pc = pa->pa_pc; 316 sc->sc_dmat = pa->pa_dmat; 317 SIMPLEQ_INIT(&sc->sc_ccb_queue); 318 SLIST_INIT(&sc->sc_ccb_freelist); 319 320 aprint_naive(": RAID controller\n"); 321 aprint_normal(": 3ware Escalade\n"); 322 323 ccb = malloc(sizeof(*ccb) * TWE_MAX_QUEUECNT, M_DEVBUF, M_NOWAIT); 324 if (ccb == NULL) { 325 aprint_error("%s: unable to allocate memory for ccbs\n", 326 sc->sc_dv.dv_xname); 327 return; 328 } 329 330 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 331 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 332 aprint_error("%s: can't map i/o space\n", sc->sc_dv.dv_xname); 333 return; 334 } 335 336 /* Enable the device. */ 337 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 338 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 339 csr | PCI_COMMAND_MASTER_ENABLE); 340 341 /* Map and establish the interrupt. */ 342 if (pci_intr_map(pa, &ih)) { 343 aprint_error("%s: can't map interrupt\n", sc->sc_dv.dv_xname); 344 return; 345 } 346 347 intrstr = pci_intr_string(pc, ih); 348 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, twe_intr, sc); 349 if (sc->sc_ih == NULL) { 350 aprint_error("%s: can't establish interrupt%s%s\n", 351 sc->sc_dv.dv_xname, 352 (intrstr) ? " at " : "", 353 (intrstr) ? intrstr : ""); 354 return; 355 } 356 357 if (intrstr != NULL) 358 aprint_normal("%s: interrupting at %s\n", 359 sc->sc_dv.dv_xname, intrstr); 360 361 /* 362 * Allocate and initialise the command blocks and CCBs. 363 */ 364 size = sizeof(struct twe_cmd) * TWE_MAX_QUEUECNT; 365 366 if ((rv = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 1, 367 &rseg, BUS_DMA_NOWAIT)) != 0) { 368 aprint_error("%s: unable to allocate commands, rv = %d\n", 369 sc->sc_dv.dv_xname, rv); 370 return; 371 } 372 373 if ((rv = bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 374 (caddr_t *)&sc->sc_cmds, 375 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 376 aprint_error("%s: unable to map commands, rv = %d\n", 377 sc->sc_dv.dv_xname, rv); 378 return; 379 } 380 381 if ((rv = bus_dmamap_create(sc->sc_dmat, size, size, 1, 0, 382 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 383 aprint_error("%s: unable to create command DMA map, rv = %d\n", 384 sc->sc_dv.dv_xname, rv); 385 return; 386 } 387 388 if ((rv = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cmds, 389 size, NULL, BUS_DMA_NOWAIT)) != 0) { 390 aprint_error("%s: unable to load command DMA map, rv = %d\n", 391 sc->sc_dv.dv_xname, rv); 392 return; 393 } 394 395 sc->sc_cmds_paddr = sc->sc_dmamap->dm_segs[0].ds_addr; 396 memset(sc->sc_cmds, 0, size); 397 398 sc->sc_ccbs = ccb; 399 tc = (struct twe_cmd *)sc->sc_cmds; 400 max_segs = twe_get_maxsegs(); 401 max_xfer = twe_get_maxxfer(max_segs); 402 403 for (i = 0; i < TWE_MAX_QUEUECNT; i++, tc++, ccb++) { 404 ccb->ccb_cmd = tc; 405 ccb->ccb_cmdid = i; 406 ccb->ccb_flags = 0; 407 rv = bus_dmamap_create(sc->sc_dmat, max_xfer, 408 max_segs, PAGE_SIZE, 0, 409 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 410 &ccb->ccb_dmamap_xfer); 411 if (rv != 0) { 412 aprint_error("%s: can't create dmamap, rv = %d\n", 413 sc->sc_dv.dv_xname, rv); 414 return; 415 } 416 417 /* Save the first CCB for AEN retrieval. */ 418 if (i != 0) 419 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, 420 ccb_chain.slist); 421 } 422 423 /* Wait for the controller to become ready. */ 424 if (twe_status_wait(sc, TWE_STS_MICROCONTROLLER_READY, 6)) { 425 aprint_error("%s: microcontroller not ready\n", 426 sc->sc_dv.dv_xname); 427 return; 428 } 429 430 twe_outl(sc, TWE_REG_CTL, TWE_CTL_DISABLE_INTRS); 431 432 /* Reset the controller. */ 433 s = splbio(); 434 rv = twe_reset(sc); 435 splx(s); 436 if (rv) { 437 aprint_error("%s: reset failed\n", sc->sc_dv.dv_xname); 438 return; 439 } 440 441 /* Initialise connection with controller. */ 442 twe_init_connection(sc); 443 444 twe_describe_controller(sc); 445 446 /* Find and attach RAID array units. */ 447 sc->sc_nunits = 0; 448 for (i = 0; i < TWE_MAX_UNITS; i++) 449 (void) twe_add_unit(sc, i); 450 451 /* ...and finally, enable interrupts. */ 452 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR | 453 TWE_CTL_UNMASK_RESP_INTR | 454 TWE_CTL_ENABLE_INTRS); 455 } 456 457 void 458 twe_register_callbacks(struct twe_softc *sc, int unit, 459 const struct twe_callbacks *tcb) 460 { 461 462 sc->sc_units[unit].td_callbacks = tcb; 463 } 464 465 static void 466 twe_recompute_openings(struct twe_softc *sc) 467 { 468 struct twe_drive *td; 469 int unit, openings; 470 471 if (sc->sc_nunits != 0) 472 openings = (TWE_MAX_QUEUECNT - 1) / sc->sc_nunits; 473 else 474 openings = 0; 475 if (openings == sc->sc_openings) 476 return; 477 sc->sc_openings = openings; 478 479 #ifdef TWE_DEBUG 480 printf("%s: %d array%s, %d openings per array\n", 481 sc->sc_dv.dv_xname, sc->sc_nunits, 482 sc->sc_nunits == 1 ? "" : "s", sc->sc_openings); 483 #endif 484 485 for (unit = 0; unit < TWE_MAX_UNITS; unit++) { 486 td = &sc->sc_units[unit]; 487 if (td->td_dev != NULL) 488 (*td->td_callbacks->tcb_openings)(td->td_dev, 489 sc->sc_openings); 490 } 491 } 492 493 static int 494 twe_add_unit(struct twe_softc *sc, int unit) 495 { 496 struct twe_param *dtp, *atp; 497 struct twe_array_descriptor *ad; 498 struct twe_drive *td; 499 struct twe_attach_args twea; 500 uint32_t newsize; 501 int rv; 502 uint16_t dsize; 503 uint8_t newtype, newstripe; 504 505 if (unit < 0 || unit >= TWE_MAX_UNITS) 506 return (EINVAL); 507 508 /* Find attached units. */ 509 rv = twe_param_get(sc, TWE_PARAM_UNITSUMMARY, 510 TWE_PARAM_UNITSUMMARY_Status, TWE_MAX_UNITS, NULL, &dtp); 511 if (rv != 0) { 512 aprint_error("%s: error %d fetching unit summary\n", 513 sc->sc_dv.dv_xname, rv); 514 return (rv); 515 } 516 517 /* For each detected unit, collect size and store in an array. */ 518 td = &sc->sc_units[unit]; 519 520 /* Unit present? */ 521 if ((dtp->tp_data[unit] & TWE_PARAM_UNITSTATUS_Online) == 0) { 522 /* 523 * XXX Should we check to see if a device has been 524 * XXX attached at this index and detach it if it 525 * XXX has? ("rescan" semantics) 526 */ 527 rv = 0; 528 goto out; 529 } 530 531 rv = twe_param_get_2(sc, TWE_PARAM_UNITINFO + unit, 532 TWE_PARAM_UNITINFO_DescriptorSize, &dsize); 533 if (rv != 0) { 534 aprint_error("%s: error %d fetching descriptor size " 535 "for unit %d\n", sc->sc_dv.dv_xname, rv, unit); 536 goto out; 537 } 538 539 rv = twe_param_get(sc, TWE_PARAM_UNITINFO + unit, 540 TWE_PARAM_UNITINFO_Descriptor, dsize - 3, NULL, &atp); 541 if (rv != 0) { 542 aprint_error("%s: error %d fetching array descriptor " 543 "for unit %d\n", sc->sc_dv.dv_xname, rv, unit); 544 goto out; 545 } 546 547 ad = (struct twe_array_descriptor *)atp->tp_data; 548 newtype = ad->configuration; 549 newstripe = ad->stripe_size; 550 free(atp, M_DEVBUF); 551 552 rv = twe_param_get_4(sc, TWE_PARAM_UNITINFO + unit, 553 TWE_PARAM_UNITINFO_Capacity, &newsize); 554 if (rv != 0) { 555 aprint_error( 556 "%s: error %d fetching capacity for unit %d\n", 557 sc->sc_dv.dv_xname, rv, unit); 558 goto out; 559 } 560 561 /* 562 * Have a device, so we need to attach it. If there is currently 563 * something sitting at the slot, and the parameters are different, 564 * then we detach the old device before attaching the new one. 565 */ 566 if (td->td_dev != NULL && 567 td->td_size == newsize && 568 td->td_type == newtype && 569 td->td_stripe == newstripe) { 570 /* Same as the old device; just keep using it. */ 571 rv = 0; 572 goto out; 573 } else if (td->td_dev != NULL) { 574 /* Detach the old device first. */ 575 (void) config_detach(td->td_dev, DETACH_FORCE); 576 td->td_dev = NULL; 577 } else if (td->td_size == 0) 578 sc->sc_nunits++; 579 580 /* 581 * Committed to the new array unit; assign its parameters and 582 * recompute the number of available command openings. 583 */ 584 td->td_size = newsize; 585 td->td_type = newtype; 586 td->td_stripe = newstripe; 587 twe_recompute_openings(sc); 588 589 twea.twea_unit = unit; 590 td->td_dev = config_found_sm(&sc->sc_dv, &twea, twe_print, 591 twe_submatch); 592 593 rv = 0; 594 out: 595 free(dtp, M_DEVBUF); 596 return (rv); 597 } 598 599 static int 600 twe_del_unit(struct twe_softc *sc, int unit) 601 { 602 struct twe_drive *td; 603 604 if (unit < 0 || unit >= TWE_MAX_UNITS) 605 return (EINVAL); 606 607 td = &sc->sc_units[unit]; 608 if (td->td_size != 0) 609 sc->sc_nunits--; 610 td->td_size = 0; 611 td->td_type = 0; 612 td->td_stripe = 0; 613 if (td->td_dev != NULL) { 614 (void) config_detach(td->td_dev, DETACH_FORCE); 615 td->td_dev = NULL; 616 } 617 twe_recompute_openings(sc); 618 return (0); 619 } 620 621 /* 622 * Reset the controller. 623 * MUST BE CALLED AT splbio()! 624 */ 625 static int 626 twe_reset(struct twe_softc *sc) 627 { 628 uint16_t aen; 629 u_int status; 630 volatile u_int32_t junk; 631 int got, rv; 632 633 /* Issue a soft reset. */ 634 twe_outl(sc, TWE_REG_CTL, TWE_CTL_ISSUE_SOFT_RESET | 635 TWE_CTL_CLEAR_HOST_INTR | 636 TWE_CTL_CLEAR_ATTN_INTR | 637 TWE_CTL_MASK_CMD_INTR | 638 TWE_CTL_MASK_RESP_INTR | 639 TWE_CTL_CLEAR_ERROR_STS | 640 TWE_CTL_DISABLE_INTRS); 641 642 /* Wait for attention... */ 643 if (twe_status_wait(sc, TWE_STS_ATTN_INTR, 15)) { 644 printf("%s: no attention interrupt\n", 645 sc->sc_dv.dv_xname); 646 return (-1); 647 } 648 649 /* ...and ACK it. */ 650 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 651 652 /* 653 * Pull AENs out of the controller; look for a soft reset AEN. 654 * Open code this, since we want to detect reset even if the 655 * queue for management tools is full. 656 */ 657 sc->sc_flags &= ~TWEF_AEN; 658 for (got = 0;;) { 659 rv = twe_aen_get(sc, &aen); 660 if (rv != 0) 661 printf("%s: error %d while draining event queue\n", 662 sc->sc_dv.dv_xname, rv); 663 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) 664 break; 665 if (TWE_AEN_CODE(aen) == TWE_AEN_SOFT_RESET) 666 got = 1; 667 twe_aen_enqueue(sc, aen, 1); 668 } 669 670 if (!got) { 671 printf("%s: reset not reported\n", sc->sc_dv.dv_xname); 672 return (-1); 673 } 674 675 /* Check controller status. */ 676 status = twe_inl(sc, TWE_REG_STS); 677 if (twe_status_check(sc, status)) { 678 printf("%s: controller errors detected\n", 679 sc->sc_dv.dv_xname); 680 return (-1); 681 } 682 683 /* Drain the response queue. */ 684 for (;;) { 685 status = twe_inl(sc, TWE_REG_STS); 686 if (twe_status_check(sc, status) != 0) { 687 printf("%s: can't drain response queue\n", 688 sc->sc_dv.dv_xname); 689 return (-1); 690 } 691 if ((status & TWE_STS_RESP_QUEUE_EMPTY) != 0) 692 break; 693 junk = twe_inl(sc, TWE_REG_RESP_QUEUE); 694 } 695 696 return (0); 697 } 698 699 /* 700 * Print autoconfiguration message for a sub-device. 701 */ 702 static int 703 twe_print(void *aux, const char *pnp) 704 { 705 struct twe_attach_args *twea; 706 707 twea = aux; 708 709 if (pnp != NULL) 710 aprint_normal("block device at %s", pnp); 711 aprint_normal(" unit %d", twea->twea_unit); 712 return (UNCONF); 713 } 714 715 /* 716 * Match a sub-device. 717 */ 718 static int 719 twe_submatch(struct device *parent, struct cfdata *cf, void *aux) 720 { 721 struct twe_attach_args *twea; 722 723 twea = aux; 724 725 if (cf->tweacf_unit != TWECF_UNIT_DEFAULT && 726 cf->tweacf_unit != twea->twea_unit) 727 return (0); 728 729 return (config_match(parent, cf, aux)); 730 } 731 732 /* 733 * Interrupt service routine. 734 */ 735 static int 736 twe_intr(void *arg) 737 { 738 struct twe_softc *sc; 739 u_int status; 740 int caught, rv; 741 742 sc = arg; 743 caught = 0; 744 status = twe_inl(sc, TWE_REG_STS); 745 twe_status_check(sc, status); 746 747 /* Host interrupts - purpose unknown. */ 748 if ((status & TWE_STS_HOST_INTR) != 0) { 749 #ifdef DEBUG 750 printf("%s: host interrupt\n", sc->sc_dv.dv_xname); 751 #endif 752 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_HOST_INTR); 753 caught = 1; 754 } 755 756 /* 757 * Attention interrupts, signalled when a controller or child device 758 * state change has occurred. 759 */ 760 if ((status & TWE_STS_ATTN_INTR) != 0) { 761 rv = twe_aen_get(sc, NULL); 762 if (rv != 0) 763 printf("%s: unable to retrieve AEN (%d)\n", 764 sc->sc_dv.dv_xname, rv); 765 else 766 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 767 caught = 1; 768 } 769 770 /* 771 * Command interrupts, signalled when the controller can accept more 772 * commands. We don't use this; instead, we try to submit commands 773 * when we receive them, and when other commands have completed. 774 * Mask it so we don't get another one. 775 */ 776 if ((status & TWE_STS_CMD_INTR) != 0) { 777 #ifdef DEBUG 778 printf("%s: command interrupt\n", sc->sc_dv.dv_xname); 779 #endif 780 twe_outl(sc, TWE_REG_CTL, TWE_CTL_MASK_CMD_INTR); 781 caught = 1; 782 } 783 784 if ((status & TWE_STS_RESP_INTR) != 0) { 785 twe_poll(sc); 786 caught = 1; 787 } 788 789 return (caught); 790 } 791 792 /* 793 * Fetch an AEN. Even though this is really like parameter 794 * retrieval, we handle this specially, because we issue this 795 * AEN retrieval command from interrupt context, and thus 796 * reserve a CCB for it to avoid resource shortage. 797 * 798 * XXX There are still potential resource shortages we could 799 * XXX encounter. Consider pre-allocating all AEN-related 800 * XXX resources. 801 * 802 * MUST BE CALLED AT splbio()! 803 */ 804 static int 805 twe_aen_get(struct twe_softc *sc, uint16_t *aenp) 806 { 807 struct twe_ccb *ccb; 808 struct twe_cmd *tc; 809 struct twe_param *tp; 810 int rv; 811 812 /* 813 * If we're already retrieving an AEN, just wait; another 814 * retrieval will be chained after the current one completes. 815 */ 816 if (sc->sc_flags & TWEF_AEN) { 817 /* 818 * It is a fatal software programming error to attempt 819 * to fetch an AEN synchronously when an AEN fetch is 820 * already pending. 821 */ 822 KASSERT(aenp == NULL); 823 return (0); 824 } 825 826 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 827 if (tp == NULL) 828 return (ENOMEM); 829 830 rv = twe_ccb_alloc(sc, &ccb, 831 TWE_CCB_AEN | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 832 if (rv != 0) 833 goto done; 834 835 ccb->ccb_data = tp; 836 ccb->ccb_datasize = TWE_SECTOR_SIZE; 837 ccb->ccb_tx.tx_handler = (aenp == NULL) ? twe_aen_handler : NULL; 838 ccb->ccb_tx.tx_context = tp; 839 ccb->ccb_tx.tx_dv = &sc->sc_dv; 840 841 tc = ccb->ccb_cmd; 842 tc->tc_size = 2; 843 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 844 tc->tc_unit = 0; 845 tc->tc_count = htole16(1); 846 847 /* Fill in the outbound parameter data. */ 848 tp->tp_table_id = htole16(TWE_PARAM_AEN); 849 tp->tp_param_id = TWE_PARAM_AEN_UnitCode; 850 tp->tp_param_size = 2; 851 852 /* Map the transfer. */ 853 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 854 twe_ccb_free(sc, ccb); 855 goto done; 856 } 857 858 /* Enqueue the command and wait. */ 859 if (aenp != NULL) { 860 rv = twe_ccb_poll(sc, ccb, 5); 861 twe_ccb_unmap(sc, ccb); 862 twe_ccb_free(sc, ccb); 863 if (rv == 0) 864 *aenp = le16toh(*(uint16_t *)tp->tp_data); 865 free(tp, M_DEVBUF); 866 } else { 867 sc->sc_flags |= TWEF_AEN; 868 twe_ccb_enqueue(sc, ccb); 869 rv = 0; 870 } 871 872 done: 873 return (rv); 874 } 875 876 /* 877 * Handle an AEN returned by the controller. 878 * MUST BE CALLED AT splbio()! 879 */ 880 static void 881 twe_aen_handler(struct twe_ccb *ccb, int error) 882 { 883 struct twe_softc *sc; 884 struct twe_param *tp; 885 uint16_t aen; 886 int rv; 887 888 sc = (struct twe_softc *)ccb->ccb_tx.tx_dv; 889 tp = ccb->ccb_tx.tx_context; 890 twe_ccb_unmap(sc, ccb); 891 892 sc->sc_flags &= ~TWEF_AEN; 893 894 if (error) { 895 printf("%s: error retrieving AEN\n", sc->sc_dv.dv_xname); 896 aen = TWE_AEN_QUEUE_EMPTY; 897 } else 898 aen = le16toh(*(u_int16_t *)tp->tp_data); 899 free(tp, M_DEVBUF); 900 twe_ccb_free(sc, ccb); 901 902 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) { 903 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 904 return; 905 } 906 907 twe_aen_enqueue(sc, aen, 0); 908 909 /* 910 * Chain another retrieval in case interrupts have been 911 * coalesced. 912 */ 913 rv = twe_aen_get(sc, NULL); 914 if (rv != 0) 915 printf("%s: unable to retrieve AEN (%d)\n", 916 sc->sc_dv.dv_xname, rv); 917 } 918 919 static void 920 twe_aen_enqueue(struct twe_softc *sc, uint16_t aen, int quiet) 921 { 922 const char *str, *msg; 923 int s, next, nextnext; 924 925 /* 926 * First report the AEN on the console. Maybe. 927 */ 928 if (! quiet) { 929 str = twe_describe_code(twe_table_aen, TWE_AEN_CODE(aen)); 930 if (str == NULL) { 931 printf("%s: unknown AEN 0x%04x\n", 932 sc->sc_dv.dv_xname, aen); 933 } else { 934 msg = str + 2; 935 switch (*str) { 936 case 'u': 937 printf("%s: unit %d: %s\n", 938 sc->sc_dv.dv_xname, TWE_AEN_UNIT(aen), msg); 939 break; 940 941 case 'p': 942 printf("%s: port %d: %s\n", 943 sc->sc_dv.dv_xname, TWE_AEN_UNIT(aen), msg); 944 break; 945 946 default: 947 printf("%s: %s\n", sc->sc_dv.dv_xname, msg); 948 } 949 } 950 } 951 952 /* Now enqueue the AEN for mangement tools. */ 953 s = splbio(); 954 955 next = (sc->sc_aen_head + 1) % TWE_AEN_Q_LENGTH; 956 nextnext = (sc->sc_aen_head + 2) % TWE_AEN_Q_LENGTH; 957 958 /* 959 * If this is the last free slot, then queue up a "queue 960 * full" message. 961 */ 962 if (nextnext == sc->sc_aen_tail) 963 aen = TWE_AEN_QUEUE_FULL; 964 965 if (next != sc->sc_aen_tail) { 966 sc->sc_aen_queue[sc->sc_aen_head] = aen; 967 sc->sc_aen_head = next; 968 } 969 970 if (sc->sc_flags & TWEF_AENQ_WAIT) { 971 sc->sc_flags &= ~TWEF_AENQ_WAIT; 972 wakeup(&sc->sc_aen_queue); 973 } 974 975 splx(s); 976 } 977 978 /* NOTE: Must be called at splbio(). */ 979 static uint16_t 980 twe_aen_dequeue(struct twe_softc *sc) 981 { 982 uint16_t aen; 983 984 if (sc->sc_aen_tail == sc->sc_aen_head) 985 aen = TWE_AEN_QUEUE_EMPTY; 986 else { 987 aen = sc->sc_aen_queue[sc->sc_aen_tail]; 988 sc->sc_aen_tail = (sc->sc_aen_tail + 1) & TWE_AEN_Q_LENGTH; 989 } 990 991 return (aen); 992 } 993 994 /* 995 * These are short-hand functions that execute TWE_OP_GET_PARAM to 996 * fetch 1, 2, and 4 byte parameter values, respectively. 997 */ 998 int 999 twe_param_get_1(struct twe_softc *sc, int table_id, int param_id, 1000 uint8_t *valp) 1001 { 1002 struct twe_param *tp; 1003 int rv; 1004 1005 rv = twe_param_get(sc, table_id, param_id, 1, NULL, &tp); 1006 if (rv != 0) 1007 return (rv); 1008 *valp = *(uint8_t *)tp->tp_data; 1009 free(tp, M_DEVBUF); 1010 return (0); 1011 } 1012 1013 int 1014 twe_param_get_2(struct twe_softc *sc, int table_id, int param_id, 1015 uint16_t *valp) 1016 { 1017 struct twe_param *tp; 1018 int rv; 1019 1020 rv = twe_param_get(sc, table_id, param_id, 2, NULL, &tp); 1021 if (rv != 0) 1022 return (rv); 1023 *valp = le16toh(*(uint16_t *)tp->tp_data); 1024 free(tp, M_DEVBUF); 1025 return (0); 1026 } 1027 1028 int 1029 twe_param_get_4(struct twe_softc *sc, int table_id, int param_id, 1030 uint32_t *valp) 1031 { 1032 struct twe_param *tp; 1033 int rv; 1034 1035 rv = twe_param_get(sc, table_id, param_id, 4, NULL, &tp); 1036 if (rv != 0) 1037 return (rv); 1038 *valp = le32toh(*(uint32_t *)tp->tp_data); 1039 free(tp, M_DEVBUF); 1040 return (0); 1041 } 1042 1043 /* 1044 * Execute a TWE_OP_GET_PARAM command. If a callback function is provided, 1045 * it will be called with generated context when the command has completed. 1046 * If no callback is provided, the command will be executed synchronously 1047 * and a pointer to a buffer containing the data returned. 1048 * 1049 * The caller or callback is responsible for freeing the buffer. 1050 */ 1051 int 1052 twe_param_get(struct twe_softc *sc, int table_id, int param_id, size_t size, 1053 void (*func)(struct twe_ccb *, int), struct twe_param **pbuf) 1054 { 1055 struct twe_ccb *ccb; 1056 struct twe_cmd *tc; 1057 struct twe_param *tp; 1058 int rv, s; 1059 1060 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 1061 if (tp == NULL) 1062 return ENOMEM; 1063 1064 rv = twe_ccb_alloc(sc, &ccb, TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1065 if (rv != 0) 1066 goto done; 1067 1068 ccb->ccb_data = tp; 1069 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1070 ccb->ccb_tx.tx_handler = func; 1071 ccb->ccb_tx.tx_context = tp; 1072 ccb->ccb_tx.tx_dv = &sc->sc_dv; 1073 1074 tc = ccb->ccb_cmd; 1075 tc->tc_size = 2; 1076 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 1077 tc->tc_unit = 0; 1078 tc->tc_count = htole16(1); 1079 1080 /* Fill in the outbound parameter data. */ 1081 tp->tp_table_id = htole16(table_id); 1082 tp->tp_param_id = param_id; 1083 tp->tp_param_size = size; 1084 1085 /* Map the transfer. */ 1086 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 1087 twe_ccb_free(sc, ccb); 1088 goto done; 1089 } 1090 1091 /* Submit the command and either wait or let the callback handle it. */ 1092 if (func == NULL) { 1093 s = splbio(); 1094 rv = twe_ccb_poll(sc, ccb, 5); 1095 twe_ccb_unmap(sc, ccb); 1096 twe_ccb_free(sc, ccb); 1097 splx(s); 1098 } else { 1099 #ifdef DEBUG 1100 if (pbuf != NULL) 1101 panic("both func and pbuf defined"); 1102 #endif 1103 twe_ccb_enqueue(sc, ccb); 1104 return 0; 1105 } 1106 1107 done: 1108 if (pbuf == NULL || rv != 0) 1109 free(tp, M_DEVBUF); 1110 else if (pbuf != NULL && rv == 0) 1111 *pbuf = tp; 1112 return rv; 1113 } 1114 1115 /* 1116 * Execute a TWE_OP_SET_PARAM command. 1117 */ 1118 static int 1119 twe_param_set(struct twe_softc *sc, int table_id, int param_id, size_t size, 1120 void *buf) 1121 { 1122 struct twe_ccb *ccb; 1123 struct twe_cmd *tc; 1124 struct twe_param *tp; 1125 int rv, s; 1126 1127 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 1128 if (tp == NULL) 1129 return ENOMEM; 1130 1131 rv = twe_ccb_alloc(sc, &ccb, TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1132 if (rv != 0) 1133 goto done; 1134 1135 ccb->ccb_data = tp; 1136 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1137 ccb->ccb_tx.tx_handler = 0; 1138 ccb->ccb_tx.tx_context = tp; 1139 ccb->ccb_tx.tx_dv = &sc->sc_dv; 1140 1141 tc = ccb->ccb_cmd; 1142 tc->tc_size = 2; 1143 tc->tc_opcode = TWE_OP_SET_PARAM | (tc->tc_size << 5); 1144 tc->tc_unit = 0; 1145 tc->tc_count = htole16(1); 1146 1147 /* Fill in the outbound parameter data. */ 1148 tp->tp_table_id = htole16(table_id); 1149 tp->tp_param_id = param_id; 1150 tp->tp_param_size = size; 1151 memcpy(tp->tp_data, buf, size); 1152 1153 /* Map the transfer. */ 1154 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 1155 twe_ccb_free(sc, ccb); 1156 goto done; 1157 } 1158 1159 /* Submit the command and wait. */ 1160 s = splbio(); 1161 rv = twe_ccb_poll(sc, ccb, 5); 1162 twe_ccb_unmap(sc, ccb); 1163 twe_ccb_free(sc, ccb); 1164 splx(s); 1165 done: 1166 free(tp, M_DEVBUF); 1167 return (rv); 1168 } 1169 1170 /* 1171 * Execute a TWE_OP_INIT_CONNECTION command. Return non-zero on error. 1172 * Must be called with interrupts blocked. 1173 */ 1174 static int 1175 twe_init_connection(struct twe_softc *sc) 1176 /*###762 [cc] warning: `twe_init_connection' was used with no prototype before its definition%%%*/ 1177 /*###762 [cc] warning: `twe_init_connection' was declared implicitly `extern' and later `static'%%%*/ 1178 { 1179 struct twe_ccb *ccb; 1180 struct twe_cmd *tc; 1181 int rv; 1182 1183 if ((rv = twe_ccb_alloc(sc, &ccb, 0)) != 0) 1184 return (rv); 1185 1186 /* Build the command. */ 1187 tc = ccb->ccb_cmd; 1188 tc->tc_size = 3; 1189 tc->tc_opcode = TWE_OP_INIT_CONNECTION; 1190 tc->tc_unit = 0; 1191 tc->tc_count = htole16(TWE_MAX_CMDS); 1192 tc->tc_args.init_connection.response_queue_pointer = 0; 1193 1194 /* Submit the command for immediate execution. */ 1195 rv = twe_ccb_poll(sc, ccb, 5); 1196 twe_ccb_free(sc, ccb); 1197 return (rv); 1198 } 1199 1200 /* 1201 * Poll the controller for completed commands. Must be called with 1202 * interrupts blocked. 1203 */ 1204 static void 1205 twe_poll(struct twe_softc *sc) 1206 { 1207 struct twe_ccb *ccb; 1208 int found; 1209 u_int status, cmdid; 1210 1211 found = 0; 1212 1213 for (;;) { 1214 status = twe_inl(sc, TWE_REG_STS); 1215 twe_status_check(sc, status); 1216 1217 if ((status & TWE_STS_RESP_QUEUE_EMPTY)) 1218 break; 1219 1220 found = 1; 1221 cmdid = twe_inl(sc, TWE_REG_RESP_QUEUE); 1222 cmdid = (cmdid & TWE_RESP_MASK) >> TWE_RESP_SHIFT; 1223 if (cmdid >= TWE_MAX_QUEUECNT) { 1224 printf("%s: bad completion\n", sc->sc_dv.dv_xname); 1225 continue; 1226 } 1227 1228 ccb = sc->sc_ccbs + cmdid; 1229 if ((ccb->ccb_flags & TWE_CCB_ACTIVE) == 0) { 1230 printf("%s: bad completion (not active)\n", 1231 sc->sc_dv.dv_xname); 1232 continue; 1233 } 1234 ccb->ccb_flags ^= TWE_CCB_COMPLETE | TWE_CCB_ACTIVE; 1235 1236 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1237 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, 1238 sizeof(struct twe_cmd), 1239 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1240 1241 /* Pass notification to upper layers. */ 1242 if (ccb->ccb_tx.tx_handler != NULL) 1243 (*ccb->ccb_tx.tx_handler)(ccb, 1244 ccb->ccb_cmd->tc_status != 0 ? EIO : 0); 1245 } 1246 1247 /* If any commands have completed, run the software queue. */ 1248 if (found) 1249 twe_ccb_enqueue(sc, NULL); 1250 } 1251 1252 /* 1253 * Wait for `status' to be set in the controller status register. Return 1254 * zero if found, non-zero if the operation timed out. 1255 */ 1256 static int 1257 twe_status_wait(struct twe_softc *sc, u_int32_t status, int timo) 1258 { 1259 1260 for (timo *= 10; timo != 0; timo--) { 1261 if ((twe_inl(sc, TWE_REG_STS) & status) == status) 1262 break; 1263 delay(100000); 1264 } 1265 1266 return (timo == 0); 1267 } 1268 1269 /* 1270 * Complain if the status bits aren't what we expect. 1271 */ 1272 static int 1273 twe_status_check(struct twe_softc *sc, u_int status) 1274 { 1275 int rv; 1276 1277 rv = 0; 1278 1279 if ((status & TWE_STS_EXPECTED_BITS) != TWE_STS_EXPECTED_BITS) { 1280 printf("%s: missing status bits: 0x%08x\n", sc->sc_dv.dv_xname, 1281 status & ~TWE_STS_EXPECTED_BITS); 1282 rv = -1; 1283 } 1284 1285 if ((status & TWE_STS_UNEXPECTED_BITS) != 0) { 1286 printf("%s: unexpected status bits: 0x%08x\n", 1287 sc->sc_dv.dv_xname, status & TWE_STS_UNEXPECTED_BITS); 1288 rv = -1; 1289 } 1290 1291 return (rv); 1292 } 1293 1294 /* 1295 * Allocate and initialise a CCB. 1296 */ 1297 int 1298 twe_ccb_alloc(struct twe_softc *sc, struct twe_ccb **ccbp, int flags) 1299 { 1300 struct twe_cmd *tc; 1301 struct twe_ccb *ccb; 1302 int s; 1303 1304 s = splbio(); 1305 if ((flags & TWE_CCB_AEN) != 0) { 1306 /* Use the reserved CCB. */ 1307 ccb = sc->sc_ccbs; 1308 } else { 1309 /* Allocate a CCB and command block. */ 1310 if (SLIST_FIRST(&sc->sc_ccb_freelist) == NULL) { 1311 splx(s); 1312 return (EAGAIN); 1313 } 1314 ccb = SLIST_FIRST(&sc->sc_ccb_freelist); 1315 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 1316 } 1317 #ifdef DIAGNOSTIC 1318 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 1319 panic("twe_ccb_alloc: CCB already allocated"); 1320 flags |= TWE_CCB_ALLOCED; 1321 #endif 1322 splx(s); 1323 1324 /* Initialise some fields and return. */ 1325 ccb->ccb_tx.tx_handler = NULL; 1326 ccb->ccb_flags = flags; 1327 tc = ccb->ccb_cmd; 1328 tc->tc_status = 0; 1329 tc->tc_flags = 0; 1330 tc->tc_cmdid = ccb->ccb_cmdid; 1331 *ccbp = ccb; 1332 1333 return (0); 1334 } 1335 1336 /* 1337 * Free a CCB. 1338 */ 1339 void 1340 twe_ccb_free(struct twe_softc *sc, struct twe_ccb *ccb) 1341 { 1342 int s; 1343 1344 s = splbio(); 1345 if ((ccb->ccb_flags & TWE_CCB_AEN) == 0) 1346 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, ccb_chain.slist); 1347 ccb->ccb_flags = 0; 1348 splx(s); 1349 } 1350 1351 /* 1352 * Map the specified CCB's command block and data buffer (if any) into 1353 * controller visible space. Perform DMA synchronisation. 1354 */ 1355 int 1356 twe_ccb_map(struct twe_softc *sc, struct twe_ccb *ccb) 1357 { 1358 struct twe_cmd *tc; 1359 int flags, nsegs, i, s, rv; 1360 void *data; 1361 1362 /* 1363 * The data as a whole must be 512-byte aligned. 1364 */ 1365 if (((u_long)ccb->ccb_data & (TWE_ALIGNMENT - 1)) != 0) { 1366 s = splvm(); 1367 /* XXX */ 1368 ccb->ccb_abuf = uvm_km_kmemalloc(kmem_map, NULL, 1369 ccb->ccb_datasize, UVM_KMF_NOWAIT); 1370 splx(s); 1371 data = (void *)ccb->ccb_abuf; 1372 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1373 memcpy(data, ccb->ccb_data, ccb->ccb_datasize); 1374 } else { 1375 ccb->ccb_abuf = (vaddr_t)0; 1376 data = ccb->ccb_data; 1377 } 1378 1379 /* 1380 * Map the data buffer into bus space and build the S/G list. 1381 */ 1382 rv = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap_xfer, data, 1383 ccb->ccb_datasize, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1384 ((ccb->ccb_flags & TWE_CCB_DATA_IN) ? 1385 BUS_DMA_READ : BUS_DMA_WRITE)); 1386 if (rv != 0) { 1387 if (ccb->ccb_abuf != (vaddr_t)0) { 1388 s = splvm(); 1389 /* XXX */ 1390 uvm_km_free(kmem_map, ccb->ccb_abuf, 1391 ccb->ccb_datasize); 1392 splx(s); 1393 } 1394 return (rv); 1395 } 1396 1397 nsegs = ccb->ccb_dmamap_xfer->dm_nsegs; 1398 tc = ccb->ccb_cmd; 1399 tc->tc_size += 2 * nsegs; 1400 1401 /* The location of the S/G list is dependant upon command type. */ 1402 switch (tc->tc_opcode >> 5) { 1403 case 2: 1404 for (i = 0; i < nsegs; i++) { 1405 tc->tc_args.param.sgl[i].tsg_address = 1406 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 1407 tc->tc_args.param.sgl[i].tsg_length = 1408 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 1409 } 1410 /* XXX Needed? */ 1411 for (; i < TWE_SG_SIZE; i++) { 1412 tc->tc_args.param.sgl[i].tsg_address = 0; 1413 tc->tc_args.param.sgl[i].tsg_length = 0; 1414 } 1415 break; 1416 case 3: 1417 for (i = 0; i < nsegs; i++) { 1418 tc->tc_args.io.sgl[i].tsg_address = 1419 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 1420 tc->tc_args.io.sgl[i].tsg_length = 1421 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 1422 } 1423 /* XXX Needed? */ 1424 for (; i < TWE_SG_SIZE; i++) { 1425 tc->tc_args.io.sgl[i].tsg_address = 0; 1426 tc->tc_args.io.sgl[i].tsg_length = 0; 1427 } 1428 break; 1429 #ifdef DEBUG 1430 default: 1431 panic("twe_ccb_map: oops"); 1432 #endif 1433 } 1434 1435 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1436 flags = BUS_DMASYNC_PREREAD; 1437 else 1438 flags = 0; 1439 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1440 flags |= BUS_DMASYNC_PREWRITE; 1441 1442 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 1443 ccb->ccb_datasize, flags); 1444 return (0); 1445 } 1446 1447 /* 1448 * Unmap the specified CCB's command block and data buffer (if any) and 1449 * perform DMA synchronisation. 1450 */ 1451 void 1452 twe_ccb_unmap(struct twe_softc *sc, struct twe_ccb *ccb) 1453 { 1454 int flags, s; 1455 1456 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1457 flags = BUS_DMASYNC_POSTREAD; 1458 else 1459 flags = 0; 1460 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1461 flags |= BUS_DMASYNC_POSTWRITE; 1462 1463 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 1464 ccb->ccb_datasize, flags); 1465 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap_xfer); 1466 1467 if (ccb->ccb_abuf != (vaddr_t)0) { 1468 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1469 memcpy(ccb->ccb_data, (void *)ccb->ccb_abuf, 1470 ccb->ccb_datasize); 1471 s = splvm(); 1472 /* XXX */ 1473 uvm_km_free(kmem_map, ccb->ccb_abuf, ccb->ccb_datasize); 1474 splx(s); 1475 } 1476 } 1477 1478 /* 1479 * Submit a command to the controller and poll on completion. Return 1480 * non-zero on timeout (but don't check status, as some command types don't 1481 * return status). Must be called with interrupts blocked. 1482 */ 1483 int 1484 twe_ccb_poll(struct twe_softc *sc, struct twe_ccb *ccb, int timo) 1485 { 1486 int rv; 1487 1488 if ((rv = twe_ccb_submit(sc, ccb)) != 0) 1489 return (rv); 1490 1491 for (timo *= 1000; timo != 0; timo--) { 1492 twe_poll(sc); 1493 if ((ccb->ccb_flags & TWE_CCB_COMPLETE) != 0) 1494 break; 1495 DELAY(100); 1496 } 1497 1498 return (timo == 0); 1499 } 1500 1501 /* 1502 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1503 * the order that they were enqueued and try to submit their command blocks 1504 * to the controller for execution. 1505 */ 1506 void 1507 twe_ccb_enqueue(struct twe_softc *sc, struct twe_ccb *ccb) 1508 { 1509 int s; 1510 1511 s = splbio(); 1512 1513 if (ccb != NULL) 1514 SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 1515 1516 while ((ccb = SIMPLEQ_FIRST(&sc->sc_ccb_queue)) != NULL) { 1517 if (twe_ccb_submit(sc, ccb)) 1518 break; 1519 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_queue, ccb_chain.simpleq); 1520 } 1521 1522 splx(s); 1523 } 1524 1525 /* 1526 * Submit the command block associated with the specified CCB to the 1527 * controller for execution. Must be called with interrupts blocked. 1528 */ 1529 int 1530 twe_ccb_submit(struct twe_softc *sc, struct twe_ccb *ccb) 1531 { 1532 bus_addr_t pa; 1533 int rv; 1534 u_int status; 1535 1536 /* Check to see if we can post a command. */ 1537 status = twe_inl(sc, TWE_REG_STS); 1538 twe_status_check(sc, status); 1539 1540 if ((status & TWE_STS_CMD_QUEUE_FULL) == 0) { 1541 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1542 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, sizeof(struct twe_cmd), 1543 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1544 ccb->ccb_flags |= TWE_CCB_ACTIVE; 1545 pa = sc->sc_cmds_paddr + 1546 ccb->ccb_cmdid * sizeof(struct twe_cmd); 1547 twe_outl(sc, TWE_REG_CMD_QUEUE, (u_int32_t)pa); 1548 rv = 0; 1549 } else 1550 rv = EBUSY; 1551 1552 return (rv); 1553 } 1554 1555 1556 /* 1557 * Accept an open operation on the control device. 1558 */ 1559 int 1560 tweopen(dev_t dev, int flag, int mode, struct proc *p) 1561 { 1562 struct twe_softc *twe; 1563 1564 if ((twe = device_lookup(&twe_cd, minor(dev))) == NULL) 1565 return (ENXIO); 1566 if ((twe->sc_flags & TWEF_OPEN) != 0) 1567 return (EBUSY); 1568 1569 twe->sc_flags |= TWEF_OPEN; 1570 return (0); 1571 } 1572 1573 /* 1574 * Accept the last close on the control device. 1575 */ 1576 int 1577 tweclose(dev_t dev, int flag, int mode, struct proc *p) 1578 { 1579 struct twe_softc *twe; 1580 1581 twe = device_lookup(&twe_cd, minor(dev)); 1582 twe->sc_flags &= ~TWEF_OPEN; 1583 return (0); 1584 } 1585 1586 /* 1587 * Handle control operations. 1588 */ 1589 int 1590 tweioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1591 { 1592 struct twe_softc *twe; 1593 #if 0 1594 struct twe_ccb *ccb; 1595 #endif 1596 struct twe_param *param; 1597 struct twe_usercommand *tu; 1598 struct twe_paramcommand *tp; 1599 union twe_statrequest *ts; 1600 void *pdata = NULL; 1601 int rv, s, error = 0; 1602 #if 0 1603 u_int8_t cmdid; 1604 #endif 1605 1606 if (securelevel >= 2) 1607 return (EPERM); 1608 1609 twe = device_lookup(&twe_cd, minor(dev)); 1610 tu = (struct twe_usercommand *)data; 1611 tp = (struct twe_paramcommand *)data; 1612 ts = (union twe_statrequest *)data; 1613 1614 /* Hmm, compatible with FreeBSD */ 1615 switch (cmd) { 1616 case TWEIO_COMMAND: 1617 #if 0 1618 /* XXXJRT This whole path needs to be cleaned up. */ 1619 if (tu->tu_size > 0) { 1620 if (tu->tu_size > TWE_SECTOR_SIZE) 1621 return EINVAL; 1622 pdata = malloc(tu->tu_size, M_DEVBUF, M_WAITOK); 1623 error = copyin(tu->tu_data, pdata, tu->tu_size); 1624 if (error != 0) 1625 goto done; 1626 error = twe_ccb_alloc(twe, &ccb, TWE_CCB_PARAM | 1627 TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1628 } else { 1629 error = twe_ccb_alloc(twe, &ccb, 0); 1630 } 1631 if (rv != 0) 1632 goto done; 1633 cmdid = ccb->ccb_cmdid; 1634 memcpy(ccb->ccb_cmd, &tu->tu_cmd, sizeof(struct twe_cmd)); 1635 ccb->ccb_cmdid = cmdid; 1636 if (ccb->ccb_flags & TWE_CCB_PARAM) { 1637 ccb->ccb_data = pdata; 1638 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1639 ccb->ccb_tx.tx_handler = 0; 1640 ccb->ccb_tx.tx_context = pdata; 1641 ccb->ccb_tx.tx_dv = &twe->sc_dv; 1642 } 1643 /* Map the transfer. */ 1644 if ((error = twe_ccb_map(twe, ccb)) != 0) { 1645 twe_ccb_free(twe, ccb); 1646 goto done; 1647 } 1648 1649 /* Submit the command and wait. */ 1650 s = splbio(); 1651 rv = twe_ccb_poll(twe, ccb, 5); 1652 twe_ccb_unmap(twe, ccb); 1653 twe_ccb_free(twe, ccb); 1654 splx(s); 1655 1656 if (tu->tu_size > 0) 1657 error = copyout(pdata, tu->tu_data, tu->tu_size); 1658 #else 1659 rv = EOPNOTSUPP; 1660 #endif 1661 goto done; 1662 1663 case TWEIO_STATS: 1664 return (ENOENT); 1665 1666 case TWEIO_AEN_POLL: 1667 s = splbio(); 1668 *(u_int *)data = twe_aen_dequeue(twe); 1669 splx(s); 1670 return (0); 1671 1672 case TWEIO_AEN_WAIT: 1673 s = splbio(); 1674 while ((*(u_int *)data = 1675 twe_aen_dequeue(twe)) == TWE_AEN_QUEUE_EMPTY) { 1676 twe->sc_flags |= TWEF_AENQ_WAIT; 1677 error = tsleep(&twe->sc_aen_queue, PRIBIO | PCATCH, 1678 "tweaen", 0); 1679 if (error == EINTR) { 1680 splx(s); 1681 return (error); 1682 } 1683 } 1684 splx(s); 1685 return (0); 1686 1687 case TWEIO_GET_PARAM: 1688 error = twe_param_get(twe, tp->tp_table_id, tp->tp_param_id, 1689 tp->tp_size, 0, ¶m); 1690 if (error != 0) 1691 return (error); 1692 if (param->tp_param_size > tp->tp_size) { 1693 error = EFAULT; 1694 goto done; 1695 } 1696 error = copyout(param->tp_data, tp->tp_data, 1697 param->tp_param_size); 1698 goto done; 1699 1700 case TWEIO_SET_PARAM: 1701 pdata = malloc(tp->tp_size, M_DEVBUF, M_WAITOK); 1702 if ((error = copyin(tp->tp_data, pdata, tp->tp_size)) != 0) 1703 goto done; 1704 error = twe_param_set(twe, tp->tp_table_id, tp->tp_param_id, 1705 tp->tp_size, pdata); 1706 goto done; 1707 1708 case TWEIO_RESET: 1709 s = splbio(); 1710 twe_reset(twe); 1711 splx(s); 1712 return (0); 1713 1714 case TWEIO_ADD_UNIT: 1715 /* XXX mutex */ 1716 return (twe_add_unit(twe, *(int *)data)); 1717 1718 case TWEIO_DEL_UNIT: 1719 /* XXX mutex */ 1720 return (twe_del_unit(twe, *(int *)data)); 1721 1722 default: 1723 return EINVAL; 1724 } 1725 done: 1726 if (pdata) 1727 free(pdata, M_DEVBUF); 1728 return error; 1729 } 1730 1731 /* 1732 * Print some information about the controller 1733 */ 1734 static void 1735 twe_describe_controller(struct twe_softc *sc) 1736 { 1737 struct twe_param *p[6]; 1738 int i, rv = 0; 1739 uint32_t dsize; 1740 uint8_t ports; 1741 1742 /* get the port count */ 1743 rv |= twe_param_get_1(sc, TWE_PARAM_CONTROLLER, 1744 TWE_PARAM_CONTROLLER_PortCount, &ports); 1745 1746 /* get version strings */ 1747 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_Mon, 1748 16, NULL, &p[0]); 1749 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_FW, 1750 16, NULL, &p[1]); 1751 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_BIOS, 1752 16, NULL, &p[2]); 1753 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_PCB, 1754 8, NULL, &p[3]); 1755 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_ATA, 1756 8, NULL, &p[4]); 1757 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_PCI, 1758 8, NULL, &p[5]); 1759 1760 if (rv) { 1761 /* some error occurred */ 1762 aprint_error("%s: failed to fetch version information\n", 1763 sc->sc_dv.dv_xname); 1764 return; 1765 } 1766 1767 aprint_normal("%s: %d ports, Firmware %.16s, BIOS %.16s\n", 1768 sc->sc_dv.dv_xname, ports, 1769 p[1]->tp_data, p[2]->tp_data); 1770 1771 aprint_verbose("%s: Monitor %.16s, PCB %.8s, Achip %.8s, Pchip %.8s\n", 1772 sc->sc_dv.dv_xname, 1773 p[0]->tp_data, p[3]->tp_data, 1774 p[4]->tp_data, p[5]->tp_data); 1775 1776 free(p[0], M_DEVBUF); 1777 free(p[1], M_DEVBUF); 1778 free(p[2], M_DEVBUF); 1779 free(p[3], M_DEVBUF); 1780 free(p[4], M_DEVBUF); 1781 free(p[5], M_DEVBUF); 1782 1783 rv = twe_param_get(sc, TWE_PARAM_DRIVESUMMARY, 1784 TWE_PARAM_DRIVESUMMARY_Status, 16, NULL, &p[0]); 1785 if (rv) { 1786 aprint_error("%s: failed to get drive status summary\n", 1787 sc->sc_dv.dv_xname); 1788 return; 1789 } 1790 for (i = 0; i < ports; i++) { 1791 if (p[0]->tp_data[i] != TWE_PARAM_DRIVESTATUS_Present) 1792 continue; 1793 rv = twe_param_get_4(sc, TWE_PARAM_DRIVEINFO + i, 1794 TWE_PARAM_DRIVEINFO_Size, &dsize); 1795 if (rv) { 1796 aprint_error( 1797 "%s: unable to get drive size for port %d\n", 1798 sc->sc_dv.dv_xname, i); 1799 continue; 1800 } 1801 rv = twe_param_get(sc, TWE_PARAM_DRIVEINFO + i, 1802 TWE_PARAM_DRIVEINFO_Model, 40, NULL, &p[1]); 1803 if (rv) { 1804 aprint_error( 1805 "%s: unable to get drive model for port %d\n", 1806 sc->sc_dv.dv_xname, i); 1807 continue; 1808 } 1809 aprint_verbose("%s: port %d: %.40s %d MB\n", sc->sc_dv.dv_xname, 1810 i, p[1]->tp_data, dsize / 2048); 1811 free(p[1], M_DEVBUF); 1812 } 1813 free(p[0], M_DEVBUF); 1814 } 1815
Indexes created Mon Sep 22 05:09:51 GMT 2025