twe.c revision 1.48
1 /* $NetBSD: twe.c,v 1.48 2003/09/23 23:10:53 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran; and by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twe.c,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 /* 69 * Driver for the 3ware Escalade family of RAID controllers. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: twe.c,v 1.48 2003/09/23 23:10:53 thorpej Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/device.h> 79 #include <sys/queue.h> 80 #include <sys/proc.h> 81 #include <sys/buf.h> 82 #include <sys/endian.h> 83 #include <sys/malloc.h> 84 #include <sys/conf.h> 85 #include <sys/disk.h> 86 87 #include <uvm/uvm_extern.h> 88 89 #include <machine/bswap.h> 90 #include <machine/bus.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/twereg.h> 96 #include <dev/pci/twevar.h> 97 #include <dev/pci/tweio.h> 98 99 #define PCI_CBIO 0x10 100 101 static int twe_aen_get(struct twe_softc *, uint16_t *); 102 static void twe_aen_handler(struct twe_ccb *, int); 103 static void twe_aen_enqueue(struct twe_softc *sc, uint16_t, int); 104 static uint16_t twe_aen_dequeue(struct twe_softc *); 105 106 static void twe_attach(struct device *, struct device *, void *); 107 static int twe_init_connection(struct twe_softc *); 108 static int twe_intr(void *); 109 static int twe_match(struct device *, struct cfdata *, void *); 110 static int twe_param_set(struct twe_softc *, int, int, size_t, void *); 111 static void twe_poll(struct twe_softc *); 112 static int twe_print(void *, const char *); 113 static int twe_reset(struct twe_softc *); 114 static int twe_submatch(struct device *, struct cfdata *, void *); 115 static int twe_status_check(struct twe_softc *, u_int); 116 static int twe_status_wait(struct twe_softc *, u_int, int); 117 static void twe_describe_controller(struct twe_softc *); 118 119 static int twe_add_unit(struct twe_softc *, int); 120 static int twe_del_unit(struct twe_softc *, int); 121 122 static inline u_int32_t twe_inl(struct twe_softc *, int); 123 static inline void twe_outl(struct twe_softc *, int, u_int32_t); 124 125 dev_type_open(tweopen); 126 dev_type_close(tweclose); 127 dev_type_ioctl(tweioctl); 128 129 const struct cdevsw twe_cdevsw = { 130 tweopen, tweclose, noread, nowrite, tweioctl, 131 nostop, notty, nopoll, nommap, 132 }; 133 134 extern struct cfdriver twe_cd; 135 136 CFATTACH_DECL(twe, sizeof(struct twe_softc), 137 twe_match, twe_attach, NULL, NULL); 138 139 /* 140 * Tables to convert numeric codes to strings. 141 */ 142 const struct twe_code_table twe_table_status[] = { 143 { 0x00, "successful completion" }, 144 145 /* info */ 146 { 0x42, "command in progress" }, 147 { 0x6c, "retrying interface CRC error from UDMA command" }, 148 149 /* warning */ 150 { 0x81, "redundant/inconsequential request ignored" }, 151 { 0x8e, "failed to write zeroes to LBA 0" }, 152 { 0x8f, "failed to profile TwinStor zones" }, 153 154 /* fatal */ 155 { 0xc1, "aborted due to system command or reconfiguration" }, 156 { 0xc4, "aborted" }, 157 { 0xc5, "access error" }, 158 { 0xc6, "access violation" }, 159 { 0xc7, "device failure" }, /* high byte may be port # */ 160 { 0xc8, "controller error" }, 161 { 0xc9, "timed out" }, 162 { 0xcb, "invalid unit number" }, 163 { 0xcf, "unit not available" }, 164 { 0xd2, "undefined opcode" }, 165 { 0xdb, "request incompatible with unit" }, 166 { 0xdc, "invalid request" }, 167 { 0xff, "firmware error, reset requested" }, 168 169 { 0, NULL } 170 }; 171 172 const struct twe_code_table twe_table_unitstate[] = { 173 { TWE_PARAM_UNITSTATUS_Normal, "Normal" }, 174 { TWE_PARAM_UNITSTATUS_Initialising, "Initializing" }, 175 { TWE_PARAM_UNITSTATUS_Degraded, "Degraded" }, 176 { TWE_PARAM_UNITSTATUS_Rebuilding, "Rebuilding" }, 177 { TWE_PARAM_UNITSTATUS_Verifying, "Verifying" }, 178 { TWE_PARAM_UNITSTATUS_Corrupt, "Corrupt" }, 179 { TWE_PARAM_UNITSTATUS_Missing, "Missing" }, 180 181 { 0, NULL } 182 }; 183 184 const struct twe_code_table twe_table_unittype[] = { 185 /* array descriptor configuration */ 186 { TWE_AD_CONFIG_RAID0, "RAID0" }, 187 { TWE_AD_CONFIG_RAID1, "RAID1" }, 188 { TWE_AD_CONFIG_TwinStor, "TwinStor" }, 189 { TWE_AD_CONFIG_RAID5, "RAID5" }, 190 { TWE_AD_CONFIG_RAID10, "RAID10" }, 191 192 { 0, NULL } 193 }; 194 195 const struct twe_code_table twe_table_stripedepth[] = { 196 { TWE_AD_STRIPE_4k, "4K" }, 197 { TWE_AD_STRIPE_8k, "8K" }, 198 { TWE_AD_STRIPE_16k, "16K" }, 199 { TWE_AD_STRIPE_32k, "32K" }, 200 { TWE_AD_STRIPE_64k, "64K" }, 201 202 { 0, NULL } 203 }; 204 205 /* 206 * Asynchronous event notification messages are qualified: 207 * a - not unit/port specific 208 * u - unit specific 209 * p - port specific 210 */ 211 const struct twe_code_table twe_table_aen[] = { 212 { 0x00, "a queue empty" }, 213 { 0x01, "a soft reset" }, 214 { 0x02, "u degraded mode" }, 215 { 0x03, "a controller error" }, 216 { 0x04, "u rebuild fail" }, 217 { 0x05, "u rebuild done" }, 218 { 0x06, "u incomplete unit" }, 219 { 0x07, "u initialization done" }, 220 { 0x08, "u unclean shutdown detected" }, 221 { 0x09, "p drive timeout" }, 222 { 0x0a, "p drive error" }, 223 { 0x0b, "u rebuild started" }, 224 { 0x0c, "u initialization started" }, 225 { 0x0d, "u logical unit deleted" }, 226 { 0x0f, "p SMART threshold exceeded" }, 227 { 0x15, "a table undefined" }, /* XXX: Not in FreeBSD's table */ 228 { 0x21, "p ATA UDMA downgrade" }, 229 { 0x22, "p ATA UDMA upgrade" }, 230 { 0x23, "p sector repair occurred" }, 231 { 0x24, "a SBUF integrity check failure" }, 232 { 0x25, "p lost cached write" }, 233 { 0x26, "p drive ECC error detected" }, 234 { 0x27, "p DCB checksum error" }, 235 { 0x28, "p DCB unsupported version" }, 236 { 0x29, "u verify started" }, 237 { 0x2a, "u verify failed" }, 238 { 0x2b, "u verify complete" }, 239 { 0x2c, "p overwrote bad sector during rebuild" }, 240 { 0x2d, "p encountered bad sector during rebuild" }, 241 { 0x2e, "p replacement drive too small" }, 242 { 0x2f, "u array not previously initialized" }, 243 { 0x30, "p drive not supported" }, 244 { 0xff, "a aen queue full" }, 245 246 { 0, NULL }, 247 }; 248 249 const char * 250 twe_describe_code(const struct twe_code_table *table, uint32_t code) 251 { 252 253 for (; table->string != NULL; table++) { 254 if (table->code == code) 255 return (table->string); 256 } 257 return (NULL); 258 } 259 260 static inline u_int32_t 261 twe_inl(struct twe_softc *sc, int off) 262 { 263 264 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 265 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 266 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, off)); 267 } 268 269 static inline void 270 twe_outl(struct twe_softc *sc, int off, u_int32_t val) 271 { 272 273 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 274 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 275 BUS_SPACE_BARRIER_WRITE); 276 } 277 278 /* 279 * Match a supported board. 280 */ 281 static int 282 twe_match(struct device *parent, struct cfdata *cfdata, void *aux) 283 { 284 struct pci_attach_args *pa; 285 286 pa = aux; 287 288 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3WARE && 289 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE || 290 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE_ASIC)); 291 } 292 293 /* 294 * Attach a supported board. 295 * 296 * XXX This doesn't fail gracefully. 297 */ 298 static void 299 twe_attach(struct device *parent, struct device *self, void *aux) 300 { 301 struct pci_attach_args *pa; 302 struct twe_softc *sc; 303 pci_chipset_tag_t pc; 304 pci_intr_handle_t ih; 305 pcireg_t csr; 306 const char *intrstr; 307 int s, size, i, rv, rseg; 308 size_t max_segs, max_xfer; 309 bus_dma_segment_t seg; 310 struct twe_cmd *tc; 311 struct twe_ccb *ccb; 312 313 sc = (struct twe_softc *)self; 314 pa = aux; 315 pc = pa->pa_pc; 316 sc->sc_dmat = pa->pa_dmat; 317 SIMPLEQ_INIT(&sc->sc_ccb_queue); 318 SLIST_INIT(&sc->sc_ccb_freelist); 319 320 aprint_naive(": RAID controller\n"); 321 aprint_normal(": 3ware Escalade\n"); 322 323 ccb = malloc(sizeof(*ccb) * TWE_MAX_QUEUECNT, M_DEVBUF, M_NOWAIT); 324 if (ccb == NULL) { 325 aprint_error("%s: unable to allocate memory for ccbs\n", 326 sc->sc_dv.dv_xname); 327 return; 328 } 329 330 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 331 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 332 aprint_error("%s: can't map i/o space\n", sc->sc_dv.dv_xname); 333 return; 334 } 335 336 /* Enable the device. */ 337 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 338 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 339 csr | PCI_COMMAND_MASTER_ENABLE); 340 341 /* Map and establish the interrupt. */ 342 if (pci_intr_map(pa, &ih)) { 343 aprint_error("%s: can't map interrupt\n", sc->sc_dv.dv_xname); 344 return; 345 } 346 347 intrstr = pci_intr_string(pc, ih); 348 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, twe_intr, sc); 349 if (sc->sc_ih == NULL) { 350 aprint_error("%s: can't establish interrupt%s%s\n", 351 sc->sc_dv.dv_xname, 352 (intrstr) ? " at " : "", 353 (intrstr) ? intrstr : ""); 354 return; 355 } 356 357 if (intrstr != NULL) 358 aprint_normal("%s: interrupting at %s\n", 359 sc->sc_dv.dv_xname, intrstr); 360 361 /* 362 * Allocate and initialise the command blocks and CCBs. 363 */ 364 size = sizeof(struct twe_cmd) * TWE_MAX_QUEUECNT; 365 366 if ((rv = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 1, 367 &rseg, BUS_DMA_NOWAIT)) != 0) { 368 aprint_error("%s: unable to allocate commands, rv = %d\n", 369 sc->sc_dv.dv_xname, rv); 370 return; 371 } 372 373 if ((rv = bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 374 (caddr_t *)&sc->sc_cmds, 375 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 376 aprint_error("%s: unable to map commands, rv = %d\n", 377 sc->sc_dv.dv_xname, rv); 378 return; 379 } 380 381 if ((rv = bus_dmamap_create(sc->sc_dmat, size, size, 1, 0, 382 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 383 aprint_error("%s: unable to create command DMA map, rv = %d\n", 384 sc->sc_dv.dv_xname, rv); 385 return; 386 } 387 388 if ((rv = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cmds, 389 size, NULL, BUS_DMA_NOWAIT)) != 0) { 390 aprint_error("%s: unable to load command DMA map, rv = %d\n", 391 sc->sc_dv.dv_xname, rv); 392 return; 393 } 394 395 sc->sc_cmds_paddr = sc->sc_dmamap->dm_segs[0].ds_addr; 396 memset(sc->sc_cmds, 0, size); 397 398 sc->sc_ccbs = ccb; 399 tc = (struct twe_cmd *)sc->sc_cmds; 400 max_segs = twe_get_maxsegs(); 401 max_xfer = twe_get_maxxfer(max_segs); 402 403 for (i = 0; i < TWE_MAX_QUEUECNT; i++, tc++, ccb++) { 404 ccb->ccb_cmd = tc; 405 ccb->ccb_cmdid = i; 406 ccb->ccb_flags = 0; 407 rv = bus_dmamap_create(sc->sc_dmat, max_xfer, 408 max_segs, PAGE_SIZE, 0, 409 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 410 &ccb->ccb_dmamap_xfer); 411 if (rv != 0) { 412 aprint_error("%s: can't create dmamap, rv = %d\n", 413 sc->sc_dv.dv_xname, rv); 414 return; 415 } 416 417 /* Save the first CCB for AEN retrieval. */ 418 if (i != 0) 419 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, 420 ccb_chain.slist); 421 } 422 423 /* Wait for the controller to become ready. */ 424 if (twe_status_wait(sc, TWE_STS_MICROCONTROLLER_READY, 6)) { 425 aprint_error("%s: microcontroller not ready\n", 426 sc->sc_dv.dv_xname); 427 return; 428 } 429 430 twe_outl(sc, TWE_REG_CTL, TWE_CTL_DISABLE_INTRS); 431 432 /* Reset the controller. */ 433 s = splbio(); 434 rv = twe_reset(sc); 435 splx(s); 436 if (rv) { 437 aprint_error("%s: reset failed\n", sc->sc_dv.dv_xname); 438 return; 439 } 440 441 /* Initialise connection with controller. */ 442 twe_init_connection(sc); 443 444 twe_describe_controller(sc); 445 446 /* Find and attach RAID array units. */ 447 sc->sc_nunits = 0; 448 for (i = 0; i < TWE_MAX_UNITS; i++) 449 (void) twe_add_unit(sc, i); 450 451 /* ...and finally, enable interrupts. */ 452 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR | 453 TWE_CTL_UNMASK_RESP_INTR | 454 TWE_CTL_ENABLE_INTRS); 455 } 456 457 void 458 twe_register_callbacks(struct twe_softc *sc, int unit, 459 const struct twe_callbacks *tcb) 460 { 461 462 sc->sc_units[unit].td_callbacks = tcb; 463 } 464 465 static void 466 twe_recompute_openings(struct twe_softc *sc) 467 { 468 struct twe_drive *td; 469 int unit, openings; 470 471 if (sc->sc_nunits != 0) 472 openings = (TWE_MAX_QUEUECNT - 1) / sc->sc_nunits; 473 else 474 openings = 0; 475 if (openings == sc->sc_openings) 476 return; 477 sc->sc_openings = openings; 478 479 #ifdef TWE_DEBUG 480 printf("%s: %d array%s, %d openings per array\n", 481 sc->sc_dv.dv_xname, sc->sc_nunits, 482 sc->sc_nunits == 1 ? "" : "s", sc->sc_openings); 483 #endif 484 485 for (unit = 0; unit < TWE_MAX_UNITS; unit++) { 486 td = &sc->sc_units[unit]; 487 if (td->td_dev != NULL) 488 (*td->td_callbacks->tcb_openings)(td->td_dev, 489 sc->sc_openings); 490 } 491 } 492 493 static int 494 twe_add_unit(struct twe_softc *sc, int unit) 495 { 496 struct twe_param *dtp, *atp; 497 struct twe_array_descriptor *ad; 498 struct twe_drive *td; 499 struct twe_attach_args twea; 500 uint32_t newsize; 501 int rv; 502 uint16_t dsize; 503 uint8_t newtype, newstripe; 504 505 if (unit < 0 || unit >= TWE_MAX_UNITS) 506 return (EINVAL); 507 508 /* Find attached units. */ 509 rv = twe_param_get(sc, TWE_PARAM_UNITSUMMARY, 510 TWE_PARAM_UNITSUMMARY_Status, TWE_MAX_UNITS, NULL, &dtp); 511 if (rv != 0) { 512 aprint_error("%s: error %d fetching unit summary\n", 513 sc->sc_dv.dv_xname, rv); 514 return (rv); 515 } 516 517 /* For each detected unit, collect size and store in an array. */ 518 td = &sc->sc_units[unit]; 519 520 /* Unit present? */ 521 if ((dtp->tp_data[unit] & TWE_PARAM_UNITSTATUS_Online) == 0) { 522 /* 523 * XXX Should we check to see if a device has been 524 * XXX attached at this index and detach it if it 525 * XXX has? ("rescan" semantics) 526 */ 527 rv = 0; 528 goto out; 529 } 530 531 rv = twe_param_get_2(sc, TWE_PARAM_UNITINFO + unit, 532 TWE_PARAM_UNITINFO_DescriptorSize, &dsize); 533 if (rv != 0) { 534 aprint_error("%s: error %d fetching descriptor size " 535 "for unit %d\n", sc->sc_dv.dv_xname, rv, unit); 536 goto out; 537 } 538 539 rv = twe_param_get(sc, TWE_PARAM_UNITINFO + unit, 540 TWE_PARAM_UNITINFO_Descriptor, dsize - 3, NULL, &atp); 541 if (rv != 0) { 542 aprint_error("%s: error %d fetching array descriptor " 543 "for unit %d\n", sc->sc_dv.dv_xname, rv, unit); 544 goto out; 545 } 546 547 ad = (struct twe_array_descriptor *)atp->tp_data; 548 newtype = ad->configuration; 549 newstripe = ad->stripe_size; 550 free(atp, M_DEVBUF); 551 552 rv = twe_param_get_4(sc, TWE_PARAM_UNITINFO + unit, 553 TWE_PARAM_UNITINFO_Capacity, &newsize); 554 if (rv != 0) { 555 aprint_error( 556 "%s: error %d fetching capacity for unit %d\n", 557 sc->sc_dv.dv_xname, rv, unit); 558 goto out; 559 } 560 561 /* 562 * Have a device, so we need to attach it. If there is currently 563 * something sitting at the slot, and the parameters are different, 564 * then we detach the old device before attaching the new one. 565 */ 566 if (td->td_dev != NULL && 567 td->td_size == newsize && 568 td->td_type == newtype && 569 td->td_stripe == newstripe) { 570 /* Same as the old device; just keep using it. */ 571 rv = 0; 572 goto out; 573 } else if (td->td_dev != NULL) { 574 /* Detach the old device first. */ 575 (void) config_detach(td->td_dev, DETACH_FORCE); 576 td->td_dev = NULL; 577 } else if (td->td_size == 0) 578 sc->sc_nunits++; 579 580 /* 581 * Committed to the new array unit; assign its parameters and 582 * recompute the number of available command openings. 583 */ 584 td->td_size = newsize; 585 td->td_type = newtype; 586 td->td_stripe = newstripe; 587 twe_recompute_openings(sc); 588 589 twea.twea_unit = unit; 590 td->td_dev = config_found_sm(&sc->sc_dv, &twea, twe_print, 591 twe_submatch); 592 593 rv = 0; 594 out: 595 free(dtp, M_DEVBUF); 596 return (rv); 597 } 598 599 static int 600 twe_del_unit(struct twe_softc *sc, int unit) 601 { 602 struct twe_drive *td; 603 604 if (unit < 0 || unit >= TWE_MAX_UNITS) 605 return (EINVAL); 606 607 td = &sc->sc_units[unit]; 608 if (td->td_size != 0) 609 sc->sc_nunits--; 610 td->td_size = 0; 611 td->td_type = 0; 612 td->td_stripe = 0; 613 if (td->td_dev != NULL) { 614 (void) config_detach(td->td_dev, DETACH_FORCE); 615 td->td_dev = NULL; 616 } 617 twe_recompute_openings(sc); 618 return (0); 619 } 620 621 /* 622 * Reset the controller. 623 * MUST BE CALLED AT splbio()! 624 */ 625 static int 626 twe_reset(struct twe_softc *sc) 627 { 628 uint16_t aen; 629 u_int status; 630 volatile u_int32_t junk; 631 int got, rv; 632 633 /* Issue a soft reset. */ 634 twe_outl(sc, TWE_REG_CTL, TWE_CTL_ISSUE_SOFT_RESET | 635 TWE_CTL_CLEAR_HOST_INTR | 636 TWE_CTL_CLEAR_ATTN_INTR | 637 TWE_CTL_MASK_CMD_INTR | 638 TWE_CTL_MASK_RESP_INTR | 639 TWE_CTL_CLEAR_ERROR_STS | 640 TWE_CTL_DISABLE_INTRS); 641 642 /* Wait for attention... */ 643 if (twe_status_wait(sc, TWE_STS_ATTN_INTR, 15)) { 644 printf("%s: no attention interrupt\n", 645 sc->sc_dv.dv_xname); 646 return (-1); 647 } 648 649 /* ...and ACK it. */ 650 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 651 652 /* 653 * Pull AENs out of the controller; look for a soft reset AEN. 654 * Open code this, since we want to detect reset even if the 655 * queue for management tools is full. 656 * 657 * Note that since: 658 * - interrupts are blocked 659 * - we have reset the controller 660 * - acknowledged the pending ATTENTION 661 * that there is no way a pending asynchronous AEN fetch would 662 * finish, so clear the flag. 663 */ 664 sc->sc_flags &= ~TWEF_AEN; 665 for (got = 0;;) { 666 rv = twe_aen_get(sc, &aen); 667 if (rv != 0) 668 printf("%s: error %d while draining event queue\n", 669 sc->sc_dv.dv_xname, rv); 670 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) 671 break; 672 if (TWE_AEN_CODE(aen) == TWE_AEN_SOFT_RESET) 673 got = 1; 674 twe_aen_enqueue(sc, aen, 1); 675 } 676 677 if (!got) { 678 printf("%s: reset not reported\n", sc->sc_dv.dv_xname); 679 return (-1); 680 } 681 682 /* Check controller status. */ 683 status = twe_inl(sc, TWE_REG_STS); 684 if (twe_status_check(sc, status)) { 685 printf("%s: controller errors detected\n", 686 sc->sc_dv.dv_xname); 687 return (-1); 688 } 689 690 /* Drain the response queue. */ 691 for (;;) { 692 status = twe_inl(sc, TWE_REG_STS); 693 if (twe_status_check(sc, status) != 0) { 694 printf("%s: can't drain response queue\n", 695 sc->sc_dv.dv_xname); 696 return (-1); 697 } 698 if ((status & TWE_STS_RESP_QUEUE_EMPTY) != 0) 699 break; 700 junk = twe_inl(sc, TWE_REG_RESP_QUEUE); 701 } 702 703 return (0); 704 } 705 706 /* 707 * Print autoconfiguration message for a sub-device. 708 */ 709 static int 710 twe_print(void *aux, const char *pnp) 711 { 712 struct twe_attach_args *twea; 713 714 twea = aux; 715 716 if (pnp != NULL) 717 aprint_normal("block device at %s", pnp); 718 aprint_normal(" unit %d", twea->twea_unit); 719 return (UNCONF); 720 } 721 722 /* 723 * Match a sub-device. 724 */ 725 static int 726 twe_submatch(struct device *parent, struct cfdata *cf, void *aux) 727 { 728 struct twe_attach_args *twea; 729 730 twea = aux; 731 732 if (cf->tweacf_unit != TWECF_UNIT_DEFAULT && 733 cf->tweacf_unit != twea->twea_unit) 734 return (0); 735 736 return (config_match(parent, cf, aux)); 737 } 738 739 /* 740 * Interrupt service routine. 741 */ 742 static int 743 twe_intr(void *arg) 744 { 745 struct twe_softc *sc; 746 u_int status; 747 int caught, rv; 748 749 sc = arg; 750 caught = 0; 751 status = twe_inl(sc, TWE_REG_STS); 752 twe_status_check(sc, status); 753 754 /* Host interrupts - purpose unknown. */ 755 if ((status & TWE_STS_HOST_INTR) != 0) { 756 #ifdef DEBUG 757 printf("%s: host interrupt\n", sc->sc_dv.dv_xname); 758 #endif 759 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_HOST_INTR); 760 caught = 1; 761 } 762 763 /* 764 * Attention interrupts, signalled when a controller or child device 765 * state change has occurred. 766 */ 767 if ((status & TWE_STS_ATTN_INTR) != 0) { 768 rv = twe_aen_get(sc, NULL); 769 if (rv != 0) 770 printf("%s: unable to retrieve AEN (%d)\n", 771 sc->sc_dv.dv_xname, rv); 772 else 773 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 774 caught = 1; 775 } 776 777 /* 778 * Command interrupts, signalled when the controller can accept more 779 * commands. We don't use this; instead, we try to submit commands 780 * when we receive them, and when other commands have completed. 781 * Mask it so we don't get another one. 782 */ 783 if ((status & TWE_STS_CMD_INTR) != 0) { 784 #ifdef DEBUG 785 printf("%s: command interrupt\n", sc->sc_dv.dv_xname); 786 #endif 787 twe_outl(sc, TWE_REG_CTL, TWE_CTL_MASK_CMD_INTR); 788 caught = 1; 789 } 790 791 if ((status & TWE_STS_RESP_INTR) != 0) { 792 twe_poll(sc); 793 caught = 1; 794 } 795 796 return (caught); 797 } 798 799 /* 800 * Fetch an AEN. Even though this is really like parameter 801 * retrieval, we handle this specially, because we issue this 802 * AEN retrieval command from interrupt context, and thus 803 * reserve a CCB for it to avoid resource shortage. 804 * 805 * XXX There are still potential resource shortages we could 806 * XXX encounter. Consider pre-allocating all AEN-related 807 * XXX resources. 808 * 809 * MUST BE CALLED AT splbio()! 810 */ 811 static int 812 twe_aen_get(struct twe_softc *sc, uint16_t *aenp) 813 { 814 struct twe_ccb *ccb; 815 struct twe_cmd *tc; 816 struct twe_param *tp; 817 int rv; 818 819 /* 820 * If we're already retrieving an AEN, just wait; another 821 * retrieval will be chained after the current one completes. 822 */ 823 if (sc->sc_flags & TWEF_AEN) { 824 /* 825 * It is a fatal software programming error to attempt 826 * to fetch an AEN synchronously when an AEN fetch is 827 * already pending. 828 */ 829 KASSERT(aenp == NULL); 830 return (0); 831 } 832 833 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 834 if (tp == NULL) 835 return (ENOMEM); 836 837 rv = twe_ccb_alloc(sc, &ccb, 838 TWE_CCB_AEN | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 839 if (rv != 0) 840 goto done; 841 842 ccb->ccb_data = tp; 843 ccb->ccb_datasize = TWE_SECTOR_SIZE; 844 ccb->ccb_tx.tx_handler = (aenp == NULL) ? twe_aen_handler : NULL; 845 ccb->ccb_tx.tx_context = tp; 846 ccb->ccb_tx.tx_dv = &sc->sc_dv; 847 848 tc = ccb->ccb_cmd; 849 tc->tc_size = 2; 850 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 851 tc->tc_unit = 0; 852 tc->tc_count = htole16(1); 853 854 /* Fill in the outbound parameter data. */ 855 tp->tp_table_id = htole16(TWE_PARAM_AEN); 856 tp->tp_param_id = TWE_PARAM_AEN_UnitCode; 857 tp->tp_param_size = 2; 858 859 /* Map the transfer. */ 860 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 861 twe_ccb_free(sc, ccb); 862 goto done; 863 } 864 865 /* Enqueue the command and wait. */ 866 if (aenp != NULL) { 867 rv = twe_ccb_poll(sc, ccb, 5); 868 twe_ccb_unmap(sc, ccb); 869 twe_ccb_free(sc, ccb); 870 if (rv == 0) 871 *aenp = le16toh(*(uint16_t *)tp->tp_data); 872 free(tp, M_DEVBUF); 873 } else { 874 sc->sc_flags |= TWEF_AEN; 875 twe_ccb_enqueue(sc, ccb); 876 rv = 0; 877 } 878 879 done: 880 return (rv); 881 } 882 883 /* 884 * Handle an AEN returned by the controller. 885 * MUST BE CALLED AT splbio()! 886 */ 887 static void 888 twe_aen_handler(struct twe_ccb *ccb, int error) 889 { 890 struct twe_softc *sc; 891 struct twe_param *tp; 892 uint16_t aen; 893 int rv; 894 895 sc = (struct twe_softc *)ccb->ccb_tx.tx_dv; 896 tp = ccb->ccb_tx.tx_context; 897 twe_ccb_unmap(sc, ccb); 898 899 sc->sc_flags &= ~TWEF_AEN; 900 901 if (error) { 902 printf("%s: error retrieving AEN\n", sc->sc_dv.dv_xname); 903 aen = TWE_AEN_QUEUE_EMPTY; 904 } else 905 aen = le16toh(*(u_int16_t *)tp->tp_data); 906 free(tp, M_DEVBUF); 907 twe_ccb_free(sc, ccb); 908 909 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) { 910 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 911 return; 912 } 913 914 twe_aen_enqueue(sc, aen, 0); 915 916 /* 917 * Chain another retrieval in case interrupts have been 918 * coalesced. 919 */ 920 rv = twe_aen_get(sc, NULL); 921 if (rv != 0) 922 printf("%s: unable to retrieve AEN (%d)\n", 923 sc->sc_dv.dv_xname, rv); 924 } 925 926 static void 927 twe_aen_enqueue(struct twe_softc *sc, uint16_t aen, int quiet) 928 { 929 const char *str, *msg; 930 int s, next, nextnext; 931 932 /* 933 * First report the AEN on the console. Maybe. 934 */ 935 if (! quiet) { 936 str = twe_describe_code(twe_table_aen, TWE_AEN_CODE(aen)); 937 if (str == NULL) { 938 printf("%s: unknown AEN 0x%04x\n", 939 sc->sc_dv.dv_xname, aen); 940 } else { 941 msg = str + 2; 942 switch (*str) { 943 case 'u': 944 printf("%s: unit %d: %s\n", 945 sc->sc_dv.dv_xname, TWE_AEN_UNIT(aen), msg); 946 break; 947 948 case 'p': 949 printf("%s: port %d: %s\n", 950 sc->sc_dv.dv_xname, TWE_AEN_UNIT(aen), msg); 951 break; 952 953 default: 954 printf("%s: %s\n", sc->sc_dv.dv_xname, msg); 955 } 956 } 957 } 958 959 /* Now enqueue the AEN for mangement tools. */ 960 s = splbio(); 961 962 next = (sc->sc_aen_head + 1) % TWE_AEN_Q_LENGTH; 963 nextnext = (sc->sc_aen_head + 2) % TWE_AEN_Q_LENGTH; 964 965 /* 966 * If this is the last free slot, then queue up a "queue 967 * full" message. 968 */ 969 if (nextnext == sc->sc_aen_tail) 970 aen = TWE_AEN_QUEUE_FULL; 971 972 if (next != sc->sc_aen_tail) { 973 sc->sc_aen_queue[sc->sc_aen_head] = aen; 974 sc->sc_aen_head = next; 975 } 976 977 if (sc->sc_flags & TWEF_AENQ_WAIT) { 978 sc->sc_flags &= ~TWEF_AENQ_WAIT; 979 wakeup(&sc->sc_aen_queue); 980 } 981 982 splx(s); 983 } 984 985 /* NOTE: Must be called at splbio(). */ 986 static uint16_t 987 twe_aen_dequeue(struct twe_softc *sc) 988 { 989 uint16_t aen; 990 991 if (sc->sc_aen_tail == sc->sc_aen_head) 992 aen = TWE_AEN_QUEUE_EMPTY; 993 else { 994 aen = sc->sc_aen_queue[sc->sc_aen_tail]; 995 sc->sc_aen_tail = (sc->sc_aen_tail + 1) & TWE_AEN_Q_LENGTH; 996 } 997 998 return (aen); 999 } 1000 1001 /* 1002 * These are short-hand functions that execute TWE_OP_GET_PARAM to 1003 * fetch 1, 2, and 4 byte parameter values, respectively. 1004 */ 1005 int 1006 twe_param_get_1(struct twe_softc *sc, int table_id, int param_id, 1007 uint8_t *valp) 1008 { 1009 struct twe_param *tp; 1010 int rv; 1011 1012 rv = twe_param_get(sc, table_id, param_id, 1, NULL, &tp); 1013 if (rv != 0) 1014 return (rv); 1015 *valp = *(uint8_t *)tp->tp_data; 1016 free(tp, M_DEVBUF); 1017 return (0); 1018 } 1019 1020 int 1021 twe_param_get_2(struct twe_softc *sc, int table_id, int param_id, 1022 uint16_t *valp) 1023 { 1024 struct twe_param *tp; 1025 int rv; 1026 1027 rv = twe_param_get(sc, table_id, param_id, 2, NULL, &tp); 1028 if (rv != 0) 1029 return (rv); 1030 *valp = le16toh(*(uint16_t *)tp->tp_data); 1031 free(tp, M_DEVBUF); 1032 return (0); 1033 } 1034 1035 int 1036 twe_param_get_4(struct twe_softc *sc, int table_id, int param_id, 1037 uint32_t *valp) 1038 { 1039 struct twe_param *tp; 1040 int rv; 1041 1042 rv = twe_param_get(sc, table_id, param_id, 4, NULL, &tp); 1043 if (rv != 0) 1044 return (rv); 1045 *valp = le32toh(*(uint32_t *)tp->tp_data); 1046 free(tp, M_DEVBUF); 1047 return (0); 1048 } 1049 1050 /* 1051 * Execute a TWE_OP_GET_PARAM command. If a callback function is provided, 1052 * it will be called with generated context when the command has completed. 1053 * If no callback is provided, the command will be executed synchronously 1054 * and a pointer to a buffer containing the data returned. 1055 * 1056 * The caller or callback is responsible for freeing the buffer. 1057 */ 1058 int 1059 twe_param_get(struct twe_softc *sc, int table_id, int param_id, size_t size, 1060 void (*func)(struct twe_ccb *, int), struct twe_param **pbuf) 1061 { 1062 struct twe_ccb *ccb; 1063 struct twe_cmd *tc; 1064 struct twe_param *tp; 1065 int rv, s; 1066 1067 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 1068 if (tp == NULL) 1069 return ENOMEM; 1070 1071 rv = twe_ccb_alloc(sc, &ccb, TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1072 if (rv != 0) 1073 goto done; 1074 1075 ccb->ccb_data = tp; 1076 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1077 ccb->ccb_tx.tx_handler = func; 1078 ccb->ccb_tx.tx_context = tp; 1079 ccb->ccb_tx.tx_dv = &sc->sc_dv; 1080 1081 tc = ccb->ccb_cmd; 1082 tc->tc_size = 2; 1083 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 1084 tc->tc_unit = 0; 1085 tc->tc_count = htole16(1); 1086 1087 /* Fill in the outbound parameter data. */ 1088 tp->tp_table_id = htole16(table_id); 1089 tp->tp_param_id = param_id; 1090 tp->tp_param_size = size; 1091 1092 /* Map the transfer. */ 1093 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 1094 twe_ccb_free(sc, ccb); 1095 goto done; 1096 } 1097 1098 /* Submit the command and either wait or let the callback handle it. */ 1099 if (func == NULL) { 1100 s = splbio(); 1101 rv = twe_ccb_poll(sc, ccb, 5); 1102 twe_ccb_unmap(sc, ccb); 1103 twe_ccb_free(sc, ccb); 1104 splx(s); 1105 } else { 1106 #ifdef DEBUG 1107 if (pbuf != NULL) 1108 panic("both func and pbuf defined"); 1109 #endif 1110 twe_ccb_enqueue(sc, ccb); 1111 return 0; 1112 } 1113 1114 done: 1115 if (pbuf == NULL || rv != 0) 1116 free(tp, M_DEVBUF); 1117 else if (pbuf != NULL && rv == 0) 1118 *pbuf = tp; 1119 return rv; 1120 } 1121 1122 /* 1123 * Execute a TWE_OP_SET_PARAM command. 1124 */ 1125 static int 1126 twe_param_set(struct twe_softc *sc, int table_id, int param_id, size_t size, 1127 void *buf) 1128 { 1129 struct twe_ccb *ccb; 1130 struct twe_cmd *tc; 1131 struct twe_param *tp; 1132 int rv, s; 1133 1134 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 1135 if (tp == NULL) 1136 return ENOMEM; 1137 1138 rv = twe_ccb_alloc(sc, &ccb, TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1139 if (rv != 0) 1140 goto done; 1141 1142 ccb->ccb_data = tp; 1143 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1144 ccb->ccb_tx.tx_handler = 0; 1145 ccb->ccb_tx.tx_context = tp; 1146 ccb->ccb_tx.tx_dv = &sc->sc_dv; 1147 1148 tc = ccb->ccb_cmd; 1149 tc->tc_size = 2; 1150 tc->tc_opcode = TWE_OP_SET_PARAM | (tc->tc_size << 5); 1151 tc->tc_unit = 0; 1152 tc->tc_count = htole16(1); 1153 1154 /* Fill in the outbound parameter data. */ 1155 tp->tp_table_id = htole16(table_id); 1156 tp->tp_param_id = param_id; 1157 tp->tp_param_size = size; 1158 memcpy(tp->tp_data, buf, size); 1159 1160 /* Map the transfer. */ 1161 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 1162 twe_ccb_free(sc, ccb); 1163 goto done; 1164 } 1165 1166 /* Submit the command and wait. */ 1167 s = splbio(); 1168 rv = twe_ccb_poll(sc, ccb, 5); 1169 twe_ccb_unmap(sc, ccb); 1170 twe_ccb_free(sc, ccb); 1171 splx(s); 1172 done: 1173 free(tp, M_DEVBUF); 1174 return (rv); 1175 } 1176 1177 /* 1178 * Execute a TWE_OP_INIT_CONNECTION command. Return non-zero on error. 1179 * Must be called with interrupts blocked. 1180 */ 1181 static int 1182 twe_init_connection(struct twe_softc *sc) 1183 /*###762 [cc] warning: `twe_init_connection' was used with no prototype before its definition%%%*/ 1184 /*###762 [cc] warning: `twe_init_connection' was declared implicitly `extern' and later `static'%%%*/ 1185 { 1186 struct twe_ccb *ccb; 1187 struct twe_cmd *tc; 1188 int rv; 1189 1190 if ((rv = twe_ccb_alloc(sc, &ccb, 0)) != 0) 1191 return (rv); 1192 1193 /* Build the command. */ 1194 tc = ccb->ccb_cmd; 1195 tc->tc_size = 3; 1196 tc->tc_opcode = TWE_OP_INIT_CONNECTION; 1197 tc->tc_unit = 0; 1198 tc->tc_count = htole16(TWE_MAX_CMDS); 1199 tc->tc_args.init_connection.response_queue_pointer = 0; 1200 1201 /* Submit the command for immediate execution. */ 1202 rv = twe_ccb_poll(sc, ccb, 5); 1203 twe_ccb_free(sc, ccb); 1204 return (rv); 1205 } 1206 1207 /* 1208 * Poll the controller for completed commands. Must be called with 1209 * interrupts blocked. 1210 */ 1211 static void 1212 twe_poll(struct twe_softc *sc) 1213 { 1214 struct twe_ccb *ccb; 1215 int found; 1216 u_int status, cmdid; 1217 1218 found = 0; 1219 1220 for (;;) { 1221 status = twe_inl(sc, TWE_REG_STS); 1222 twe_status_check(sc, status); 1223 1224 if ((status & TWE_STS_RESP_QUEUE_EMPTY)) 1225 break; 1226 1227 found = 1; 1228 cmdid = twe_inl(sc, TWE_REG_RESP_QUEUE); 1229 cmdid = (cmdid & TWE_RESP_MASK) >> TWE_RESP_SHIFT; 1230 if (cmdid >= TWE_MAX_QUEUECNT) { 1231 printf("%s: bad completion\n", sc->sc_dv.dv_xname); 1232 continue; 1233 } 1234 1235 ccb = sc->sc_ccbs + cmdid; 1236 if ((ccb->ccb_flags & TWE_CCB_ACTIVE) == 0) { 1237 printf("%s: bad completion (not active)\n", 1238 sc->sc_dv.dv_xname); 1239 continue; 1240 } 1241 ccb->ccb_flags ^= TWE_CCB_COMPLETE | TWE_CCB_ACTIVE; 1242 1243 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1244 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, 1245 sizeof(struct twe_cmd), 1246 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1247 1248 /* Pass notification to upper layers. */ 1249 if (ccb->ccb_tx.tx_handler != NULL) 1250 (*ccb->ccb_tx.tx_handler)(ccb, 1251 ccb->ccb_cmd->tc_status != 0 ? EIO : 0); 1252 } 1253 1254 /* If any commands have completed, run the software queue. */ 1255 if (found) 1256 twe_ccb_enqueue(sc, NULL); 1257 } 1258 1259 /* 1260 * Wait for `status' to be set in the controller status register. Return 1261 * zero if found, non-zero if the operation timed out. 1262 */ 1263 static int 1264 twe_status_wait(struct twe_softc *sc, u_int32_t status, int timo) 1265 { 1266 1267 for (timo *= 10; timo != 0; timo--) { 1268 if ((twe_inl(sc, TWE_REG_STS) & status) == status) 1269 break; 1270 delay(100000); 1271 } 1272 1273 return (timo == 0); 1274 } 1275 1276 /* 1277 * Complain if the status bits aren't what we expect. 1278 */ 1279 static int 1280 twe_status_check(struct twe_softc *sc, u_int status) 1281 { 1282 int rv; 1283 1284 rv = 0; 1285 1286 if ((status & TWE_STS_EXPECTED_BITS) != TWE_STS_EXPECTED_BITS) { 1287 printf("%s: missing status bits: 0x%08x\n", sc->sc_dv.dv_xname, 1288 status & ~TWE_STS_EXPECTED_BITS); 1289 rv = -1; 1290 } 1291 1292 if ((status & TWE_STS_UNEXPECTED_BITS) != 0) { 1293 printf("%s: unexpected status bits: 0x%08x\n", 1294 sc->sc_dv.dv_xname, status & TWE_STS_UNEXPECTED_BITS); 1295 rv = -1; 1296 } 1297 1298 return (rv); 1299 } 1300 1301 /* 1302 * Allocate and initialise a CCB. 1303 */ 1304 int 1305 twe_ccb_alloc(struct twe_softc *sc, struct twe_ccb **ccbp, int flags) 1306 { 1307 struct twe_cmd *tc; 1308 struct twe_ccb *ccb; 1309 int s; 1310 1311 s = splbio(); 1312 if ((flags & TWE_CCB_AEN) != 0) { 1313 /* Use the reserved CCB. */ 1314 ccb = sc->sc_ccbs; 1315 } else { 1316 /* Allocate a CCB and command block. */ 1317 if (SLIST_FIRST(&sc->sc_ccb_freelist) == NULL) { 1318 splx(s); 1319 return (EAGAIN); 1320 } 1321 ccb = SLIST_FIRST(&sc->sc_ccb_freelist); 1322 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 1323 } 1324 #ifdef DIAGNOSTIC 1325 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 1326 panic("twe_ccb_alloc: CCB already allocated"); 1327 flags |= TWE_CCB_ALLOCED; 1328 #endif 1329 splx(s); 1330 1331 /* Initialise some fields and return. */ 1332 ccb->ccb_tx.tx_handler = NULL; 1333 ccb->ccb_flags = flags; 1334 tc = ccb->ccb_cmd; 1335 tc->tc_status = 0; 1336 tc->tc_flags = 0; 1337 tc->tc_cmdid = ccb->ccb_cmdid; 1338 *ccbp = ccb; 1339 1340 return (0); 1341 } 1342 1343 /* 1344 * Free a CCB. 1345 */ 1346 void 1347 twe_ccb_free(struct twe_softc *sc, struct twe_ccb *ccb) 1348 { 1349 int s; 1350 1351 s = splbio(); 1352 if ((ccb->ccb_flags & TWE_CCB_AEN) == 0) 1353 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, ccb_chain.slist); 1354 ccb->ccb_flags = 0; 1355 splx(s); 1356 } 1357 1358 /* 1359 * Map the specified CCB's command block and data buffer (if any) into 1360 * controller visible space. Perform DMA synchronisation. 1361 */ 1362 int 1363 twe_ccb_map(struct twe_softc *sc, struct twe_ccb *ccb) 1364 { 1365 struct twe_cmd *tc; 1366 int flags, nsegs, i, s, rv; 1367 void *data; 1368 1369 /* 1370 * The data as a whole must be 512-byte aligned. 1371 */ 1372 if (((u_long)ccb->ccb_data & (TWE_ALIGNMENT - 1)) != 0) { 1373 s = splvm(); 1374 /* XXX */ 1375 ccb->ccb_abuf = uvm_km_kmemalloc(kmem_map, NULL, 1376 ccb->ccb_datasize, UVM_KMF_NOWAIT); 1377 splx(s); 1378 data = (void *)ccb->ccb_abuf; 1379 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1380 memcpy(data, ccb->ccb_data, ccb->ccb_datasize); 1381 } else { 1382 ccb->ccb_abuf = (vaddr_t)0; 1383 data = ccb->ccb_data; 1384 } 1385 1386 /* 1387 * Map the data buffer into bus space and build the S/G list. 1388 */ 1389 rv = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap_xfer, data, 1390 ccb->ccb_datasize, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1391 ((ccb->ccb_flags & TWE_CCB_DATA_IN) ? 1392 BUS_DMA_READ : BUS_DMA_WRITE)); 1393 if (rv != 0) { 1394 if (ccb->ccb_abuf != (vaddr_t)0) { 1395 s = splvm(); 1396 /* XXX */ 1397 uvm_km_free(kmem_map, ccb->ccb_abuf, 1398 ccb->ccb_datasize); 1399 splx(s); 1400 } 1401 return (rv); 1402 } 1403 1404 nsegs = ccb->ccb_dmamap_xfer->dm_nsegs; 1405 tc = ccb->ccb_cmd; 1406 tc->tc_size += 2 * nsegs; 1407 1408 /* The location of the S/G list is dependant upon command type. */ 1409 switch (tc->tc_opcode >> 5) { 1410 case 2: 1411 for (i = 0; i < nsegs; i++) { 1412 tc->tc_args.param.sgl[i].tsg_address = 1413 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 1414 tc->tc_args.param.sgl[i].tsg_length = 1415 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 1416 } 1417 /* XXX Needed? */ 1418 for (; i < TWE_SG_SIZE; i++) { 1419 tc->tc_args.param.sgl[i].tsg_address = 0; 1420 tc->tc_args.param.sgl[i].tsg_length = 0; 1421 } 1422 break; 1423 case 3: 1424 for (i = 0; i < nsegs; i++) { 1425 tc->tc_args.io.sgl[i].tsg_address = 1426 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 1427 tc->tc_args.io.sgl[i].tsg_length = 1428 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 1429 } 1430 /* XXX Needed? */ 1431 for (; i < TWE_SG_SIZE; i++) { 1432 tc->tc_args.io.sgl[i].tsg_address = 0; 1433 tc->tc_args.io.sgl[i].tsg_length = 0; 1434 } 1435 break; 1436 #ifdef DEBUG 1437 default: 1438 panic("twe_ccb_map: oops"); 1439 #endif 1440 } 1441 1442 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1443 flags = BUS_DMASYNC_PREREAD; 1444 else 1445 flags = 0; 1446 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1447 flags |= BUS_DMASYNC_PREWRITE; 1448 1449 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 1450 ccb->ccb_datasize, flags); 1451 return (0); 1452 } 1453 1454 /* 1455 * Unmap the specified CCB's command block and data buffer (if any) and 1456 * perform DMA synchronisation. 1457 */ 1458 void 1459 twe_ccb_unmap(struct twe_softc *sc, struct twe_ccb *ccb) 1460 { 1461 int flags, s; 1462 1463 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1464 flags = BUS_DMASYNC_POSTREAD; 1465 else 1466 flags = 0; 1467 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1468 flags |= BUS_DMASYNC_POSTWRITE; 1469 1470 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 1471 ccb->ccb_datasize, flags); 1472 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap_xfer); 1473 1474 if (ccb->ccb_abuf != (vaddr_t)0) { 1475 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1476 memcpy(ccb->ccb_data, (void *)ccb->ccb_abuf, 1477 ccb->ccb_datasize); 1478 s = splvm(); 1479 /* XXX */ 1480 uvm_km_free(kmem_map, ccb->ccb_abuf, ccb->ccb_datasize); 1481 splx(s); 1482 } 1483 } 1484 1485 /* 1486 * Submit a command to the controller and poll on completion. Return 1487 * non-zero on timeout (but don't check status, as some command types don't 1488 * return status). Must be called with interrupts blocked. 1489 */ 1490 int 1491 twe_ccb_poll(struct twe_softc *sc, struct twe_ccb *ccb, int timo) 1492 { 1493 int rv; 1494 1495 if ((rv = twe_ccb_submit(sc, ccb)) != 0) 1496 return (rv); 1497 1498 for (timo *= 1000; timo != 0; timo--) { 1499 twe_poll(sc); 1500 if ((ccb->ccb_flags & TWE_CCB_COMPLETE) != 0) 1501 break; 1502 DELAY(100); 1503 } 1504 1505 return (timo == 0); 1506 } 1507 1508 /* 1509 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1510 * the order that they were enqueued and try to submit their command blocks 1511 * to the controller for execution. 1512 */ 1513 void 1514 twe_ccb_enqueue(struct twe_softc *sc, struct twe_ccb *ccb) 1515 { 1516 int s; 1517 1518 s = splbio(); 1519 1520 if (ccb != NULL) 1521 SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 1522 1523 while ((ccb = SIMPLEQ_FIRST(&sc->sc_ccb_queue)) != NULL) { 1524 if (twe_ccb_submit(sc, ccb)) 1525 break; 1526 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_queue, ccb_chain.simpleq); 1527 } 1528 1529 splx(s); 1530 } 1531 1532 /* 1533 * Submit the command block associated with the specified CCB to the 1534 * controller for execution. Must be called with interrupts blocked. 1535 */ 1536 int 1537 twe_ccb_submit(struct twe_softc *sc, struct twe_ccb *ccb) 1538 { 1539 bus_addr_t pa; 1540 int rv; 1541 u_int status; 1542 1543 /* Check to see if we can post a command. */ 1544 status = twe_inl(sc, TWE_REG_STS); 1545 twe_status_check(sc, status); 1546 1547 if ((status & TWE_STS_CMD_QUEUE_FULL) == 0) { 1548 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1549 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, sizeof(struct twe_cmd), 1550 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1551 ccb->ccb_flags |= TWE_CCB_ACTIVE; 1552 pa = sc->sc_cmds_paddr + 1553 ccb->ccb_cmdid * sizeof(struct twe_cmd); 1554 twe_outl(sc, TWE_REG_CMD_QUEUE, (u_int32_t)pa); 1555 rv = 0; 1556 } else 1557 rv = EBUSY; 1558 1559 return (rv); 1560 } 1561 1562 1563 /* 1564 * Accept an open operation on the control device. 1565 */ 1566 int 1567 tweopen(dev_t dev, int flag, int mode, struct proc *p) 1568 { 1569 struct twe_softc *twe; 1570 1571 if ((twe = device_lookup(&twe_cd, minor(dev))) == NULL) 1572 return (ENXIO); 1573 if ((twe->sc_flags & TWEF_OPEN) != 0) 1574 return (EBUSY); 1575 1576 twe->sc_flags |= TWEF_OPEN; 1577 return (0); 1578 } 1579 1580 /* 1581 * Accept the last close on the control device. 1582 */ 1583 int 1584 tweclose(dev_t dev, int flag, int mode, struct proc *p) 1585 { 1586 struct twe_softc *twe; 1587 1588 twe = device_lookup(&twe_cd, minor(dev)); 1589 twe->sc_flags &= ~TWEF_OPEN; 1590 return (0); 1591 } 1592 1593 /* 1594 * Handle control operations. 1595 */ 1596 int 1597 tweioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1598 { 1599 struct twe_softc *twe; 1600 #if 0 1601 struct twe_ccb *ccb; 1602 #endif 1603 struct twe_param *param; 1604 struct twe_usercommand *tu; 1605 struct twe_paramcommand *tp; 1606 union twe_statrequest *ts; 1607 void *pdata = NULL; 1608 int rv, s, error = 0; 1609 #if 0 1610 u_int8_t cmdid; 1611 #endif 1612 1613 if (securelevel >= 2) 1614 return (EPERM); 1615 1616 twe = device_lookup(&twe_cd, minor(dev)); 1617 tu = (struct twe_usercommand *)data; 1618 tp = (struct twe_paramcommand *)data; 1619 ts = (union twe_statrequest *)data; 1620 1621 /* Hmm, compatible with FreeBSD */ 1622 switch (cmd) { 1623 case TWEIO_COMMAND: 1624 #if 0 1625 /* XXXJRT This whole path needs to be cleaned up. */ 1626 if (tu->tu_size > 0) { 1627 if (tu->tu_size > TWE_SECTOR_SIZE) 1628 return EINVAL; 1629 pdata = malloc(tu->tu_size, M_DEVBUF, M_WAITOK); 1630 error = copyin(tu->tu_data, pdata, tu->tu_size); 1631 if (error != 0) 1632 goto done; 1633 error = twe_ccb_alloc(twe, &ccb, TWE_CCB_PARAM | 1634 TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1635 } else { 1636 error = twe_ccb_alloc(twe, &ccb, 0); 1637 } 1638 if (rv != 0) 1639 goto done; 1640 cmdid = ccb->ccb_cmdid; 1641 memcpy(ccb->ccb_cmd, &tu->tu_cmd, sizeof(struct twe_cmd)); 1642 ccb->ccb_cmdid = cmdid; 1643 if (ccb->ccb_flags & TWE_CCB_PARAM) { 1644 ccb->ccb_data = pdata; 1645 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1646 ccb->ccb_tx.tx_handler = 0; 1647 ccb->ccb_tx.tx_context = pdata; 1648 ccb->ccb_tx.tx_dv = &twe->sc_dv; 1649 } 1650 /* Map the transfer. */ 1651 if ((error = twe_ccb_map(twe, ccb)) != 0) { 1652 twe_ccb_free(twe, ccb); 1653 goto done; 1654 } 1655 1656 /* Submit the command and wait. */ 1657 s = splbio(); 1658 rv = twe_ccb_poll(twe, ccb, 5); 1659 twe_ccb_unmap(twe, ccb); 1660 twe_ccb_free(twe, ccb); 1661 splx(s); 1662 1663 if (tu->tu_size > 0) 1664 error = copyout(pdata, tu->tu_data, tu->tu_size); 1665 #else 1666 rv = EOPNOTSUPP; 1667 #endif 1668 goto done; 1669 1670 case TWEIO_STATS: 1671 return (ENOENT); 1672 1673 case TWEIO_AEN_POLL: 1674 s = splbio(); 1675 *(u_int *)data = twe_aen_dequeue(twe); 1676 splx(s); 1677 return (0); 1678 1679 case TWEIO_AEN_WAIT: 1680 s = splbio(); 1681 while ((*(u_int *)data = 1682 twe_aen_dequeue(twe)) == TWE_AEN_QUEUE_EMPTY) { 1683 twe->sc_flags |= TWEF_AENQ_WAIT; 1684 error = tsleep(&twe->sc_aen_queue, PRIBIO | PCATCH, 1685 "tweaen", 0); 1686 if (error == EINTR) { 1687 splx(s); 1688 return (error); 1689 } 1690 } 1691 splx(s); 1692 return (0); 1693 1694 case TWEIO_GET_PARAM: 1695 error = twe_param_get(twe, tp->tp_table_id, tp->tp_param_id, 1696 tp->tp_size, 0, ¶m); 1697 if (error != 0) 1698 return (error); 1699 if (param->tp_param_size > tp->tp_size) { 1700 error = EFAULT; 1701 goto done; 1702 } 1703 error = copyout(param->tp_data, tp->tp_data, 1704 param->tp_param_size); 1705 goto done; 1706 1707 case TWEIO_SET_PARAM: 1708 pdata = malloc(tp->tp_size, M_DEVBUF, M_WAITOK); 1709 if ((error = copyin(tp->tp_data, pdata, tp->tp_size)) != 0) 1710 goto done; 1711 error = twe_param_set(twe, tp->tp_table_id, tp->tp_param_id, 1712 tp->tp_size, pdata); 1713 goto done; 1714 1715 case TWEIO_RESET: 1716 s = splbio(); 1717 twe_reset(twe); 1718 splx(s); 1719 return (0); 1720 1721 case TWEIO_ADD_UNIT: 1722 /* XXX mutex */ 1723 return (twe_add_unit(twe, *(int *)data)); 1724 1725 case TWEIO_DEL_UNIT: 1726 /* XXX mutex */ 1727 return (twe_del_unit(twe, *(int *)data)); 1728 1729 default: 1730 return EINVAL; 1731 } 1732 done: 1733 if (pdata) 1734 free(pdata, M_DEVBUF); 1735 return error; 1736 } 1737 1738 /* 1739 * Print some information about the controller 1740 */ 1741 static void 1742 twe_describe_controller(struct twe_softc *sc) 1743 { 1744 struct twe_param *p[6]; 1745 int i, rv = 0; 1746 uint32_t dsize; 1747 uint8_t ports; 1748 1749 /* get the port count */ 1750 rv |= twe_param_get_1(sc, TWE_PARAM_CONTROLLER, 1751 TWE_PARAM_CONTROLLER_PortCount, &ports); 1752 1753 /* get version strings */ 1754 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_Mon, 1755 16, NULL, &p[0]); 1756 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_FW, 1757 16, NULL, &p[1]); 1758 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_BIOS, 1759 16, NULL, &p[2]); 1760 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_PCB, 1761 8, NULL, &p[3]); 1762 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_ATA, 1763 8, NULL, &p[4]); 1764 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_PCI, 1765 8, NULL, &p[5]); 1766 1767 if (rv) { 1768 /* some error occurred */ 1769 aprint_error("%s: failed to fetch version information\n", 1770 sc->sc_dv.dv_xname); 1771 return; 1772 } 1773 1774 aprint_normal("%s: %d ports, Firmware %.16s, BIOS %.16s\n", 1775 sc->sc_dv.dv_xname, ports, 1776 p[1]->tp_data, p[2]->tp_data); 1777 1778 aprint_verbose("%s: Monitor %.16s, PCB %.8s, Achip %.8s, Pchip %.8s\n", 1779 sc->sc_dv.dv_xname, 1780 p[0]->tp_data, p[3]->tp_data, 1781 p[4]->tp_data, p[5]->tp_data); 1782 1783 free(p[0], M_DEVBUF); 1784 free(p[1], M_DEVBUF); 1785 free(p[2], M_DEVBUF); 1786 free(p[3], M_DEVBUF); 1787 free(p[4], M_DEVBUF); 1788 free(p[5], M_DEVBUF); 1789 1790 rv = twe_param_get(sc, TWE_PARAM_DRIVESUMMARY, 1791 TWE_PARAM_DRIVESUMMARY_Status, 16, NULL, &p[0]); 1792 if (rv) { 1793 aprint_error("%s: failed to get drive status summary\n", 1794 sc->sc_dv.dv_xname); 1795 return; 1796 } 1797 for (i = 0; i < ports; i++) { 1798 if (p[0]->tp_data[i] != TWE_PARAM_DRIVESTATUS_Present) 1799 continue; 1800 rv = twe_param_get_4(sc, TWE_PARAM_DRIVEINFO + i, 1801 TWE_PARAM_DRIVEINFO_Size, &dsize); 1802 if (rv) { 1803 aprint_error( 1804 "%s: unable to get drive size for port %d\n", 1805 sc->sc_dv.dv_xname, i); 1806 continue; 1807 } 1808 rv = twe_param_get(sc, TWE_PARAM_DRIVEINFO + i, 1809 TWE_PARAM_DRIVEINFO_Model, 40, NULL, &p[1]); 1810 if (rv) { 1811 aprint_error( 1812 "%s: unable to get drive model for port %d\n", 1813 sc->sc_dv.dv_xname, i); 1814 continue; 1815 } 1816 aprint_verbose("%s: port %d: %.40s %d MB\n", sc->sc_dv.dv_xname, 1817 i, p[1]->tp_data, dsize / 2048); 1818 free(p[1], M_DEVBUF); 1819 } 1820 free(p[0], M_DEVBUF); 1821 } 1822
Indexes created Wed Oct 01 07:09:59 GMT 2025