twe.c revision 1.69
1 /* $NetBSD: twe.c,v 1.69 2005/08/25 18:35:39 drochner Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran; and by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twe.c,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 /* 69 * Driver for the 3ware Escalade family of RAID controllers. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: twe.c,v 1.69 2005/08/25 18:35:39 drochner Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/device.h> 79 #include <sys/queue.h> 80 #include <sys/proc.h> 81 #include <sys/buf.h> 82 #include <sys/endian.h> 83 #include <sys/malloc.h> 84 #include <sys/conf.h> 85 #include <sys/disk.h> 86 #include <sys/sysctl.h> 87 #include <sys/syslog.h> 88 89 #include <uvm/uvm_extern.h> 90 91 #include <machine/bswap.h> 92 #include <machine/bus.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcidevs.h> 97 #include <dev/pci/twereg.h> 98 #include <dev/pci/twevar.h> 99 #include <dev/pci/tweio.h> 100 101 #include "locators.h" 102 103 #define PCI_CBIO 0x10 104 105 static int twe_aen_get(struct twe_softc *, uint16_t *); 106 static void twe_aen_handler(struct twe_ccb *, int); 107 static void twe_aen_enqueue(struct twe_softc *sc, uint16_t, int); 108 static uint16_t twe_aen_dequeue(struct twe_softc *); 109 110 static void twe_attach(struct device *, struct device *, void *); 111 static int twe_init_connection(struct twe_softc *); 112 static int twe_intr(void *); 113 static int twe_match(struct device *, struct cfdata *, void *); 114 static int twe_param_set(struct twe_softc *, int, int, size_t, void *); 115 static void twe_poll(struct twe_softc *); 116 static int twe_print(void *, const char *); 117 static int twe_reset(struct twe_softc *); 118 static int twe_submatch(struct device *, struct cfdata *, 119 const locdesc_t *, void *); 120 static int twe_status_check(struct twe_softc *, u_int); 121 static int twe_status_wait(struct twe_softc *, u_int, int); 122 static void twe_describe_controller(struct twe_softc *); 123 static void twe_clear_pci_abort(struct twe_softc *sc); 124 static void twe_clear_pci_parity_error(struct twe_softc *sc); 125 126 static int twe_add_unit(struct twe_softc *, int); 127 static int twe_del_unit(struct twe_softc *, int); 128 129 static inline u_int32_t twe_inl(struct twe_softc *, int); 130 static inline void twe_outl(struct twe_softc *, int, u_int32_t); 131 132 extern struct cfdriver twe_cd; 133 134 CFATTACH_DECL(twe, sizeof(struct twe_softc), 135 twe_match, twe_attach, NULL, NULL); 136 137 /* FreeBSD driver revision for sysctl expected by the 3ware cli */ 138 const char twever[] = "1.50.01.002"; 139 140 /* 141 * Tables to convert numeric codes to strings. 142 */ 143 const struct twe_code_table twe_table_status[] = { 144 { 0x00, "successful completion" }, 145 146 /* info */ 147 { 0x42, "command in progress" }, 148 { 0x6c, "retrying interface CRC error from UDMA command" }, 149 150 /* warning */ 151 { 0x81, "redundant/inconsequential request ignored" }, 152 { 0x8e, "failed to write zeroes to LBA 0" }, 153 { 0x8f, "failed to profile TwinStor zones" }, 154 155 /* fatal */ 156 { 0xc1, "aborted due to system command or reconfiguration" }, 157 { 0xc4, "aborted" }, 158 { 0xc5, "access error" }, 159 { 0xc6, "access violation" }, 160 { 0xc7, "device failure" }, /* high byte may be port # */ 161 { 0xc8, "controller error" }, 162 { 0xc9, "timed out" }, 163 { 0xcb, "invalid unit number" }, 164 { 0xcf, "unit not available" }, 165 { 0xd2, "undefined opcode" }, 166 { 0xdb, "request incompatible with unit" }, 167 { 0xdc, "invalid request" }, 168 { 0xff, "firmware error, reset requested" }, 169 170 { 0, NULL } 171 }; 172 173 const struct twe_code_table twe_table_unitstate[] = { 174 { TWE_PARAM_UNITSTATUS_Normal, "Normal" }, 175 { TWE_PARAM_UNITSTATUS_Initialising, "Initializing" }, 176 { TWE_PARAM_UNITSTATUS_Degraded, "Degraded" }, 177 { TWE_PARAM_UNITSTATUS_Rebuilding, "Rebuilding" }, 178 { TWE_PARAM_UNITSTATUS_Verifying, "Verifying" }, 179 { TWE_PARAM_UNITSTATUS_Corrupt, "Corrupt" }, 180 { TWE_PARAM_UNITSTATUS_Missing, "Missing" }, 181 182 { 0, NULL } 183 }; 184 185 const struct twe_code_table twe_table_unittype[] = { 186 /* array descriptor configuration */ 187 { TWE_AD_CONFIG_RAID0, "RAID0" }, 188 { TWE_AD_CONFIG_RAID1, "RAID1" }, 189 { TWE_AD_CONFIG_TwinStor, "TwinStor" }, 190 { TWE_AD_CONFIG_RAID5, "RAID5" }, 191 { TWE_AD_CONFIG_RAID10, "RAID10" }, 192 { TWE_UD_CONFIG_JBOD, "JBOD" }, 193 194 { 0, NULL } 195 }; 196 197 const struct twe_code_table twe_table_stripedepth[] = { 198 { TWE_AD_STRIPE_4k, "4K" }, 199 { TWE_AD_STRIPE_8k, "8K" }, 200 { TWE_AD_STRIPE_16k, "16K" }, 201 { TWE_AD_STRIPE_32k, "32K" }, 202 { TWE_AD_STRIPE_64k, "64K" }, 203 { TWE_AD_STRIPE_128k, "128K" }, 204 { TWE_AD_STRIPE_256k, "256K" }, 205 { TWE_AD_STRIPE_512k, "512K" }, 206 { TWE_AD_STRIPE_1024k, "1024K" }, 207 208 { 0, NULL } 209 }; 210 211 /* 212 * Asynchronous event notification messages are qualified: 213 * a - not unit/port specific 214 * u - unit specific 215 * p - port specific 216 * 217 * They are further qualified with a severity: 218 * E - LOG_EMERG 219 * a - LOG_ALERT 220 * c - LOG_CRIT 221 * e - LOG_ERR 222 * w - LOG_WARNING 223 * n - LOG_NOTICE 224 * i - LOG_INFO 225 * d - LOG_DEBUG 226 * blank - just use printf 227 */ 228 const struct twe_code_table twe_table_aen[] = { 229 { 0x00, "a queue empty" }, 230 { 0x01, "a soft reset" }, 231 { 0x02, "uc degraded mode" }, 232 { 0x03, "aa controller error" }, 233 { 0x04, "uE rebuild fail" }, 234 { 0x05, "un rebuild done" }, 235 { 0x06, "ue incomplete unit" }, 236 { 0x07, "un initialization done" }, 237 { 0x08, "uw unclean shutdown detected" }, 238 { 0x09, "pe drive timeout" }, 239 { 0x0a, "pc drive error" }, 240 { 0x0b, "un rebuild started" }, 241 { 0x0c, "un initialization started" }, 242 { 0x0d, "ui logical unit deleted" }, 243 { 0x0f, "pc SMART threshold exceeded" }, 244 { 0x15, "a table undefined" }, /* XXX: Not in FreeBSD's table */ 245 { 0x21, "pe ATA UDMA downgrade" }, 246 { 0x22, "pi ATA UDMA upgrade" }, 247 { 0x23, "pw sector repair occurred" }, 248 { 0x24, "aa SBUF integrity check failure" }, 249 { 0x25, "pa lost cached write" }, 250 { 0x26, "pa drive ECC error detected" }, 251 { 0x27, "pe DCB checksum error" }, 252 { 0x28, "pn DCB unsupported version" }, 253 { 0x29, "ui verify started" }, 254 { 0x2a, "ua verify failed" }, 255 { 0x2b, "ui verify complete" }, 256 { 0x2c, "pw overwrote bad sector during rebuild" }, 257 { 0x2d, "pa encountered bad sector during rebuild" }, 258 { 0x2e, "pe replacement drive too small" }, 259 { 0x2f, "ue array not previously initialized" }, 260 { 0x30, "p drive not supported" }, 261 { 0xff, "a aen queue full" }, 262 263 { 0, NULL }, 264 }; 265 266 const char * 267 twe_describe_code(const struct twe_code_table *table, uint32_t code) 268 { 269 270 for (; table->string != NULL; table++) { 271 if (table->code == code) 272 return (table->string); 273 } 274 return (NULL); 275 } 276 277 static inline u_int32_t 278 twe_inl(struct twe_softc *sc, int off) 279 { 280 281 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 282 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 283 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, off)); 284 } 285 286 static inline void 287 twe_outl(struct twe_softc *sc, int off, u_int32_t val) 288 { 289 290 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 291 bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, 292 BUS_SPACE_BARRIER_WRITE); 293 } 294 295 /* 296 * Match a supported board. 297 */ 298 static int 299 twe_match(struct device *parent, struct cfdata *cfdata, void *aux) 300 { 301 struct pci_attach_args *pa; 302 303 pa = aux; 304 305 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3WARE && 306 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE || 307 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3WARE_ESCALADE_ASIC)); 308 } 309 310 /* 311 * Attach a supported board. 312 * 313 * XXX This doesn't fail gracefully. 314 */ 315 static void 316 twe_attach(struct device *parent, struct device *self, void *aux) 317 { 318 struct pci_attach_args *pa; 319 struct twe_softc *sc; 320 pci_chipset_tag_t pc; 321 pci_intr_handle_t ih; 322 pcireg_t csr; 323 const char *intrstr; 324 int s, size, i, rv, rseg; 325 size_t max_segs, max_xfer; 326 bus_dma_segment_t seg; 327 struct ctlname ctlnames[] = CTL_NAMES; 328 const struct sysctlnode *node; 329 struct twe_cmd *tc; 330 struct twe_ccb *ccb; 331 332 sc = (struct twe_softc *)self; 333 pa = aux; 334 pc = pa->pa_pc; 335 sc->sc_dmat = pa->pa_dmat; 336 SIMPLEQ_INIT(&sc->sc_ccb_queue); 337 SLIST_INIT(&sc->sc_ccb_freelist); 338 339 aprint_naive(": RAID controller\n"); 340 aprint_normal(": 3ware Escalade\n"); 341 342 ccb = malloc(sizeof(*ccb) * TWE_MAX_QUEUECNT, M_DEVBUF, M_NOWAIT); 343 if (ccb == NULL) { 344 aprint_error("%s: unable to allocate memory for ccbs\n", 345 sc->sc_dv.dv_xname); 346 return; 347 } 348 349 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 350 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 351 aprint_error("%s: can't map i/o space\n", sc->sc_dv.dv_xname); 352 return; 353 } 354 355 /* Enable the device. */ 356 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 357 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 358 csr | PCI_COMMAND_MASTER_ENABLE); 359 360 /* Map and establish the interrupt. */ 361 if (pci_intr_map(pa, &ih)) { 362 aprint_error("%s: can't map interrupt\n", sc->sc_dv.dv_xname); 363 return; 364 } 365 366 intrstr = pci_intr_string(pc, ih); 367 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, twe_intr, sc); 368 if (sc->sc_ih == NULL) { 369 aprint_error("%s: can't establish interrupt%s%s\n", 370 sc->sc_dv.dv_xname, 371 (intrstr) ? " at " : "", 372 (intrstr) ? intrstr : ""); 373 return; 374 } 375 376 if (intrstr != NULL) 377 aprint_normal("%s: interrupting at %s\n", 378 sc->sc_dv.dv_xname, intrstr); 379 380 /* 381 * Allocate and initialise the command blocks and CCBs. 382 */ 383 size = sizeof(struct twe_cmd) * TWE_MAX_QUEUECNT; 384 385 if ((rv = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 1, 386 &rseg, BUS_DMA_NOWAIT)) != 0) { 387 aprint_error("%s: unable to allocate commands, rv = %d\n", 388 sc->sc_dv.dv_xname, rv); 389 return; 390 } 391 392 if ((rv = bus_dmamem_map(sc->sc_dmat, &seg, rseg, size, 393 (caddr_t *)&sc->sc_cmds, 394 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 395 aprint_error("%s: unable to map commands, rv = %d\n", 396 sc->sc_dv.dv_xname, rv); 397 return; 398 } 399 400 if ((rv = bus_dmamap_create(sc->sc_dmat, size, size, 1, 0, 401 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 402 aprint_error("%s: unable to create command DMA map, rv = %d\n", 403 sc->sc_dv.dv_xname, rv); 404 return; 405 } 406 407 if ((rv = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_cmds, 408 size, NULL, BUS_DMA_NOWAIT)) != 0) { 409 aprint_error("%s: unable to load command DMA map, rv = %d\n", 410 sc->sc_dv.dv_xname, rv); 411 return; 412 } 413 414 sc->sc_cmds_paddr = sc->sc_dmamap->dm_segs[0].ds_addr; 415 memset(sc->sc_cmds, 0, size); 416 417 sc->sc_ccbs = ccb; 418 tc = (struct twe_cmd *)sc->sc_cmds; 419 max_segs = twe_get_maxsegs(); 420 max_xfer = twe_get_maxxfer(max_segs); 421 422 for (i = 0; i < TWE_MAX_QUEUECNT; i++, tc++, ccb++) { 423 ccb->ccb_cmd = tc; 424 ccb->ccb_cmdid = i; 425 ccb->ccb_flags = 0; 426 rv = bus_dmamap_create(sc->sc_dmat, max_xfer, 427 max_segs, PAGE_SIZE, 0, 428 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 429 &ccb->ccb_dmamap_xfer); 430 if (rv != 0) { 431 aprint_error("%s: can't create dmamap, rv = %d\n", 432 sc->sc_dv.dv_xname, rv); 433 return; 434 } 435 436 /* Save the first CCB for AEN retrieval. */ 437 if (i != 0) 438 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, 439 ccb_chain.slist); 440 } 441 442 /* Wait for the controller to become ready. */ 443 if (twe_status_wait(sc, TWE_STS_MICROCONTROLLER_READY, 6)) { 444 aprint_error("%s: microcontroller not ready\n", 445 sc->sc_dv.dv_xname); 446 return; 447 } 448 449 twe_outl(sc, TWE_REG_CTL, TWE_CTL_DISABLE_INTRS); 450 451 /* Reset the controller. */ 452 s = splbio(); 453 rv = twe_reset(sc); 454 splx(s); 455 if (rv) { 456 aprint_error("%s: reset failed\n", sc->sc_dv.dv_xname); 457 return; 458 } 459 460 /* Initialise connection with controller. */ 461 twe_init_connection(sc); 462 463 twe_describe_controller(sc); 464 465 /* Find and attach RAID array units. */ 466 sc->sc_nunits = 0; 467 for (i = 0; i < TWE_MAX_UNITS; i++) 468 (void) twe_add_unit(sc, i); 469 470 /* ...and finally, enable interrupts. */ 471 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR | 472 TWE_CTL_UNMASK_RESP_INTR | 473 TWE_CTL_ENABLE_INTRS); 474 475 /* sysctl set-up for 3ware cli */ 476 if (sysctl_createv(NULL, 0, NULL, NULL, 477 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", 478 NULL, NULL, 0, NULL, 0, 479 CTL_HW, CTL_EOL) != 0) { 480 printf("%s: could not create %s sysctl node\n", 481 sc->sc_dv.dv_xname, ctlnames[CTL_HW].ctl_name); 482 return; 483 } 484 if (sysctl_createv(NULL, 0, NULL, &node, 485 0, CTLTYPE_NODE, sc->sc_dv.dv_xname, 486 SYSCTL_DESCR("twe driver information"), 487 NULL, 0, NULL, 0, 488 CTL_HW, CTL_CREATE, CTL_EOL) != 0) { 489 printf("%s: could not create %s.%s sysctl node\n", 490 sc->sc_dv.dv_xname, ctlnames[CTL_HW].ctl_name, 491 sc->sc_dv.dv_xname); 492 return; 493 } 494 if ((i = sysctl_createv(NULL, 0, NULL, NULL, 495 0, CTLTYPE_STRING, "driver_version", 496 SYSCTL_DESCR("twe0 driver version"), 497 NULL, 0, &twever, 0, 498 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL)) 499 != 0) { 500 printf("%s: could not create %s.%s.driver_version sysctl\n", 501 sc->sc_dv.dv_xname, ctlnames[CTL_HW].ctl_name, 502 sc->sc_dv.dv_xname); 503 return; 504 } 505 } 506 507 void 508 twe_register_callbacks(struct twe_softc *sc, int unit, 509 const struct twe_callbacks *tcb) 510 { 511 512 sc->sc_units[unit].td_callbacks = tcb; 513 } 514 515 static void 516 twe_recompute_openings(struct twe_softc *sc) 517 { 518 struct twe_drive *td; 519 int unit, openings; 520 521 if (sc->sc_nunits != 0) 522 openings = (TWE_MAX_QUEUECNT - 1) / sc->sc_nunits; 523 else 524 openings = 0; 525 if (openings == sc->sc_openings) 526 return; 527 sc->sc_openings = openings; 528 529 #ifdef TWE_DEBUG 530 printf("%s: %d array%s, %d openings per array\n", 531 sc->sc_dv.dv_xname, sc->sc_nunits, 532 sc->sc_nunits == 1 ? "" : "s", sc->sc_openings); 533 #endif 534 535 for (unit = 0; unit < TWE_MAX_UNITS; unit++) { 536 td = &sc->sc_units[unit]; 537 if (td->td_dev != NULL) 538 (*td->td_callbacks->tcb_openings)(td->td_dev, 539 sc->sc_openings); 540 } 541 } 542 543 static int 544 twe_add_unit(struct twe_softc *sc, int unit) 545 { 546 struct twe_param *dtp, *atp; 547 struct twe_array_descriptor *ad; 548 struct twe_drive *td; 549 struct twe_attach_args twea; 550 uint32_t newsize; 551 int rv; 552 uint16_t dsize; 553 uint8_t newtype, newstripe; 554 int locs[TWECF_NLOCS]; 555 556 if (unit < 0 || unit >= TWE_MAX_UNITS) 557 return (EINVAL); 558 559 /* Find attached units. */ 560 rv = twe_param_get(sc, TWE_PARAM_UNITSUMMARY, 561 TWE_PARAM_UNITSUMMARY_Status, TWE_MAX_UNITS, NULL, &dtp); 562 if (rv != 0) { 563 aprint_error("%s: error %d fetching unit summary\n", 564 sc->sc_dv.dv_xname, rv); 565 return (rv); 566 } 567 568 /* For each detected unit, collect size and store in an array. */ 569 td = &sc->sc_units[unit]; 570 571 /* Unit present? */ 572 if ((dtp->tp_data[unit] & TWE_PARAM_UNITSTATUS_Online) == 0) { 573 /* 574 * XXX Should we check to see if a device has been 575 * XXX attached at this index and detach it if it 576 * XXX has? ("rescan" semantics) 577 */ 578 rv = 0; 579 goto out; 580 } 581 582 rv = twe_param_get_2(sc, TWE_PARAM_UNITINFO + unit, 583 TWE_PARAM_UNITINFO_DescriptorSize, &dsize); 584 if (rv != 0) { 585 aprint_error("%s: error %d fetching descriptor size " 586 "for unit %d\n", sc->sc_dv.dv_xname, rv, unit); 587 goto out; 588 } 589 590 rv = twe_param_get(sc, TWE_PARAM_UNITINFO + unit, 591 TWE_PARAM_UNITINFO_Descriptor, dsize - 3, NULL, &atp); 592 if (rv != 0) { 593 aprint_error("%s: error %d fetching array descriptor " 594 "for unit %d\n", sc->sc_dv.dv_xname, rv, unit); 595 goto out; 596 } 597 598 ad = (struct twe_array_descriptor *)atp->tp_data; 599 newtype = ad->configuration; 600 newstripe = ad->stripe_size; 601 free(atp, M_DEVBUF); 602 603 rv = twe_param_get_4(sc, TWE_PARAM_UNITINFO + unit, 604 TWE_PARAM_UNITINFO_Capacity, &newsize); 605 if (rv != 0) { 606 aprint_error( 607 "%s: error %d fetching capacity for unit %d\n", 608 sc->sc_dv.dv_xname, rv, unit); 609 goto out; 610 } 611 612 /* 613 * Have a device, so we need to attach it. If there is currently 614 * something sitting at the slot, and the parameters are different, 615 * then we detach the old device before attaching the new one. 616 */ 617 if (td->td_dev != NULL && 618 td->td_size == newsize && 619 td->td_type == newtype && 620 td->td_stripe == newstripe) { 621 /* Same as the old device; just keep using it. */ 622 rv = 0; 623 goto out; 624 } else if (td->td_dev != NULL) { 625 /* Detach the old device first. */ 626 (void) config_detach(td->td_dev, DETACH_FORCE); 627 td->td_dev = NULL; 628 } else if (td->td_size == 0) 629 sc->sc_nunits++; 630 631 /* 632 * Committed to the new array unit; assign its parameters and 633 * recompute the number of available command openings. 634 */ 635 td->td_size = newsize; 636 td->td_type = newtype; 637 td->td_stripe = newstripe; 638 twe_recompute_openings(sc); 639 640 twea.twea_unit = unit; 641 642 locs[TWECF_UNIT] = unit; 643 644 td->td_dev = config_found_sm_loc(&sc->sc_dv, "twe", locs, &twea, 645 twe_print, twe_submatch); 646 647 rv = 0; 648 out: 649 free(dtp, M_DEVBUF); 650 return (rv); 651 } 652 653 static int 654 twe_del_unit(struct twe_softc *sc, int unit) 655 { 656 struct twe_drive *td; 657 658 if (unit < 0 || unit >= TWE_MAX_UNITS) 659 return (EINVAL); 660 661 td = &sc->sc_units[unit]; 662 if (td->td_size != 0) 663 sc->sc_nunits--; 664 td->td_size = 0; 665 td->td_type = 0; 666 td->td_stripe = 0; 667 if (td->td_dev != NULL) { 668 (void) config_detach(td->td_dev, DETACH_FORCE); 669 td->td_dev = NULL; 670 } 671 twe_recompute_openings(sc); 672 return (0); 673 } 674 675 /* 676 * Reset the controller. 677 * MUST BE CALLED AT splbio()! 678 */ 679 static int 680 twe_reset(struct twe_softc *sc) 681 { 682 uint16_t aen; 683 u_int status; 684 volatile u_int32_t junk; 685 int got, rv; 686 687 /* Issue a soft reset. */ 688 twe_outl(sc, TWE_REG_CTL, TWE_CTL_ISSUE_SOFT_RESET | 689 TWE_CTL_CLEAR_HOST_INTR | 690 TWE_CTL_CLEAR_ATTN_INTR | 691 TWE_CTL_MASK_CMD_INTR | 692 TWE_CTL_MASK_RESP_INTR | 693 TWE_CTL_CLEAR_ERROR_STS | 694 TWE_CTL_DISABLE_INTRS); 695 696 /* Wait for attention... */ 697 if (twe_status_wait(sc, TWE_STS_ATTN_INTR, 30)) { 698 printf("%s: timeout waiting for attention interrupt\n", 699 sc->sc_dv.dv_xname); 700 return (-1); 701 } 702 703 /* ...and ACK it. */ 704 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 705 706 /* 707 * Pull AENs out of the controller; look for a soft reset AEN. 708 * Open code this, since we want to detect reset even if the 709 * queue for management tools is full. 710 * 711 * Note that since: 712 * - interrupts are blocked 713 * - we have reset the controller 714 * - acknowledged the pending ATTENTION 715 * that there is no way a pending asynchronous AEN fetch would 716 * finish, so clear the flag. 717 */ 718 sc->sc_flags &= ~TWEF_AEN; 719 for (got = 0;;) { 720 rv = twe_aen_get(sc, &aen); 721 if (rv != 0) 722 printf("%s: error %d while draining event queue\n", 723 sc->sc_dv.dv_xname, rv); 724 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) 725 break; 726 if (TWE_AEN_CODE(aen) == TWE_AEN_SOFT_RESET) 727 got = 1; 728 twe_aen_enqueue(sc, aen, 1); 729 } 730 731 if (!got) { 732 printf("%s: reset not reported\n", sc->sc_dv.dv_xname); 733 return (-1); 734 } 735 736 /* Check controller status. */ 737 status = twe_inl(sc, TWE_REG_STS); 738 if (twe_status_check(sc, status)) { 739 printf("%s: controller errors detected\n", 740 sc->sc_dv.dv_xname); 741 return (-1); 742 } 743 744 /* Drain the response queue. */ 745 for (;;) { 746 status = twe_inl(sc, TWE_REG_STS); 747 if (twe_status_check(sc, status) != 0) { 748 printf("%s: can't drain response queue\n", 749 sc->sc_dv.dv_xname); 750 return (-1); 751 } 752 if ((status & TWE_STS_RESP_QUEUE_EMPTY) != 0) 753 break; 754 junk = twe_inl(sc, TWE_REG_RESP_QUEUE); 755 } 756 757 return (0); 758 } 759 760 /* 761 * Print autoconfiguration message for a sub-device. 762 */ 763 static int 764 twe_print(void *aux, const char *pnp) 765 { 766 struct twe_attach_args *twea; 767 768 twea = aux; 769 770 if (pnp != NULL) 771 aprint_normal("block device at %s", pnp); 772 aprint_normal(" unit %d", twea->twea_unit); 773 return (UNCONF); 774 } 775 776 /* 777 * Match a sub-device. 778 */ 779 static int 780 twe_submatch(struct device *parent, struct cfdata *cf, 781 const locdesc_t *locs, void *aux) 782 { 783 784 if (cf->cf_loc[TWECF_UNIT] != TWECF_UNIT_DEFAULT && 785 cf->cf_loc[TWECF_UNIT] != locs[TWECF_UNIT]) 786 return (0); 787 788 return (config_match(parent, cf, aux)); 789 } 790 791 /* 792 * Interrupt service routine. 793 */ 794 static int 795 twe_intr(void *arg) 796 { 797 struct twe_softc *sc; 798 u_int status; 799 int caught, rv; 800 801 sc = arg; 802 caught = 0; 803 status = twe_inl(sc, TWE_REG_STS); 804 twe_status_check(sc, status); 805 806 /* Host interrupts - purpose unknown. */ 807 if ((status & TWE_STS_HOST_INTR) != 0) { 808 #ifdef DEBUG 809 printf("%s: host interrupt\n", sc->sc_dv.dv_xname); 810 #endif 811 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_HOST_INTR); 812 caught = 1; 813 } 814 815 /* 816 * Attention interrupts, signalled when a controller or child device 817 * state change has occurred. 818 */ 819 if ((status & TWE_STS_ATTN_INTR) != 0) { 820 rv = twe_aen_get(sc, NULL); 821 if (rv != 0) 822 printf("%s: unable to retrieve AEN (%d)\n", 823 sc->sc_dv.dv_xname, rv); 824 else 825 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 826 caught = 1; 827 } 828 829 /* 830 * Command interrupts, signalled when the controller can accept more 831 * commands. We don't use this; instead, we try to submit commands 832 * when we receive them, and when other commands have completed. 833 * Mask it so we don't get another one. 834 */ 835 if ((status & TWE_STS_CMD_INTR) != 0) { 836 #ifdef DEBUG 837 printf("%s: command interrupt\n", sc->sc_dv.dv_xname); 838 #endif 839 twe_outl(sc, TWE_REG_CTL, TWE_CTL_MASK_CMD_INTR); 840 caught = 1; 841 } 842 843 if ((status & TWE_STS_RESP_INTR) != 0) { 844 twe_poll(sc); 845 caught = 1; 846 } 847 848 return (caught); 849 } 850 851 /* 852 * Fetch an AEN. Even though this is really like parameter 853 * retrieval, we handle this specially, because we issue this 854 * AEN retrieval command from interrupt context, and thus 855 * reserve a CCB for it to avoid resource shortage. 856 * 857 * XXX There are still potential resource shortages we could 858 * XXX encounter. Consider pre-allocating all AEN-related 859 * XXX resources. 860 * 861 * MUST BE CALLED AT splbio()! 862 */ 863 static int 864 twe_aen_get(struct twe_softc *sc, uint16_t *aenp) 865 { 866 struct twe_ccb *ccb; 867 struct twe_cmd *tc; 868 struct twe_param *tp; 869 int rv; 870 871 /* 872 * If we're already retrieving an AEN, just wait; another 873 * retrieval will be chained after the current one completes. 874 */ 875 if (sc->sc_flags & TWEF_AEN) { 876 /* 877 * It is a fatal software programming error to attempt 878 * to fetch an AEN synchronously when an AEN fetch is 879 * already pending. 880 */ 881 KASSERT(aenp == NULL); 882 return (0); 883 } 884 885 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 886 if (tp == NULL) 887 return (ENOMEM); 888 889 ccb = twe_ccb_alloc(sc, 890 TWE_CCB_AEN | TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 891 KASSERT(ccb != NULL); 892 893 ccb->ccb_data = tp; 894 ccb->ccb_datasize = TWE_SECTOR_SIZE; 895 ccb->ccb_tx.tx_handler = (aenp == NULL) ? twe_aen_handler : NULL; 896 ccb->ccb_tx.tx_context = tp; 897 ccb->ccb_tx.tx_dv = &sc->sc_dv; 898 899 tc = ccb->ccb_cmd; 900 tc->tc_size = 2; 901 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 902 tc->tc_unit = 0; 903 tc->tc_count = htole16(1); 904 905 /* Fill in the outbound parameter data. */ 906 tp->tp_table_id = htole16(TWE_PARAM_AEN); 907 tp->tp_param_id = TWE_PARAM_AEN_UnitCode; 908 tp->tp_param_size = 2; 909 910 /* Map the transfer. */ 911 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 912 twe_ccb_free(sc, ccb); 913 goto done; 914 } 915 916 /* Enqueue the command and wait. */ 917 if (aenp != NULL) { 918 rv = twe_ccb_poll(sc, ccb, 5); 919 twe_ccb_unmap(sc, ccb); 920 twe_ccb_free(sc, ccb); 921 if (rv == 0) 922 *aenp = le16toh(*(uint16_t *)tp->tp_data); 923 free(tp, M_DEVBUF); 924 } else { 925 sc->sc_flags |= TWEF_AEN; 926 twe_ccb_enqueue(sc, ccb); 927 rv = 0; 928 } 929 930 done: 931 return (rv); 932 } 933 934 /* 935 * Handle an AEN returned by the controller. 936 * MUST BE CALLED AT splbio()! 937 */ 938 static void 939 twe_aen_handler(struct twe_ccb *ccb, int error) 940 { 941 struct twe_softc *sc; 942 struct twe_param *tp; 943 uint16_t aen; 944 int rv; 945 946 sc = (struct twe_softc *)ccb->ccb_tx.tx_dv; 947 tp = ccb->ccb_tx.tx_context; 948 twe_ccb_unmap(sc, ccb); 949 950 sc->sc_flags &= ~TWEF_AEN; 951 952 if (error) { 953 printf("%s: error retrieving AEN\n", sc->sc_dv.dv_xname); 954 aen = TWE_AEN_QUEUE_EMPTY; 955 } else 956 aen = le16toh(*(u_int16_t *)tp->tp_data); 957 free(tp, M_DEVBUF); 958 twe_ccb_free(sc, ccb); 959 960 if (TWE_AEN_CODE(aen) == TWE_AEN_QUEUE_EMPTY) { 961 twe_outl(sc, TWE_REG_CTL, TWE_CTL_CLEAR_ATTN_INTR); 962 return; 963 } 964 965 twe_aen_enqueue(sc, aen, 0); 966 967 /* 968 * Chain another retrieval in case interrupts have been 969 * coalesced. 970 */ 971 rv = twe_aen_get(sc, NULL); 972 if (rv != 0) 973 printf("%s: unable to retrieve AEN (%d)\n", 974 sc->sc_dv.dv_xname, rv); 975 } 976 977 static void 978 twe_aen_enqueue(struct twe_softc *sc, uint16_t aen, int quiet) 979 { 980 const char *str, *msg; 981 int s, next, nextnext, level; 982 983 /* 984 * First report the AEN on the console. Maybe. 985 */ 986 if (! quiet) { 987 str = twe_describe_code(twe_table_aen, TWE_AEN_CODE(aen)); 988 if (str == NULL) { 989 printf("%s: unknown AEN 0x%04x\n", 990 sc->sc_dv.dv_xname, aen); 991 } else { 992 msg = str + 3; 993 switch (str[1]) { 994 case 'E': level = LOG_EMERG; break; 995 case 'a': level = LOG_ALERT; break; 996 case 'c': level = LOG_CRIT; break; 997 case 'e': level = LOG_ERR; break; 998 case 'w': level = LOG_WARNING; break; 999 case 'n': level = LOG_NOTICE; break; 1000 case 'i': level = LOG_INFO; break; 1001 case 'd': level = LOG_DEBUG; break; 1002 default: 1003 /* Don't use syslog. */ 1004 level = -1; 1005 } 1006 1007 if (level < 0) { 1008 switch (str[0]) { 1009 case 'u': 1010 case 'p': 1011 printf("%s: %s %d: %s\n", 1012 sc->sc_dv.dv_xname, 1013 str[0] == 'u' ? "unit" : "port", 1014 TWE_AEN_UNIT(aen), msg); 1015 break; 1016 1017 default: 1018 printf("%s: %s\n", 1019 sc->sc_dv.dv_xname, msg); 1020 } 1021 } else { 1022 switch (str[0]) { 1023 case 'u': 1024 case 'p': 1025 log(level, "%s: %s %d: %s\n", 1026 sc->sc_dv.dv_xname, 1027 str[0] == 'u' ? "unit" : "port", 1028 TWE_AEN_UNIT(aen), msg); 1029 break; 1030 1031 default: 1032 log(level, "%s: %s\n", 1033 sc->sc_dv.dv_xname, msg); 1034 } 1035 } 1036 } 1037 } 1038 1039 /* Now enqueue the AEN for mangement tools. */ 1040 s = splbio(); 1041 1042 next = (sc->sc_aen_head + 1) % TWE_AEN_Q_LENGTH; 1043 nextnext = (sc->sc_aen_head + 2) % TWE_AEN_Q_LENGTH; 1044 1045 /* 1046 * If this is the last free slot, then queue up a "queue 1047 * full" message. 1048 */ 1049 if (nextnext == sc->sc_aen_tail) 1050 aen = TWE_AEN_QUEUE_FULL; 1051 1052 if (next != sc->sc_aen_tail) { 1053 sc->sc_aen_queue[sc->sc_aen_head] = aen; 1054 sc->sc_aen_head = next; 1055 } 1056 1057 if (sc->sc_flags & TWEF_AENQ_WAIT) { 1058 sc->sc_flags &= ~TWEF_AENQ_WAIT; 1059 wakeup(&sc->sc_aen_queue); 1060 } 1061 1062 splx(s); 1063 } 1064 1065 /* NOTE: Must be called at splbio(). */ 1066 static uint16_t 1067 twe_aen_dequeue(struct twe_softc *sc) 1068 { 1069 uint16_t aen; 1070 1071 if (sc->sc_aen_tail == sc->sc_aen_head) 1072 aen = TWE_AEN_QUEUE_EMPTY; 1073 else { 1074 aen = sc->sc_aen_queue[sc->sc_aen_tail]; 1075 sc->sc_aen_tail = (sc->sc_aen_tail + 1) % TWE_AEN_Q_LENGTH; 1076 } 1077 1078 return (aen); 1079 } 1080 1081 /* 1082 * These are short-hand functions that execute TWE_OP_GET_PARAM to 1083 * fetch 1, 2, and 4 byte parameter values, respectively. 1084 */ 1085 int 1086 twe_param_get_1(struct twe_softc *sc, int table_id, int param_id, 1087 uint8_t *valp) 1088 { 1089 struct twe_param *tp; 1090 int rv; 1091 1092 rv = twe_param_get(sc, table_id, param_id, 1, NULL, &tp); 1093 if (rv != 0) 1094 return (rv); 1095 *valp = *(uint8_t *)tp->tp_data; 1096 free(tp, M_DEVBUF); 1097 return (0); 1098 } 1099 1100 int 1101 twe_param_get_2(struct twe_softc *sc, int table_id, int param_id, 1102 uint16_t *valp) 1103 { 1104 struct twe_param *tp; 1105 int rv; 1106 1107 rv = twe_param_get(sc, table_id, param_id, 2, NULL, &tp); 1108 if (rv != 0) 1109 return (rv); 1110 *valp = le16toh(*(uint16_t *)tp->tp_data); 1111 free(tp, M_DEVBUF); 1112 return (0); 1113 } 1114 1115 int 1116 twe_param_get_4(struct twe_softc *sc, int table_id, int param_id, 1117 uint32_t *valp) 1118 { 1119 struct twe_param *tp; 1120 int rv; 1121 1122 rv = twe_param_get(sc, table_id, param_id, 4, NULL, &tp); 1123 if (rv != 0) 1124 return (rv); 1125 *valp = le32toh(*(uint32_t *)tp->tp_data); 1126 free(tp, M_DEVBUF); 1127 return (0); 1128 } 1129 1130 /* 1131 * Execute a TWE_OP_GET_PARAM command. If a callback function is provided, 1132 * it will be called with generated context when the command has completed. 1133 * If no callback is provided, the command will be executed synchronously 1134 * and a pointer to a buffer containing the data returned. 1135 * 1136 * The caller or callback is responsible for freeing the buffer. 1137 * 1138 * NOTE: We assume we can sleep here to wait for a CCB to become available. 1139 */ 1140 int 1141 twe_param_get(struct twe_softc *sc, int table_id, int param_id, size_t size, 1142 void (*func)(struct twe_ccb *, int), struct twe_param **pbuf) 1143 { 1144 struct twe_ccb *ccb; 1145 struct twe_cmd *tc; 1146 struct twe_param *tp; 1147 int rv, s; 1148 1149 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 1150 if (tp == NULL) 1151 return ENOMEM; 1152 1153 ccb = twe_ccb_alloc_wait(sc, TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1154 KASSERT(ccb != NULL); 1155 1156 ccb->ccb_data = tp; 1157 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1158 ccb->ccb_tx.tx_handler = func; 1159 ccb->ccb_tx.tx_context = tp; 1160 ccb->ccb_tx.tx_dv = &sc->sc_dv; 1161 1162 tc = ccb->ccb_cmd; 1163 tc->tc_size = 2; 1164 tc->tc_opcode = TWE_OP_GET_PARAM | (tc->tc_size << 5); 1165 tc->tc_unit = 0; 1166 tc->tc_count = htole16(1); 1167 1168 /* Fill in the outbound parameter data. */ 1169 tp->tp_table_id = htole16(table_id); 1170 tp->tp_param_id = param_id; 1171 tp->tp_param_size = size; 1172 1173 /* Map the transfer. */ 1174 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 1175 twe_ccb_free(sc, ccb); 1176 goto done; 1177 } 1178 1179 /* Submit the command and either wait or let the callback handle it. */ 1180 if (func == NULL) { 1181 s = splbio(); 1182 rv = twe_ccb_poll(sc, ccb, 5); 1183 twe_ccb_unmap(sc, ccb); 1184 twe_ccb_free(sc, ccb); 1185 splx(s); 1186 } else { 1187 #ifdef DEBUG 1188 if (pbuf != NULL) 1189 panic("both func and pbuf defined"); 1190 #endif 1191 twe_ccb_enqueue(sc, ccb); 1192 return 0; 1193 } 1194 1195 done: 1196 if (pbuf == NULL || rv != 0) 1197 free(tp, M_DEVBUF); 1198 else if (pbuf != NULL && rv == 0) 1199 *pbuf = tp; 1200 return rv; 1201 } 1202 1203 /* 1204 * Execute a TWE_OP_SET_PARAM command. 1205 * 1206 * NOTE: We assume we can sleep here to wait for a CCB to become available. 1207 */ 1208 static int 1209 twe_param_set(struct twe_softc *sc, int table_id, int param_id, size_t size, 1210 void *sbuf) 1211 { 1212 struct twe_ccb *ccb; 1213 struct twe_cmd *tc; 1214 struct twe_param *tp; 1215 int rv, s; 1216 1217 tp = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_NOWAIT); 1218 if (tp == NULL) 1219 return ENOMEM; 1220 1221 ccb = twe_ccb_alloc_wait(sc, TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1222 KASSERT(ccb != NULL); 1223 1224 ccb->ccb_data = tp; 1225 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1226 ccb->ccb_tx.tx_handler = 0; 1227 ccb->ccb_tx.tx_context = tp; 1228 ccb->ccb_tx.tx_dv = &sc->sc_dv; 1229 1230 tc = ccb->ccb_cmd; 1231 tc->tc_size = 2; 1232 tc->tc_opcode = TWE_OP_SET_PARAM | (tc->tc_size << 5); 1233 tc->tc_unit = 0; 1234 tc->tc_count = htole16(1); 1235 1236 /* Fill in the outbound parameter data. */ 1237 tp->tp_table_id = htole16(table_id); 1238 tp->tp_param_id = param_id; 1239 tp->tp_param_size = size; 1240 memcpy(tp->tp_data, sbuf, size); 1241 1242 /* Map the transfer. */ 1243 if ((rv = twe_ccb_map(sc, ccb)) != 0) { 1244 twe_ccb_free(sc, ccb); 1245 goto done; 1246 } 1247 1248 /* Submit the command and wait. */ 1249 s = splbio(); 1250 rv = twe_ccb_poll(sc, ccb, 5); 1251 twe_ccb_unmap(sc, ccb); 1252 twe_ccb_free(sc, ccb); 1253 splx(s); 1254 done: 1255 free(tp, M_DEVBUF); 1256 return (rv); 1257 } 1258 1259 /* 1260 * Execute a TWE_OP_INIT_CONNECTION command. Return non-zero on error. 1261 * Must be called with interrupts blocked. 1262 */ 1263 static int 1264 twe_init_connection(struct twe_softc *sc) 1265 /*###762 [cc] warning: `twe_init_connection' was used with no prototype before its definition%%%*/ 1266 /*###762 [cc] warning: `twe_init_connection' was declared implicitly `extern' and later `static'%%%*/ 1267 { 1268 struct twe_ccb *ccb; 1269 struct twe_cmd *tc; 1270 int rv; 1271 1272 if ((ccb = twe_ccb_alloc(sc, 0)) == NULL) 1273 return (EAGAIN); 1274 1275 /* Build the command. */ 1276 tc = ccb->ccb_cmd; 1277 tc->tc_size = 3; 1278 tc->tc_opcode = TWE_OP_INIT_CONNECTION; 1279 tc->tc_unit = 0; 1280 tc->tc_count = htole16(TWE_MAX_CMDS); 1281 tc->tc_args.init_connection.response_queue_pointer = 0; 1282 1283 /* Submit the command for immediate execution. */ 1284 rv = twe_ccb_poll(sc, ccb, 5); 1285 twe_ccb_free(sc, ccb); 1286 return (rv); 1287 } 1288 1289 /* 1290 * Poll the controller for completed commands. Must be called with 1291 * interrupts blocked. 1292 */ 1293 static void 1294 twe_poll(struct twe_softc *sc) 1295 { 1296 struct twe_ccb *ccb; 1297 int found; 1298 u_int status, cmdid; 1299 1300 found = 0; 1301 1302 for (;;) { 1303 status = twe_inl(sc, TWE_REG_STS); 1304 twe_status_check(sc, status); 1305 1306 if ((status & TWE_STS_RESP_QUEUE_EMPTY)) 1307 break; 1308 1309 found = 1; 1310 cmdid = twe_inl(sc, TWE_REG_RESP_QUEUE); 1311 cmdid = (cmdid & TWE_RESP_MASK) >> TWE_RESP_SHIFT; 1312 if (cmdid >= TWE_MAX_QUEUECNT) { 1313 printf("%s: bad cmdid %d\n", sc->sc_dv.dv_xname, cmdid); 1314 continue; 1315 } 1316 1317 ccb = sc->sc_ccbs + cmdid; 1318 if ((ccb->ccb_flags & TWE_CCB_ACTIVE) == 0) { 1319 printf("%s: CCB for cmdid %d not active\n", 1320 sc->sc_dv.dv_xname, cmdid); 1321 continue; 1322 } 1323 ccb->ccb_flags ^= TWE_CCB_COMPLETE | TWE_CCB_ACTIVE; 1324 1325 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1326 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, 1327 sizeof(struct twe_cmd), 1328 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1329 1330 /* Pass notification to upper layers. */ 1331 if (ccb->ccb_tx.tx_handler != NULL) 1332 (*ccb->ccb_tx.tx_handler)(ccb, 1333 ccb->ccb_cmd->tc_status != 0 ? EIO : 0); 1334 } 1335 1336 /* If any commands have completed, run the software queue. */ 1337 if (found) 1338 twe_ccb_enqueue(sc, NULL); 1339 } 1340 1341 /* 1342 * Wait for `status' to be set in the controller status register. Return 1343 * zero if found, non-zero if the operation timed out. 1344 */ 1345 static int 1346 twe_status_wait(struct twe_softc *sc, u_int32_t status, int timo) 1347 { 1348 1349 for (timo *= 10; timo != 0; timo--) { 1350 if ((twe_inl(sc, TWE_REG_STS) & status) == status) 1351 break; 1352 delay(100000); 1353 } 1354 1355 return (timo == 0); 1356 } 1357 1358 /* 1359 * Clear a PCI parity error. 1360 */ 1361 static void 1362 twe_clear_pci_parity_error(struct twe_softc *sc) 1363 { 1364 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x0, TWE_CTL_CLEAR_PARITY_ERROR); 1365 1366 //FreeBSD: pci_write_config(sc->twe_dev, PCIR_STATUS, TWE_PCI_CLEAR_PARITY_ERROR, 2); 1367 } 1368 1369 1370 /* 1371 * Clear a PCI abort. 1372 */ 1373 static void 1374 twe_clear_pci_abort(struct twe_softc *sc) 1375 { 1376 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x0, TWE_CTL_CLEAR_PCI_ABORT); 1377 1378 //FreeBSD: pci_write_config(sc->twe_dev, PCIR_STATUS, TWE_PCI_CLEAR_PCI_ABORT, 2); 1379 } 1380 1381 /* 1382 * Complain if the status bits aren't what we expect. 1383 */ 1384 static int 1385 twe_status_check(struct twe_softc *sc, u_int status) 1386 { 1387 int rv; 1388 1389 rv = 0; 1390 1391 if ((status & TWE_STS_EXPECTED_BITS) != TWE_STS_EXPECTED_BITS) { 1392 printf("%s: missing status bits: 0x%08x\n", sc->sc_dv.dv_xname, 1393 status & ~TWE_STS_EXPECTED_BITS); 1394 rv = -1; 1395 } 1396 1397 if ((status & TWE_STS_UNEXPECTED_BITS) != 0) { 1398 printf("%s: unexpected status bits: 0x%08x\n", 1399 sc->sc_dv.dv_xname, status & TWE_STS_UNEXPECTED_BITS); 1400 rv = -1; 1401 if (status & TWE_STS_PCI_PARITY_ERROR) { 1402 printf("%s: PCI parity error: Reseat card, move card " 1403 "or buggy device present.\n", 1404 sc->sc_dv.dv_xname); 1405 twe_clear_pci_parity_error(sc); 1406 } 1407 if (status & TWE_STS_PCI_ABORT) { 1408 printf("%s: PCI abort, clearing.\n", 1409 sc->sc_dv.dv_xname); 1410 twe_clear_pci_abort(sc); 1411 } 1412 } 1413 1414 return (rv); 1415 } 1416 1417 /* 1418 * Allocate and initialise a CCB. 1419 */ 1420 static __inline void 1421 twe_ccb_init(struct twe_softc *sc, struct twe_ccb *ccb, int flags) 1422 { 1423 struct twe_cmd *tc; 1424 1425 ccb->ccb_tx.tx_handler = NULL; 1426 ccb->ccb_flags = flags; 1427 tc = ccb->ccb_cmd; 1428 tc->tc_status = 0; 1429 tc->tc_flags = 0; 1430 tc->tc_cmdid = ccb->ccb_cmdid; 1431 } 1432 1433 struct twe_ccb * 1434 twe_ccb_alloc(struct twe_softc *sc, int flags) 1435 { 1436 struct twe_ccb *ccb; 1437 int s; 1438 1439 s = splbio(); 1440 if (__predict_false((flags & TWE_CCB_AEN) != 0)) { 1441 /* Use the reserved CCB. */ 1442 ccb = sc->sc_ccbs; 1443 } else { 1444 /* Allocate a CCB and command block. */ 1445 if (__predict_false((ccb = 1446 SLIST_FIRST(&sc->sc_ccb_freelist)) == NULL)) { 1447 splx(s); 1448 return (NULL); 1449 } 1450 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 1451 } 1452 #ifdef DIAGNOSTIC 1453 if ((long)(ccb - sc->sc_ccbs) == 0 && (flags & TWE_CCB_AEN) == 0) 1454 panic("twe_ccb_alloc: got reserved CCB for non-AEN"); 1455 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 1456 panic("twe_ccb_alloc: CCB %ld already allocated", 1457 (long)(ccb - sc->sc_ccbs)); 1458 flags |= TWE_CCB_ALLOCED; 1459 #endif 1460 splx(s); 1461 1462 twe_ccb_init(sc, ccb, flags); 1463 return (ccb); 1464 } 1465 1466 struct twe_ccb * 1467 twe_ccb_alloc_wait(struct twe_softc *sc, int flags) 1468 { 1469 struct twe_ccb *ccb; 1470 int s; 1471 1472 KASSERT((flags & TWE_CCB_AEN) == 0); 1473 1474 s = splbio(); 1475 while (__predict_false((ccb = 1476 SLIST_FIRST(&sc->sc_ccb_freelist)) == NULL)) { 1477 sc->sc_flags |= TWEF_WAIT_CCB; 1478 (void) tsleep(&sc->sc_ccb_freelist, PRIBIO, "tweccb", 0); 1479 } 1480 SLIST_REMOVE_HEAD(&sc->sc_ccb_freelist, ccb_chain.slist); 1481 #ifdef DIAGNOSTIC 1482 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) != 0) 1483 panic("twe_ccb_alloc_wait: CCB %ld already allocated", 1484 (long)(ccb - sc->sc_ccbs)); 1485 flags |= TWE_CCB_ALLOCED; 1486 #endif 1487 splx(s); 1488 1489 twe_ccb_init(sc, ccb, flags); 1490 return (ccb); 1491 } 1492 1493 /* 1494 * Free a CCB. 1495 */ 1496 void 1497 twe_ccb_free(struct twe_softc *sc, struct twe_ccb *ccb) 1498 { 1499 int s; 1500 1501 s = splbio(); 1502 if ((ccb->ccb_flags & TWE_CCB_AEN) == 0) { 1503 SLIST_INSERT_HEAD(&sc->sc_ccb_freelist, ccb, ccb_chain.slist); 1504 if (__predict_false((sc->sc_flags & TWEF_WAIT_CCB) != 0)) { 1505 sc->sc_flags &= ~TWEF_WAIT_CCB; 1506 wakeup(&sc->sc_ccb_freelist); 1507 } 1508 } 1509 ccb->ccb_flags = 0; 1510 splx(s); 1511 } 1512 1513 /* 1514 * Map the specified CCB's command block and data buffer (if any) into 1515 * controller visible space. Perform DMA synchronisation. 1516 */ 1517 int 1518 twe_ccb_map(struct twe_softc *sc, struct twe_ccb *ccb) 1519 { 1520 struct twe_cmd *tc; 1521 int flags, nsegs, i, s, rv; 1522 void *data; 1523 1524 /* 1525 * The data as a whole must be 512-byte aligned. 1526 */ 1527 if (((u_long)ccb->ccb_data & (TWE_ALIGNMENT - 1)) != 0) { 1528 s = splvm(); 1529 /* XXX */ 1530 ccb->ccb_abuf = uvm_km_alloc(kmem_map, 1531 ccb->ccb_datasize, 0, UVM_KMF_NOWAIT|UVM_KMF_WIRED); 1532 splx(s); 1533 data = (void *)ccb->ccb_abuf; 1534 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1535 memcpy(data, ccb->ccb_data, ccb->ccb_datasize); 1536 } else { 1537 ccb->ccb_abuf = (vaddr_t)0; 1538 data = ccb->ccb_data; 1539 } 1540 1541 /* 1542 * Map the data buffer into bus space and build the S/G list. 1543 */ 1544 rv = bus_dmamap_load(sc->sc_dmat, ccb->ccb_dmamap_xfer, data, 1545 ccb->ccb_datasize, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1546 ((ccb->ccb_flags & TWE_CCB_DATA_IN) ? 1547 BUS_DMA_READ : BUS_DMA_WRITE)); 1548 if (rv != 0) { 1549 if (ccb->ccb_abuf != (vaddr_t)0) { 1550 s = splvm(); 1551 /* XXX */ 1552 uvm_km_free(kmem_map, ccb->ccb_abuf, 1553 ccb->ccb_datasize, UVM_KMF_WIRED); 1554 splx(s); 1555 } 1556 return (rv); 1557 } 1558 1559 nsegs = ccb->ccb_dmamap_xfer->dm_nsegs; 1560 tc = ccb->ccb_cmd; 1561 tc->tc_size += 2 * nsegs; 1562 1563 /* The location of the S/G list is dependant upon command type. */ 1564 switch (tc->tc_opcode >> 5) { 1565 case 2: 1566 for (i = 0; i < nsegs; i++) { 1567 tc->tc_args.param.sgl[i].tsg_address = 1568 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 1569 tc->tc_args.param.sgl[i].tsg_length = 1570 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 1571 } 1572 /* XXX Needed? */ 1573 for (; i < TWE_SG_SIZE; i++) { 1574 tc->tc_args.param.sgl[i].tsg_address = 0; 1575 tc->tc_args.param.sgl[i].tsg_length = 0; 1576 } 1577 break; 1578 case 3: 1579 for (i = 0; i < nsegs; i++) { 1580 tc->tc_args.io.sgl[i].tsg_address = 1581 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_addr); 1582 tc->tc_args.io.sgl[i].tsg_length = 1583 htole32(ccb->ccb_dmamap_xfer->dm_segs[i].ds_len); 1584 } 1585 /* XXX Needed? */ 1586 for (; i < TWE_SG_SIZE; i++) { 1587 tc->tc_args.io.sgl[i].tsg_address = 0; 1588 tc->tc_args.io.sgl[i].tsg_length = 0; 1589 } 1590 break; 1591 default: 1592 /* 1593 * In all likelihood, this is a command passed from 1594 * management tools in userspace where no S/G list is 1595 * necessary because no data is being passed. 1596 */ 1597 break; 1598 } 1599 1600 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1601 flags = BUS_DMASYNC_PREREAD; 1602 else 1603 flags = 0; 1604 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1605 flags |= BUS_DMASYNC_PREWRITE; 1606 1607 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 1608 ccb->ccb_datasize, flags); 1609 return (0); 1610 } 1611 1612 /* 1613 * Unmap the specified CCB's command block and data buffer (if any) and 1614 * perform DMA synchronisation. 1615 */ 1616 void 1617 twe_ccb_unmap(struct twe_softc *sc, struct twe_ccb *ccb) 1618 { 1619 int flags, s; 1620 1621 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1622 flags = BUS_DMASYNC_POSTREAD; 1623 else 1624 flags = 0; 1625 if ((ccb->ccb_flags & TWE_CCB_DATA_OUT) != 0) 1626 flags |= BUS_DMASYNC_POSTWRITE; 1627 1628 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap_xfer, 0, 1629 ccb->ccb_datasize, flags); 1630 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap_xfer); 1631 1632 if (ccb->ccb_abuf != (vaddr_t)0) { 1633 if ((ccb->ccb_flags & TWE_CCB_DATA_IN) != 0) 1634 memcpy(ccb->ccb_data, (void *)ccb->ccb_abuf, 1635 ccb->ccb_datasize); 1636 s = splvm(); 1637 /* XXX */ 1638 uvm_km_free(kmem_map, ccb->ccb_abuf, ccb->ccb_datasize, 1639 UVM_KMF_WIRED); 1640 splx(s); 1641 } 1642 } 1643 1644 /* 1645 * Submit a command to the controller and poll on completion. Return 1646 * non-zero on timeout (but don't check status, as some command types don't 1647 * return status). Must be called with interrupts blocked. 1648 */ 1649 int 1650 twe_ccb_poll(struct twe_softc *sc, struct twe_ccb *ccb, int timo) 1651 { 1652 int rv; 1653 1654 if ((rv = twe_ccb_submit(sc, ccb)) != 0) 1655 return (rv); 1656 1657 for (timo *= 1000; timo != 0; timo--) { 1658 twe_poll(sc); 1659 if ((ccb->ccb_flags & TWE_CCB_COMPLETE) != 0) 1660 break; 1661 DELAY(100); 1662 } 1663 1664 return (timo == 0); 1665 } 1666 1667 /* 1668 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1669 * the order that they were enqueued and try to submit their command blocks 1670 * to the controller for execution. 1671 */ 1672 void 1673 twe_ccb_enqueue(struct twe_softc *sc, struct twe_ccb *ccb) 1674 { 1675 int s; 1676 1677 s = splbio(); 1678 1679 if (ccb != NULL) 1680 SIMPLEQ_INSERT_TAIL(&sc->sc_ccb_queue, ccb, ccb_chain.simpleq); 1681 1682 while ((ccb = SIMPLEQ_FIRST(&sc->sc_ccb_queue)) != NULL) { 1683 if (twe_ccb_submit(sc, ccb)) 1684 break; 1685 SIMPLEQ_REMOVE_HEAD(&sc->sc_ccb_queue, ccb_chain.simpleq); 1686 } 1687 1688 splx(s); 1689 } 1690 1691 /* 1692 * Submit the command block associated with the specified CCB to the 1693 * controller for execution. Must be called with interrupts blocked. 1694 */ 1695 int 1696 twe_ccb_submit(struct twe_softc *sc, struct twe_ccb *ccb) 1697 { 1698 bus_addr_t pa; 1699 int rv; 1700 u_int status; 1701 1702 /* Check to see if we can post a command. */ 1703 status = twe_inl(sc, TWE_REG_STS); 1704 twe_status_check(sc, status); 1705 1706 if ((status & TWE_STS_CMD_QUEUE_FULL) == 0) { 1707 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1708 (caddr_t)ccb->ccb_cmd - sc->sc_cmds, sizeof(struct twe_cmd), 1709 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1710 #ifdef DIAGNOSTIC 1711 if ((ccb->ccb_flags & TWE_CCB_ALLOCED) == 0) 1712 panic("%s: CCB %ld not ALLOCED\n", 1713 sc->sc_dv.dv_xname, (long)(ccb - sc->sc_ccbs)); 1714 #endif 1715 ccb->ccb_flags |= TWE_CCB_ACTIVE; 1716 pa = sc->sc_cmds_paddr + 1717 ccb->ccb_cmdid * sizeof(struct twe_cmd); 1718 twe_outl(sc, TWE_REG_CMD_QUEUE, (u_int32_t)pa); 1719 rv = 0; 1720 } else 1721 rv = EBUSY; 1722 1723 return (rv); 1724 } 1725 1726 1727 /* 1728 * Accept an open operation on the control device. 1729 */ 1730 static int 1731 tweopen(dev_t dev, int flag, int mode, struct proc *p) 1732 { 1733 struct twe_softc *twe; 1734 1735 if ((twe = device_lookup(&twe_cd, minor(dev))) == NULL) 1736 return (ENXIO); 1737 if ((twe->sc_flags & TWEF_OPEN) != 0) 1738 return (EBUSY); 1739 1740 twe->sc_flags |= TWEF_OPEN; 1741 return (0); 1742 } 1743 1744 /* 1745 * Accept the last close on the control device. 1746 */ 1747 static int 1748 tweclose(dev_t dev, int flag, int mode, struct proc *p) 1749 { 1750 struct twe_softc *twe; 1751 1752 twe = device_lookup(&twe_cd, minor(dev)); 1753 twe->sc_flags &= ~TWEF_OPEN; 1754 return (0); 1755 } 1756 1757 void 1758 twe_ccb_wait_handler(struct twe_ccb *ccb, int error) 1759 { 1760 1761 /* Just wake up the sleeper. */ 1762 wakeup(ccb); 1763 } 1764 1765 /* 1766 * Handle control operations. 1767 */ 1768 static int 1769 tweioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1770 { 1771 struct twe_softc *twe; 1772 struct twe_ccb *ccb; 1773 struct twe_param *param; 1774 struct twe_usercommand *tu; 1775 struct twe_paramcommand *tp; 1776 struct twe_drivecommand *td; 1777 void *pdata = NULL; 1778 int s, error = 0; 1779 u_int8_t cmdid; 1780 1781 if (securelevel >= 2) 1782 return (EPERM); 1783 1784 twe = device_lookup(&twe_cd, minor(dev)); 1785 tu = (struct twe_usercommand *)data; 1786 tp = (struct twe_paramcommand *)data; 1787 td = (struct twe_drivecommand *)data; 1788 1789 /* This is intended to be compatible with the FreeBSD interface. */ 1790 switch (cmd) { 1791 case TWEIO_COMMAND: 1792 /* XXX mutex */ 1793 if (tu->tu_size > 0) { 1794 /* 1795 * XXX Handle > TWE_SECTOR_SIZE? Let's see if 1796 * it's really necessary, first. 1797 */ 1798 if (tu->tu_size > TWE_SECTOR_SIZE) { 1799 #ifdef TWE_DEBUG 1800 printf("%s: TWEIO_COMMAND: tu_size = %d\n", 1801 twe->sc_dv.dv_xname, tu->tu_size); 1802 #endif 1803 return EINVAL; 1804 } 1805 pdata = malloc(TWE_SECTOR_SIZE, M_DEVBUF, M_WAITOK); 1806 error = copyin(tu->tu_data, pdata, tu->tu_size); 1807 if (error != 0) 1808 goto done; 1809 ccb = twe_ccb_alloc_wait(twe, 1810 TWE_CCB_DATA_IN | TWE_CCB_DATA_OUT); 1811 KASSERT(ccb != NULL); 1812 ccb->ccb_data = pdata; 1813 ccb->ccb_datasize = TWE_SECTOR_SIZE; 1814 } else { 1815 ccb = twe_ccb_alloc_wait(twe, 0); 1816 KASSERT(ccb != NULL); 1817 } 1818 1819 ccb->ccb_tx.tx_handler = twe_ccb_wait_handler; 1820 ccb->ccb_tx.tx_context = NULL; 1821 ccb->ccb_tx.tx_dv = &twe->sc_dv; 1822 1823 cmdid = ccb->ccb_cmdid; 1824 memcpy(ccb->ccb_cmd, &tu->tu_cmd, sizeof(struct twe_cmd)); 1825 ccb->ccb_cmd->tc_cmdid = cmdid; 1826 1827 /* Map the transfer. */ 1828 if ((error = twe_ccb_map(twe, ccb)) != 0) { 1829 twe_ccb_free(twe, ccb); 1830 goto done; 1831 } 1832 1833 /* Submit the command and wait up to 1 minute. */ 1834 error = 0; 1835 twe_ccb_enqueue(twe, ccb); 1836 s = splbio(); 1837 while ((ccb->ccb_flags & TWE_CCB_COMPLETE) == 0) 1838 if ((error = tsleep(ccb, PRIBIO, "tweioctl", 1839 60 * hz)) != 0) 1840 break; 1841 splx(s); 1842 1843 /* Copy the command back to the ioctl argument. */ 1844 memcpy(&tu->tu_cmd, ccb->ccb_cmd, sizeof(struct twe_cmd)); 1845 #ifdef TWE_DEBUG 1846 printf("%s: TWEIO_COMMAND: tc_opcode = 0x%02x, " 1847 "tc_status = 0x%02x\n", twe->sc_dv.dv_xname, 1848 tu->tu_cmd.tc_opcode, tu->tu_cmd.tc_status); 1849 #endif 1850 1851 s = splbio(); 1852 twe_ccb_free(twe, ccb); 1853 splx(s); 1854 1855 if (tu->tu_size > 0) 1856 error = copyout(pdata, tu->tu_data, tu->tu_size); 1857 goto done; 1858 1859 case TWEIO_STATS: 1860 return (ENOENT); 1861 1862 case TWEIO_AEN_POLL: 1863 s = splbio(); 1864 *(u_int *)data = twe_aen_dequeue(twe); 1865 splx(s); 1866 return (0); 1867 1868 case TWEIO_AEN_WAIT: 1869 s = splbio(); 1870 while ((*(u_int *)data = 1871 twe_aen_dequeue(twe)) == TWE_AEN_QUEUE_EMPTY) { 1872 twe->sc_flags |= TWEF_AENQ_WAIT; 1873 error = tsleep(&twe->sc_aen_queue, PRIBIO | PCATCH, 1874 "tweaen", 0); 1875 if (error == EINTR) { 1876 splx(s); 1877 return (error); 1878 } 1879 } 1880 splx(s); 1881 return (0); 1882 1883 case TWEIO_GET_PARAM: 1884 error = twe_param_get(twe, tp->tp_table_id, tp->tp_param_id, 1885 tp->tp_size, 0, ¶m); 1886 if (error != 0) 1887 return (error); 1888 if (param->tp_param_size > tp->tp_size) { 1889 error = EFAULT; 1890 goto done; 1891 } 1892 error = copyout(param->tp_data, tp->tp_data, 1893 param->tp_param_size); 1894 goto done; 1895 1896 case TWEIO_SET_PARAM: 1897 pdata = malloc(tp->tp_size, M_DEVBUF, M_WAITOK); 1898 if ((error = copyin(tp->tp_data, pdata, tp->tp_size)) != 0) 1899 goto done; 1900 error = twe_param_set(twe, tp->tp_table_id, tp->tp_param_id, 1901 tp->tp_size, pdata); 1902 goto done; 1903 1904 case TWEIO_RESET: 1905 s = splbio(); 1906 twe_reset(twe); 1907 splx(s); 1908 return (0); 1909 1910 case TWEIO_ADD_UNIT: 1911 /* XXX mutex */ 1912 return (twe_add_unit(twe, td->td_unit)); 1913 1914 case TWEIO_DEL_UNIT: 1915 /* XXX mutex */ 1916 return (twe_del_unit(twe, td->td_unit)); 1917 1918 default: 1919 return EINVAL; 1920 } 1921 done: 1922 if (pdata) 1923 free(pdata, M_DEVBUF); 1924 return error; 1925 } 1926 1927 const struct cdevsw twe_cdevsw = { 1928 tweopen, tweclose, noread, nowrite, tweioctl, 1929 nostop, notty, nopoll, nommap, 1930 }; 1931 1932 /* 1933 * Print some information about the controller 1934 */ 1935 static void 1936 twe_describe_controller(struct twe_softc *sc) 1937 { 1938 struct twe_param *p[6]; 1939 int i, rv = 0; 1940 uint32_t dsize; 1941 uint8_t ports; 1942 1943 /* get the port count */ 1944 rv |= twe_param_get_1(sc, TWE_PARAM_CONTROLLER, 1945 TWE_PARAM_CONTROLLER_PortCount, &ports); 1946 1947 /* get version strings */ 1948 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_Mon, 1949 16, NULL, &p[0]); 1950 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_FW, 1951 16, NULL, &p[1]); 1952 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_BIOS, 1953 16, NULL, &p[2]); 1954 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_PCB, 1955 8, NULL, &p[3]); 1956 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_ATA, 1957 8, NULL, &p[4]); 1958 rv |= twe_param_get(sc, TWE_PARAM_VERSION, TWE_PARAM_VERSION_PCI, 1959 8, NULL, &p[5]); 1960 1961 if (rv) { 1962 /* some error occurred */ 1963 aprint_error("%s: failed to fetch version information\n", 1964 sc->sc_dv.dv_xname); 1965 return; 1966 } 1967 1968 aprint_normal("%s: %d ports, Firmware %.16s, BIOS %.16s\n", 1969 sc->sc_dv.dv_xname, ports, 1970 p[1]->tp_data, p[2]->tp_data); 1971 1972 aprint_verbose("%s: Monitor %.16s, PCB %.8s, Achip %.8s, Pchip %.8s\n", 1973 sc->sc_dv.dv_xname, 1974 p[0]->tp_data, p[3]->tp_data, 1975 p[4]->tp_data, p[5]->tp_data); 1976 1977 free(p[0], M_DEVBUF); 1978 free(p[1], M_DEVBUF); 1979 free(p[2], M_DEVBUF); 1980 free(p[3], M_DEVBUF); 1981 free(p[4], M_DEVBUF); 1982 free(p[5], M_DEVBUF); 1983 1984 rv = twe_param_get(sc, TWE_PARAM_DRIVESUMMARY, 1985 TWE_PARAM_DRIVESUMMARY_Status, 16, NULL, &p[0]); 1986 if (rv) { 1987 aprint_error("%s: failed to get drive status summary\n", 1988 sc->sc_dv.dv_xname); 1989 return; 1990 } 1991 for (i = 0; i < ports; i++) { 1992 if (p[0]->tp_data[i] != TWE_PARAM_DRIVESTATUS_Present) 1993 continue; 1994 rv = twe_param_get_4(sc, TWE_PARAM_DRIVEINFO + i, 1995 TWE_PARAM_DRIVEINFO_Size, &dsize); 1996 if (rv) { 1997 aprint_error( 1998 "%s: unable to get drive size for port %d\n", 1999 sc->sc_dv.dv_xname, i); 2000 continue; 2001 } 2002 rv = twe_param_get(sc, TWE_PARAM_DRIVEINFO + i, 2003 TWE_PARAM_DRIVEINFO_Model, 40, NULL, &p[1]); 2004 if (rv) { 2005 aprint_error( 2006 "%s: unable to get drive model for port %d\n", 2007 sc->sc_dv.dv_xname, i); 2008 continue; 2009 } 2010 aprint_verbose("%s: port %d: %.40s %d MB\n", sc->sc_dv.dv_xname, 2011 i, p[1]->tp_data, dsize / 2048); 2012 free(p[1], M_DEVBUF); 2013 } 2014 free(p[0], M_DEVBUF); 2015 } 2016
Indexes created Mon Sep 22 13:09:51 GMT 2025