twereg.h revision 1.1
1 /* $NetBSD: twereg.h,v 1.1 2000/10/19 14:11:31 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: twereg.h,v 1.1 2000/05/24 23:35:23 msmith Exp 66 */ 67 68 #ifndef _PCI_TWEREG_H_ 69 #define _PCI_TWEREG_H_ 70 71 /* Board registers. */ 72 #define TWE_REG_CTL 0x00 73 #define TWE_REG_STS 0x04 74 #define TWE_REG_CMD_QUEUE 0x08 75 #define TWE_REG_RESP_QUEUE 0x0c 76 77 /* Control register bit definitions. */ 78 #define TWE_CTL_CLEAR_HOST_INTR 0x00080000 79 #define TWE_CTL_CLEAR_ATTN_INTR 0x00040000 80 #define TWE_CTL_MASK_CMD_INTR 0x00020000 81 #define TWE_CTL_MASK_RESP_INTR 0x00010000 82 #define TWE_CTL_UNMASK_CMD_INTR 0x00008000 83 #define TWE_CTL_UNMASK_RESP_INTR 0x00004000 84 #define TWE_CTL_CLEAR_ERROR_STS 0x00000200 85 #define TWE_CTL_ISSUE_SOFT_RESET 0x00000100 86 #define TWE_CTL_ENABLE_INTRS 0x00000080 87 #define TWE_CTL_DISABLE_INTRS 0x00000040 88 #define TWE_CTL_ISSUE_HOST_INTR 0x00000020 89 90 /* Status register bit definitions. */ 91 #define TWE_STS_MAJOR_VERSION_MASK 0xf0000000 92 #define TWE_STS_MINOR_VERSION_MASK 0x0f000000 93 #define TWE_STS_PCI_PARITY_ERROR 0x00800000 94 #define TWE_STS_QUEUE_ERROR 0x00400000 95 #define TWE_STS_MICROCONTROLLER_ERROR 0x00200000 96 #define TWE_STS_PCI_ABORT 0x00100000 97 #define TWE_STS_HOST_INTR 0x00080000 98 #define TWE_STS_ATTN_INTR 0x00040000 99 #define TWE_STS_CMD_INTR 0x00020000 100 #define TWE_STS_RESP_INTR 0x00010000 101 #define TWE_STS_CMD_QUEUE_FULL 0x00008000 102 #define TWE_STS_RESP_QUEUE_EMPTY 0x00004000 103 #define TWE_STS_MICROCONTROLLER_READY 0x00002000 104 #define TWE_STS_CMD_QUEUE_EMPTY 0x00001000 105 106 #define TWE_STS_ALL_INTRS 0x000f0000 107 #define TWE_STS_CLEARABLE_BITS 0x00d00000 108 #define TWE_STS_EXPECTED_BITS 0x00002000 109 #define TWE_STS_UNEXPECTED_BITS 0x00f80000 110 111 /* Command packet opcodes. */ 112 #define TWE_OP_NOP 0x00 113 #define TWE_OP_INIT_CONNECTION 0x01 114 #define TWE_OP_READ 0x02 115 #define TWE_OP_WRITE 0x03 116 #define TWE_OP_VERIFY 0x04 117 #define TWE_OP_GET_PARAM 0x12 118 #define TWE_OP_SET_PARAM 0x13 119 #define TWE_OP_SECTOR_INFO 0x1a 120 #define TWE_OP_AEN_LISTEN 0x1c 121 122 /* Asynchronous event notification (AEN) codes. */ 123 #define TWE_AEN_QUEUE_EMPTY 0x0000 124 #define TWE_AEN_SOFT_RESET 0x0001 125 #define TWE_AEN_DEGRADED_MIRROR 0x0002 126 #define TWE_AEN_CONTROLLER_ERROR 0x0003 127 #define TWE_AEN_REBUILD_FAIL 0x0004 128 #define TWE_AEN_REBUILD_DONE 0x0005 129 #define TWE_AEN_TABLE_UNDEFINED 0x0015 130 #define TWE_AEN_QUEUE_FULL 0x00ff 131 132 /* Response queue entries. Masking and shifting yields request ID. */ 133 #define TWE_RESP_MASK 0x00000ff0 134 #define TWE_RESP_SHIFT 4 135 136 /* Miscellenous constants. */ 137 #define TWE_ALIGNMENT 512 138 #define TWE_MAX_UNITS 16 139 #define TWE_INIT_MESSAGE_CREDITS 0x100 140 #define TWE_INIT_CMD_PACKET_SIZE 0x3 141 #define TWE_SG_SIZE 62 142 #define TWE_MAX_CMDS 256 143 #define TWE_Q_START 0 144 #define TWE_UNIT_INFORMATION_TABLE_BASE 0x300 145 #define TWE_IOCTL 0x80 146 #define TWE_MAX_AEN_TRIES 100 147 #define TWE_SECTOR_SIZE 512 148 149 /* Maximum transfer size. XXX This is an arbitrarily chosen value. */ 150 #define TWE_MAX_XFER 1048576 151 152 /* Scatter/gather block. */ 153 struct twe_sgb { 154 u_int32_t tsg_address; 155 u_int32_t tsg_length; 156 } __attribute__ ((packed)); 157 158 /* 159 * Command block. This is 512 (really 508) bytes in size, and must be 160 * aligned on a 512 byte boundary. 161 */ 162 struct twe_cmd { 163 u_int8_t tc_opcode; /* high 3 bits is S/G list offset */ 164 u_int8_t tc_size; 165 u_int8_t tc_cmdid; 166 u_int8_t tc_unit; /* high nybble is host ID */ 167 u_int8_t tc_status; 168 u_int8_t tc_flags; 169 u_int16_t tc_count; /* block & param count, msg credits */ 170 union { 171 struct { 172 u_int32_t lba; 173 struct twe_sgb sgl[TWE_SG_SIZE]; 174 } io __attribute__ ((packed)); 175 struct { 176 struct twe_sgb sgl[TWE_SG_SIZE]; 177 } param __attribute__ ((packed)); 178 struct { 179 u_int32_t response_queue_pointer; 180 } init_connection __attribute__ ((packed)); 181 } tc_args __attribute__ ((packed)); 182 int32_t tc_pad; 183 } __attribute__ ((packed)); 184 185 /* Get/set parameter block. */ 186 struct twe_param { 187 u_int16_t tp_table_id; 188 u_int8_t tp_param_id; 189 u_int8_t tp_param_size; 190 u_int8_t tp_data[1]; 191 } __attribute__ ((packed)); 192 193 #endif /* !_PCI_TWEREG_H_ */ 194
Indexes created Wed Sep 24 14:09:57 GMT 2025