ubsec.c revision 1.14
1 /* $NetBSD: ubsec.c,v 1.14 2007/12/11 11:25:53 lukem Exp $ */ 2 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.6 2003/01/23 21:06:43 sam Exp $ */ 3 /* $OpenBSD: ubsec.c,v 1.127 2003/06/04 14:04:58 jason Exp $ */ 4 5 /* 6 * Copyright (c) 2000 Jason L. Wright (jason (at) thought.net) 7 * Copyright (c) 2000 Theo de Raadt (deraadt (at) openbsd.org) 8 * Copyright (c) 2001 Patrik Lindergren (patrik (at) ipunplugged.com) 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Effort sponsored in part by the Defense Advanced Research Projects 32 * Agency (DARPA) and Air Force Research Laboratory, Air Force 33 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 34 * 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: ubsec.c,v 1.14 2007/12/11 11:25:53 lukem Exp $"); 39 40 #undef UBSEC_DEBUG 41 42 /* 43 * uBsec 5[56]01, bcm580xx, bcm582x hardware crypto accelerator 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/proc.h> 49 #include <sys/endian.h> 50 #ifdef __NetBSD__ 51 #define letoh16 htole16 52 #define letoh32 htole32 53 #define UBSEC_NO_RNG /* until statistically tested */ 54 #endif 55 #include <sys/errno.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/mbuf.h> 59 #include <sys/device.h> 60 #include <sys/queue.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <opencrypto/cryptodev.h> 65 #include <opencrypto/xform.h> 66 #ifdef __OpenBSD__ 67 #include <dev/rndvar.h> 68 #include <sys/md5k.h> 69 #else 70 #include <sys/rnd.h> 71 #include <sys/md5.h> 72 #endif 73 #include <sys/sha1.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/ubsecreg.h> 80 #include <dev/pci/ubsecvar.h> 81 82 /* 83 * Prototypes and count for the pci_device structure 84 */ 85 static int ubsec_probe(struct device *, struct cfdata *, void *); 86 static void ubsec_attach(struct device *, struct device *, void *); 87 static void ubsec_reset_board(struct ubsec_softc *); 88 static void ubsec_init_board(struct ubsec_softc *); 89 static void ubsec_init_pciregs(struct pci_attach_args *pa); 90 static void ubsec_cleanchip(struct ubsec_softc *); 91 static void ubsec_totalreset(struct ubsec_softc *); 92 static int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); 93 94 #ifdef __OpenBSD__ 95 struct cfattach ubsec_ca = { 96 sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 97 }; 98 99 struct cfdriver ubsec_cd = { 100 0, "ubsec", DV_DULL 101 }; 102 #else 103 CFATTACH_DECL(ubsec, sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 104 NULL, NULL); 105 extern struct cfdriver ubsec_cd; 106 #endif 107 108 /* patchable */ 109 #ifdef UBSEC_DEBUG 110 extern int ubsec_debug; 111 int ubsec_debug=1; 112 #endif 113 114 static int ubsec_intr(void *); 115 static int ubsec_newsession(void*, u_int32_t *, struct cryptoini *); 116 static int ubsec_freesession(void*, u_int64_t); 117 static int ubsec_process(void*, struct cryptop *, int hint); 118 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 119 static void ubsec_feed(struct ubsec_softc *); 120 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 121 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 122 static void ubsec_feed2(struct ubsec_softc *); 123 #ifndef UBSEC_NO_RNG 124 static void ubsec_rng(void *); 125 #endif /* UBSEC_NO_RNG */ 126 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 127 struct ubsec_dma_alloc *, int); 128 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 129 static int ubsec_dmamap_aligned(bus_dmamap_t); 130 131 static int ubsec_kprocess(void*, struct cryptkop *, int); 132 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, 133 struct cryptkop *, int); 134 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, 135 struct cryptkop *, int); 136 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, 137 struct cryptkop *, int); 138 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 139 static int ubsec_ksigbits(struct crparam *); 140 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 141 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 142 143 #ifdef UBSEC_DEBUG 144 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 145 static void ubsec_dump_mcr(struct ubsec_mcr *); 146 static void ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *); 147 #endif 148 149 #define READ_REG(sc,r) \ 150 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 151 152 #define WRITE_REG(sc,reg,val) \ 153 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 154 155 #define SWAP32(x) (x) = htole32(ntohl((x))) 156 #ifndef HTOLE32 157 #define HTOLE32(x) (x) = htole32(x) 158 #endif 159 160 struct ubsec_stats ubsecstats; 161 162 /* 163 * ubsec_maxbatch controls the number of crypto ops to voluntarily 164 * collect into one submission to the hardware. This batching happens 165 * when ops are dispatched from the crypto subsystem with a hint that 166 * more are to follow immediately. These ops must also not be marked 167 * with a ``no delay'' flag. 168 */ 169 static int ubsec_maxbatch = 1; 170 #ifdef SYSCTL_INT 171 SYSCTL_INT(_kern, OID_AUTO, ubsec_maxbatch, CTLFLAG_RW, &ubsec_maxbatch, 172 0, "Broadcom driver: max ops to batch w/o interrupt"); 173 #endif 174 175 /* 176 * ubsec_maxaggr controls the number of crypto ops to submit to the 177 * hardware as a unit. This aggregation reduces the number of interrupts 178 * to the host at the expense of increased latency (for all but the last 179 * operation). For network traffic setting this to one yields the highest 180 * performance but at the expense of more interrupt processing. 181 */ 182 static int ubsec_maxaggr = 1; 183 #ifdef SYSCTL_INT 184 SYSCTL_INT(_kern, OID_AUTO, ubsec_maxaggr, CTLFLAG_RW, &ubsec_maxaggr, 185 0, "Broadcom driver: max ops to aggregate under one interrupt"); 186 #endif 187 188 static const struct ubsec_product { 189 pci_vendor_id_t ubsec_vendor; 190 pci_product_id_t ubsec_product; 191 int ubsec_flags; 192 int ubsec_statmask; 193 const char *ubsec_name; 194 } ubsec_products[] = { 195 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5501, 196 0, 197 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 198 "Bluesteel 5501" 199 }, 200 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5601, 201 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 202 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 203 "Bluesteel 5601" 204 }, 205 206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5801, 207 0, 208 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 209 "Broadcom BCM5801" 210 }, 211 212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5802, 213 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 214 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 215 "Broadcom BCM5802" 216 }, 217 218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5805, 219 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 220 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 221 "Broadcom BCM5805" 222 }, 223 224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5820, 225 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 226 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 227 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 228 "Broadcom BCM5820" 229 }, 230 231 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5821, 232 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 233 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 234 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 235 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 236 "Broadcom BCM5821" 237 }, 238 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_SCA1K, 239 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 240 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 241 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 242 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 243 "Sun Crypto Accelerator 1000" 244 }, 245 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_5821, 246 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 247 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 248 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 249 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 250 "Broadcom BCM5821 (Sun)" 251 }, 252 253 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5822, 254 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 255 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 256 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 257 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 258 "Broadcom BCM5822" 259 }, 260 261 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5823, 262 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 263 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 264 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 265 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 266 "Broadcom BCM5823" 267 }, 268 269 { 0, 0, 270 0, 271 0, 272 NULL 273 } 274 }; 275 276 static const struct ubsec_product * 277 ubsec_lookup(const struct pci_attach_args *pa) 278 { 279 const struct ubsec_product *up; 280 281 for (up = ubsec_products; up->ubsec_name != NULL; up++) { 282 if (PCI_VENDOR(pa->pa_id) == up->ubsec_vendor && 283 PCI_PRODUCT(pa->pa_id) == up->ubsec_product) 284 return (up); 285 } 286 return (NULL); 287 } 288 289 static int 290 ubsec_probe(struct device *parent, struct cfdata *match, 291 void *aux) 292 { 293 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 294 295 if (ubsec_lookup(pa) != NULL) 296 return (1); 297 298 return (0); 299 } 300 301 static void 302 ubsec_attach(struct device *parent, struct device *self, void *aux) 303 { 304 struct ubsec_softc *sc = (struct ubsec_softc *)self; 305 struct pci_attach_args *pa = aux; 306 const struct ubsec_product *up; 307 pci_chipset_tag_t pc = pa->pa_pc; 308 pci_intr_handle_t ih; 309 const char *intrstr = NULL; 310 struct ubsec_dma *dmap; 311 u_int32_t cmd, i; 312 313 up = ubsec_lookup(pa); 314 if (up == NULL) { 315 printf("\n"); 316 panic("ubsec_attach: impossible"); 317 } 318 319 aprint_naive(": Crypto processor\n"); 320 aprint_normal(": %s, rev. %d\n", up->ubsec_name, 321 PCI_REVISION(pa->pa_class)); 322 323 SIMPLEQ_INIT(&sc->sc_queue); 324 SIMPLEQ_INIT(&sc->sc_qchip); 325 SIMPLEQ_INIT(&sc->sc_queue2); 326 SIMPLEQ_INIT(&sc->sc_qchip2); 327 SIMPLEQ_INIT(&sc->sc_q2free); 328 329 sc->sc_flags = up->ubsec_flags; 330 sc->sc_statmask = up->ubsec_statmask; 331 332 cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 333 cmd |= PCI_COMMAND_MASTER_ENABLE; 334 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, cmd); 335 336 if (pci_mapreg_map(pa, BS_BAR, PCI_MAPREG_TYPE_MEM, 0, 337 &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 338 aprint_error("%s: can't find mem space", 339 sc->sc_dv.dv_xname); 340 return; 341 } 342 343 sc->sc_dmat = pa->pa_dmat; 344 345 if (pci_intr_map(pa, &ih)) { 346 aprint_error("%s: couldn't map interrupt\n", 347 sc->sc_dv.dv_xname); 348 return; 349 } 350 intrstr = pci_intr_string(pc, ih); 351 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ubsec_intr, sc); 352 if (sc->sc_ih == NULL) { 353 aprint_error("%s: couldn't establish interrupt", 354 sc->sc_dv.dv_xname); 355 if (intrstr != NULL) 356 aprint_normal(" at %s", intrstr); 357 aprint_normal("\n"); 358 return; 359 } 360 aprint_normal("%s: interrupting at %s\n", sc->sc_dv.dv_xname, intrstr); 361 362 sc->sc_cid = crypto_get_driverid(0); 363 if (sc->sc_cid < 0) { 364 aprint_error("%s: couldn't get crypto driver id\n", 365 sc->sc_dv.dv_xname); 366 pci_intr_disestablish(pc, sc->sc_ih); 367 return; 368 } 369 370 SIMPLEQ_INIT(&sc->sc_freequeue); 371 dmap = sc->sc_dmaa; 372 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 373 struct ubsec_q *q; 374 375 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 376 M_DEVBUF, M_NOWAIT); 377 if (q == NULL) { 378 aprint_error("%s: can't allocate queue buffers\n", 379 sc->sc_dv.dv_xname); 380 break; 381 } 382 383 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 384 &dmap->d_alloc, 0)) { 385 aprint_error("%s: can't allocate dma buffers\n", 386 sc->sc_dv.dv_xname); 387 free(q, M_DEVBUF); 388 break; 389 } 390 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 391 392 q->q_dma = dmap; 393 sc->sc_queuea[i] = q; 394 395 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 396 } 397 398 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 399 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 400 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 401 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 402 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 403 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 404 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 405 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 406 407 /* 408 * Reset Broadcom chip 409 */ 410 ubsec_reset_board(sc); 411 412 /* 413 * Init Broadcom specific PCI settings 414 */ 415 ubsec_init_pciregs(pa); 416 417 /* 418 * Init Broadcom chip 419 */ 420 ubsec_init_board(sc); 421 422 #ifndef UBSEC_NO_RNG 423 if (sc->sc_flags & UBS_FLAGS_RNG) { 424 sc->sc_statmask |= BS_STAT_MCR2_DONE; 425 426 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 427 &sc->sc_rng.rng_q.q_mcr, 0)) 428 goto skip_rng; 429 430 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 431 &sc->sc_rng.rng_q.q_ctx, 0)) { 432 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 433 goto skip_rng; 434 } 435 436 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 437 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 438 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 439 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 440 goto skip_rng; 441 } 442 443 if (hz >= 100) 444 sc->sc_rnghz = hz / 100; 445 else 446 sc->sc_rnghz = 1; 447 #ifdef __OpenBSD__ 448 timeout_set(&sc->sc_rngto, ubsec_rng, sc); 449 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 450 #else 451 callout_init(&sc->sc_rngto, 0); 452 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 453 #endif 454 skip_rng: 455 if (sc->sc_rnghz) 456 aprint_normal("%s: random number generator enabled\n", 457 sc->sc_dv.dv_xname); 458 else 459 aprint_error("%s: WARNING: random number generator " 460 "disabled\n", sc->sc_dv.dv_xname); 461 } 462 #endif /* UBSEC_NO_RNG */ 463 464 if (sc->sc_flags & UBS_FLAGS_KEY) { 465 sc->sc_statmask |= BS_STAT_MCR2_DONE; 466 467 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 468 ubsec_kprocess, sc); 469 #if 0 470 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 471 ubsec_kprocess, sc); 472 #endif 473 } 474 } 475 476 /* 477 * UBSEC Interrupt routine 478 */ 479 static int 480 ubsec_intr(void *arg) 481 { 482 struct ubsec_softc *sc = arg; 483 volatile u_int32_t stat; 484 struct ubsec_q *q; 485 struct ubsec_dma *dmap; 486 int npkts = 0, i; 487 488 stat = READ_REG(sc, BS_STAT); 489 stat &= sc->sc_statmask; 490 if (stat == 0) { 491 return (0); 492 } 493 494 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 495 496 /* 497 * Check to see if we have any packets waiting for us 498 */ 499 if ((stat & BS_STAT_MCR1_DONE)) { 500 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 501 q = SIMPLEQ_FIRST(&sc->sc_qchip); 502 dmap = q->q_dma; 503 504 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 505 break; 506 507 q = SIMPLEQ_FIRST(&sc->sc_qchip); 508 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 509 510 npkts = q->q_nstacked_mcrs; 511 sc->sc_nqchip -= 1+npkts; 512 /* 513 * search for further sc_qchip ubsec_q's that share 514 * the same MCR, and complete them too, they must be 515 * at the top. 516 */ 517 for (i = 0; i < npkts; i++) { 518 if(q->q_stacked_mcr[i]) 519 ubsec_callback(sc, q->q_stacked_mcr[i]); 520 else 521 break; 522 } 523 ubsec_callback(sc, q); 524 } 525 526 /* 527 * Don't send any more packet to chip if there has been 528 * a DMAERR. 529 */ 530 if (!(stat & BS_STAT_DMAERR)) 531 ubsec_feed(sc); 532 } 533 534 /* 535 * Check to see if we have any key setups/rng's waiting for us 536 */ 537 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 538 (stat & BS_STAT_MCR2_DONE)) { 539 struct ubsec_q2 *q2; 540 struct ubsec_mcr *mcr; 541 542 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 543 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 544 545 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 546 0, q2->q_mcr.dma_map->dm_mapsize, 547 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 548 549 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 550 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 551 bus_dmamap_sync(sc->sc_dmat, 552 q2->q_mcr.dma_map, 0, 553 q2->q_mcr.dma_map->dm_mapsize, 554 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 555 break; 556 } 557 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 558 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, /*q2,*/ q_next); 559 ubsec_callback2(sc, q2); 560 /* 561 * Don't send any more packet to chip if there has been 562 * a DMAERR. 563 */ 564 if (!(stat & BS_STAT_DMAERR)) 565 ubsec_feed2(sc); 566 } 567 } 568 569 /* 570 * Check to see if we got any DMA Error 571 */ 572 if (stat & BS_STAT_DMAERR) { 573 #ifdef UBSEC_DEBUG 574 if (ubsec_debug) { 575 volatile u_int32_t a = READ_REG(sc, BS_ERR); 576 577 printf("%s: dmaerr %s@%08x\n", sc->sc_dv.dv_xname, 578 (a & BS_ERR_READ) ? "read" : "write", 579 a & BS_ERR_ADDR); 580 } 581 #endif /* UBSEC_DEBUG */ 582 ubsecstats.hst_dmaerr++; 583 ubsec_totalreset(sc); 584 ubsec_feed(sc); 585 } 586 587 if (sc->sc_needwakeup) { /* XXX check high watermark */ 588 int wkeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 589 #ifdef UBSEC_DEBUG 590 if (ubsec_debug) 591 printf("%s: wakeup crypto (%x)\n", sc->sc_dv.dv_xname, 592 sc->sc_needwakeup); 593 #endif /* UBSEC_DEBUG */ 594 sc->sc_needwakeup &= ~wkeup; 595 crypto_unblock(sc->sc_cid, wkeup); 596 } 597 return (1); 598 } 599 600 /* 601 * ubsec_feed() - aggregate and post requests to chip 602 * OpenBSD comments: 603 * It is assumed that the caller set splnet() 604 */ 605 static void 606 ubsec_feed(struct ubsec_softc *sc) 607 { 608 struct ubsec_q *q, *q2; 609 int npkts, i; 610 void *v; 611 u_int32_t stat; 612 #ifdef UBSEC_DEBUG 613 static int max; 614 #endif /* UBSEC_DEBUG */ 615 616 npkts = sc->sc_nqueue; 617 if (npkts > ubsecstats.hst_maxqueue) 618 ubsecstats.hst_maxqueue = npkts; 619 if (npkts < 2) 620 goto feed1; 621 622 /* 623 * Decide how many ops to combine in a single MCR. We cannot 624 * aggregate more than UBS_MAX_AGGR because this is the number 625 * of slots defined in the data structure. Otherwise we clamp 626 * based on the tunable parameter ubsec_maxaggr. Note that 627 * aggregation can happen in two ways: either by batching ops 628 * from above or because the h/w backs up and throttles us. 629 * Aggregating ops reduces the number of interrupts to the host 630 * but also (potentially) increases the latency for processing 631 * completed ops as we only get an interrupt when all aggregated 632 * ops have completed. 633 */ 634 if (npkts > UBS_MAX_AGGR) 635 npkts = UBS_MAX_AGGR; 636 if (npkts > ubsec_maxaggr) 637 npkts = ubsec_maxaggr; 638 if (npkts > ubsecstats.hst_maxbatch) 639 ubsecstats.hst_maxbatch = npkts; 640 if (npkts < 2) 641 goto feed1; 642 ubsecstats.hst_totbatch += npkts-1; 643 644 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 645 if (stat & BS_STAT_DMAERR) { 646 ubsec_totalreset(sc); 647 ubsecstats.hst_dmaerr++; 648 } else { 649 ubsecstats.hst_mcr1full++; 650 } 651 return; 652 } 653 654 #ifdef UBSEC_DEBUG 655 if (ubsec_debug) 656 printf("merging %d records\n", npkts); 657 /* XXX temporary aggregation statistics reporting code */ 658 if (max < npkts) { 659 max = npkts; 660 printf("%s: new max aggregate %d\n", sc->sc_dv.dv_xname, max); 661 } 662 #endif /* UBSEC_DEBUG */ 663 664 q = SIMPLEQ_FIRST(&sc->sc_queue); 665 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 666 --sc->sc_nqueue; 667 668 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 669 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 670 if (q->q_dst_map != NULL) 671 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 672 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 673 674 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 675 676 for (i = 0; i < q->q_nstacked_mcrs; i++) { 677 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 678 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 679 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 680 if (q2->q_dst_map != NULL) 681 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 682 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 683 q2= SIMPLEQ_FIRST(&sc->sc_queue); 684 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q2,*/ q_next); 685 --sc->sc_nqueue; 686 687 v = ((void *)&q2->q_dma->d_dma->d_mcr); 688 v = (char*)v + (sizeof(struct ubsec_mcr) - 689 sizeof(struct ubsec_mcr_add)); 690 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 691 q->q_stacked_mcr[i] = q2; 692 } 693 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 694 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 695 sc->sc_nqchip += npkts; 696 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 697 ubsecstats.hst_maxqchip = sc->sc_nqchip; 698 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 699 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 700 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 701 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 702 offsetof(struct ubsec_dmachunk, d_mcr)); 703 return; 704 705 feed1: 706 while (!SIMPLEQ_EMPTY(&sc->sc_queue)) { 707 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 708 if (stat & BS_STAT_DMAERR) { 709 ubsec_totalreset(sc); 710 ubsecstats.hst_dmaerr++; 711 } else { 712 ubsecstats.hst_mcr1full++; 713 } 714 break; 715 } 716 717 q = SIMPLEQ_FIRST(&sc->sc_queue); 718 719 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 720 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 721 if (q->q_dst_map != NULL) 722 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 723 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 724 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 725 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 726 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 727 728 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 729 offsetof(struct ubsec_dmachunk, d_mcr)); 730 #ifdef UBSEC_DEBUG 731 if (ubsec_debug) 732 printf("feed: q->chip %p %08x stat %08x\n", 733 q, (u_int32_t)q->q_dma->d_alloc.dma_paddr, 734 stat); 735 #endif /* UBSEC_DEBUG */ 736 q = SIMPLEQ_FIRST(&sc->sc_queue); 737 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 738 --sc->sc_nqueue; 739 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 740 sc->sc_nqchip++; 741 } 742 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 743 ubsecstats.hst_maxqchip = sc->sc_nqchip; 744 } 745 746 /* 747 * Allocate a new 'session' and return an encoded session id. 'sidp' 748 * contains our registration id, and should contain an encoded session 749 * id on successful allocation. 750 */ 751 static int 752 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 753 { 754 struct cryptoini *c, *encini = NULL, *macini = NULL; 755 struct ubsec_softc *sc; 756 struct ubsec_session *ses = NULL; 757 MD5_CTX md5ctx; 758 SHA1_CTX sha1ctx; 759 int i, sesn; 760 761 sc = arg; 762 KASSERT(sc != NULL /*, ("ubsec_newsession: null softc")*/); 763 764 if (sidp == NULL || cri == NULL || sc == NULL) 765 return (EINVAL); 766 767 for (c = cri; c != NULL; c = c->cri_next) { 768 if (c->cri_alg == CRYPTO_MD5_HMAC || 769 c->cri_alg == CRYPTO_SHA1_HMAC) { 770 if (macini) 771 return (EINVAL); 772 macini = c; 773 } else if (c->cri_alg == CRYPTO_DES_CBC || 774 c->cri_alg == CRYPTO_3DES_CBC) { 775 if (encini) 776 return (EINVAL); 777 encini = c; 778 } else 779 return (EINVAL); 780 } 781 if (encini == NULL && macini == NULL) 782 return (EINVAL); 783 784 if (sc->sc_sessions == NULL) { 785 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 786 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 787 if (ses == NULL) 788 return (ENOMEM); 789 sesn = 0; 790 sc->sc_nsessions = 1; 791 } else { 792 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 793 if (sc->sc_sessions[sesn].ses_used == 0) { 794 ses = &sc->sc_sessions[sesn]; 795 break; 796 } 797 } 798 799 if (ses == NULL) { 800 sesn = sc->sc_nsessions; 801 ses = (struct ubsec_session *)malloc((sesn + 1) * 802 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 803 if (ses == NULL) 804 return (ENOMEM); 805 bcopy(sc->sc_sessions, ses, sesn * 806 sizeof(struct ubsec_session)); 807 bzero(sc->sc_sessions, sesn * 808 sizeof(struct ubsec_session)); 809 free(sc->sc_sessions, M_DEVBUF); 810 sc->sc_sessions = ses; 811 ses = &sc->sc_sessions[sesn]; 812 sc->sc_nsessions++; 813 } 814 } 815 816 bzero(ses, sizeof(struct ubsec_session)); 817 ses->ses_used = 1; 818 if (encini) { 819 /* get an IV, network byte order */ 820 #ifdef __NetBSD__ 821 rnd_extract_data(ses->ses_iv, 822 sizeof(ses->ses_iv), RND_EXTRACT_ANY); 823 #else 824 get_random_bytes(ses->ses_iv, sizeof(ses->ses_iv)); 825 #endif 826 827 /* Go ahead and compute key in ubsec's byte order */ 828 if (encini->cri_alg == CRYPTO_DES_CBC) { 829 bcopy(encini->cri_key, &ses->ses_deskey[0], 8); 830 bcopy(encini->cri_key, &ses->ses_deskey[2], 8); 831 bcopy(encini->cri_key, &ses->ses_deskey[4], 8); 832 } else 833 bcopy(encini->cri_key, ses->ses_deskey, 24); 834 835 SWAP32(ses->ses_deskey[0]); 836 SWAP32(ses->ses_deskey[1]); 837 SWAP32(ses->ses_deskey[2]); 838 SWAP32(ses->ses_deskey[3]); 839 SWAP32(ses->ses_deskey[4]); 840 SWAP32(ses->ses_deskey[5]); 841 } 842 843 if (macini) { 844 for (i = 0; i < macini->cri_klen / 8; i++) 845 macini->cri_key[i] ^= HMAC_IPAD_VAL; 846 847 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 848 MD5Init(&md5ctx); 849 MD5Update(&md5ctx, macini->cri_key, 850 macini->cri_klen / 8); 851 MD5Update(&md5ctx, hmac_ipad_buffer, 852 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 853 bcopy(md5ctx.state, ses->ses_hminner, 854 sizeof(md5ctx.state)); 855 } else { 856 SHA1Init(&sha1ctx); 857 SHA1Update(&sha1ctx, macini->cri_key, 858 macini->cri_klen / 8); 859 SHA1Update(&sha1ctx, hmac_ipad_buffer, 860 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 861 bcopy(sha1ctx.state, ses->ses_hminner, 862 sizeof(sha1ctx.state)); 863 } 864 865 for (i = 0; i < macini->cri_klen / 8; i++) 866 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 867 868 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 869 MD5Init(&md5ctx); 870 MD5Update(&md5ctx, macini->cri_key, 871 macini->cri_klen / 8); 872 MD5Update(&md5ctx, hmac_opad_buffer, 873 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 874 bcopy(md5ctx.state, ses->ses_hmouter, 875 sizeof(md5ctx.state)); 876 } else { 877 SHA1Init(&sha1ctx); 878 SHA1Update(&sha1ctx, macini->cri_key, 879 macini->cri_klen / 8); 880 SHA1Update(&sha1ctx, hmac_opad_buffer, 881 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 882 bcopy(sha1ctx.state, ses->ses_hmouter, 883 sizeof(sha1ctx.state)); 884 } 885 886 for (i = 0; i < macini->cri_klen / 8; i++) 887 macini->cri_key[i] ^= HMAC_OPAD_VAL; 888 } 889 890 *sidp = UBSEC_SID(device_unit(&sc->sc_dv), sesn); 891 return (0); 892 } 893 894 /* 895 * Deallocate a session. 896 */ 897 static int 898 ubsec_freesession(void *arg, u_int64_t tid) 899 { 900 struct ubsec_softc *sc; 901 int session; 902 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 903 904 sc = arg; 905 KASSERT(sc != NULL /*, ("ubsec_freesession: null softc")*/); 906 907 session = UBSEC_SESSION(sid); 908 if (session >= sc->sc_nsessions) 909 return (EINVAL); 910 911 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 912 return (0); 913 } 914 915 #ifdef __FreeBSD__ /* Ugly gratuitous changes to bus_dma */ 916 static void 917 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 918 { 919 struct ubsec_operand *op = arg; 920 921 KASSERT(nsegs <= UBS_MAX_SCATTER 922 /*, ("Too many DMA segments returned when mapping operand")*/); 923 #ifdef UBSEC_DEBUG 924 if (ubsec_debug) 925 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 926 (u_int) mapsize, nsegs); 927 #endif 928 op->mapsize = mapsize; 929 op->nsegs = nsegs; 930 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 931 } 932 #endif 933 934 static int 935 ubsec_process(void *arg, struct cryptop *crp, int hint) 936 { 937 struct ubsec_q *q = NULL; 938 #ifdef __OpenBSD__ 939 int card; 940 #endif 941 int err = 0, i, j, s, nicealign; 942 struct ubsec_softc *sc; 943 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 944 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 945 int sskip, dskip, stheend, dtheend; 946 int16_t coffset; 947 struct ubsec_session *ses; 948 struct ubsec_pktctx ctx; 949 struct ubsec_dma *dmap = NULL; 950 951 sc = arg; 952 KASSERT(sc != NULL /*, ("ubsec_process: null softc")*/); 953 954 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 955 ubsecstats.hst_invalid++; 956 return (EINVAL); 957 } 958 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 959 ubsecstats.hst_badsession++; 960 return (EINVAL); 961 } 962 963 s = splnet(); 964 965 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 966 ubsecstats.hst_queuefull++; 967 sc->sc_needwakeup |= CRYPTO_SYMQ; 968 splx(s); 969 return(ERESTART); 970 } 971 972 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 973 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, /*q,*/ q_next); 974 splx(s); 975 976 dmap = q->q_dma; /* Save dma pointer */ 977 bzero(q, sizeof(struct ubsec_q)); 978 bzero(&ctx, sizeof(ctx)); 979 980 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 981 q->q_dma = dmap; 982 ses = &sc->sc_sessions[q->q_sesn]; 983 984 if (crp->crp_flags & CRYPTO_F_IMBUF) { 985 q->q_src_m = (struct mbuf *)crp->crp_buf; 986 q->q_dst_m = (struct mbuf *)crp->crp_buf; 987 } else if (crp->crp_flags & CRYPTO_F_IOV) { 988 q->q_src_io = (struct uio *)crp->crp_buf; 989 q->q_dst_io = (struct uio *)crp->crp_buf; 990 } else { 991 ubsecstats.hst_badflags++; 992 err = EINVAL; 993 goto errout; /* XXX we don't handle contiguous blocks! */ 994 } 995 996 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 997 998 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 999 dmap->d_dma->d_mcr.mcr_flags = 0; 1000 q->q_crp = crp; 1001 1002 crd1 = crp->crp_desc; 1003 if (crd1 == NULL) { 1004 ubsecstats.hst_nodesc++; 1005 err = EINVAL; 1006 goto errout; 1007 } 1008 crd2 = crd1->crd_next; 1009 1010 if (crd2 == NULL) { 1011 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 1012 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 1013 maccrd = crd1; 1014 enccrd = NULL; 1015 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1016 crd1->crd_alg == CRYPTO_3DES_CBC) { 1017 maccrd = NULL; 1018 enccrd = crd1; 1019 } else { 1020 ubsecstats.hst_badalg++; 1021 err = EINVAL; 1022 goto errout; 1023 } 1024 } else { 1025 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1026 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1027 (crd2->crd_alg == CRYPTO_DES_CBC || 1028 crd2->crd_alg == CRYPTO_3DES_CBC) && 1029 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1030 maccrd = crd1; 1031 enccrd = crd2; 1032 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1033 crd1->crd_alg == CRYPTO_3DES_CBC) && 1034 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1035 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1036 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1037 enccrd = crd1; 1038 maccrd = crd2; 1039 } else { 1040 /* 1041 * We cannot order the ubsec as requested 1042 */ 1043 ubsecstats.hst_badalg++; 1044 err = EINVAL; 1045 goto errout; 1046 } 1047 } 1048 1049 if (enccrd) { 1050 encoffset = enccrd->crd_skip; 1051 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1052 1053 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1054 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1055 1056 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1057 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1058 else { 1059 ctx.pc_iv[0] = ses->ses_iv[0]; 1060 ctx.pc_iv[1] = ses->ses_iv[1]; 1061 } 1062 1063 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1064 if (crp->crp_flags & CRYPTO_F_IMBUF) 1065 m_copyback(q->q_src_m, 1066 enccrd->crd_inject, 1067 8, (void *)ctx.pc_iv); 1068 else if (crp->crp_flags & CRYPTO_F_IOV) 1069 cuio_copyback(q->q_src_io, 1070 enccrd->crd_inject, 1071 8, (void *)ctx.pc_iv); 1072 } 1073 } else { 1074 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1075 1076 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1077 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1078 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1079 m_copydata(q->q_src_m, enccrd->crd_inject, 1080 8, (void *)ctx.pc_iv); 1081 else if (crp->crp_flags & CRYPTO_F_IOV) 1082 cuio_copydata(q->q_src_io, 1083 enccrd->crd_inject, 8, 1084 (void *)ctx.pc_iv); 1085 } 1086 1087 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1088 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1089 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1090 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1091 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1092 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1093 SWAP32(ctx.pc_iv[0]); 1094 SWAP32(ctx.pc_iv[1]); 1095 } 1096 1097 if (maccrd) { 1098 macoffset = maccrd->crd_skip; 1099 1100 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1101 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1102 else 1103 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1104 1105 for (i = 0; i < 5; i++) { 1106 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1107 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1108 1109 HTOLE32(ctx.pc_hminner[i]); 1110 HTOLE32(ctx.pc_hmouter[i]); 1111 } 1112 } 1113 1114 if (enccrd && maccrd) { 1115 /* 1116 * ubsec cannot handle packets where the end of encryption 1117 * and authentication are not the same, or where the 1118 * encrypted part begins before the authenticated part. 1119 */ 1120 if ((encoffset + enccrd->crd_len) != 1121 (macoffset + maccrd->crd_len)) { 1122 ubsecstats.hst_lenmismatch++; 1123 err = EINVAL; 1124 goto errout; 1125 } 1126 if (enccrd->crd_skip < maccrd->crd_skip) { 1127 ubsecstats.hst_skipmismatch++; 1128 err = EINVAL; 1129 goto errout; 1130 } 1131 sskip = maccrd->crd_skip; 1132 cpskip = dskip = enccrd->crd_skip; 1133 stheend = maccrd->crd_len; 1134 dtheend = enccrd->crd_len; 1135 coffset = enccrd->crd_skip - maccrd->crd_skip; 1136 cpoffset = cpskip + dtheend; 1137 #ifdef UBSEC_DEBUG 1138 if (ubsec_debug) { 1139 printf("mac: skip %d, len %d, inject %d\n", 1140 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1141 printf("enc: skip %d, len %d, inject %d\n", 1142 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1143 printf("src: skip %d, len %d\n", sskip, stheend); 1144 printf("dst: skip %d, len %d\n", dskip, dtheend); 1145 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1146 coffset, stheend, cpskip, cpoffset); 1147 } 1148 #endif 1149 } else { 1150 cpskip = dskip = sskip = macoffset + encoffset; 1151 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1152 cpoffset = cpskip + dtheend; 1153 coffset = 0; 1154 } 1155 ctx.pc_offset = htole16(coffset >> 2); 1156 1157 /* XXX FIXME: jonathan asks, what the heck's that 0xfff0? */ 1158 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, 1159 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { 1160 err = ENOMEM; 1161 goto errout; 1162 } 1163 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1164 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1165 q->q_src_m, BUS_DMA_NOWAIT) != 0) { 1166 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1167 q->q_src_map = NULL; 1168 ubsecstats.hst_noload++; 1169 err = ENOMEM; 1170 goto errout; 1171 } 1172 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1173 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1174 q->q_src_io, BUS_DMA_NOWAIT) != 0) { 1175 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1176 q->q_src_map = NULL; 1177 ubsecstats.hst_noload++; 1178 err = ENOMEM; 1179 goto errout; 1180 } 1181 } 1182 nicealign = ubsec_dmamap_aligned(q->q_src_map); 1183 1184 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1185 1186 #ifdef UBSEC_DEBUG 1187 if (ubsec_debug) 1188 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1189 #endif 1190 for (i = j = 0; i < q->q_src_map->dm_nsegs; i++) { 1191 struct ubsec_pktbuf *pb; 1192 bus_size_t packl = q->q_src_map->dm_segs[i].ds_len; 1193 bus_addr_t packp = q->q_src_map->dm_segs[i].ds_addr; 1194 1195 if (sskip >= packl) { 1196 sskip -= packl; 1197 continue; 1198 } 1199 1200 packl -= sskip; 1201 packp += sskip; 1202 sskip = 0; 1203 1204 if (packl > 0xfffc) { 1205 err = EIO; 1206 goto errout; 1207 } 1208 1209 if (j == 0) 1210 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1211 else 1212 pb = &dmap->d_dma->d_sbuf[j - 1]; 1213 1214 pb->pb_addr = htole32(packp); 1215 1216 if (stheend) { 1217 if (packl > stheend) { 1218 pb->pb_len = htole32(stheend); 1219 stheend = 0; 1220 } else { 1221 pb->pb_len = htole32(packl); 1222 stheend -= packl; 1223 } 1224 } else 1225 pb->pb_len = htole32(packl); 1226 1227 if ((i + 1) == q->q_src_map->dm_nsegs) 1228 pb->pb_next = 0; 1229 else 1230 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1231 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1232 j++; 1233 } 1234 1235 if (enccrd == NULL && maccrd != NULL) { 1236 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1237 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1238 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1239 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1240 #ifdef UBSEC_DEBUG 1241 if (ubsec_debug) 1242 printf("opkt: %x %x %x\n", 1243 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1244 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1245 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1246 1247 #endif 1248 } else { 1249 if (crp->crp_flags & CRYPTO_F_IOV) { 1250 if (!nicealign) { 1251 ubsecstats.hst_iovmisaligned++; 1252 err = EINVAL; 1253 goto errout; 1254 } 1255 /* XXX: ``what the heck's that'' 0xfff0? */ 1256 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, 1257 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, 1258 &q->q_dst_map) != 0) { 1259 ubsecstats.hst_nomap++; 1260 err = ENOMEM; 1261 goto errout; 1262 } 1263 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1264 q->q_dst_io, BUS_DMA_NOWAIT) != 0) { 1265 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1266 q->q_dst_map = NULL; 1267 ubsecstats.hst_noload++; 1268 err = ENOMEM; 1269 goto errout; 1270 } 1271 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1272 if (nicealign) { 1273 q->q_dst_m = q->q_src_m; 1274 q->q_dst_map = q->q_src_map; 1275 } else { 1276 int totlen, len; 1277 struct mbuf *m, *top, **mp; 1278 1279 ubsecstats.hst_unaligned++; 1280 totlen = q->q_src_map->dm_mapsize; 1281 if (q->q_src_m->m_flags & M_PKTHDR) { 1282 len = MHLEN; 1283 MGETHDR(m, M_DONTWAIT, MT_DATA); 1284 /*XXX FIXME: m_dup_pkthdr */ 1285 if (m && 1 /*!m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)*/) { 1286 m_free(m); 1287 m = NULL; 1288 } 1289 } else { 1290 len = MLEN; 1291 MGET(m, M_DONTWAIT, MT_DATA); 1292 } 1293 if (m == NULL) { 1294 ubsecstats.hst_nombuf++; 1295 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1296 goto errout; 1297 } 1298 if (len == MHLEN) 1299 /*XXX was M_DUP_PKTHDR*/ 1300 M_COPY_PKTHDR(m, q->q_src_m); 1301 if (totlen >= MINCLSIZE) { 1302 MCLGET(m, M_DONTWAIT); 1303 if ((m->m_flags & M_EXT) == 0) { 1304 m_free(m); 1305 ubsecstats.hst_nomcl++; 1306 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1307 goto errout; 1308 } 1309 len = MCLBYTES; 1310 } 1311 m->m_len = len; 1312 top = NULL; 1313 mp = ⊤ 1314 1315 while (totlen > 0) { 1316 if (top) { 1317 MGET(m, M_DONTWAIT, MT_DATA); 1318 if (m == NULL) { 1319 m_freem(top); 1320 ubsecstats.hst_nombuf++; 1321 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1322 goto errout; 1323 } 1324 len = MLEN; 1325 } 1326 if (top && totlen >= MINCLSIZE) { 1327 MCLGET(m, M_DONTWAIT); 1328 if ((m->m_flags & M_EXT) == 0) { 1329 *mp = m; 1330 m_freem(top); 1331 ubsecstats.hst_nomcl++; 1332 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1333 goto errout; 1334 } 1335 len = MCLBYTES; 1336 } 1337 m->m_len = len = min(totlen, len); 1338 totlen -= len; 1339 *mp = m; 1340 mp = &m->m_next; 1341 } 1342 q->q_dst_m = top; 1343 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1344 cpskip, cpoffset); 1345 /* XXX again, what the heck is that 0xfff0? */ 1346 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, 1347 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, 1348 &q->q_dst_map) != 0) { 1349 ubsecstats.hst_nomap++; 1350 err = ENOMEM; 1351 goto errout; 1352 } 1353 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1354 q->q_dst_map, q->q_dst_m, 1355 BUS_DMA_NOWAIT) != 0) { 1356 bus_dmamap_destroy(sc->sc_dmat, 1357 q->q_dst_map); 1358 q->q_dst_map = NULL; 1359 ubsecstats.hst_noload++; 1360 err = ENOMEM; 1361 goto errout; 1362 } 1363 } 1364 } else { 1365 ubsecstats.hst_badflags++; 1366 err = EINVAL; 1367 goto errout; 1368 } 1369 1370 #ifdef UBSEC_DEBUG 1371 if (ubsec_debug) 1372 printf("dst skip: %d\n", dskip); 1373 #endif 1374 for (i = j = 0; i < q->q_dst_map->dm_nsegs; i++) { 1375 struct ubsec_pktbuf *pb; 1376 bus_size_t packl = q->q_dst_map->dm_segs[i].ds_len; 1377 bus_addr_t packp = q->q_dst_map->dm_segs[i].ds_addr; 1378 1379 if (dskip >= packl) { 1380 dskip -= packl; 1381 continue; 1382 } 1383 1384 packl -= dskip; 1385 packp += dskip; 1386 dskip = 0; 1387 1388 if (packl > 0xfffc) { 1389 err = EIO; 1390 goto errout; 1391 } 1392 1393 if (j == 0) 1394 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1395 else 1396 pb = &dmap->d_dma->d_dbuf[j - 1]; 1397 1398 pb->pb_addr = htole32(packp); 1399 1400 if (dtheend) { 1401 if (packl > dtheend) { 1402 pb->pb_len = htole32(dtheend); 1403 dtheend = 0; 1404 } else { 1405 pb->pb_len = htole32(packl); 1406 dtheend -= packl; 1407 } 1408 } else 1409 pb->pb_len = htole32(packl); 1410 1411 if ((i + 1) == q->q_dst_map->dm_nsegs) { 1412 if (maccrd) 1413 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1414 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1415 else 1416 pb->pb_next = 0; 1417 } else 1418 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1419 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1420 j++; 1421 } 1422 } 1423 1424 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1425 offsetof(struct ubsec_dmachunk, d_ctx)); 1426 1427 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1428 struct ubsec_pktctx_long *ctxl; 1429 1430 ctxl = (struct ubsec_pktctx_long *)((char *)dmap->d_alloc.dma_vaddr + 1431 offsetof(struct ubsec_dmachunk, d_ctx)); 1432 1433 /* transform small context into long context */ 1434 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1435 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1436 ctxl->pc_flags = ctx.pc_flags; 1437 ctxl->pc_offset = ctx.pc_offset; 1438 for (i = 0; i < 6; i++) 1439 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1440 for (i = 0; i < 5; i++) 1441 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1442 for (i = 0; i < 5; i++) 1443 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1444 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1445 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1446 } else 1447 memcpy((char *)dmap->d_alloc.dma_vaddr + 1448 offsetof(struct ubsec_dmachunk, d_ctx), &ctx, 1449 sizeof(struct ubsec_pktctx)); 1450 1451 s = splnet(); 1452 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1453 sc->sc_nqueue++; 1454 ubsecstats.hst_ipackets++; 1455 ubsecstats.hst_ibytes += dmap->d_alloc.dma_map->dm_mapsize; 1456 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= ubsec_maxbatch) 1457 ubsec_feed(sc); 1458 splx(s); 1459 return (0); 1460 1461 errout: 1462 if (q != NULL) { 1463 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1464 m_freem(q->q_dst_m); 1465 1466 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1467 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1468 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1469 } 1470 if (q->q_src_map != NULL) { 1471 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1472 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1473 } 1474 1475 s = splnet(); 1476 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1477 splx(s); 1478 } 1479 #if 0 /* jonathan says: this openbsd code seems to be subsumed elsewhere */ 1480 if (err == EINVAL) 1481 ubsecstats.hst_invalid++; 1482 else 1483 ubsecstats.hst_nomem++; 1484 #endif 1485 if (err != ERESTART) { 1486 crp->crp_etype = err; 1487 crypto_done(crp); 1488 } else { 1489 sc->sc_needwakeup |= CRYPTO_SYMQ; 1490 } 1491 return (err); 1492 } 1493 1494 static void 1495 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1496 { 1497 struct cryptop *crp = (struct cryptop *)q->q_crp; 1498 struct cryptodesc *crd; 1499 struct ubsec_dma *dmap = q->q_dma; 1500 1501 ubsecstats.hst_opackets++; 1502 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1503 1504 bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, 1505 dmap->d_alloc.dma_map->dm_mapsize, 1506 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1507 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1508 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1509 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1510 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1511 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1512 } 1513 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 1514 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1515 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1516 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1517 1518 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1519 m_freem(q->q_src_m); 1520 crp->crp_buf = (void *)q->q_dst_m; 1521 } 1522 1523 /* copy out IV for future use */ 1524 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1525 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1526 if (crd->crd_alg != CRYPTO_DES_CBC && 1527 crd->crd_alg != CRYPTO_3DES_CBC) 1528 continue; 1529 if (crp->crp_flags & CRYPTO_F_IMBUF) 1530 m_copydata((struct mbuf *)crp->crp_buf, 1531 crd->crd_skip + crd->crd_len - 8, 8, 1532 (void *)sc->sc_sessions[q->q_sesn].ses_iv); 1533 else if (crp->crp_flags & CRYPTO_F_IOV) { 1534 cuio_copydata((struct uio *)crp->crp_buf, 1535 crd->crd_skip + crd->crd_len - 8, 8, 1536 (void *)sc->sc_sessions[q->q_sesn].ses_iv); 1537 } 1538 break; 1539 } 1540 } 1541 1542 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1543 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1544 crd->crd_alg != CRYPTO_SHA1_HMAC) 1545 continue; 1546 if (crp->crp_flags & CRYPTO_F_IMBUF) 1547 m_copyback((struct mbuf *)crp->crp_buf, 1548 crd->crd_inject, 12, 1549 (void *)dmap->d_dma->d_macbuf); 1550 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1551 bcopy((void *)dmap->d_dma->d_macbuf, 1552 crp->crp_mac, 12); 1553 break; 1554 } 1555 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1556 crypto_done(crp); 1557 } 1558 1559 static void 1560 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1561 { 1562 int i, j, dlen, slen; 1563 char *dptr, *sptr; 1564 1565 j = 0; 1566 sptr = srcm->m_data; 1567 slen = srcm->m_len; 1568 dptr = dstm->m_data; 1569 dlen = dstm->m_len; 1570 1571 while (1) { 1572 for (i = 0; i < min(slen, dlen); i++) { 1573 if (j < hoffset || j >= toffset) 1574 *dptr++ = *sptr++; 1575 slen--; 1576 dlen--; 1577 j++; 1578 } 1579 if (slen == 0) { 1580 srcm = srcm->m_next; 1581 if (srcm == NULL) 1582 return; 1583 sptr = srcm->m_data; 1584 slen = srcm->m_len; 1585 } 1586 if (dlen == 0) { 1587 dstm = dstm->m_next; 1588 if (dstm == NULL) 1589 return; 1590 dptr = dstm->m_data; 1591 dlen = dstm->m_len; 1592 } 1593 } 1594 } 1595 1596 /* 1597 * feed the key generator, must be called at splnet() or higher. 1598 */ 1599 static void 1600 ubsec_feed2(struct ubsec_softc *sc) 1601 { 1602 struct ubsec_q2 *q; 1603 1604 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1605 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1606 break; 1607 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1608 1609 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1610 q->q_mcr.dma_map->dm_mapsize, 1611 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1612 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1613 q->q_ctx.dma_map->dm_mapsize, 1614 BUS_DMASYNC_PREWRITE); 1615 1616 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1617 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1618 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, /*q,*/ q_next); 1619 --sc->sc_nqueue2; 1620 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1621 } 1622 } 1623 1624 /* 1625 * Callback for handling random numbers 1626 */ 1627 static void 1628 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1629 { 1630 struct cryptkop *krp; 1631 struct ubsec_ctx_keyop *ctx; 1632 1633 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1634 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1635 q->q_ctx.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1636 1637 switch (q->q_type) { 1638 #ifndef UBSEC_NO_RNG 1639 case UBS_CTXOP_RNGSHA1: 1640 case UBS_CTXOP_RNGBYPASS: { 1641 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1642 u_int32_t *p; 1643 int i; 1644 1645 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 1646 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1647 p = (u_int32_t *)rng->rng_buf.dma_vaddr; 1648 #ifndef __NetBSD__ 1649 for (i = 0; i < UBSEC_RNG_BUFSIZ; p++, i++) 1650 add_true_randomness(letoh32(*p)); 1651 rng->rng_used = 0; 1652 #else 1653 /* XXX NetBSD rnd subsystem too weak */ 1654 i = 0; (void)i; /* shut off gcc warnings */ 1655 #endif 1656 #ifdef __OpenBSD__ 1657 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 1658 #else 1659 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1660 #endif 1661 break; 1662 } 1663 #endif 1664 case UBS_CTXOP_MODEXP: { 1665 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1666 u_int rlen, clen; 1667 1668 krp = me->me_krp; 1669 rlen = (me->me_modbits + 7) / 8; 1670 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1671 1672 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 1673 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1674 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 1675 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1676 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 1677 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1678 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 1679 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1680 1681 if (clen < rlen) 1682 krp->krp_status = E2BIG; 1683 else { 1684 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1685 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1686 (krp->krp_param[krp->krp_iparams].crp_nbits 1687 + 7) / 8); 1688 bcopy(me->me_C.dma_vaddr, 1689 krp->krp_param[krp->krp_iparams].crp_p, 1690 (me->me_modbits + 7) / 8); 1691 } else 1692 ubsec_kshift_l(me->me_shiftbits, 1693 me->me_C.dma_vaddr, me->me_normbits, 1694 krp->krp_param[krp->krp_iparams].crp_p, 1695 krp->krp_param[krp->krp_iparams].crp_nbits); 1696 } 1697 1698 crypto_kdone(krp); 1699 1700 /* bzero all potentially sensitive data */ 1701 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1702 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1703 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1704 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1705 1706 /* Can't free here, so put us on the free list. */ 1707 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1708 break; 1709 } 1710 case UBS_CTXOP_RSAPRIV: { 1711 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1712 u_int len; 1713 1714 krp = rp->rpr_krp; 1715 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 0, 1716 rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1717 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 0, 1718 rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1719 1720 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1721 bcopy(rp->rpr_msgout.dma_vaddr, 1722 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1723 1724 crypto_kdone(krp); 1725 1726 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1727 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1728 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1729 1730 /* Can't free here, so put us on the free list. */ 1731 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1732 break; 1733 } 1734 default: 1735 printf("%s: unknown ctx op: %x\n", sc->sc_dv.dv_xname, 1736 letoh16(ctx->ctx_op)); 1737 break; 1738 } 1739 } 1740 1741 #ifndef UBSEC_NO_RNG 1742 static void 1743 ubsec_rng(void *vsc) 1744 { 1745 struct ubsec_softc *sc = vsc; 1746 struct ubsec_q2_rng *rng = &sc->sc_rng; 1747 struct ubsec_mcr *mcr; 1748 struct ubsec_ctx_rngbypass *ctx; 1749 int s; 1750 1751 s = splnet(); 1752 if (rng->rng_used) { 1753 splx(s); 1754 return; 1755 } 1756 sc->sc_nqueue2++; 1757 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1758 goto out; 1759 1760 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1761 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1762 1763 mcr->mcr_pkts = htole16(1); 1764 mcr->mcr_flags = 0; 1765 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1766 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1767 mcr->mcr_ipktbuf.pb_len = 0; 1768 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1769 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1770 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1771 UBS_PKTBUF_LEN); 1772 mcr->mcr_opktbuf.pb_next = 0; 1773 1774 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1775 ctx->rbp_op = htole16(UBS_CTXOP_RNGSHA1); 1776 rng->rng_q.q_type = UBS_CTXOP_RNGSHA1; 1777 1778 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 1779 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1780 1781 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1782 rng->rng_used = 1; 1783 ubsec_feed2(sc); 1784 ubsecstats.hst_rng++; 1785 splx(s); 1786 1787 return; 1788 1789 out: 1790 /* 1791 * Something weird happened, generate our own call back. 1792 */ 1793 sc->sc_nqueue2--; 1794 splx(s); 1795 #ifdef __OpenBSD__ 1796 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 1797 #else 1798 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1799 #endif 1800 } 1801 #endif /* UBSEC_NO_RNG */ 1802 1803 static int 1804 ubsec_dma_malloc(struct ubsec_softc *sc, bus_size_t size, 1805 struct ubsec_dma_alloc *dma,int mapflags) 1806 { 1807 int r; 1808 1809 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1810 &dma->dma_seg, 1, &dma->dma_nseg, BUS_DMA_NOWAIT)) != 0) 1811 goto fail_0; 1812 1813 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1814 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1815 goto fail_1; 1816 1817 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1818 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1819 goto fail_2; 1820 1821 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1822 size, NULL, BUS_DMA_NOWAIT)) != 0) 1823 goto fail_3; 1824 1825 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1826 dma->dma_size = size; 1827 return (0); 1828 1829 fail_3: 1830 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1831 fail_2: 1832 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1833 fail_1: 1834 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1835 fail_0: 1836 dma->dma_map = NULL; 1837 return (r); 1838 } 1839 1840 static void 1841 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1842 { 1843 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1844 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 1845 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1846 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1847 } 1848 1849 /* 1850 * Resets the board. Values in the regesters are left as is 1851 * from the reset (i.e. initial values are assigned elsewhere). 1852 */ 1853 static void 1854 ubsec_reset_board(struct ubsec_softc *sc) 1855 { 1856 volatile u_int32_t ctrl; 1857 1858 ctrl = READ_REG(sc, BS_CTRL); 1859 ctrl |= BS_CTRL_RESET; 1860 WRITE_REG(sc, BS_CTRL, ctrl); 1861 1862 /* 1863 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1864 */ 1865 DELAY(10); 1866 } 1867 1868 /* 1869 * Init Broadcom registers 1870 */ 1871 static void 1872 ubsec_init_board(struct ubsec_softc *sc) 1873 { 1874 u_int32_t ctrl; 1875 1876 ctrl = READ_REG(sc, BS_CTRL); 1877 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1878 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1879 1880 /* 1881 * XXX: Sam Leffler's code has (UBS_FLAGS_KEY|UBS_FLAGS_RNG)). 1882 * anyone got hw docs? 1883 */ 1884 if (sc->sc_flags & UBS_FLAGS_KEY) 1885 ctrl |= BS_CTRL_MCR2INT; 1886 else 1887 ctrl &= ~BS_CTRL_MCR2INT; 1888 1889 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1890 ctrl &= ~BS_CTRL_SWNORM; 1891 1892 WRITE_REG(sc, BS_CTRL, ctrl); 1893 } 1894 1895 /* 1896 * Init Broadcom PCI registers 1897 */ 1898 static void 1899 ubsec_init_pciregs(struct pci_attach_args *pa) 1900 { 1901 pci_chipset_tag_t pc = pa->pa_pc; 1902 u_int32_t misc; 1903 1904 /* 1905 * This will set the cache line size to 1, this will 1906 * force the BCM58xx chip just to do burst read/writes. 1907 * Cache line read/writes are to slow 1908 */ 1909 misc = pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 1910 misc = (misc & ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)) 1911 | ((UBS_DEF_CACHELINE & 0xff) << PCI_CACHELINE_SHIFT); 1912 pci_conf_write(pc, pa->pa_tag, PCI_BHLC_REG, misc); 1913 } 1914 1915 /* 1916 * Clean up after a chip crash. 1917 * It is assumed that the caller in splnet() 1918 */ 1919 static void 1920 ubsec_cleanchip(struct ubsec_softc *sc) 1921 { 1922 struct ubsec_q *q; 1923 1924 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 1925 q = SIMPLEQ_FIRST(&sc->sc_qchip); 1926 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 1927 ubsec_free_q(sc, q); 1928 } 1929 sc->sc_nqchip = 0; 1930 } 1931 1932 /* 1933 * free a ubsec_q 1934 * It is assumed that the caller is within splnet() 1935 */ 1936 static int 1937 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 1938 { 1939 struct ubsec_q *q2; 1940 struct cryptop *crp; 1941 int npkts; 1942 int i; 1943 1944 npkts = q->q_nstacked_mcrs; 1945 1946 for (i = 0; i < npkts; i++) { 1947 if(q->q_stacked_mcr[i]) { 1948 q2 = q->q_stacked_mcr[i]; 1949 1950 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 1951 m_freem(q2->q_dst_m); 1952 1953 crp = (struct cryptop *)q2->q_crp; 1954 1955 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 1956 1957 crp->crp_etype = EFAULT; 1958 crypto_done(crp); 1959 } else { 1960 break; 1961 } 1962 } 1963 1964 /* 1965 * Free header MCR 1966 */ 1967 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1968 m_freem(q->q_dst_m); 1969 1970 crp = (struct cryptop *)q->q_crp; 1971 1972 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1973 1974 crp->crp_etype = EFAULT; 1975 crypto_done(crp); 1976 return(0); 1977 } 1978 1979 /* 1980 * Routine to reset the chip and clean up. 1981 * It is assumed that the caller is in splnet() 1982 */ 1983 static void 1984 ubsec_totalreset(struct ubsec_softc *sc) 1985 { 1986 ubsec_reset_board(sc); 1987 ubsec_init_board(sc); 1988 ubsec_cleanchip(sc); 1989 } 1990 1991 static int 1992 ubsec_dmamap_aligned(bus_dmamap_t map) 1993 { 1994 int i; 1995 1996 for (i = 0; i < map->dm_nsegs; i++) { 1997 if (map->dm_segs[i].ds_addr & 3) 1998 return (0); 1999 if ((i != (map->dm_nsegs - 1)) && 2000 (map->dm_segs[i].ds_len & 3)) 2001 return (0); 2002 } 2003 return (1); 2004 } 2005 2006 #ifdef __OpenBSD__ 2007 struct ubsec_softc * 2008 ubsec_kfind(struct cryptkop *krp) 2009 { 2010 struct ubsec_softc *sc; 2011 int i; 2012 2013 for (i = 0; i < ubsec_cd.cd_ndevs; i++) { 2014 sc = ubsec_cd.cd_devs[i]; 2015 if (sc == NULL) 2016 continue; 2017 if (sc->sc_cid == krp->krp_hid) 2018 return (sc); 2019 } 2020 return (NULL); 2021 } 2022 #endif 2023 2024 static void 2025 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2026 { 2027 switch (q->q_type) { 2028 case UBS_CTXOP_MODEXP: { 2029 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2030 2031 ubsec_dma_free(sc, &me->me_q.q_mcr); 2032 ubsec_dma_free(sc, &me->me_q.q_ctx); 2033 ubsec_dma_free(sc, &me->me_M); 2034 ubsec_dma_free(sc, &me->me_E); 2035 ubsec_dma_free(sc, &me->me_C); 2036 ubsec_dma_free(sc, &me->me_epb); 2037 free(me, M_DEVBUF); 2038 break; 2039 } 2040 case UBS_CTXOP_RSAPRIV: { 2041 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2042 2043 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2044 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2045 ubsec_dma_free(sc, &rp->rpr_msgin); 2046 ubsec_dma_free(sc, &rp->rpr_msgout); 2047 free(rp, M_DEVBUF); 2048 break; 2049 } 2050 default: 2051 printf("%s: invalid kfree 0x%x\n", sc->sc_dv.dv_xname, 2052 q->q_type); 2053 break; 2054 } 2055 } 2056 2057 static int 2058 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2059 { 2060 struct ubsec_softc *sc; 2061 int r; 2062 2063 if (krp == NULL || krp->krp_callback == NULL) 2064 return (EINVAL); 2065 #ifdef __OpenBSD__ 2066 if ((sc = ubsec_kfind(krp)) == NULL) 2067 return (EINVAL); 2068 #else 2069 sc = arg; 2070 KASSERT(sc != NULL /*, ("ubsec_kprocess: null softc")*/); 2071 #endif 2072 2073 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2074 struct ubsec_q2 *q; 2075 2076 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2077 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, /*q,*/ q_next); 2078 ubsec_kfree(sc, q); 2079 } 2080 2081 switch (krp->krp_op) { 2082 case CRK_MOD_EXP: 2083 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2084 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2085 else 2086 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2087 break; 2088 case CRK_MOD_EXP_CRT: 2089 r = ubsec_kprocess_rsapriv(sc, krp, hint); 2090 break; 2091 default: 2092 printf("%s: kprocess: invalid op 0x%x\n", 2093 sc->sc_dv.dv_xname, krp->krp_op); 2094 krp->krp_status = EOPNOTSUPP; 2095 crypto_kdone(krp); 2096 r = 0; 2097 } 2098 return (r); 2099 } 2100 2101 /* 2102 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2103 */ 2104 static int 2105 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, 2106 int hint) 2107 { 2108 struct ubsec_q2_modexp *me; 2109 struct ubsec_mcr *mcr; 2110 struct ubsec_ctx_modexp *ctx; 2111 struct ubsec_pktbuf *epb; 2112 int s, err = 0; 2113 u_int nbits, normbits, mbits, shiftbits, ebits; 2114 2115 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2116 if (me == NULL) { 2117 err = ENOMEM; 2118 goto errout; 2119 } 2120 bzero(me, sizeof *me); 2121 me->me_krp = krp; 2122 me->me_q.q_type = UBS_CTXOP_MODEXP; 2123 2124 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2125 if (nbits <= 512) 2126 normbits = 512; 2127 else if (nbits <= 768) 2128 normbits = 768; 2129 else if (nbits <= 1024) 2130 normbits = 1024; 2131 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2132 normbits = 1536; 2133 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2134 normbits = 2048; 2135 else { 2136 err = E2BIG; 2137 goto errout; 2138 } 2139 2140 shiftbits = normbits - nbits; 2141 2142 me->me_modbits = nbits; 2143 me->me_shiftbits = shiftbits; 2144 me->me_normbits = normbits; 2145 2146 /* Sanity check: result bits must be >= true modulus bits. */ 2147 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2148 err = ERANGE; 2149 goto errout; 2150 } 2151 2152 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2153 &me->me_q.q_mcr, 0)) { 2154 err = ENOMEM; 2155 goto errout; 2156 } 2157 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2158 2159 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2160 &me->me_q.q_ctx, 0)) { 2161 err = ENOMEM; 2162 goto errout; 2163 } 2164 2165 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2166 if (mbits > nbits) { 2167 err = E2BIG; 2168 goto errout; 2169 } 2170 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2171 err = ENOMEM; 2172 goto errout; 2173 } 2174 ubsec_kshift_r(shiftbits, 2175 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2176 me->me_M.dma_vaddr, normbits); 2177 2178 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2179 err = ENOMEM; 2180 goto errout; 2181 } 2182 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2183 2184 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2185 if (ebits > nbits) { 2186 err = E2BIG; 2187 goto errout; 2188 } 2189 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2190 err = ENOMEM; 2191 goto errout; 2192 } 2193 ubsec_kshift_r(shiftbits, 2194 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2195 me->me_E.dma_vaddr, normbits); 2196 2197 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2198 &me->me_epb, 0)) { 2199 err = ENOMEM; 2200 goto errout; 2201 } 2202 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2203 epb->pb_addr = htole32(me->me_E.dma_paddr); 2204 epb->pb_next = 0; 2205 epb->pb_len = htole32(normbits / 8); 2206 2207 #ifdef UBSEC_DEBUG 2208 if (ubsec_debug) { 2209 printf("Epb "); 2210 ubsec_dump_pb(epb); 2211 } 2212 #endif 2213 2214 mcr->mcr_pkts = htole16(1); 2215 mcr->mcr_flags = 0; 2216 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2217 mcr->mcr_reserved = 0; 2218 mcr->mcr_pktlen = 0; 2219 2220 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2221 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2222 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2223 2224 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2225 mcr->mcr_opktbuf.pb_next = 0; 2226 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2227 2228 #ifdef DIAGNOSTIC 2229 /* Misaligned output buffer will hang the chip. */ 2230 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2231 panic("%s: modexp invalid addr 0x%x", 2232 sc->sc_dv.dv_xname, letoh32(mcr->mcr_opktbuf.pb_addr)); 2233 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2234 panic("%s: modexp invalid len 0x%x", 2235 sc->sc_dv.dv_xname, letoh32(mcr->mcr_opktbuf.pb_len)); 2236 #endif 2237 2238 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2239 bzero(ctx, sizeof(*ctx)); 2240 ubsec_kshift_r(shiftbits, 2241 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2242 ctx->me_N, normbits); 2243 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2244 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2245 ctx->me_E_len = htole16(nbits); 2246 ctx->me_N_len = htole16(nbits); 2247 2248 #ifdef UBSEC_DEBUG 2249 if (ubsec_debug) { 2250 ubsec_dump_mcr(mcr); 2251 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2252 } 2253 #endif 2254 2255 /* 2256 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2257 * everything else. 2258 */ 2259 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2260 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2261 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2262 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2263 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2264 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2265 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2266 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2267 2268 /* Enqueue and we're done... */ 2269 s = splnet(); 2270 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2271 ubsec_feed2(sc); 2272 ubsecstats.hst_modexp++; 2273 splx(s); 2274 2275 return (0); 2276 2277 errout: 2278 if (me != NULL) { 2279 if (me->me_q.q_mcr.dma_map != NULL) 2280 ubsec_dma_free(sc, &me->me_q.q_mcr); 2281 if (me->me_q.q_ctx.dma_map != NULL) { 2282 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2283 ubsec_dma_free(sc, &me->me_q.q_ctx); 2284 } 2285 if (me->me_M.dma_map != NULL) { 2286 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2287 ubsec_dma_free(sc, &me->me_M); 2288 } 2289 if (me->me_E.dma_map != NULL) { 2290 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2291 ubsec_dma_free(sc, &me->me_E); 2292 } 2293 if (me->me_C.dma_map != NULL) { 2294 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2295 ubsec_dma_free(sc, &me->me_C); 2296 } 2297 if (me->me_epb.dma_map != NULL) 2298 ubsec_dma_free(sc, &me->me_epb); 2299 free(me, M_DEVBUF); 2300 } 2301 krp->krp_status = err; 2302 crypto_kdone(krp); 2303 return (0); 2304 } 2305 2306 /* 2307 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2308 */ 2309 static int 2310 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, 2311 int hint) 2312 { 2313 struct ubsec_q2_modexp *me; 2314 struct ubsec_mcr *mcr; 2315 struct ubsec_ctx_modexp *ctx; 2316 struct ubsec_pktbuf *epb; 2317 int s, err = 0; 2318 u_int nbits, normbits, mbits, shiftbits, ebits; 2319 2320 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2321 if (me == NULL) { 2322 err = ENOMEM; 2323 goto errout; 2324 } 2325 bzero(me, sizeof *me); 2326 me->me_krp = krp; 2327 me->me_q.q_type = UBS_CTXOP_MODEXP; 2328 2329 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2330 if (nbits <= 512) 2331 normbits = 512; 2332 else if (nbits <= 768) 2333 normbits = 768; 2334 else if (nbits <= 1024) 2335 normbits = 1024; 2336 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2337 normbits = 1536; 2338 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2339 normbits = 2048; 2340 else { 2341 err = E2BIG; 2342 goto errout; 2343 } 2344 2345 shiftbits = normbits - nbits; 2346 2347 /* XXX ??? */ 2348 me->me_modbits = nbits; 2349 me->me_shiftbits = shiftbits; 2350 me->me_normbits = normbits; 2351 2352 /* Sanity check: result bits must be >= true modulus bits. */ 2353 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2354 err = ERANGE; 2355 goto errout; 2356 } 2357 2358 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2359 &me->me_q.q_mcr, 0)) { 2360 err = ENOMEM; 2361 goto errout; 2362 } 2363 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2364 2365 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2366 &me->me_q.q_ctx, 0)) { 2367 err = ENOMEM; 2368 goto errout; 2369 } 2370 2371 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2372 if (mbits > nbits) { 2373 err = E2BIG; 2374 goto errout; 2375 } 2376 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2377 err = ENOMEM; 2378 goto errout; 2379 } 2380 bzero(me->me_M.dma_vaddr, normbits / 8); 2381 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2382 me->me_M.dma_vaddr, (mbits + 7) / 8); 2383 2384 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2385 err = ENOMEM; 2386 goto errout; 2387 } 2388 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2389 2390 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2391 if (ebits > nbits) { 2392 err = E2BIG; 2393 goto errout; 2394 } 2395 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2396 err = ENOMEM; 2397 goto errout; 2398 } 2399 bzero(me->me_E.dma_vaddr, normbits / 8); 2400 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2401 me->me_E.dma_vaddr, (ebits + 7) / 8); 2402 2403 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2404 &me->me_epb, 0)) { 2405 err = ENOMEM; 2406 goto errout; 2407 } 2408 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2409 epb->pb_addr = htole32(me->me_E.dma_paddr); 2410 epb->pb_next = 0; 2411 epb->pb_len = htole32((ebits + 7) / 8); 2412 2413 #ifdef UBSEC_DEBUG 2414 if (ubsec_debug) { 2415 printf("Epb "); 2416 ubsec_dump_pb(epb); 2417 } 2418 #endif 2419 2420 mcr->mcr_pkts = htole16(1); 2421 mcr->mcr_flags = 0; 2422 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2423 mcr->mcr_reserved = 0; 2424 mcr->mcr_pktlen = 0; 2425 2426 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2427 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2428 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2429 2430 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2431 mcr->mcr_opktbuf.pb_next = 0; 2432 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2433 2434 #ifdef DIAGNOSTIC 2435 /* Misaligned output buffer will hang the chip. */ 2436 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2437 panic("%s: modexp invalid addr 0x%x", 2438 sc->sc_dv.dv_xname, letoh32(mcr->mcr_opktbuf.pb_addr)); 2439 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2440 panic("%s: modexp invalid len 0x%x", 2441 sc->sc_dv.dv_xname, letoh32(mcr->mcr_opktbuf.pb_len)); 2442 #endif 2443 2444 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2445 bzero(ctx, sizeof(*ctx)); 2446 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2447 (nbits + 7) / 8); 2448 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2449 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2450 ctx->me_E_len = htole16(ebits); 2451 ctx->me_N_len = htole16(nbits); 2452 2453 #ifdef UBSEC_DEBUG 2454 if (ubsec_debug) { 2455 ubsec_dump_mcr(mcr); 2456 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2457 } 2458 #endif 2459 2460 /* 2461 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2462 * everything else. 2463 */ 2464 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2465 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2466 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2467 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2468 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2469 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2470 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2471 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2472 2473 /* Enqueue and we're done... */ 2474 s = splnet(); 2475 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2476 ubsec_feed2(sc); 2477 splx(s); 2478 2479 return (0); 2480 2481 errout: 2482 if (me != NULL) { 2483 if (me->me_q.q_mcr.dma_map != NULL) 2484 ubsec_dma_free(sc, &me->me_q.q_mcr); 2485 if (me->me_q.q_ctx.dma_map != NULL) { 2486 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2487 ubsec_dma_free(sc, &me->me_q.q_ctx); 2488 } 2489 if (me->me_M.dma_map != NULL) { 2490 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2491 ubsec_dma_free(sc, &me->me_M); 2492 } 2493 if (me->me_E.dma_map != NULL) { 2494 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2495 ubsec_dma_free(sc, &me->me_E); 2496 } 2497 if (me->me_C.dma_map != NULL) { 2498 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2499 ubsec_dma_free(sc, &me->me_C); 2500 } 2501 if (me->me_epb.dma_map != NULL) 2502 ubsec_dma_free(sc, &me->me_epb); 2503 free(me, M_DEVBUF); 2504 } 2505 krp->krp_status = err; 2506 crypto_kdone(krp); 2507 return (0); 2508 } 2509 2510 static int 2511 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, 2512 int hint) 2513 { 2514 struct ubsec_q2_rsapriv *rp = NULL; 2515 struct ubsec_mcr *mcr; 2516 struct ubsec_ctx_rsapriv *ctx; 2517 int s, err = 0; 2518 u_int padlen, msglen; 2519 2520 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2521 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2522 if (msglen > padlen) 2523 padlen = msglen; 2524 2525 if (padlen <= 256) 2526 padlen = 256; 2527 else if (padlen <= 384) 2528 padlen = 384; 2529 else if (padlen <= 512) 2530 padlen = 512; 2531 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2532 padlen = 768; 2533 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2534 padlen = 1024; 2535 else { 2536 err = E2BIG; 2537 goto errout; 2538 } 2539 2540 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2541 err = E2BIG; 2542 goto errout; 2543 } 2544 2545 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2546 err = E2BIG; 2547 goto errout; 2548 } 2549 2550 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2551 err = E2BIG; 2552 goto errout; 2553 } 2554 2555 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT); 2556 if (rp == NULL) 2557 return (ENOMEM); 2558 bzero(rp, sizeof *rp); 2559 rp->rpr_krp = krp; 2560 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2561 2562 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2563 &rp->rpr_q.q_mcr, 0)) { 2564 err = ENOMEM; 2565 goto errout; 2566 } 2567 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2568 2569 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2570 &rp->rpr_q.q_ctx, 0)) { 2571 err = ENOMEM; 2572 goto errout; 2573 } 2574 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2575 bzero(ctx, sizeof *ctx); 2576 2577 /* Copy in p */ 2578 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2579 &ctx->rpr_buf[0 * (padlen / 8)], 2580 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2581 2582 /* Copy in q */ 2583 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2584 &ctx->rpr_buf[1 * (padlen / 8)], 2585 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2586 2587 /* Copy in dp */ 2588 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2589 &ctx->rpr_buf[2 * (padlen / 8)], 2590 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2591 2592 /* Copy in dq */ 2593 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2594 &ctx->rpr_buf[3 * (padlen / 8)], 2595 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2596 2597 /* Copy in pinv */ 2598 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2599 &ctx->rpr_buf[4 * (padlen / 8)], 2600 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2601 2602 msglen = padlen * 2; 2603 2604 /* Copy in input message (aligned buffer/length). */ 2605 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2606 /* Is this likely? */ 2607 err = E2BIG; 2608 goto errout; 2609 } 2610 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2611 err = ENOMEM; 2612 goto errout; 2613 } 2614 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2615 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2616 rp->rpr_msgin.dma_vaddr, 2617 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2618 2619 /* Prepare space for output message (aligned buffer/length). */ 2620 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2621 /* Is this likely? */ 2622 err = E2BIG; 2623 goto errout; 2624 } 2625 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2626 err = ENOMEM; 2627 goto errout; 2628 } 2629 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2630 2631 mcr->mcr_pkts = htole16(1); 2632 mcr->mcr_flags = 0; 2633 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2634 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2635 mcr->mcr_ipktbuf.pb_next = 0; 2636 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2637 mcr->mcr_reserved = 0; 2638 mcr->mcr_pktlen = htole16(msglen); 2639 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2640 mcr->mcr_opktbuf.pb_next = 0; 2641 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2642 2643 #ifdef DIAGNOSTIC 2644 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2645 panic("%s: rsapriv: invalid msgin 0x%lx(0x%lx)", 2646 sc->sc_dv.dv_xname, (u_long) rp->rpr_msgin.dma_paddr, 2647 (u_long) rp->rpr_msgin.dma_size); 2648 } 2649 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2650 panic("%s: rsapriv: invalid msgout 0x%lx(0x%lx)", 2651 sc->sc_dv.dv_xname, (u_long) rp->rpr_msgout.dma_paddr, 2652 (u_long) rp->rpr_msgout.dma_size); 2653 } 2654 #endif 2655 2656 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2657 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2658 ctx->rpr_q_len = htole16(padlen); 2659 ctx->rpr_p_len = htole16(padlen); 2660 2661 /* 2662 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2663 * everything else. 2664 */ 2665 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 2666 0, rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2667 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 2668 0, rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2669 2670 /* Enqueue and we're done... */ 2671 s = splnet(); 2672 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2673 ubsec_feed2(sc); 2674 ubsecstats.hst_modexpcrt++; 2675 splx(s); 2676 return (0); 2677 2678 errout: 2679 if (rp != NULL) { 2680 if (rp->rpr_q.q_mcr.dma_map != NULL) 2681 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2682 if (rp->rpr_msgin.dma_map != NULL) { 2683 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2684 ubsec_dma_free(sc, &rp->rpr_msgin); 2685 } 2686 if (rp->rpr_msgout.dma_map != NULL) { 2687 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2688 ubsec_dma_free(sc, &rp->rpr_msgout); 2689 } 2690 free(rp, M_DEVBUF); 2691 } 2692 krp->krp_status = err; 2693 crypto_kdone(krp); 2694 return (0); 2695 } 2696 2697 #ifdef UBSEC_DEBUG 2698 static void 2699 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2700 { 2701 printf("addr 0x%x (0x%x) next 0x%x\n", 2702 pb->pb_addr, pb->pb_len, pb->pb_next); 2703 } 2704 2705 static void 2706 ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *c) 2707 { 2708 printf("CTX (0x%x):\n", c->ctx_len); 2709 switch (letoh16(c->ctx_op)) { 2710 case UBS_CTXOP_RNGBYPASS: 2711 case UBS_CTXOP_RNGSHA1: 2712 break; 2713 case UBS_CTXOP_MODEXP: 2714 { 2715 struct ubsec_ctx_modexp *cx = (void *)c; 2716 int i, len; 2717 2718 printf(" Elen %u, Nlen %u\n", 2719 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2720 len = (cx->me_N_len + 7)/8; 2721 for (i = 0; i < len; i++) 2722 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2723 printf("\n"); 2724 break; 2725 } 2726 default: 2727 printf("unknown context: %x\n", c->ctx_op); 2728 } 2729 printf("END CTX\n"); 2730 } 2731 2732 static void 2733 ubsec_dump_mcr(struct ubsec_mcr *mcr) 2734 { 2735 volatile struct ubsec_mcr_add *ma; 2736 int i; 2737 2738 printf("MCR:\n"); 2739 printf(" pkts: %u, flags 0x%x\n", 2740 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2741 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2742 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2743 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2744 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2745 letoh16(ma->mcr_reserved)); 2746 printf(" %d: ipkt ", i); 2747 ubsec_dump_pb(&ma->mcr_ipktbuf); 2748 printf(" %d: opkt ", i); 2749 ubsec_dump_pb(&ma->mcr_opktbuf); 2750 ma++; 2751 } 2752 printf("END MCR\n"); 2753 } 2754 #endif /* UBSEC_DEBUG */ 2755 2756 /* 2757 * Return the number of significant bits of a big number. 2758 */ 2759 static int 2760 ubsec_ksigbits(struct crparam *cr) 2761 { 2762 u_int plen = (cr->crp_nbits + 7) / 8; 2763 int i, sig = plen * 8; 2764 u_int8_t c, *p = cr->crp_p; 2765 2766 for (i = plen - 1; i >= 0; i--) { 2767 c = p[i]; 2768 if (c != 0) { 2769 while ((c & 0x80) == 0) { 2770 sig--; 2771 c <<= 1; 2772 } 2773 break; 2774 } 2775 sig -= 8; 2776 } 2777 return (sig); 2778 } 2779 2780 static void 2781 ubsec_kshift_r(u_int shiftbits, u_int8_t *src, u_int srcbits, 2782 u_int8_t *dst, u_int dstbits) 2783 { 2784 u_int slen, dlen; 2785 int i, si, di, n; 2786 2787 slen = (srcbits + 7) / 8; 2788 dlen = (dstbits + 7) / 8; 2789 2790 for (i = 0; i < slen; i++) 2791 dst[i] = src[i]; 2792 for (i = 0; i < dlen - slen; i++) 2793 dst[slen + i] = 0; 2794 2795 n = shiftbits / 8; 2796 if (n != 0) { 2797 si = dlen - n - 1; 2798 di = dlen - 1; 2799 while (si >= 0) 2800 dst[di--] = dst[si--]; 2801 while (di >= 0) 2802 dst[di--] = 0; 2803 } 2804 2805 n = shiftbits % 8; 2806 if (n != 0) { 2807 for (i = dlen - 1; i > 0; i--) 2808 dst[i] = (dst[i] << n) | 2809 (dst[i - 1] >> (8 - n)); 2810 dst[0] = dst[0] << n; 2811 } 2812 } 2813 2814 static void 2815 ubsec_kshift_l(u_int shiftbits, u_int8_t *src, u_int srcbits, 2816 u_int8_t *dst, u_int dstbits) 2817 { 2818 int slen, dlen, i, n; 2819 2820 slen = (srcbits + 7) / 8; 2821 dlen = (dstbits + 7) / 8; 2822 2823 n = shiftbits / 8; 2824 for (i = 0; i < slen; i++) 2825 dst[i] = src[i + n]; 2826 for (i = 0; i < dlen - slen; i++) 2827 dst[slen + i] = 0; 2828 2829 n = shiftbits % 8; 2830 if (n != 0) { 2831 for (i = 0; i < (dlen - 1); i++) 2832 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2833 dst[dlen - 1] = dst[dlen - 1] >> n; 2834 } 2835 } 2836
Indexes created Mon Sep 22 10:09:38 GMT 2025