ubsec.c revision 1.27.6.2
1 /* $NetBSD: ubsec.c,v 1.27.6.2 2013/06/23 06:20:21 tls Exp $ */ 2 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.6 2003/01/23 21:06:43 sam Exp $ */ 3 /* $OpenBSD: ubsec.c,v 1.127 2003/06/04 14:04:58 jason Exp $ */ 4 5 /* 6 * Copyright (c) 2000 Jason L. Wright (jason (at) thought.net) 7 * Copyright (c) 2000 Theo de Raadt (deraadt (at) openbsd.org) 8 * Copyright (c) 2001 Patrik Lindergren (patrik (at) ipunplugged.com) 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Effort sponsored in part by the Defense Advanced Research Projects 32 * Agency (DARPA) and Air Force Research Laboratory, Air Force 33 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 34 * 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: ubsec.c,v 1.27.6.2 2013/06/23 06:20:21 tls Exp $"); 39 40 #undef UBSEC_DEBUG 41 42 /* 43 * uBsec 5[56]01, bcm580xx, bcm582x hardware crypto accelerator 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/proc.h> 49 #include <sys/endian.h> 50 #ifdef __NetBSD__ 51 #define UBSEC_NO_RNG /* hangs on attach */ 52 #define letoh16 htole16 53 #define letoh32 htole32 54 #endif 55 #include <sys/errno.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/mbuf.h> 59 #include <sys/device.h> 60 #include <sys/queue.h> 61 62 #include <opencrypto/cryptodev.h> 63 #include <opencrypto/xform.h> 64 #ifdef __OpenBSD__ 65 #include <dev/rndvar.h> 66 #include <sys/md5k.h> 67 #else 68 #include <sys/cprng.h> 69 #include <sys/md5.h> 70 #endif 71 #include <sys/sha1.h> 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcidevs.h> 76 77 #include <dev/pci/ubsecreg.h> 78 #include <dev/pci/ubsecvar.h> 79 80 /* 81 * Prototypes and count for the pci_device structure 82 */ 83 static int ubsec_probe(device_t, cfdata_t, void *); 84 static void ubsec_attach(device_t, device_t, void *); 85 static void ubsec_reset_board(struct ubsec_softc *); 86 static void ubsec_init_board(struct ubsec_softc *); 87 static void ubsec_init_pciregs(struct pci_attach_args *pa); 88 static void ubsec_cleanchip(struct ubsec_softc *); 89 static void ubsec_totalreset(struct ubsec_softc *); 90 static int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); 91 92 #ifdef __OpenBSD__ 93 struct cfattach ubsec_ca = { 94 sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 95 }; 96 97 struct cfdriver ubsec_cd = { 98 0, "ubsec", DV_DULL 99 }; 100 #else 101 CFATTACH_DECL_NEW(ubsec, sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 102 NULL, NULL); 103 extern struct cfdriver ubsec_cd; 104 #endif 105 106 /* patchable */ 107 #ifdef UBSEC_DEBUG 108 extern int ubsec_debug; 109 int ubsec_debug=1; 110 #endif 111 112 static int ubsec_intr(void *); 113 static int ubsec_newsession(void*, u_int32_t *, struct cryptoini *); 114 static int ubsec_freesession(void*, u_int64_t); 115 static int ubsec_process(void*, struct cryptop *, int hint); 116 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 117 static void ubsec_feed(struct ubsec_softc *); 118 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 119 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 120 static void ubsec_feed2(struct ubsec_softc *); 121 #ifndef UBSEC_NO_RNG 122 static void ubsec_rng(void *); 123 static void ubsec_rng_locked(void *); 124 static void ubsec_rng_get(size_t, void *); 125 #endif /* UBSEC_NO_RNG */ 126 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 127 struct ubsec_dma_alloc *, int); 128 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 129 static int ubsec_dmamap_aligned(bus_dmamap_t); 130 131 static int ubsec_kprocess(void*, struct cryptkop *, int); 132 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, 133 struct cryptkop *, int); 134 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, 135 struct cryptkop *, int); 136 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, 137 struct cryptkop *, int); 138 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 139 static int ubsec_ksigbits(struct crparam *); 140 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 141 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 142 143 #ifdef UBSEC_DEBUG 144 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 145 static void ubsec_dump_mcr(struct ubsec_mcr *); 146 static void ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *); 147 #endif 148 149 #define READ_REG(sc,r) \ 150 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 151 152 #define WRITE_REG(sc,reg,val) \ 153 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 154 155 #define SWAP32(x) (x) = htole32(ntohl((x))) 156 #ifndef HTOLE32 157 #define HTOLE32(x) (x) = htole32(x) 158 #endif 159 160 struct ubsec_stats ubsecstats; 161 162 /* 163 * ubsec_maxbatch controls the number of crypto ops to voluntarily 164 * collect into one submission to the hardware. This batching happens 165 * when ops are dispatched from the crypto subsystem with a hint that 166 * more are to follow immediately. These ops must also not be marked 167 * with a ``no delay'' flag. 168 */ 169 static int ubsec_maxbatch = 1; 170 #ifdef SYSCTL_INT 171 SYSCTL_INT(_kern, OID_AUTO, ubsec_maxbatch, CTLFLAG_RW, &ubsec_maxbatch, 172 0, "Broadcom driver: max ops to batch w/o interrupt"); 173 #endif 174 175 /* 176 * ubsec_maxaggr controls the number of crypto ops to submit to the 177 * hardware as a unit. This aggregation reduces the number of interrupts 178 * to the host at the expense of increased latency (for all but the last 179 * operation). For network traffic setting this to one yields the highest 180 * performance but at the expense of more interrupt processing. 181 */ 182 static int ubsec_maxaggr = 1; 183 #ifdef SYSCTL_INT 184 SYSCTL_INT(_kern, OID_AUTO, ubsec_maxaggr, CTLFLAG_RW, &ubsec_maxaggr, 185 0, "Broadcom driver: max ops to aggregate under one interrupt"); 186 #endif 187 188 static const struct ubsec_product { 189 pci_vendor_id_t ubsec_vendor; 190 pci_product_id_t ubsec_product; 191 int ubsec_flags; 192 int ubsec_statmask; 193 const char *ubsec_name; 194 } ubsec_products[] = { 195 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5501, 196 0, 197 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 198 "Bluesteel 5501" 199 }, 200 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5601, 201 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 202 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 203 "Bluesteel 5601" 204 }, 205 206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5801, 207 0, 208 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 209 "Broadcom BCM5801" 210 }, 211 212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5802, 213 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 214 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 215 "Broadcom BCM5802" 216 }, 217 218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5805, 219 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 220 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 221 "Broadcom BCM5805" 222 }, 223 224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5820, 225 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 226 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 227 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 228 "Broadcom BCM5820" 229 }, 230 231 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5821, 232 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 233 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 234 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 235 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 236 "Broadcom BCM5821" 237 }, 238 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_SCA1K, 239 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 240 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 241 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 242 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 243 "Sun Crypto Accelerator 1000" 244 }, 245 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_5821, 246 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 247 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 248 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 249 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 250 "Broadcom BCM5821 (Sun)" 251 }, 252 253 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5822, 254 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 255 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 256 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 257 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 258 "Broadcom BCM5822" 259 }, 260 261 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5823, 262 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 263 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 264 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 265 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 266 "Broadcom BCM5823" 267 }, 268 269 { 0, 0, 270 0, 271 0, 272 NULL 273 } 274 }; 275 276 static const struct ubsec_product * 277 ubsec_lookup(const struct pci_attach_args *pa) 278 { 279 const struct ubsec_product *up; 280 281 for (up = ubsec_products; up->ubsec_name != NULL; up++) { 282 if (PCI_VENDOR(pa->pa_id) == up->ubsec_vendor && 283 PCI_PRODUCT(pa->pa_id) == up->ubsec_product) 284 return (up); 285 } 286 return (NULL); 287 } 288 289 static int 290 ubsec_probe(device_t parent, cfdata_t match, void *aux) 291 { 292 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 293 294 if (ubsec_lookup(pa) != NULL) 295 return (1); 296 297 return (0); 298 } 299 300 static void 301 ubsec_attach(device_t parent, device_t self, void *aux) 302 { 303 struct ubsec_softc *sc = device_private(self); 304 struct pci_attach_args *pa = aux; 305 const struct ubsec_product *up; 306 pci_chipset_tag_t pc = pa->pa_pc; 307 pci_intr_handle_t ih; 308 const char *intrstr = NULL; 309 struct ubsec_dma *dmap; 310 u_int32_t cmd, i; 311 312 sc->sc_dev = self; 313 up = ubsec_lookup(pa); 314 if (up == NULL) { 315 printf("\n"); 316 panic("ubsec_attach: impossible"); 317 } 318 319 pci_aprint_devinfo_fancy(pa, "Crypto processor", up->ubsec_name, 1); 320 321 SIMPLEQ_INIT(&sc->sc_queue); 322 SIMPLEQ_INIT(&sc->sc_qchip); 323 SIMPLEQ_INIT(&sc->sc_queue2); 324 SIMPLEQ_INIT(&sc->sc_qchip2); 325 SIMPLEQ_INIT(&sc->sc_q2free); 326 327 sc->sc_flags = up->ubsec_flags; 328 sc->sc_statmask = up->ubsec_statmask; 329 330 cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 331 cmd |= PCI_COMMAND_MASTER_ENABLE; 332 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, cmd); 333 334 if (pci_mapreg_map(pa, BS_BAR, PCI_MAPREG_TYPE_MEM, 0, 335 &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 336 aprint_error_dev(self, "can't find mem space"); 337 return; 338 } 339 340 sc->sc_dmat = pa->pa_dmat; 341 342 if (pci_intr_map(pa, &ih)) { 343 aprint_error_dev(self, "couldn't map interrupt\n"); 344 return; 345 } 346 intrstr = pci_intr_string(pc, ih); 347 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ubsec_intr, sc); 348 if (sc->sc_ih == NULL) { 349 aprint_error_dev(self, "couldn't establish interrupt"); 350 if (intrstr != NULL) 351 aprint_error(" at %s", intrstr); 352 aprint_error("\n"); 353 return; 354 } 355 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 356 357 sc->sc_cid = crypto_get_driverid(0); 358 if (sc->sc_cid < 0) { 359 aprint_error_dev(self, "couldn't get crypto driver id\n"); 360 pci_intr_disestablish(pc, sc->sc_ih); 361 return; 362 } 363 364 sc->sc_rng_need = RND_POOLBITS / NBBY; 365 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_VM); 366 367 SIMPLEQ_INIT(&sc->sc_freequeue); 368 dmap = sc->sc_dmaa; 369 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 370 struct ubsec_q *q; 371 372 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 373 M_DEVBUF, M_NOWAIT); 374 if (q == NULL) { 375 aprint_error_dev(self, "can't allocate queue buffers\n"); 376 break; 377 } 378 379 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 380 &dmap->d_alloc, 0)) { 381 aprint_error_dev(self, "can't allocate dma buffers\n"); 382 free(q, M_DEVBUF); 383 break; 384 } 385 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 386 387 q->q_dma = dmap; 388 sc->sc_queuea[i] = q; 389 390 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 391 } 392 393 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 394 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 395 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 396 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 397 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC_96, 0, 0, 398 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 399 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC_96, 0, 0, 400 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 401 402 /* 403 * Reset Broadcom chip 404 */ 405 ubsec_reset_board(sc); 406 407 /* 408 * Init Broadcom specific PCI settings 409 */ 410 ubsec_init_pciregs(pa); 411 412 /* 413 * Init Broadcom chip 414 */ 415 ubsec_init_board(sc); 416 417 #ifndef UBSEC_NO_RNG 418 if (sc->sc_flags & UBS_FLAGS_RNG) { 419 sc->sc_statmask |= BS_STAT_MCR2_DONE; 420 421 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 422 &sc->sc_rng.rng_q.q_mcr, 0)) 423 goto skip_rng; 424 425 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 426 &sc->sc_rng.rng_q.q_ctx, 0)) { 427 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 428 goto skip_rng; 429 } 430 431 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 432 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 433 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 434 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 435 goto skip_rng; 436 } 437 438 rndsource_setcb(&sc->sc_rnd_source, ubsec_rng_get, sc); 439 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 440 RND_TYPE_RNG, 441 RND_FLAG_NO_ESTIMATE|RND_FLAG_HASCB); 442 if (hz >= 100) 443 sc->sc_rnghz = hz / 100; 444 else 445 sc->sc_rnghz = 1; 446 #ifdef __OpenBSD__ 447 timeout_set(&sc->sc_rngto, ubsec_rng, sc); 448 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 449 #else 450 callout_init(&sc->sc_rngto, 0); 451 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 452 #endif 453 skip_rng: 454 if (sc->sc_rnghz) 455 aprint_normal_dev(self, "random number generator enabled\n"); 456 else 457 aprint_error_dev(self, "WARNING: random number generator " 458 "disabled\n"); 459 } 460 #endif /* UBSEC_NO_RNG */ 461 462 if (sc->sc_flags & UBS_FLAGS_KEY) { 463 sc->sc_statmask |= BS_STAT_MCR2_DONE; 464 465 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 466 ubsec_kprocess, sc); 467 #if 0 468 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 469 ubsec_kprocess, sc); 470 #endif 471 } 472 } 473 474 /* 475 * UBSEC Interrupt routine 476 */ 477 static int 478 ubsec_intr(void *arg) 479 { 480 struct ubsec_softc *sc = arg; 481 volatile u_int32_t stat; 482 struct ubsec_q *q; 483 struct ubsec_dma *dmap; 484 int npkts = 0, i; 485 486 mutex_spin_enter(&sc->sc_mtx); 487 stat = READ_REG(sc, BS_STAT); 488 stat &= sc->sc_statmask; 489 if (stat == 0) { 490 mutex_spin_exit(&sc->sc_mtx); 491 return (0); 492 } 493 494 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 495 496 /* 497 * Check to see if we have any packets waiting for us 498 */ 499 if ((stat & BS_STAT_MCR1_DONE)) { 500 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 501 q = SIMPLEQ_FIRST(&sc->sc_qchip); 502 dmap = q->q_dma; 503 504 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 505 break; 506 507 q = SIMPLEQ_FIRST(&sc->sc_qchip); 508 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 509 510 npkts = q->q_nstacked_mcrs; 511 sc->sc_nqchip -= 1+npkts; 512 /* 513 * search for further sc_qchip ubsec_q's that share 514 * the same MCR, and complete them too, they must be 515 * at the top. 516 */ 517 for (i = 0; i < npkts; i++) { 518 if(q->q_stacked_mcr[i]) 519 ubsec_callback(sc, q->q_stacked_mcr[i]); 520 else 521 break; 522 } 523 ubsec_callback(sc, q); 524 } 525 526 /* 527 * Don't send any more packet to chip if there has been 528 * a DMAERR. 529 */ 530 if (!(stat & BS_STAT_DMAERR)) 531 ubsec_feed(sc); 532 } 533 534 /* 535 * Check to see if we have any key setups/rng's waiting for us 536 */ 537 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 538 (stat & BS_STAT_MCR2_DONE)) { 539 struct ubsec_q2 *q2; 540 struct ubsec_mcr *mcr; 541 542 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 543 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 544 545 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 546 0, q2->q_mcr.dma_map->dm_mapsize, 547 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 548 549 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 550 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 551 bus_dmamap_sync(sc->sc_dmat, 552 q2->q_mcr.dma_map, 0, 553 q2->q_mcr.dma_map->dm_mapsize, 554 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 555 break; 556 } 557 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 558 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, /*q2,*/ q_next); 559 ubsec_callback2(sc, q2); 560 /* 561 * Don't send any more packet to chip if there has been 562 * a DMAERR. 563 */ 564 if (!(stat & BS_STAT_DMAERR)) 565 ubsec_feed2(sc); 566 } 567 } 568 569 /* 570 * Check to see if we got any DMA Error 571 */ 572 if (stat & BS_STAT_DMAERR) { 573 #ifdef UBSEC_DEBUG 574 if (ubsec_debug) { 575 volatile u_int32_t a = READ_REG(sc, BS_ERR); 576 577 printf("%s: dmaerr %s@%08x\n", device_xname(sc->sc_dev), 578 (a & BS_ERR_READ) ? "read" : "write", 579 a & BS_ERR_ADDR); 580 } 581 #endif /* UBSEC_DEBUG */ 582 ubsecstats.hst_dmaerr++; 583 ubsec_totalreset(sc); 584 ubsec_feed(sc); 585 } 586 587 if (sc->sc_needwakeup) { /* XXX check high watermark */ 588 int wkeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 589 #ifdef UBSEC_DEBUG 590 if (ubsec_debug) 591 printf("%s: wakeup crypto (%x)\n", device_xname(sc->sc_dev), 592 sc->sc_needwakeup); 593 #endif /* UBSEC_DEBUG */ 594 sc->sc_needwakeup &= ~wkeup; 595 crypto_unblock(sc->sc_cid, wkeup); 596 } 597 mutex_spin_exit(&sc->sc_mtx); 598 return (1); 599 } 600 601 /* 602 * ubsec_feed() - aggregate and post requests to chip 603 * OpenBSD comments: 604 * It is assumed that the caller set splnet() 605 */ 606 static void 607 ubsec_feed(struct ubsec_softc *sc) 608 { 609 struct ubsec_q *q, *q2; 610 int npkts, i; 611 void *v; 612 u_int32_t stat; 613 #ifdef UBSEC_DEBUG 614 static int max; 615 #endif /* UBSEC_DEBUG */ 616 617 npkts = sc->sc_nqueue; 618 if (npkts > ubsecstats.hst_maxqueue) 619 ubsecstats.hst_maxqueue = npkts; 620 if (npkts < 2) 621 goto feed1; 622 623 /* 624 * Decide how many ops to combine in a single MCR. We cannot 625 * aggregate more than UBS_MAX_AGGR because this is the number 626 * of slots defined in the data structure. Otherwise we clamp 627 * based on the tunable parameter ubsec_maxaggr. Note that 628 * aggregation can happen in two ways: either by batching ops 629 * from above or because the h/w backs up and throttles us. 630 * Aggregating ops reduces the number of interrupts to the host 631 * but also (potentially) increases the latency for processing 632 * completed ops as we only get an interrupt when all aggregated 633 * ops have completed. 634 */ 635 if (npkts > UBS_MAX_AGGR) 636 npkts = UBS_MAX_AGGR; 637 if (npkts > ubsec_maxaggr) 638 npkts = ubsec_maxaggr; 639 if (npkts > ubsecstats.hst_maxbatch) 640 ubsecstats.hst_maxbatch = npkts; 641 if (npkts < 2) 642 goto feed1; 643 ubsecstats.hst_totbatch += npkts-1; 644 645 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 646 if (stat & BS_STAT_DMAERR) { 647 ubsec_totalreset(sc); 648 ubsecstats.hst_dmaerr++; 649 } else { 650 ubsecstats.hst_mcr1full++; 651 } 652 return; 653 } 654 655 #ifdef UBSEC_DEBUG 656 if (ubsec_debug) 657 printf("merging %d records\n", npkts); 658 /* XXX temporary aggregation statistics reporting code */ 659 if (max < npkts) { 660 max = npkts; 661 printf("%s: new max aggregate %d\n", device_xname(sc->sc_dev), max); 662 } 663 #endif /* UBSEC_DEBUG */ 664 665 q = SIMPLEQ_FIRST(&sc->sc_queue); 666 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 667 --sc->sc_nqueue; 668 669 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 670 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 671 if (q->q_dst_map != NULL) 672 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 673 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 674 675 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 676 677 for (i = 0; i < q->q_nstacked_mcrs; i++) { 678 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 679 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 680 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 681 if (q2->q_dst_map != NULL) 682 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 683 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 684 q2= SIMPLEQ_FIRST(&sc->sc_queue); 685 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q2,*/ q_next); 686 --sc->sc_nqueue; 687 688 v = ((void *)&q2->q_dma->d_dma->d_mcr); 689 v = (char*)v + (sizeof(struct ubsec_mcr) - 690 sizeof(struct ubsec_mcr_add)); 691 memcpy(&q->q_dma->d_dma->d_mcradd[i], v, sizeof(struct ubsec_mcr_add)); 692 q->q_stacked_mcr[i] = q2; 693 } 694 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 695 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 696 sc->sc_nqchip += npkts; 697 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 698 ubsecstats.hst_maxqchip = sc->sc_nqchip; 699 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 700 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 701 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 702 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 703 offsetof(struct ubsec_dmachunk, d_mcr)); 704 return; 705 706 feed1: 707 while (!SIMPLEQ_EMPTY(&sc->sc_queue)) { 708 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 709 if (stat & BS_STAT_DMAERR) { 710 ubsec_totalreset(sc); 711 ubsecstats.hst_dmaerr++; 712 } else { 713 ubsecstats.hst_mcr1full++; 714 } 715 break; 716 } 717 718 q = SIMPLEQ_FIRST(&sc->sc_queue); 719 720 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 721 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 722 if (q->q_dst_map != NULL) 723 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 724 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 725 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 726 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 727 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 728 729 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 730 offsetof(struct ubsec_dmachunk, d_mcr)); 731 #ifdef UBSEC_DEBUG 732 if (ubsec_debug) 733 printf("feed: q->chip %p %08x stat %08x\n", 734 q, (u_int32_t)q->q_dma->d_alloc.dma_paddr, 735 stat); 736 #endif /* UBSEC_DEBUG */ 737 q = SIMPLEQ_FIRST(&sc->sc_queue); 738 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 739 --sc->sc_nqueue; 740 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 741 sc->sc_nqchip++; 742 } 743 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 744 ubsecstats.hst_maxqchip = sc->sc_nqchip; 745 } 746 747 /* 748 * Allocate a new 'session' and return an encoded session id. 'sidp' 749 * contains our registration id, and should contain an encoded session 750 * id on successful allocation. 751 */ 752 static int 753 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 754 { 755 struct cryptoini *c, *encini = NULL, *macini = NULL; 756 struct ubsec_softc *sc; 757 struct ubsec_session *ses = NULL; 758 MD5_CTX md5ctx; 759 SHA1_CTX sha1ctx; 760 int i, sesn; 761 762 sc = arg; 763 KASSERT(sc != NULL /*, ("ubsec_newsession: null softc")*/); 764 765 if (sidp == NULL || cri == NULL || sc == NULL) 766 return (EINVAL); 767 768 for (c = cri; c != NULL; c = c->cri_next) { 769 if (c->cri_alg == CRYPTO_MD5_HMAC_96 || 770 c->cri_alg == CRYPTO_SHA1_HMAC_96) { 771 if (macini) 772 return (EINVAL); 773 macini = c; 774 } else if (c->cri_alg == CRYPTO_DES_CBC || 775 c->cri_alg == CRYPTO_3DES_CBC) { 776 if (encini) 777 return (EINVAL); 778 encini = c; 779 } else 780 return (EINVAL); 781 } 782 if (encini == NULL && macini == NULL) 783 return (EINVAL); 784 785 if (sc->sc_sessions == NULL) { 786 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 787 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 788 if (ses == NULL) 789 return (ENOMEM); 790 sesn = 0; 791 sc->sc_nsessions = 1; 792 } else { 793 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 794 if (sc->sc_sessions[sesn].ses_used == 0) { 795 ses = &sc->sc_sessions[sesn]; 796 break; 797 } 798 } 799 800 if (ses == NULL) { 801 sesn = sc->sc_nsessions; 802 ses = (struct ubsec_session *)malloc((sesn + 1) * 803 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 804 if (ses == NULL) 805 return (ENOMEM); 806 memcpy(ses, sc->sc_sessions, sesn * 807 sizeof(struct ubsec_session)); 808 memset(sc->sc_sessions, 0, sesn * 809 sizeof(struct ubsec_session)); 810 free(sc->sc_sessions, M_DEVBUF); 811 sc->sc_sessions = ses; 812 ses = &sc->sc_sessions[sesn]; 813 sc->sc_nsessions++; 814 } 815 } 816 817 memset(ses, 0, sizeof(struct ubsec_session)); 818 ses->ses_used = 1; 819 if (encini) { 820 /* get an IV, network byte order */ 821 #ifdef __NetBSD__ 822 cprng_fast(ses->ses_iv, sizeof(ses->ses_iv)); 823 #else 824 get_random_bytes(ses->ses_iv, sizeof(ses->ses_iv)); 825 #endif 826 827 /* Go ahead and compute key in ubsec's byte order */ 828 if (encini->cri_alg == CRYPTO_DES_CBC) { 829 memcpy(&ses->ses_deskey[0], encini->cri_key, 8); 830 memcpy(&ses->ses_deskey[2], encini->cri_key, 8); 831 memcpy(&ses->ses_deskey[4], encini->cri_key, 8); 832 } else 833 memcpy(ses->ses_deskey, encini->cri_key, 24); 834 835 SWAP32(ses->ses_deskey[0]); 836 SWAP32(ses->ses_deskey[1]); 837 SWAP32(ses->ses_deskey[2]); 838 SWAP32(ses->ses_deskey[3]); 839 SWAP32(ses->ses_deskey[4]); 840 SWAP32(ses->ses_deskey[5]); 841 } 842 843 if (macini) { 844 for (i = 0; i < macini->cri_klen / 8; i++) 845 macini->cri_key[i] ^= HMAC_IPAD_VAL; 846 847 if (macini->cri_alg == CRYPTO_MD5_HMAC_96) { 848 MD5Init(&md5ctx); 849 MD5Update(&md5ctx, macini->cri_key, 850 macini->cri_klen / 8); 851 MD5Update(&md5ctx, hmac_ipad_buffer, 852 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 853 memcpy(ses->ses_hminner, md5ctx.state, 854 sizeof(md5ctx.state)); 855 } else { 856 SHA1Init(&sha1ctx); 857 SHA1Update(&sha1ctx, macini->cri_key, 858 macini->cri_klen / 8); 859 SHA1Update(&sha1ctx, hmac_ipad_buffer, 860 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 861 memcpy(ses->ses_hminner, sha1ctx.state, 862 sizeof(sha1ctx.state)); 863 } 864 865 for (i = 0; i < macini->cri_klen / 8; i++) 866 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 867 868 if (macini->cri_alg == CRYPTO_MD5_HMAC_96) { 869 MD5Init(&md5ctx); 870 MD5Update(&md5ctx, macini->cri_key, 871 macini->cri_klen / 8); 872 MD5Update(&md5ctx, hmac_opad_buffer, 873 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 874 memcpy(ses->ses_hmouter, md5ctx.state, 875 sizeof(md5ctx.state)); 876 } else { 877 SHA1Init(&sha1ctx); 878 SHA1Update(&sha1ctx, macini->cri_key, 879 macini->cri_klen / 8); 880 SHA1Update(&sha1ctx, hmac_opad_buffer, 881 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 882 memcpy(ses->ses_hmouter, sha1ctx.state, 883 sizeof(sha1ctx.state)); 884 } 885 886 for (i = 0; i < macini->cri_klen / 8; i++) 887 macini->cri_key[i] ^= HMAC_OPAD_VAL; 888 } 889 890 *sidp = UBSEC_SID(device_unit(sc->sc_dev), sesn); 891 return (0); 892 } 893 894 /* 895 * Deallocate a session. 896 */ 897 static int 898 ubsec_freesession(void *arg, u_int64_t tid) 899 { 900 struct ubsec_softc *sc; 901 int session; 902 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 903 904 sc = arg; 905 KASSERT(sc != NULL /*, ("ubsec_freesession: null softc")*/); 906 907 session = UBSEC_SESSION(sid); 908 if (session >= sc->sc_nsessions) 909 return (EINVAL); 910 911 memset(&sc->sc_sessions[session], 0, sizeof(sc->sc_sessions[session])); 912 return (0); 913 } 914 915 #ifdef __FreeBSD__ /* Ugly gratuitous changes to bus_dma */ 916 static void 917 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 918 { 919 struct ubsec_operand *op = arg; 920 921 KASSERT(nsegs <= UBS_MAX_SCATTER 922 /*, ("Too many DMA segments returned when mapping operand")*/); 923 #ifdef UBSEC_DEBUG 924 if (ubsec_debug) 925 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 926 (u_int) mapsize, nsegs); 927 #endif 928 op->mapsize = mapsize; 929 op->nsegs = nsegs; 930 memcpy(op->segs, seg, nsegs * sizeof (seg[0])); 931 } 932 #endif 933 934 static int 935 ubsec_process(void *arg, struct cryptop *crp, int hint) 936 { 937 struct ubsec_q *q = NULL; 938 #ifdef __OpenBSD__ 939 int card; 940 #endif 941 int err = 0, i, j, nicealign; 942 struct ubsec_softc *sc; 943 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 944 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 945 int sskip, dskip, stheend, dtheend; 946 int16_t coffset; 947 struct ubsec_session *ses; 948 struct ubsec_pktctx ctx; 949 struct ubsec_dma *dmap = NULL; 950 951 sc = arg; 952 KASSERT(sc != NULL /*, ("ubsec_process: null softc")*/); 953 954 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 955 ubsecstats.hst_invalid++; 956 return (EINVAL); 957 } 958 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 959 ubsecstats.hst_badsession++; 960 return (EINVAL); 961 } 962 963 mutex_spin_enter(&sc->sc_mtx); 964 965 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 966 ubsecstats.hst_queuefull++; 967 sc->sc_needwakeup |= CRYPTO_SYMQ; 968 mutex_spin_exit(&sc->sc_mtx); 969 return(ERESTART); 970 } 971 972 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 973 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, /*q,*/ q_next); 974 mutex_spin_exit(&sc->sc_mtx); 975 976 dmap = q->q_dma; /* Save dma pointer */ 977 memset(q, 0, sizeof(struct ubsec_q)); 978 memset(&ctx, 0, sizeof(ctx)); 979 980 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 981 q->q_dma = dmap; 982 ses = &sc->sc_sessions[q->q_sesn]; 983 984 if (crp->crp_flags & CRYPTO_F_IMBUF) { 985 q->q_src_m = (struct mbuf *)crp->crp_buf; 986 q->q_dst_m = (struct mbuf *)crp->crp_buf; 987 } else if (crp->crp_flags & CRYPTO_F_IOV) { 988 q->q_src_io = (struct uio *)crp->crp_buf; 989 q->q_dst_io = (struct uio *)crp->crp_buf; 990 } else { 991 ubsecstats.hst_badflags++; 992 err = EINVAL; 993 goto errout; /* XXX we don't handle contiguous blocks! */ 994 } 995 996 memset(&dmap->d_dma->d_mcr, 0, sizeof(struct ubsec_mcr)); 997 998 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 999 dmap->d_dma->d_mcr.mcr_flags = 0; 1000 q->q_crp = crp; 1001 1002 crd1 = crp->crp_desc; 1003 if (crd1 == NULL) { 1004 ubsecstats.hst_nodesc++; 1005 err = EINVAL; 1006 goto errout; 1007 } 1008 crd2 = crd1->crd_next; 1009 1010 if (crd2 == NULL) { 1011 if (crd1->crd_alg == CRYPTO_MD5_HMAC_96 || 1012 crd1->crd_alg == CRYPTO_SHA1_HMAC_96) { 1013 maccrd = crd1; 1014 enccrd = NULL; 1015 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1016 crd1->crd_alg == CRYPTO_3DES_CBC) { 1017 maccrd = NULL; 1018 enccrd = crd1; 1019 } else { 1020 ubsecstats.hst_badalg++; 1021 err = EINVAL; 1022 goto errout; 1023 } 1024 } else { 1025 if ((crd1->crd_alg == CRYPTO_MD5_HMAC_96 || 1026 crd1->crd_alg == CRYPTO_SHA1_HMAC_96) && 1027 (crd2->crd_alg == CRYPTO_DES_CBC || 1028 crd2->crd_alg == CRYPTO_3DES_CBC) && 1029 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1030 maccrd = crd1; 1031 enccrd = crd2; 1032 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1033 crd1->crd_alg == CRYPTO_3DES_CBC) && 1034 (crd2->crd_alg == CRYPTO_MD5_HMAC_96 || 1035 crd2->crd_alg == CRYPTO_SHA1_HMAC_96) && 1036 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1037 enccrd = crd1; 1038 maccrd = crd2; 1039 } else { 1040 /* 1041 * We cannot order the ubsec as requested 1042 */ 1043 ubsecstats.hst_badalg++; 1044 err = EINVAL; 1045 goto errout; 1046 } 1047 } 1048 1049 if (enccrd) { 1050 encoffset = enccrd->crd_skip; 1051 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1052 1053 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1054 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1055 1056 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1057 memcpy(ctx.pc_iv, enccrd->crd_iv, 8); 1058 else { 1059 ctx.pc_iv[0] = ses->ses_iv[0]; 1060 ctx.pc_iv[1] = ses->ses_iv[1]; 1061 } 1062 1063 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1064 if (crp->crp_flags & CRYPTO_F_IMBUF) 1065 m_copyback(q->q_src_m, 1066 enccrd->crd_inject, 1067 8, (void *)ctx.pc_iv); 1068 else if (crp->crp_flags & CRYPTO_F_IOV) 1069 cuio_copyback(q->q_src_io, 1070 enccrd->crd_inject, 1071 8, (void *)ctx.pc_iv); 1072 } 1073 } else { 1074 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1075 1076 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1077 memcpy(ctx.pc_iv, enccrd->crd_iv, 8); 1078 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1079 m_copydata(q->q_src_m, enccrd->crd_inject, 1080 8, (void *)ctx.pc_iv); 1081 else if (crp->crp_flags & CRYPTO_F_IOV) 1082 cuio_copydata(q->q_src_io, 1083 enccrd->crd_inject, 8, 1084 (void *)ctx.pc_iv); 1085 } 1086 1087 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1088 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1089 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1090 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1091 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1092 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1093 SWAP32(ctx.pc_iv[0]); 1094 SWAP32(ctx.pc_iv[1]); 1095 } 1096 1097 if (maccrd) { 1098 macoffset = maccrd->crd_skip; 1099 1100 if (maccrd->crd_alg == CRYPTO_MD5_HMAC_96) 1101 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1102 else 1103 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1104 1105 for (i = 0; i < 5; i++) { 1106 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1107 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1108 1109 HTOLE32(ctx.pc_hminner[i]); 1110 HTOLE32(ctx.pc_hmouter[i]); 1111 } 1112 } 1113 1114 if (enccrd && maccrd) { 1115 /* 1116 * ubsec cannot handle packets where the end of encryption 1117 * and authentication are not the same, or where the 1118 * encrypted part begins before the authenticated part. 1119 */ 1120 if ((encoffset + enccrd->crd_len) != 1121 (macoffset + maccrd->crd_len)) { 1122 ubsecstats.hst_lenmismatch++; 1123 err = EINVAL; 1124 goto errout; 1125 } 1126 if (enccrd->crd_skip < maccrd->crd_skip) { 1127 ubsecstats.hst_skipmismatch++; 1128 err = EINVAL; 1129 goto errout; 1130 } 1131 sskip = maccrd->crd_skip; 1132 cpskip = dskip = enccrd->crd_skip; 1133 stheend = maccrd->crd_len; 1134 dtheend = enccrd->crd_len; 1135 coffset = enccrd->crd_skip - maccrd->crd_skip; 1136 cpoffset = cpskip + dtheend; 1137 #ifdef UBSEC_DEBUG 1138 if (ubsec_debug) { 1139 printf("mac: skip %d, len %d, inject %d\n", 1140 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1141 printf("enc: skip %d, len %d, inject %d\n", 1142 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1143 printf("src: skip %d, len %d\n", sskip, stheend); 1144 printf("dst: skip %d, len %d\n", dskip, dtheend); 1145 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1146 coffset, stheend, cpskip, cpoffset); 1147 } 1148 #endif 1149 } else { 1150 cpskip = dskip = sskip = macoffset + encoffset; 1151 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1152 cpoffset = cpskip + dtheend; 1153 coffset = 0; 1154 } 1155 ctx.pc_offset = htole16(coffset >> 2); 1156 1157 /* XXX FIXME: jonathan asks, what the heck's that 0xfff0? */ 1158 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, 1159 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { 1160 err = ENOMEM; 1161 goto errout; 1162 } 1163 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1164 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1165 q->q_src_m, BUS_DMA_NOWAIT) != 0) { 1166 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1167 q->q_src_map = NULL; 1168 ubsecstats.hst_noload++; 1169 err = ENOMEM; 1170 goto errout; 1171 } 1172 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1173 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1174 q->q_src_io, BUS_DMA_NOWAIT) != 0) { 1175 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1176 q->q_src_map = NULL; 1177 ubsecstats.hst_noload++; 1178 err = ENOMEM; 1179 goto errout; 1180 } 1181 } 1182 nicealign = ubsec_dmamap_aligned(q->q_src_map); 1183 1184 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1185 1186 #ifdef UBSEC_DEBUG 1187 if (ubsec_debug) 1188 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1189 #endif 1190 for (i = j = 0; i < q->q_src_map->dm_nsegs; i++) { 1191 struct ubsec_pktbuf *pb; 1192 bus_size_t packl = q->q_src_map->dm_segs[i].ds_len; 1193 bus_addr_t packp = q->q_src_map->dm_segs[i].ds_addr; 1194 1195 if (sskip >= packl) { 1196 sskip -= packl; 1197 continue; 1198 } 1199 1200 packl -= sskip; 1201 packp += sskip; 1202 sskip = 0; 1203 1204 if (packl > 0xfffc) { 1205 err = EIO; 1206 goto errout; 1207 } 1208 1209 if (j == 0) 1210 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1211 else 1212 pb = &dmap->d_dma->d_sbuf[j - 1]; 1213 1214 pb->pb_addr = htole32(packp); 1215 1216 if (stheend) { 1217 if (packl > stheend) { 1218 pb->pb_len = htole32(stheend); 1219 stheend = 0; 1220 } else { 1221 pb->pb_len = htole32(packl); 1222 stheend -= packl; 1223 } 1224 } else 1225 pb->pb_len = htole32(packl); 1226 1227 if ((i + 1) == q->q_src_map->dm_nsegs) 1228 pb->pb_next = 0; 1229 else 1230 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1231 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1232 j++; 1233 } 1234 1235 if (enccrd == NULL && maccrd != NULL) { 1236 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1237 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1238 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1239 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1240 #ifdef UBSEC_DEBUG 1241 if (ubsec_debug) 1242 printf("opkt: %x %x %x\n", 1243 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1244 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1245 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1246 1247 #endif 1248 } else { 1249 if (crp->crp_flags & CRYPTO_F_IOV) { 1250 if (!nicealign) { 1251 ubsecstats.hst_iovmisaligned++; 1252 err = EINVAL; 1253 goto errout; 1254 } 1255 /* XXX: ``what the heck's that'' 0xfff0? */ 1256 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, 1257 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, 1258 &q->q_dst_map) != 0) { 1259 ubsecstats.hst_nomap++; 1260 err = ENOMEM; 1261 goto errout; 1262 } 1263 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1264 q->q_dst_io, BUS_DMA_NOWAIT) != 0) { 1265 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1266 q->q_dst_map = NULL; 1267 ubsecstats.hst_noload++; 1268 err = ENOMEM; 1269 goto errout; 1270 } 1271 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1272 if (nicealign) { 1273 q->q_dst_m = q->q_src_m; 1274 q->q_dst_map = q->q_src_map; 1275 } else { 1276 int totlen, len; 1277 struct mbuf *m, *top, **mp; 1278 1279 ubsecstats.hst_unaligned++; 1280 totlen = q->q_src_map->dm_mapsize; 1281 if (q->q_src_m->m_flags & M_PKTHDR) { 1282 len = MHLEN; 1283 MGETHDR(m, M_DONTWAIT, MT_DATA); 1284 /*XXX FIXME: m_dup_pkthdr */ 1285 if (m && 1 /*!m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)*/) { 1286 m_free(m); 1287 m = NULL; 1288 } 1289 } else { 1290 len = MLEN; 1291 MGET(m, M_DONTWAIT, MT_DATA); 1292 } 1293 if (m == NULL) { 1294 ubsecstats.hst_nombuf++; 1295 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1296 goto errout; 1297 } 1298 if (len == MHLEN) 1299 /*XXX was M_DUP_PKTHDR*/ 1300 M_COPY_PKTHDR(m, q->q_src_m); 1301 if (totlen >= MINCLSIZE) { 1302 MCLGET(m, M_DONTWAIT); 1303 if ((m->m_flags & M_EXT) == 0) { 1304 m_free(m); 1305 ubsecstats.hst_nomcl++; 1306 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1307 goto errout; 1308 } 1309 len = MCLBYTES; 1310 } 1311 m->m_len = len; 1312 top = NULL; 1313 mp = ⊤ 1314 1315 while (totlen > 0) { 1316 if (top) { 1317 MGET(m, M_DONTWAIT, MT_DATA); 1318 if (m == NULL) { 1319 m_freem(top); 1320 ubsecstats.hst_nombuf++; 1321 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1322 goto errout; 1323 } 1324 len = MLEN; 1325 } 1326 if (top && totlen >= MINCLSIZE) { 1327 MCLGET(m, M_DONTWAIT); 1328 if ((m->m_flags & M_EXT) == 0) { 1329 *mp = m; 1330 m_freem(top); 1331 ubsecstats.hst_nomcl++; 1332 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1333 goto errout; 1334 } 1335 len = MCLBYTES; 1336 } 1337 m->m_len = len = min(totlen, len); 1338 totlen -= len; 1339 *mp = m; 1340 mp = &m->m_next; 1341 } 1342 q->q_dst_m = top; 1343 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1344 cpskip, cpoffset); 1345 /* XXX again, what the heck is that 0xfff0? */ 1346 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, 1347 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, 1348 &q->q_dst_map) != 0) { 1349 ubsecstats.hst_nomap++; 1350 err = ENOMEM; 1351 goto errout; 1352 } 1353 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1354 q->q_dst_map, q->q_dst_m, 1355 BUS_DMA_NOWAIT) != 0) { 1356 bus_dmamap_destroy(sc->sc_dmat, 1357 q->q_dst_map); 1358 q->q_dst_map = NULL; 1359 ubsecstats.hst_noload++; 1360 err = ENOMEM; 1361 goto errout; 1362 } 1363 } 1364 } else { 1365 ubsecstats.hst_badflags++; 1366 err = EINVAL; 1367 goto errout; 1368 } 1369 1370 #ifdef UBSEC_DEBUG 1371 if (ubsec_debug) 1372 printf("dst skip: %d\n", dskip); 1373 #endif 1374 for (i = j = 0; i < q->q_dst_map->dm_nsegs; i++) { 1375 struct ubsec_pktbuf *pb; 1376 bus_size_t packl = q->q_dst_map->dm_segs[i].ds_len; 1377 bus_addr_t packp = q->q_dst_map->dm_segs[i].ds_addr; 1378 1379 if (dskip >= packl) { 1380 dskip -= packl; 1381 continue; 1382 } 1383 1384 packl -= dskip; 1385 packp += dskip; 1386 dskip = 0; 1387 1388 if (packl > 0xfffc) { 1389 err = EIO; 1390 goto errout; 1391 } 1392 1393 if (j == 0) 1394 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1395 else 1396 pb = &dmap->d_dma->d_dbuf[j - 1]; 1397 1398 pb->pb_addr = htole32(packp); 1399 1400 if (dtheend) { 1401 if (packl > dtheend) { 1402 pb->pb_len = htole32(dtheend); 1403 dtheend = 0; 1404 } else { 1405 pb->pb_len = htole32(packl); 1406 dtheend -= packl; 1407 } 1408 } else 1409 pb->pb_len = htole32(packl); 1410 1411 if ((i + 1) == q->q_dst_map->dm_nsegs) { 1412 if (maccrd) 1413 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1414 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1415 else 1416 pb->pb_next = 0; 1417 } else 1418 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1419 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1420 j++; 1421 } 1422 } 1423 1424 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1425 offsetof(struct ubsec_dmachunk, d_ctx)); 1426 1427 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1428 struct ubsec_pktctx_long *ctxl; 1429 1430 ctxl = (struct ubsec_pktctx_long *)((char *)dmap->d_alloc.dma_vaddr + 1431 offsetof(struct ubsec_dmachunk, d_ctx)); 1432 1433 /* transform small context into long context */ 1434 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1435 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1436 ctxl->pc_flags = ctx.pc_flags; 1437 ctxl->pc_offset = ctx.pc_offset; 1438 for (i = 0; i < 6; i++) 1439 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1440 for (i = 0; i < 5; i++) 1441 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1442 for (i = 0; i < 5; i++) 1443 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1444 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1445 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1446 } else 1447 memcpy((char *)dmap->d_alloc.dma_vaddr + 1448 offsetof(struct ubsec_dmachunk, d_ctx), &ctx, 1449 sizeof(struct ubsec_pktctx)); 1450 1451 mutex_spin_enter(&sc->sc_mtx); 1452 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1453 sc->sc_nqueue++; 1454 ubsecstats.hst_ipackets++; 1455 ubsecstats.hst_ibytes += dmap->d_alloc.dma_map->dm_mapsize; 1456 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= ubsec_maxbatch) 1457 ubsec_feed(sc); 1458 mutex_spin_exit(&sc->sc_mtx); 1459 return (0); 1460 1461 errout: 1462 if (q != NULL) { 1463 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1464 m_freem(q->q_dst_m); 1465 1466 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1467 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1468 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1469 } 1470 if (q->q_src_map != NULL) { 1471 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1472 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1473 } 1474 1475 mutex_spin_enter(&sc->sc_mtx); 1476 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1477 mutex_spin_exit(&sc->sc_mtx); 1478 } 1479 #if 0 /* jonathan says: this openbsd code seems to be subsumed elsewhere */ 1480 if (err == EINVAL) 1481 ubsecstats.hst_invalid++; 1482 else 1483 ubsecstats.hst_nomem++; 1484 #endif 1485 if (err != ERESTART) { 1486 crp->crp_etype = err; 1487 crypto_done(crp); 1488 } else { 1489 sc->sc_needwakeup |= CRYPTO_SYMQ; 1490 } 1491 return (err); 1492 } 1493 1494 static void 1495 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1496 { 1497 struct cryptop *crp = (struct cryptop *)q->q_crp; 1498 struct cryptodesc *crd; 1499 struct ubsec_dma *dmap = q->q_dma; 1500 1501 ubsecstats.hst_opackets++; 1502 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1503 1504 bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, 1505 dmap->d_alloc.dma_map->dm_mapsize, 1506 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1507 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1508 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1509 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1510 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1511 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1512 } 1513 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 1514 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1515 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1516 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1517 1518 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1519 m_freem(q->q_src_m); 1520 crp->crp_buf = (void *)q->q_dst_m; 1521 } 1522 1523 /* copy out IV for future use */ 1524 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1525 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1526 if (crd->crd_alg != CRYPTO_DES_CBC && 1527 crd->crd_alg != CRYPTO_3DES_CBC) 1528 continue; 1529 if (crp->crp_flags & CRYPTO_F_IMBUF) 1530 m_copydata((struct mbuf *)crp->crp_buf, 1531 crd->crd_skip + crd->crd_len - 8, 8, 1532 (void *)sc->sc_sessions[q->q_sesn].ses_iv); 1533 else if (crp->crp_flags & CRYPTO_F_IOV) { 1534 cuio_copydata((struct uio *)crp->crp_buf, 1535 crd->crd_skip + crd->crd_len - 8, 8, 1536 (void *)sc->sc_sessions[q->q_sesn].ses_iv); 1537 } 1538 break; 1539 } 1540 } 1541 1542 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1543 if (crd->crd_alg != CRYPTO_MD5_HMAC_96 && 1544 crd->crd_alg != CRYPTO_SHA1_HMAC_96) 1545 continue; 1546 if (crp->crp_flags & CRYPTO_F_IMBUF) 1547 m_copyback((struct mbuf *)crp->crp_buf, 1548 crd->crd_inject, 12, 1549 (void *)dmap->d_dma->d_macbuf); 1550 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1551 bcopy((void *)dmap->d_dma->d_macbuf, 1552 crp->crp_mac, 12); 1553 break; 1554 } 1555 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1556 crypto_done(crp); 1557 } 1558 1559 static void 1560 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1561 { 1562 int i, j, dlen, slen; 1563 char *dptr, *sptr; 1564 1565 j = 0; 1566 sptr = srcm->m_data; 1567 slen = srcm->m_len; 1568 dptr = dstm->m_data; 1569 dlen = dstm->m_len; 1570 1571 while (1) { 1572 for (i = 0; i < min(slen, dlen); i++) { 1573 if (j < hoffset || j >= toffset) 1574 *dptr++ = *sptr++; 1575 slen--; 1576 dlen--; 1577 j++; 1578 } 1579 if (slen == 0) { 1580 srcm = srcm->m_next; 1581 if (srcm == NULL) 1582 return; 1583 sptr = srcm->m_data; 1584 slen = srcm->m_len; 1585 } 1586 if (dlen == 0) { 1587 dstm = dstm->m_next; 1588 if (dstm == NULL) 1589 return; 1590 dptr = dstm->m_data; 1591 dlen = dstm->m_len; 1592 } 1593 } 1594 } 1595 1596 /* 1597 * feed the key generator, must be called at splnet() or higher. 1598 */ 1599 static void 1600 ubsec_feed2(struct ubsec_softc *sc) 1601 { 1602 struct ubsec_q2 *q; 1603 1604 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1605 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1606 break; 1607 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1608 1609 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1610 q->q_mcr.dma_map->dm_mapsize, 1611 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1612 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1613 q->q_ctx.dma_map->dm_mapsize, 1614 BUS_DMASYNC_PREWRITE); 1615 1616 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1617 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1618 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, /*q,*/ q_next); 1619 --sc->sc_nqueue2; 1620 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1621 } 1622 } 1623 1624 /* 1625 * Callback for handling random numbers 1626 */ 1627 static void 1628 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1629 { 1630 struct cryptkop *krp; 1631 struct ubsec_ctx_keyop *ctx; 1632 1633 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1634 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1635 q->q_ctx.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1636 1637 switch (q->q_type) { 1638 #ifndef UBSEC_NO_RNG 1639 case UBS_CTXOP_RNGSHA1: 1640 case UBS_CTXOP_RNGBYPASS: { 1641 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1642 u_int32_t *p; 1643 int i; 1644 1645 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 1646 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1647 p = (u_int32_t *)rng->rng_buf.dma_vaddr; 1648 #ifndef __NetBSD__ 1649 for (i = 0; i < UBSEC_RNG_BUFSIZ; p++, i++) 1650 add_true_randomness(letoh32(*p)); 1651 rng->rng_used = 0; 1652 #else 1653 i = UBSEC_RNG_BUFSIZ * sizeof(u_int32_t); 1654 rnd_add_data(&sc->sc_rnd_source, (char *)p, i, i * NBBY); 1655 sc->sc_rng_need -= i; 1656 rng->rng_used = 0; 1657 #endif 1658 #ifdef __OpenBSD__ 1659 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 1660 #else 1661 if (sc->sc_rng_need > 0) { 1662 callout_reset(&sc->sc_rngto, sc->sc_rnghz, 1663 ubsec_rng, sc); 1664 } 1665 #endif 1666 break; 1667 } 1668 #endif 1669 case UBS_CTXOP_MODEXP: { 1670 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1671 u_int rlen, clen; 1672 1673 krp = me->me_krp; 1674 rlen = (me->me_modbits + 7) / 8; 1675 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1676 1677 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 1678 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1679 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 1680 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1681 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 1682 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1683 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 1684 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1685 1686 if (clen < rlen) 1687 krp->krp_status = E2BIG; 1688 else { 1689 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1690 memset(krp->krp_param[krp->krp_iparams].crp_p, 0, 1691 (krp->krp_param[krp->krp_iparams].crp_nbits 1692 + 7) / 8); 1693 bcopy(me->me_C.dma_vaddr, 1694 krp->krp_param[krp->krp_iparams].crp_p, 1695 (me->me_modbits + 7) / 8); 1696 } else 1697 ubsec_kshift_l(me->me_shiftbits, 1698 me->me_C.dma_vaddr, me->me_normbits, 1699 krp->krp_param[krp->krp_iparams].crp_p, 1700 krp->krp_param[krp->krp_iparams].crp_nbits); 1701 } 1702 1703 crypto_kdone(krp); 1704 1705 /* bzero all potentially sensitive data */ 1706 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 1707 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 1708 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 1709 memset(me->me_q.q_ctx.dma_vaddr, 0, me->me_q.q_ctx.dma_size); 1710 1711 /* Can't free here, so put us on the free list. */ 1712 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1713 break; 1714 } 1715 case UBS_CTXOP_RSAPRIV: { 1716 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1717 u_int len; 1718 1719 krp = rp->rpr_krp; 1720 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 0, 1721 rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1722 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 0, 1723 rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1724 1725 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1726 bcopy(rp->rpr_msgout.dma_vaddr, 1727 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1728 1729 crypto_kdone(krp); 1730 1731 memset(rp->rpr_msgin.dma_vaddr, 0, rp->rpr_msgin.dma_size); 1732 memset(rp->rpr_msgout.dma_vaddr, 0, rp->rpr_msgout.dma_size); 1733 memset(rp->rpr_q.q_ctx.dma_vaddr, 0, rp->rpr_q.q_ctx.dma_size); 1734 1735 /* Can't free here, so put us on the free list. */ 1736 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1737 break; 1738 } 1739 default: 1740 printf("%s: unknown ctx op: %x\n", device_xname(sc->sc_dev), 1741 letoh16(ctx->ctx_op)); 1742 break; 1743 } 1744 } 1745 1746 #ifndef UBSEC_NO_RNG 1747 1748 static void 1749 ubsec_rng_get(size_t bytes, void *vsc) 1750 { 1751 struct ubsec_softc *sc = vsc; 1752 1753 mutex_spin_enter(&sc->sc_mtx); 1754 sc->sc_rng_need = bytes; 1755 ubsec_rng_locked(sc); 1756 mutex_spin_exit(&sc->sc_mtx); 1757 1758 } 1759 1760 static void 1761 ubsec_rng(void *vsc) 1762 { 1763 struct ubsec_softc *sc = vsc; 1764 mutex_spin_enter(&sc->sc_mtx); 1765 ubsec_rng_locked(sc); 1766 mutex_spin_exit(&sc->sc_mtx); 1767 } 1768 1769 static void 1770 ubsec_rng_locked(void *vsc) 1771 { 1772 struct ubsec_softc *sc = vsc; 1773 struct ubsec_q2_rng *rng = &sc->sc_rng; 1774 struct ubsec_mcr *mcr; 1775 struct ubsec_ctx_rngbypass *ctx; 1776 1777 mutex_spin_enter(&sc->sc_mtx); 1778 if (rng->rng_used) { 1779 mutex_spin_exit(&sc->sc_mtx); 1780 return; 1781 } 1782 1783 if (sc->sc_rng_need < 1) { 1784 callout_stop(&sc->sc_rngto); 1785 mutex_spin_exit(&sc->sc_mtx); 1786 return; 1787 } 1788 1789 sc->sc_nqueue2++; 1790 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1791 goto out; 1792 1793 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1794 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1795 1796 mcr->mcr_pkts = htole16(1); 1797 mcr->mcr_flags = 0; 1798 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1799 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1800 mcr->mcr_ipktbuf.pb_len = 0; 1801 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1802 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1803 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1804 UBS_PKTBUF_LEN); 1805 mcr->mcr_opktbuf.pb_next = 0; 1806 1807 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1808 ctx->rbp_op = htole16(UBS_CTXOP_RNGSHA1); 1809 rng->rng_q.q_type = UBS_CTXOP_RNGSHA1; 1810 1811 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 1812 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1813 1814 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1815 rng->rng_used = 1; 1816 ubsec_feed2(sc); 1817 ubsecstats.hst_rng++; 1818 mutex_spin_exit(&sc->sc_mtx); 1819 1820 return; 1821 1822 out: 1823 /* 1824 * Something weird happened, generate our own call back. 1825 */ 1826 sc->sc_nqueue2--; 1827 mutex_spin_exit(&sc->sc_mtx); 1828 #ifdef __OpenBSD__ 1829 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 1830 #else 1831 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1832 #endif 1833 } 1834 #endif /* UBSEC_NO_RNG */ 1835 1836 static int 1837 ubsec_dma_malloc(struct ubsec_softc *sc, bus_size_t size, 1838 struct ubsec_dma_alloc *dma,int mapflags) 1839 { 1840 int r; 1841 1842 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1843 &dma->dma_seg, 1, &dma->dma_nseg, BUS_DMA_NOWAIT)) != 0) 1844 goto fail_0; 1845 1846 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1847 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1848 goto fail_1; 1849 1850 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1851 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1852 goto fail_2; 1853 1854 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1855 size, NULL, BUS_DMA_NOWAIT)) != 0) 1856 goto fail_3; 1857 1858 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1859 dma->dma_size = size; 1860 return (0); 1861 1862 fail_3: 1863 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1864 fail_2: 1865 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1866 fail_1: 1867 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1868 fail_0: 1869 dma->dma_map = NULL; 1870 return (r); 1871 } 1872 1873 static void 1874 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1875 { 1876 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1877 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 1878 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1879 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1880 } 1881 1882 /* 1883 * Resets the board. Values in the regesters are left as is 1884 * from the reset (i.e. initial values are assigned elsewhere). 1885 */ 1886 static void 1887 ubsec_reset_board(struct ubsec_softc *sc) 1888 { 1889 volatile u_int32_t ctrl; 1890 1891 ctrl = READ_REG(sc, BS_CTRL); 1892 ctrl |= BS_CTRL_RESET; 1893 WRITE_REG(sc, BS_CTRL, ctrl); 1894 1895 /* 1896 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1897 */ 1898 DELAY(10); 1899 } 1900 1901 /* 1902 * Init Broadcom registers 1903 */ 1904 static void 1905 ubsec_init_board(struct ubsec_softc *sc) 1906 { 1907 u_int32_t ctrl; 1908 1909 ctrl = READ_REG(sc, BS_CTRL); 1910 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1911 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1912 1913 /* 1914 * XXX: Sam Leffler's code has (UBS_FLAGS_KEY|UBS_FLAGS_RNG)). 1915 * anyone got hw docs? 1916 */ 1917 if (sc->sc_flags & UBS_FLAGS_KEY) 1918 ctrl |= BS_CTRL_MCR2INT; 1919 else 1920 ctrl &= ~BS_CTRL_MCR2INT; 1921 1922 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1923 ctrl &= ~BS_CTRL_SWNORM; 1924 1925 WRITE_REG(sc, BS_CTRL, ctrl); 1926 } 1927 1928 /* 1929 * Init Broadcom PCI registers 1930 */ 1931 static void 1932 ubsec_init_pciregs(struct pci_attach_args *pa) 1933 { 1934 pci_chipset_tag_t pc = pa->pa_pc; 1935 u_int32_t misc; 1936 1937 /* 1938 * This will set the cache line size to 1, this will 1939 * force the BCM58xx chip just to do burst read/writes. 1940 * Cache line read/writes are to slow 1941 */ 1942 misc = pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 1943 misc = (misc & ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)) 1944 | ((UBS_DEF_CACHELINE & 0xff) << PCI_CACHELINE_SHIFT); 1945 pci_conf_write(pc, pa->pa_tag, PCI_BHLC_REG, misc); 1946 } 1947 1948 /* 1949 * Clean up after a chip crash. 1950 * It is assumed that the caller in splnet() 1951 */ 1952 static void 1953 ubsec_cleanchip(struct ubsec_softc *sc) 1954 { 1955 struct ubsec_q *q; 1956 1957 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 1958 q = SIMPLEQ_FIRST(&sc->sc_qchip); 1959 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 1960 ubsec_free_q(sc, q); 1961 } 1962 sc->sc_nqchip = 0; 1963 } 1964 1965 /* 1966 * free a ubsec_q 1967 * It is assumed that the caller is within splnet() 1968 */ 1969 static int 1970 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 1971 { 1972 struct ubsec_q *q2; 1973 struct cryptop *crp; 1974 int npkts; 1975 int i; 1976 1977 npkts = q->q_nstacked_mcrs; 1978 1979 for (i = 0; i < npkts; i++) { 1980 if(q->q_stacked_mcr[i]) { 1981 q2 = q->q_stacked_mcr[i]; 1982 1983 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 1984 m_freem(q2->q_dst_m); 1985 1986 crp = (struct cryptop *)q2->q_crp; 1987 1988 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 1989 1990 crp->crp_etype = EFAULT; 1991 crypto_done(crp); 1992 } else { 1993 break; 1994 } 1995 } 1996 1997 /* 1998 * Free header MCR 1999 */ 2000 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2001 m_freem(q->q_dst_m); 2002 2003 crp = (struct cryptop *)q->q_crp; 2004 2005 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2006 2007 crp->crp_etype = EFAULT; 2008 crypto_done(crp); 2009 return(0); 2010 } 2011 2012 /* 2013 * Routine to reset the chip and clean up. 2014 * It is assumed that the caller is in splnet() 2015 */ 2016 static void 2017 ubsec_totalreset(struct ubsec_softc *sc) 2018 { 2019 ubsec_reset_board(sc); 2020 ubsec_init_board(sc); 2021 ubsec_cleanchip(sc); 2022 } 2023 2024 static int 2025 ubsec_dmamap_aligned(bus_dmamap_t map) 2026 { 2027 int i; 2028 2029 for (i = 0; i < map->dm_nsegs; i++) { 2030 if (map->dm_segs[i].ds_addr & 3) 2031 return (0); 2032 if ((i != (map->dm_nsegs - 1)) && 2033 (map->dm_segs[i].ds_len & 3)) 2034 return (0); 2035 } 2036 return (1); 2037 } 2038 2039 #ifdef __OpenBSD__ 2040 struct ubsec_softc * 2041 ubsec_kfind(struct cryptkop *krp) 2042 { 2043 struct ubsec_softc *sc; 2044 int i; 2045 2046 for (i = 0; i < ubsec_cd.cd_ndevs; i++) { 2047 sc = ubsec_cd.cd_devs[i]; 2048 if (sc == NULL) 2049 continue; 2050 if (sc->sc_cid == krp->krp_hid) 2051 return (sc); 2052 } 2053 return (NULL); 2054 } 2055 #endif 2056 2057 static void 2058 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2059 { 2060 switch (q->q_type) { 2061 case UBS_CTXOP_MODEXP: { 2062 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2063 2064 ubsec_dma_free(sc, &me->me_q.q_mcr); 2065 ubsec_dma_free(sc, &me->me_q.q_ctx); 2066 ubsec_dma_free(sc, &me->me_M); 2067 ubsec_dma_free(sc, &me->me_E); 2068 ubsec_dma_free(sc, &me->me_C); 2069 ubsec_dma_free(sc, &me->me_epb); 2070 free(me, M_DEVBUF); 2071 break; 2072 } 2073 case UBS_CTXOP_RSAPRIV: { 2074 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2075 2076 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2077 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2078 ubsec_dma_free(sc, &rp->rpr_msgin); 2079 ubsec_dma_free(sc, &rp->rpr_msgout); 2080 free(rp, M_DEVBUF); 2081 break; 2082 } 2083 default: 2084 printf("%s: invalid kfree 0x%x\n", device_xname(sc->sc_dev), 2085 q->q_type); 2086 break; 2087 } 2088 } 2089 2090 static int 2091 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2092 { 2093 struct ubsec_softc *sc; 2094 int r; 2095 2096 if (krp == NULL || krp->krp_callback == NULL) 2097 return (EINVAL); 2098 #ifdef __OpenBSD__ 2099 if ((sc = ubsec_kfind(krp)) == NULL) 2100 return (EINVAL); 2101 #else 2102 sc = arg; 2103 KASSERT(sc != NULL /*, ("ubsec_kprocess: null softc")*/); 2104 #endif 2105 2106 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2107 struct ubsec_q2 *q; 2108 2109 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2110 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, /*q,*/ q_next); 2111 ubsec_kfree(sc, q); 2112 } 2113 2114 switch (krp->krp_op) { 2115 case CRK_MOD_EXP: 2116 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2117 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2118 else 2119 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2120 break; 2121 case CRK_MOD_EXP_CRT: 2122 r = ubsec_kprocess_rsapriv(sc, krp, hint); 2123 break; 2124 default: 2125 printf("%s: kprocess: invalid op 0x%x\n", 2126 device_xname(sc->sc_dev), krp->krp_op); 2127 krp->krp_status = EOPNOTSUPP; 2128 crypto_kdone(krp); 2129 r = 0; 2130 } 2131 return (r); 2132 } 2133 2134 /* 2135 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2136 */ 2137 static int 2138 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, 2139 int hint) 2140 { 2141 struct ubsec_q2_modexp *me; 2142 struct ubsec_mcr *mcr; 2143 struct ubsec_ctx_modexp *ctx; 2144 struct ubsec_pktbuf *epb; 2145 int err = 0; 2146 u_int nbits, normbits, mbits, shiftbits, ebits; 2147 2148 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2149 if (me == NULL) { 2150 err = ENOMEM; 2151 goto errout; 2152 } 2153 memset(me, 0, sizeof *me); 2154 me->me_krp = krp; 2155 me->me_q.q_type = UBS_CTXOP_MODEXP; 2156 2157 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2158 if (nbits <= 512) 2159 normbits = 512; 2160 else if (nbits <= 768) 2161 normbits = 768; 2162 else if (nbits <= 1024) 2163 normbits = 1024; 2164 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2165 normbits = 1536; 2166 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2167 normbits = 2048; 2168 else { 2169 err = E2BIG; 2170 goto errout; 2171 } 2172 2173 shiftbits = normbits - nbits; 2174 2175 me->me_modbits = nbits; 2176 me->me_shiftbits = shiftbits; 2177 me->me_normbits = normbits; 2178 2179 /* Sanity check: result bits must be >= true modulus bits. */ 2180 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2181 err = ERANGE; 2182 goto errout; 2183 } 2184 2185 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2186 &me->me_q.q_mcr, 0)) { 2187 err = ENOMEM; 2188 goto errout; 2189 } 2190 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2191 2192 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2193 &me->me_q.q_ctx, 0)) { 2194 err = ENOMEM; 2195 goto errout; 2196 } 2197 2198 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2199 if (mbits > nbits) { 2200 err = E2BIG; 2201 goto errout; 2202 } 2203 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2204 err = ENOMEM; 2205 goto errout; 2206 } 2207 ubsec_kshift_r(shiftbits, 2208 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2209 me->me_M.dma_vaddr, normbits); 2210 2211 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2212 err = ENOMEM; 2213 goto errout; 2214 } 2215 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2216 2217 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2218 if (ebits > nbits) { 2219 err = E2BIG; 2220 goto errout; 2221 } 2222 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2223 err = ENOMEM; 2224 goto errout; 2225 } 2226 ubsec_kshift_r(shiftbits, 2227 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2228 me->me_E.dma_vaddr, normbits); 2229 2230 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2231 &me->me_epb, 0)) { 2232 err = ENOMEM; 2233 goto errout; 2234 } 2235 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2236 epb->pb_addr = htole32(me->me_E.dma_paddr); 2237 epb->pb_next = 0; 2238 epb->pb_len = htole32(normbits / 8); 2239 2240 #ifdef UBSEC_DEBUG 2241 if (ubsec_debug) { 2242 printf("Epb "); 2243 ubsec_dump_pb(epb); 2244 } 2245 #endif 2246 2247 mcr->mcr_pkts = htole16(1); 2248 mcr->mcr_flags = 0; 2249 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2250 mcr->mcr_reserved = 0; 2251 mcr->mcr_pktlen = 0; 2252 2253 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2254 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2255 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2256 2257 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2258 mcr->mcr_opktbuf.pb_next = 0; 2259 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2260 2261 #ifdef DIAGNOSTIC 2262 /* Misaligned output buffer will hang the chip. */ 2263 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2264 panic("%s: modexp invalid addr 0x%x", 2265 device_xname(sc->sc_dev), letoh32(mcr->mcr_opktbuf.pb_addr)); 2266 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2267 panic("%s: modexp invalid len 0x%x", 2268 device_xname(sc->sc_dev), letoh32(mcr->mcr_opktbuf.pb_len)); 2269 #endif 2270 2271 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2272 memset(ctx, 0, sizeof(*ctx)); 2273 ubsec_kshift_r(shiftbits, 2274 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2275 ctx->me_N, normbits); 2276 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2277 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2278 ctx->me_E_len = htole16(nbits); 2279 ctx->me_N_len = htole16(nbits); 2280 2281 #ifdef UBSEC_DEBUG 2282 if (ubsec_debug) { 2283 ubsec_dump_mcr(mcr); 2284 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2285 } 2286 #endif 2287 2288 /* 2289 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2290 * everything else. 2291 */ 2292 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2293 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2294 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2295 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2296 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2297 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2298 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2299 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2300 2301 /* Enqueue and we're done... */ 2302 mutex_spin_enter(&sc->sc_mtx); 2303 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2304 ubsec_feed2(sc); 2305 ubsecstats.hst_modexp++; 2306 mutex_spin_exit(&sc->sc_mtx); 2307 2308 return (0); 2309 2310 errout: 2311 if (me != NULL) { 2312 if (me->me_q.q_mcr.dma_map != NULL) 2313 ubsec_dma_free(sc, &me->me_q.q_mcr); 2314 if (me->me_q.q_ctx.dma_map != NULL) { 2315 memset(me->me_q.q_ctx.dma_vaddr, 0, me->me_q.q_ctx.dma_size); 2316 ubsec_dma_free(sc, &me->me_q.q_ctx); 2317 } 2318 if (me->me_M.dma_map != NULL) { 2319 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2320 ubsec_dma_free(sc, &me->me_M); 2321 } 2322 if (me->me_E.dma_map != NULL) { 2323 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2324 ubsec_dma_free(sc, &me->me_E); 2325 } 2326 if (me->me_C.dma_map != NULL) { 2327 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2328 ubsec_dma_free(sc, &me->me_C); 2329 } 2330 if (me->me_epb.dma_map != NULL) 2331 ubsec_dma_free(sc, &me->me_epb); 2332 free(me, M_DEVBUF); 2333 } 2334 krp->krp_status = err; 2335 crypto_kdone(krp); 2336 return (0); 2337 } 2338 2339 /* 2340 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2341 */ 2342 static int 2343 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, 2344 int hint) 2345 { 2346 struct ubsec_q2_modexp *me; 2347 struct ubsec_mcr *mcr; 2348 struct ubsec_ctx_modexp *ctx; 2349 struct ubsec_pktbuf *epb; 2350 int err = 0; 2351 u_int nbits, normbits, mbits, shiftbits, ebits; 2352 2353 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2354 if (me == NULL) { 2355 err = ENOMEM; 2356 goto errout; 2357 } 2358 memset(me, 0, sizeof *me); 2359 me->me_krp = krp; 2360 me->me_q.q_type = UBS_CTXOP_MODEXP; 2361 2362 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2363 if (nbits <= 512) 2364 normbits = 512; 2365 else if (nbits <= 768) 2366 normbits = 768; 2367 else if (nbits <= 1024) 2368 normbits = 1024; 2369 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2370 normbits = 1536; 2371 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2372 normbits = 2048; 2373 else { 2374 err = E2BIG; 2375 goto errout; 2376 } 2377 2378 shiftbits = normbits - nbits; 2379 2380 /* XXX ??? */ 2381 me->me_modbits = nbits; 2382 me->me_shiftbits = shiftbits; 2383 me->me_normbits = normbits; 2384 2385 /* Sanity check: result bits must be >= true modulus bits. */ 2386 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2387 err = ERANGE; 2388 goto errout; 2389 } 2390 2391 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2392 &me->me_q.q_mcr, 0)) { 2393 err = ENOMEM; 2394 goto errout; 2395 } 2396 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2397 2398 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2399 &me->me_q.q_ctx, 0)) { 2400 err = ENOMEM; 2401 goto errout; 2402 } 2403 2404 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2405 if (mbits > nbits) { 2406 err = E2BIG; 2407 goto errout; 2408 } 2409 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2410 err = ENOMEM; 2411 goto errout; 2412 } 2413 memset(me->me_M.dma_vaddr, 0, normbits / 8); 2414 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2415 me->me_M.dma_vaddr, (mbits + 7) / 8); 2416 2417 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2418 err = ENOMEM; 2419 goto errout; 2420 } 2421 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2422 2423 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2424 if (ebits > nbits) { 2425 err = E2BIG; 2426 goto errout; 2427 } 2428 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2429 err = ENOMEM; 2430 goto errout; 2431 } 2432 memset(me->me_E.dma_vaddr, 0, normbits / 8); 2433 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2434 me->me_E.dma_vaddr, (ebits + 7) / 8); 2435 2436 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2437 &me->me_epb, 0)) { 2438 err = ENOMEM; 2439 goto errout; 2440 } 2441 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2442 epb->pb_addr = htole32(me->me_E.dma_paddr); 2443 epb->pb_next = 0; 2444 epb->pb_len = htole32((ebits + 7) / 8); 2445 2446 #ifdef UBSEC_DEBUG 2447 if (ubsec_debug) { 2448 printf("Epb "); 2449 ubsec_dump_pb(epb); 2450 } 2451 #endif 2452 2453 mcr->mcr_pkts = htole16(1); 2454 mcr->mcr_flags = 0; 2455 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2456 mcr->mcr_reserved = 0; 2457 mcr->mcr_pktlen = 0; 2458 2459 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2460 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2461 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2462 2463 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2464 mcr->mcr_opktbuf.pb_next = 0; 2465 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2466 2467 #ifdef DIAGNOSTIC 2468 /* Misaligned output buffer will hang the chip. */ 2469 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2470 panic("%s: modexp invalid addr 0x%x", 2471 device_xname(sc->sc_dev), letoh32(mcr->mcr_opktbuf.pb_addr)); 2472 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2473 panic("%s: modexp invalid len 0x%x", 2474 device_xname(sc->sc_dev), letoh32(mcr->mcr_opktbuf.pb_len)); 2475 #endif 2476 2477 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2478 memset(ctx, 0, sizeof(*ctx)); 2479 memcpy(ctx->me_N, krp->krp_param[UBS_MODEXP_PAR_N].crp_p, 2480 (nbits + 7) / 8); 2481 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2482 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2483 ctx->me_E_len = htole16(ebits); 2484 ctx->me_N_len = htole16(nbits); 2485 2486 #ifdef UBSEC_DEBUG 2487 if (ubsec_debug) { 2488 ubsec_dump_mcr(mcr); 2489 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2490 } 2491 #endif 2492 2493 /* 2494 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2495 * everything else. 2496 */ 2497 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2498 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2499 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2500 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2501 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2502 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2503 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2504 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2505 2506 /* Enqueue and we're done... */ 2507 mutex_spin_enter(&sc->sc_mtx); 2508 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2509 ubsec_feed2(sc); 2510 mutex_spin_exit(&sc->sc_mtx); 2511 2512 return (0); 2513 2514 errout: 2515 if (me != NULL) { 2516 if (me->me_q.q_mcr.dma_map != NULL) 2517 ubsec_dma_free(sc, &me->me_q.q_mcr); 2518 if (me->me_q.q_ctx.dma_map != NULL) { 2519 memset(me->me_q.q_ctx.dma_vaddr, 0, me->me_q.q_ctx.dma_size); 2520 ubsec_dma_free(sc, &me->me_q.q_ctx); 2521 } 2522 if (me->me_M.dma_map != NULL) { 2523 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2524 ubsec_dma_free(sc, &me->me_M); 2525 } 2526 if (me->me_E.dma_map != NULL) { 2527 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2528 ubsec_dma_free(sc, &me->me_E); 2529 } 2530 if (me->me_C.dma_map != NULL) { 2531 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2532 ubsec_dma_free(sc, &me->me_C); 2533 } 2534 if (me->me_epb.dma_map != NULL) 2535 ubsec_dma_free(sc, &me->me_epb); 2536 free(me, M_DEVBUF); 2537 } 2538 krp->krp_status = err; 2539 crypto_kdone(krp); 2540 return (0); 2541 } 2542 2543 static int 2544 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, 2545 int hint) 2546 { 2547 struct ubsec_q2_rsapriv *rp = NULL; 2548 struct ubsec_mcr *mcr; 2549 struct ubsec_ctx_rsapriv *ctx; 2550 int err = 0; 2551 u_int padlen, msglen; 2552 2553 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2554 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2555 if (msglen > padlen) 2556 padlen = msglen; 2557 2558 if (padlen <= 256) 2559 padlen = 256; 2560 else if (padlen <= 384) 2561 padlen = 384; 2562 else if (padlen <= 512) 2563 padlen = 512; 2564 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2565 padlen = 768; 2566 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2567 padlen = 1024; 2568 else { 2569 err = E2BIG; 2570 goto errout; 2571 } 2572 2573 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2574 err = E2BIG; 2575 goto errout; 2576 } 2577 2578 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2579 err = E2BIG; 2580 goto errout; 2581 } 2582 2583 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2584 err = E2BIG; 2585 goto errout; 2586 } 2587 2588 rp = malloc(sizeof *rp, M_DEVBUF, M_NOWAIT|M_ZERO); 2589 if (rp == NULL) 2590 return (ENOMEM); 2591 rp->rpr_krp = krp; 2592 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2593 2594 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2595 &rp->rpr_q.q_mcr, 0)) { 2596 err = ENOMEM; 2597 goto errout; 2598 } 2599 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2600 2601 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2602 &rp->rpr_q.q_ctx, 0)) { 2603 err = ENOMEM; 2604 goto errout; 2605 } 2606 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2607 memset(ctx, 0, sizeof *ctx); 2608 2609 /* Copy in p */ 2610 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2611 &ctx->rpr_buf[0 * (padlen / 8)], 2612 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2613 2614 /* Copy in q */ 2615 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2616 &ctx->rpr_buf[1 * (padlen / 8)], 2617 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2618 2619 /* Copy in dp */ 2620 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2621 &ctx->rpr_buf[2 * (padlen / 8)], 2622 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2623 2624 /* Copy in dq */ 2625 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2626 &ctx->rpr_buf[3 * (padlen / 8)], 2627 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2628 2629 /* Copy in pinv */ 2630 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2631 &ctx->rpr_buf[4 * (padlen / 8)], 2632 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2633 2634 msglen = padlen * 2; 2635 2636 /* Copy in input message (aligned buffer/length). */ 2637 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2638 /* Is this likely? */ 2639 err = E2BIG; 2640 goto errout; 2641 } 2642 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2643 err = ENOMEM; 2644 goto errout; 2645 } 2646 memset(rp->rpr_msgin.dma_vaddr, 0, (msglen + 7) / 8); 2647 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2648 rp->rpr_msgin.dma_vaddr, 2649 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2650 2651 /* Prepare space for output message (aligned buffer/length). */ 2652 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2653 /* Is this likely? */ 2654 err = E2BIG; 2655 goto errout; 2656 } 2657 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2658 err = ENOMEM; 2659 goto errout; 2660 } 2661 memset(rp->rpr_msgout.dma_vaddr, 0, (msglen + 7) / 8); 2662 2663 mcr->mcr_pkts = htole16(1); 2664 mcr->mcr_flags = 0; 2665 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2666 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2667 mcr->mcr_ipktbuf.pb_next = 0; 2668 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2669 mcr->mcr_reserved = 0; 2670 mcr->mcr_pktlen = htole16(msglen); 2671 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2672 mcr->mcr_opktbuf.pb_next = 0; 2673 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2674 2675 #ifdef DIAGNOSTIC 2676 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2677 panic("%s: rsapriv: invalid msgin 0x%lx(0x%lx)", 2678 device_xname(sc->sc_dev), (u_long) rp->rpr_msgin.dma_paddr, 2679 (u_long) rp->rpr_msgin.dma_size); 2680 } 2681 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2682 panic("%s: rsapriv: invalid msgout 0x%lx(0x%lx)", 2683 device_xname(sc->sc_dev), (u_long) rp->rpr_msgout.dma_paddr, 2684 (u_long) rp->rpr_msgout.dma_size); 2685 } 2686 #endif 2687 2688 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2689 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2690 ctx->rpr_q_len = htole16(padlen); 2691 ctx->rpr_p_len = htole16(padlen); 2692 2693 /* 2694 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2695 * everything else. 2696 */ 2697 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 2698 0, rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2699 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 2700 0, rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2701 2702 /* Enqueue and we're done... */ 2703 mutex_spin_enter(&sc->sc_mtx); 2704 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2705 ubsec_feed2(sc); 2706 ubsecstats.hst_modexpcrt++; 2707 mutex_spin_exit(&sc->sc_mtx); 2708 return (0); 2709 2710 errout: 2711 if (rp != NULL) { 2712 if (rp->rpr_q.q_mcr.dma_map != NULL) 2713 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2714 if (rp->rpr_msgin.dma_map != NULL) { 2715 memset(rp->rpr_msgin.dma_vaddr, 0, rp->rpr_msgin.dma_size); 2716 ubsec_dma_free(sc, &rp->rpr_msgin); 2717 } 2718 if (rp->rpr_msgout.dma_map != NULL) { 2719 memset(rp->rpr_msgout.dma_vaddr, 0, rp->rpr_msgout.dma_size); 2720 ubsec_dma_free(sc, &rp->rpr_msgout); 2721 } 2722 free(rp, M_DEVBUF); 2723 } 2724 krp->krp_status = err; 2725 crypto_kdone(krp); 2726 return (0); 2727 } 2728 2729 #ifdef UBSEC_DEBUG 2730 static void 2731 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2732 { 2733 printf("addr 0x%x (0x%x) next 0x%x\n", 2734 pb->pb_addr, pb->pb_len, pb->pb_next); 2735 } 2736 2737 static void 2738 ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *c) 2739 { 2740 printf("CTX (0x%x):\n", c->ctx_len); 2741 switch (letoh16(c->ctx_op)) { 2742 case UBS_CTXOP_RNGBYPASS: 2743 case UBS_CTXOP_RNGSHA1: 2744 break; 2745 case UBS_CTXOP_MODEXP: 2746 { 2747 struct ubsec_ctx_modexp *cx = (void *)c; 2748 int i, len; 2749 2750 printf(" Elen %u, Nlen %u\n", 2751 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2752 len = (cx->me_N_len + 7)/8; 2753 for (i = 0; i < len; i++) 2754 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2755 printf("\n"); 2756 break; 2757 } 2758 default: 2759 printf("unknown context: %x\n", c->ctx_op); 2760 } 2761 printf("END CTX\n"); 2762 } 2763 2764 static void 2765 ubsec_dump_mcr(struct ubsec_mcr *mcr) 2766 { 2767 volatile struct ubsec_mcr_add *ma; 2768 int i; 2769 2770 printf("MCR:\n"); 2771 printf(" pkts: %u, flags 0x%x\n", 2772 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2773 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2774 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2775 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2776 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2777 letoh16(ma->mcr_reserved)); 2778 printf(" %d: ipkt ", i); 2779 ubsec_dump_pb(&ma->mcr_ipktbuf); 2780 printf(" %d: opkt ", i); 2781 ubsec_dump_pb(&ma->mcr_opktbuf); 2782 ma++; 2783 } 2784 printf("END MCR\n"); 2785 } 2786 #endif /* UBSEC_DEBUG */ 2787 2788 /* 2789 * Return the number of significant bits of a big number. 2790 */ 2791 static int 2792 ubsec_ksigbits(struct crparam *cr) 2793 { 2794 u_int plen = (cr->crp_nbits + 7) / 8; 2795 int i, sig = plen * 8; 2796 u_int8_t c, *p = cr->crp_p; 2797 2798 for (i = plen - 1; i >= 0; i--) { 2799 c = p[i]; 2800 if (c != 0) { 2801 while ((c & 0x80) == 0) { 2802 sig--; 2803 c <<= 1; 2804 } 2805 break; 2806 } 2807 sig -= 8; 2808 } 2809 return (sig); 2810 } 2811 2812 static void 2813 ubsec_kshift_r(u_int shiftbits, u_int8_t *src, u_int srcbits, 2814 u_int8_t *dst, u_int dstbits) 2815 { 2816 u_int slen, dlen; 2817 int i, si, di, n; 2818 2819 slen = (srcbits + 7) / 8; 2820 dlen = (dstbits + 7) / 8; 2821 2822 for (i = 0; i < slen; i++) 2823 dst[i] = src[i]; 2824 for (i = 0; i < dlen - slen; i++) 2825 dst[slen + i] = 0; 2826 2827 n = shiftbits / 8; 2828 if (n != 0) { 2829 si = dlen - n - 1; 2830 di = dlen - 1; 2831 while (si >= 0) 2832 dst[di--] = dst[si--]; 2833 while (di >= 0) 2834 dst[di--] = 0; 2835 } 2836 2837 n = shiftbits % 8; 2838 if (n != 0) { 2839 for (i = dlen - 1; i > 0; i--) 2840 dst[i] = (dst[i] << n) | 2841 (dst[i - 1] >> (8 - n)); 2842 dst[0] = dst[0] << n; 2843 } 2844 } 2845 2846 static void 2847 ubsec_kshift_l(u_int shiftbits, u_int8_t *src, u_int srcbits, 2848 u_int8_t *dst, u_int dstbits) 2849 { 2850 int slen, dlen, i, n; 2851 2852 slen = (srcbits + 7) / 8; 2853 dlen = (dstbits + 7) / 8; 2854 2855 n = shiftbits / 8; 2856 for (i = 0; i < slen; i++) 2857 dst[i] = src[i + n]; 2858 for (i = 0; i < dlen - slen; i++) 2859 dst[slen + i] = 0; 2860 2861 n = shiftbits % 8; 2862 if (n != 0) { 2863 for (i = 0; i < (dlen - 1); i++) 2864 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2865 dst[dlen - 1] = dst[dlen - 1] >> n; 2866 } 2867 } 2868
Indexes created Wed Oct 01 19:09:53 GMT 2025