ubsec.c revision 1.43.18.2
1 /* $NetBSD: ubsec.c,v 1.43.18.2 2020/04/08 14:08:10 martin Exp $ */ 2 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.6 2003/01/23 21:06:43 sam Exp $ */ 3 /* $OpenBSD: ubsec.c,v 1.143 2009/03/27 13:31:30 reyk Exp$ */ 4 5 /* 6 * Copyright (c) 2000 Jason L. Wright (jason (at) thought.net) 7 * Copyright (c) 2000 Theo de Raadt (deraadt (at) openbsd.org) 8 * Copyright (c) 2001 Patrik Lindergren (patrik (at) ipunplugged.com) 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Effort sponsored in part by the Defense Advanced Research Projects 32 * Agency (DARPA) and Air Force Research Laboratory, Air Force 33 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 34 * 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: ubsec.c,v 1.43.18.2 2020/04/08 14:08:10 martin Exp $"); 39 40 #undef UBSEC_DEBUG 41 42 /* 43 * uBsec 5[56]01, 58xx hardware crypto accelerator 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/proc.h> 49 #include <sys/endian.h> 50 #ifdef __NetBSD__ 51 #define UBSEC_NO_RNG /* hangs on attach */ 52 #define letoh16 htole16 53 #define letoh32 htole32 54 #endif 55 #include <sys/errno.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/mbuf.h> 59 #include <sys/device.h> 60 #include <sys/module.h> 61 #include <sys/queue.h> 62 #include <sys/sysctl.h> 63 64 #include <opencrypto/cryptodev.h> 65 #include <opencrypto/xform.h> 66 #ifdef __OpenBSD__ 67 #include <dev/rndvar.h> 68 #include <sys/md5k.h> 69 #else 70 #include <sys/cprng.h> 71 #include <sys/md5.h> 72 #include <sys/rndpool.h> 73 #include <sys/rndsource.h> 74 #endif 75 #include <sys/sha1.h> 76 77 #include <dev/pci/pcireg.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pcidevs.h> 80 81 #include <dev/pci/ubsecreg.h> 82 #include <dev/pci/ubsecvar.h> 83 84 /* 85 * Prototypes and count for the pci_device structure 86 */ 87 static int ubsec_probe(device_t, cfdata_t, void *); 88 static void ubsec_attach(device_t, device_t, void *); 89 static int ubsec_detach(device_t, int); 90 static void ubsec_reset_board(struct ubsec_softc *); 91 static void ubsec_init_board(struct ubsec_softc *); 92 static void ubsec_init_pciregs(struct pci_attach_args *pa); 93 static void ubsec_cleanchip(struct ubsec_softc *); 94 static void ubsec_totalreset(struct ubsec_softc *); 95 static int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); 96 97 #ifdef __OpenBSD__ 98 struct cfattach ubsec_ca = { 99 sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 100 }; 101 102 struct cfdriver ubsec_cd = { 103 0, "ubsec", DV_DULL 104 }; 105 #else 106 CFATTACH_DECL_NEW(ubsec, sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 107 ubsec_detach, NULL); 108 extern struct cfdriver ubsec_cd; 109 #endif 110 111 /* patchable */ 112 #ifdef UBSEC_DEBUG 113 extern int ubsec_debug; 114 int ubsec_debug=1; 115 #endif 116 117 static int ubsec_intr(void *); 118 static int ubsec_newsession(void*, u_int32_t *, struct cryptoini *); 119 static int ubsec_freesession(void*, u_int64_t); 120 static int ubsec_process(void*, struct cryptop *, int hint); 121 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 122 static void ubsec_feed(struct ubsec_softc *); 123 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 124 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 125 static void ubsec_feed2(struct ubsec_softc *); 126 static void ubsec_feed4(struct ubsec_softc *); 127 #ifndef UBSEC_NO_RNG 128 static void ubsec_rng(void *); 129 static void ubsec_rng_locked(void *); 130 static void ubsec_rng_get(size_t, void *); 131 #endif /* UBSEC_NO_RNG */ 132 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 133 struct ubsec_dma_alloc *, int); 134 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 135 static int ubsec_dmamap_aligned(bus_dmamap_t); 136 137 static int ubsec_kprocess(void*, struct cryptkop *, int); 138 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, 139 struct cryptkop *, int); 140 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, 141 struct cryptkop *, int); 142 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, 143 struct cryptkop *, int); 144 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 145 static int ubsec_ksigbits(struct crparam *); 146 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 147 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 148 149 #ifdef UBSEC_DEBUG 150 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 151 static void ubsec_dump_mcr(struct ubsec_mcr *); 152 static void ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *); 153 #endif 154 155 #define READ_REG(sc,r) \ 156 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 157 158 #define WRITE_REG(sc,reg,val) \ 159 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 160 161 #define SWAP32(x) (x) = htole32(ntohl((x))) 162 #ifndef HTOLE32 163 #define HTOLE32(x) (x) = htole32(x) 164 #endif 165 166 struct ubsec_stats ubsecstats; 167 168 /* 169 * ubsec_maxbatch controls the number of crypto ops to voluntarily 170 * collect into one submission to the hardware. This batching happens 171 * when ops are dispatched from the crypto subsystem with a hint that 172 * more are to follow immediately. These ops must also not be marked 173 * with a ``no delay'' flag. 174 */ 175 static int ubsec_maxbatch = 1; 176 177 /* 178 * ubsec_maxaggr controls the number of crypto ops to submit to the 179 * hardware as a unit. This aggregation reduces the number of interrupts 180 * to the host at the expense of increased latency (for all but the last 181 * operation). For network traffic setting this to one yields the highest 182 * performance but at the expense of more interrupt processing. 183 */ 184 static int ubsec_maxaggr = 1; 185 186 static const struct ubsec_product { 187 pci_vendor_id_t ubsec_vendor; 188 pci_product_id_t ubsec_product; 189 int ubsec_flags; 190 int ubsec_statmask; 191 int ubsec_maxaggr; 192 const char *ubsec_name; 193 } ubsec_products[] = { 194 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5501, 195 0, 196 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 197 UBS_MIN_AGGR, 198 "Bluesteel 5501" 199 }, 200 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5601, 201 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 202 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 203 UBS_MIN_AGGR, 204 "Bluesteel 5601" 205 }, 206 207 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5801, 208 0, 209 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 210 UBS_MIN_AGGR, 211 "Broadcom BCM5801" 212 }, 213 214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5802, 215 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 216 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 217 UBS_MIN_AGGR, 218 "Broadcom BCM5802" 219 }, 220 221 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5805, 222 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 223 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 224 UBS_MIN_AGGR, 225 "Broadcom BCM5805" 226 }, 227 228 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5820, 229 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 230 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 231 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 232 UBS_MIN_AGGR, 233 "Broadcom BCM5820" 234 }, 235 236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5821, 237 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 238 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 239 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 240 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 241 UBS_MIN_AGGR, 242 "Broadcom BCM5821" 243 }, 244 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_SCA1K, 245 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 246 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 247 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 248 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 249 UBS_MIN_AGGR, 250 "Sun Crypto Accelerator 1000" 251 }, 252 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_5821, 253 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 254 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 255 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 256 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 257 UBS_MIN_AGGR, 258 "Broadcom BCM5821 (Sun)" 259 }, 260 261 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5822, 262 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 263 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 264 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 265 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 266 UBS_MIN_AGGR, 267 "Broadcom BCM5822" 268 }, 269 270 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5823, 271 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 272 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 273 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 274 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 275 UBS_MIN_AGGR, 276 "Broadcom BCM5823" 277 }, 278 279 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5825, 280 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 281 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 282 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 283 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 284 UBS_MIN_AGGR, 285 "Broadcom BCM5825" 286 }, 287 288 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5860, 289 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 290 UBS_FLAGS_LONGCTX | 291 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 292 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 293 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 294 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 295 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 296 UBS_MAX_AGGR, 297 "Broadcom BCM5860" 298 }, 299 300 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5861, 301 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 302 UBS_FLAGS_LONGCTX | 303 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 304 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 305 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 306 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 307 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 308 UBS_MAX_AGGR, 309 "Broadcom BCM5861" 310 }, 311 312 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5862, 313 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 314 UBS_FLAGS_LONGCTX | 315 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 316 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 317 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 318 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 319 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 320 UBS_MAX_AGGR, 321 "Broadcom BCM5862" 322 }, 323 324 { 0, 0, 325 0, 326 0, 327 0, 328 NULL 329 } 330 }; 331 332 static const struct ubsec_product * 333 ubsec_lookup(const struct pci_attach_args *pa) 334 { 335 const struct ubsec_product *up; 336 337 for (up = ubsec_products; up->ubsec_name != NULL; up++) { 338 if (PCI_VENDOR(pa->pa_id) == up->ubsec_vendor && 339 PCI_PRODUCT(pa->pa_id) == up->ubsec_product) 340 return (up); 341 } 342 return (NULL); 343 } 344 345 static int 346 ubsec_probe(device_t parent, cfdata_t match, void *aux) 347 { 348 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 349 350 if (ubsec_lookup(pa) != NULL) 351 return (1); 352 353 return (0); 354 } 355 356 static void 357 ubsec_attach(device_t parent, device_t self, void *aux) 358 { 359 struct ubsec_softc *sc = device_private(self); 360 struct pci_attach_args *pa = aux; 361 const struct ubsec_product *up; 362 pci_chipset_tag_t pc = pa->pa_pc; 363 pci_intr_handle_t ih; 364 const char *intrstr = NULL; 365 pcireg_t memtype; 366 struct ubsec_dma *dmap; 367 u_int32_t cmd, i; 368 char intrbuf[PCI_INTRSTR_LEN]; 369 370 sc->sc_dev = self; 371 sc->sc_pct = pc; 372 373 up = ubsec_lookup(pa); 374 if (up == NULL) { 375 printf("\n"); 376 panic("ubsec_attach: impossible"); 377 } 378 379 pci_aprint_devinfo_fancy(pa, "Crypto processor", up->ubsec_name, 1); 380 381 SIMPLEQ_INIT(&sc->sc_queue); 382 SIMPLEQ_INIT(&sc->sc_qchip); 383 SIMPLEQ_INIT(&sc->sc_queue2); 384 SIMPLEQ_INIT(&sc->sc_qchip2); 385 SIMPLEQ_INIT(&sc->sc_queue4); 386 SIMPLEQ_INIT(&sc->sc_qchip4); 387 SIMPLEQ_INIT(&sc->sc_q2free); 388 389 sc->sc_flags = up->ubsec_flags; 390 sc->sc_statmask = up->ubsec_statmask; 391 sc->sc_maxaggr = up->ubsec_maxaggr; 392 393 cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 394 cmd |= PCI_COMMAND_MASTER_ENABLE; 395 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, cmd); 396 397 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BS_BAR); 398 if (pci_mapreg_map(pa, BS_BAR, memtype, 0, 399 &sc->sc_st, &sc->sc_sh, NULL, &sc->sc_memsize)) { 400 aprint_error_dev(self, "can't find mem space"); 401 return; 402 } 403 404 sc->sc_dmat = pa->pa_dmat; 405 406 if (pci_intr_map(pa, &ih)) { 407 aprint_error_dev(self, "couldn't map interrupt\n"); 408 return; 409 } 410 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 411 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ubsec_intr, sc, 412 device_xname(self)); 413 if (sc->sc_ih == NULL) { 414 aprint_error_dev(self, "couldn't establish interrupt"); 415 if (intrstr != NULL) 416 aprint_error(" at %s", intrstr); 417 aprint_error("\n"); 418 return; 419 } 420 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 421 422 sc->sc_cid = crypto_get_driverid(0); 423 if (sc->sc_cid < 0) { 424 aprint_error_dev(self, "couldn't get crypto driver id\n"); 425 pci_intr_disestablish(pc, sc->sc_ih); 426 return; 427 } 428 429 sc->sc_rng_need = RND_POOLBITS / NBBY; 430 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_VM); 431 432 SIMPLEQ_INIT(&sc->sc_freequeue); 433 dmap = sc->sc_dmaa; 434 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 435 struct ubsec_q *q; 436 437 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 438 M_DEVBUF, M_ZERO|M_NOWAIT); 439 if (q == NULL) { 440 aprint_error_dev(self, 441 "can't allocate queue buffers\n"); 442 break; 443 } 444 445 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 446 &dmap->d_alloc, 0)) { 447 aprint_error_dev(self, "can't allocate dma buffers\n"); 448 free(q, M_DEVBUF); 449 break; 450 } 451 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 452 453 q->q_dma = dmap; 454 sc->sc_queuea[i] = q; 455 456 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 457 } 458 459 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 460 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 461 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 462 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 463 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC_96, 0, 0, 464 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 465 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC_96, 0, 0, 466 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 467 if (sc->sc_flags & UBS_FLAGS_AES) { 468 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 469 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 470 } 471 472 /* 473 * Reset Broadcom chip 474 */ 475 ubsec_reset_board(sc); 476 477 /* 478 * Init Broadcom specific PCI settings 479 */ 480 ubsec_init_pciregs(pa); 481 482 /* 483 * Init Broadcom chip 484 */ 485 ubsec_init_board(sc); 486 487 #ifndef UBSEC_NO_RNG 488 if (sc->sc_flags & UBS_FLAGS_RNG) { 489 if (sc->sc_flags & UBS_FLAGS_RNG4) 490 sc->sc_statmask |= BS_STAT_MCR4_DONE; 491 else 492 sc->sc_statmask |= BS_STAT_MCR2_DONE; 493 494 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 495 &sc->sc_rng.rng_q.q_mcr, 0)) 496 goto skip_rng; 497 498 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 499 &sc->sc_rng.rng_q.q_ctx, 0)) { 500 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 501 goto skip_rng; 502 } 503 504 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 505 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 506 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 507 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 508 goto skip_rng; 509 } 510 511 rndsource_setcb(&sc->sc_rnd_source, ubsec_rng_get, sc); 512 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 513 RND_TYPE_RNG, 514 RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB); 515 if (hz >= 100) 516 sc->sc_rnghz = hz / 100; 517 else 518 sc->sc_rnghz = 1; 519 #ifdef __OpenBSD__ 520 timeout_set(&sc->sc_rngto, ubsec_rng, sc); 521 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 522 #else 523 callout_init(&sc->sc_rngto, 0); 524 callout_setfunc(&sc->sc_rngto, ubsec_rng, sc); 525 callout_schedule(&sc->sc_rngto, sc->sc_rnghz); 526 #endif 527 skip_rng: 528 if (sc->sc_rnghz) 529 aprint_normal_dev(self, 530 "random number generator enabled\n"); 531 else 532 aprint_error_dev(self, 533 "WARNING: random number generator disabled\n"); 534 } 535 #endif /* UBSEC_NO_RNG */ 536 537 if (sc->sc_flags & UBS_FLAGS_KEY) { 538 sc->sc_statmask |= BS_STAT_MCR2_DONE; 539 540 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 541 ubsec_kprocess, sc); 542 #if 0 543 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 544 ubsec_kprocess, sc); 545 #endif 546 } 547 } 548 549 static int 550 ubsec_detach(device_t self, int flags) 551 { 552 struct ubsec_softc *sc = device_private(self); 553 struct ubsec_q *q, *qtmp; 554 volatile u_int32_t ctrl; 555 556 /* disable interrupts */ 557 /* XXX wait/abort current ops? where is DMAERR enabled? */ 558 ctrl = READ_REG(sc, BS_CTRL); 559 560 ctrl &= ~(BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR); 561 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) 562 ctrl &= ~BS_CTRL_MCR4INT; 563 564 WRITE_REG(sc, BS_CTRL, ctrl); 565 566 #ifndef UBSEC_NO_RNG 567 if (sc->sc_flags & UBS_FLAGS_RNG) { 568 callout_halt(&sc->sc_rngto, NULL); 569 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 570 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 571 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 572 rnd_detach_source(&sc->sc_rnd_source); 573 } 574 #endif /* UBSEC_NO_RNG */ 575 576 crypto_unregister_all(sc->sc_cid); 577 578 mutex_spin_enter(&sc->sc_mtx); 579 580 ubsec_totalreset(sc); /* XXX leaves the chip running */ 581 582 SIMPLEQ_FOREACH_SAFE(q, &sc->sc_freequeue, q_next, qtmp) { 583 ubsec_dma_free(sc, &q->q_dma->d_alloc); 584 if (q->q_src_map != NULL) 585 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 586 if (q->q_cached_dst_map != NULL) 587 bus_dmamap_destroy(sc->sc_dmat, q->q_cached_dst_map); 588 free(q, M_DEVBUF); 589 } 590 591 mutex_spin_exit(&sc->sc_mtx); 592 593 if (sc->sc_ih != NULL) { 594 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 595 sc->sc_ih = NULL; 596 } 597 598 if (sc->sc_memsize != 0) { 599 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_memsize); 600 sc->sc_memsize = 0; 601 } 602 603 return 0; 604 } 605 606 MODULE(MODULE_CLASS_DRIVER, ubsec, "pci,opencrypto"); 607 608 #ifdef _MODULE 609 #include "ioconf.c" 610 #endif 611 612 static int 613 ubsec_modcmd(modcmd_t cmd, void *data) 614 { 615 int error = 0; 616 617 switch (cmd) { 618 case MODULE_CMD_INIT: 619 #ifdef _MODULE 620 error = config_init_component(cfdriver_ioconf_ubsec, 621 cfattach_ioconf_ubsec, cfdata_ioconf_ubsec); 622 #endif 623 return error; 624 case MODULE_CMD_FINI: 625 #ifdef _MODULE 626 error = config_fini_component(cfdriver_ioconf_ubsec, 627 cfattach_ioconf_ubsec, cfdata_ioconf_ubsec); 628 #endif 629 return error; 630 default: 631 return ENOTTY; 632 } 633 } 634 635 SYSCTL_SETUP(ubsec_sysctl_init, "ubsec sysctl") 636 { 637 const struct sysctlnode *node = NULL; 638 639 sysctl_createv(clog, 0, NULL, &node, 640 CTLFLAG_PERMANENT, 641 CTLTYPE_NODE, "ubsec", 642 SYSCTL_DESCR("ubsec opetions"), 643 NULL, 0, NULL, 0, 644 CTL_HW, CTL_CREATE, CTL_EOL); 645 sysctl_createv(clog, 0, &node, NULL, 646 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 647 CTLTYPE_INT, "maxbatch", 648 SYSCTL_DESCR("max ops to batch w/o interrupt"), 649 NULL, 0, &ubsec_maxbatch, 0, 650 CTL_CREATE, CTL_EOL); 651 sysctl_createv(clog, 0, &node, NULL, 652 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 653 CTLTYPE_INT, "maxaggr", 654 SYSCTL_DESCR("max ops to aggregate under one interrupt"), 655 NULL, 0, &ubsec_maxaggr, 0, 656 CTL_CREATE, CTL_EOL); 657 658 return; 659 } 660 661 /* 662 * UBSEC Interrupt routine 663 */ 664 static int 665 ubsec_intr(void *arg) 666 { 667 struct ubsec_softc *sc = arg; 668 volatile u_int32_t stat; 669 struct ubsec_q *q; 670 struct ubsec_dma *dmap; 671 int flags; 672 int npkts = 0, i; 673 674 mutex_spin_enter(&sc->sc_mtx); 675 stat = READ_REG(sc, BS_STAT); 676 stat &= sc->sc_statmask; 677 if (stat == 0) { 678 mutex_spin_exit(&sc->sc_mtx); 679 return (0); 680 } 681 682 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 683 684 /* 685 * Check to see if we have any packets waiting for us 686 */ 687 if ((stat & BS_STAT_MCR1_DONE)) { 688 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 689 q = SIMPLEQ_FIRST(&sc->sc_qchip); 690 dmap = q->q_dma; 691 692 if ((dmap->d_dma->d_mcr.mcr_flags 693 & htole16(UBS_MCR_DONE)) == 0) 694 break; 695 696 q = SIMPLEQ_FIRST(&sc->sc_qchip); 697 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 698 699 npkts = q->q_nstacked_mcrs; 700 sc->sc_nqchip -= 1+npkts; 701 /* 702 * search for further sc_qchip ubsec_q's that share 703 * the same MCR, and complete them too, they must be 704 * at the top. 705 */ 706 for (i = 0; i < npkts; i++) { 707 if(q->q_stacked_mcr[i]) 708 ubsec_callback(sc, q->q_stacked_mcr[i]); 709 else 710 break; 711 } 712 ubsec_callback(sc, q); 713 } 714 715 /* 716 * Don't send any more packet to chip if there has been 717 * a DMAERR. 718 */ 719 if (!(stat & BS_STAT_DMAERR)) 720 ubsec_feed(sc); 721 } 722 723 /* 724 * Check to see if we have any key setups/rng's waiting for us 725 */ 726 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 727 (stat & BS_STAT_MCR2_DONE)) { 728 struct ubsec_q2 *q2; 729 struct ubsec_mcr *mcr; 730 731 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 732 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 733 734 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 735 0, q2->q_mcr.dma_map->dm_mapsize, 736 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 737 738 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 739 740 /* A bug in new devices requires to swap this field */ 741 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) 742 flags = htole16(mcr->mcr_flags); 743 else 744 flags = mcr->mcr_flags; 745 if ((flags & htole16(UBS_MCR_DONE)) == 0) { 746 bus_dmamap_sync(sc->sc_dmat, 747 q2->q_mcr.dma_map, 0, 748 q2->q_mcr.dma_map->dm_mapsize, 749 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 750 break; 751 } 752 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 753 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, /*q2,*/ q_next); 754 ubsec_callback2(sc, q2); 755 /* 756 * Don't send any more packet to chip if there has been 757 * a DMAERR. 758 */ 759 if (!(stat & BS_STAT_DMAERR)) 760 ubsec_feed2(sc); 761 } 762 } 763 if ((sc->sc_flags & UBS_FLAGS_RNG4) && (stat & BS_STAT_MCR4_DONE)) { 764 struct ubsec_q2 *q2; 765 struct ubsec_mcr *mcr; 766 767 while (!SIMPLEQ_EMPTY(&sc->sc_qchip4)) { 768 q2 = SIMPLEQ_FIRST(&sc->sc_qchip4); 769 770 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 771 0, q2->q_mcr.dma_map->dm_mapsize, 772 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 773 774 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 775 776 /* A bug in new devices requires to swap this field */ 777 flags = htole16(mcr->mcr_flags); 778 779 if ((flags & htole16(UBS_MCR_DONE)) == 0) { 780 bus_dmamap_sync(sc->sc_dmat, 781 q2->q_mcr.dma_map, 0, 782 q2->q_mcr.dma_map->dm_mapsize, 783 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 784 break; 785 } 786 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip4, q_next); 787 ubsec_callback2(sc, q2); 788 /* 789 * Don't send any more packet to chip if there has been 790 * a DMAERR. 791 */ 792 if (!(stat & BS_STAT_DMAERR)) 793 ubsec_feed4(sc); 794 } 795 } 796 797 /* 798 * Check to see if we got any DMA Error 799 */ 800 if (stat & BS_STAT_DMAERR) { 801 #ifdef UBSEC_DEBUG 802 if (ubsec_debug) { 803 volatile u_int32_t a = READ_REG(sc, BS_ERR); 804 805 printf("%s: dmaerr %s@%08x\n", device_xname(sc->sc_dev), 806 (a & BS_ERR_READ) ? "read" : "write", 807 a & BS_ERR_ADDR); 808 } 809 #endif /* UBSEC_DEBUG */ 810 ubsecstats.hst_dmaerr++; 811 ubsec_totalreset(sc); 812 ubsec_feed(sc); 813 } 814 815 if (sc->sc_needwakeup) { /* XXX check high watermark */ 816 int wkeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 817 #ifdef UBSEC_DEBUG 818 if (ubsec_debug) 819 printf("%s: wakeup crypto (%x)\n", 820 device_xname(sc->sc_dev), sc->sc_needwakeup); 821 #endif /* UBSEC_DEBUG */ 822 sc->sc_needwakeup &= ~wkeup; 823 crypto_unblock(sc->sc_cid, wkeup); 824 } 825 mutex_spin_exit(&sc->sc_mtx); 826 return (1); 827 } 828 829 /* 830 * ubsec_feed() - aggregate and post requests to chip 831 * OpenBSD comments: 832 * It is assumed that the caller set splnet() 833 */ 834 static void 835 ubsec_feed(struct ubsec_softc *sc) 836 { 837 struct ubsec_q *q, *q2; 838 int npkts, i; 839 void *v; 840 u_int32_t stat; 841 #ifdef UBSEC_DEBUG 842 static int max; 843 #endif /* UBSEC_DEBUG */ 844 845 npkts = sc->sc_nqueue; 846 if (npkts > ubsecstats.hst_maxqueue) 847 ubsecstats.hst_maxqueue = npkts; 848 if (npkts < 2) 849 goto feed1; 850 851 /* 852 * Decide how many ops to combine in a single MCR. We cannot 853 * aggregate more than UBS_MAX_AGGR because this is the number 854 * of slots defined in the data structure. Otherwise we clamp 855 * based on the tunable parameter ubsec_maxaggr. Note that 856 * aggregation can happen in two ways: either by batching ops 857 * from above or because the h/w backs up and throttles us. 858 * Aggregating ops reduces the number of interrupts to the host 859 * but also (potentially) increases the latency for processing 860 * completed ops as we only get an interrupt when all aggregated 861 * ops have completed. 862 */ 863 if (npkts > sc->sc_maxaggr) 864 npkts = sc->sc_maxaggr; 865 if (npkts > ubsec_maxaggr) 866 npkts = ubsec_maxaggr; 867 if (npkts > ubsecstats.hst_maxbatch) 868 ubsecstats.hst_maxbatch = npkts; 869 if (npkts < 2) 870 goto feed1; 871 ubsecstats.hst_totbatch += npkts-1; 872 873 if ((stat = READ_REG(sc, BS_STAT)) 874 & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 875 if (stat & BS_STAT_DMAERR) { 876 ubsec_totalreset(sc); 877 ubsecstats.hst_dmaerr++; 878 } else { 879 ubsecstats.hst_mcr1full++; 880 } 881 return; 882 } 883 884 #ifdef UBSEC_DEBUG 885 if (ubsec_debug) 886 printf("merging %d records\n", npkts); 887 /* XXX temporary aggregation statistics reporting code */ 888 if (max < npkts) { 889 max = npkts; 890 printf("%s: new max aggregate %d\n", device_xname(sc->sc_dev), 891 max); 892 } 893 #endif /* UBSEC_DEBUG */ 894 895 q = SIMPLEQ_FIRST(&sc->sc_queue); 896 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 897 --sc->sc_nqueue; 898 899 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 900 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 901 if (q->q_dst_map != NULL) 902 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 903 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 904 905 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 906 907 for (i = 0; i < q->q_nstacked_mcrs; i++) { 908 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 909 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 910 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 911 if (q2->q_dst_map != NULL) 912 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 913 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 914 q2= SIMPLEQ_FIRST(&sc->sc_queue); 915 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q2,*/ q_next); 916 --sc->sc_nqueue; 917 918 v = ((void *)&q2->q_dma->d_dma->d_mcr); 919 v = (char*)v + (sizeof(struct ubsec_mcr) - 920 sizeof(struct ubsec_mcr_add)); 921 memcpy(&q->q_dma->d_dma->d_mcradd[i], v, 922 sizeof(struct ubsec_mcr_add)); 923 q->q_stacked_mcr[i] = q2; 924 } 925 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 926 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 927 sc->sc_nqchip += npkts; 928 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 929 ubsecstats.hst_maxqchip = sc->sc_nqchip; 930 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 931 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 932 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 933 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 934 offsetof(struct ubsec_dmachunk, d_mcr)); 935 return; 936 937 feed1: 938 while (!SIMPLEQ_EMPTY(&sc->sc_queue)) { 939 if ((stat = READ_REG(sc, BS_STAT)) 940 & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 941 if (stat & BS_STAT_DMAERR) { 942 ubsec_totalreset(sc); 943 ubsecstats.hst_dmaerr++; 944 } else { 945 ubsecstats.hst_mcr1full++; 946 } 947 break; 948 } 949 950 q = SIMPLEQ_FIRST(&sc->sc_queue); 951 952 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 953 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 954 if (q->q_dst_map != NULL) 955 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 956 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 957 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 958 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 959 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 960 961 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 962 offsetof(struct ubsec_dmachunk, d_mcr)); 963 #ifdef UBSEC_DEBUG 964 if (ubsec_debug) 965 printf("feed: q->chip %p %08x stat %08x\n", 966 q, (u_int32_t)q->q_dma->d_alloc.dma_paddr, 967 stat); 968 #endif /* UBSEC_DEBUG */ 969 q = SIMPLEQ_FIRST(&sc->sc_queue); 970 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 971 --sc->sc_nqueue; 972 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 973 sc->sc_nqchip++; 974 } 975 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 976 ubsecstats.hst_maxqchip = sc->sc_nqchip; 977 } 978 979 /* 980 * Allocate a new 'session' and return an encoded session id. 'sidp' 981 * contains our registration id, and should contain an encoded session 982 * id on successful allocation. 983 */ 984 static int 985 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 986 { 987 struct cryptoini *c, *encini = NULL, *macini = NULL; 988 struct ubsec_softc *sc; 989 struct ubsec_session *ses = NULL; 990 MD5_CTX md5ctx; 991 SHA1_CTX sha1ctx; 992 int i, sesn; 993 994 sc = arg; 995 KASSERT(sc != NULL /*, ("ubsec_newsession: null softc")*/); 996 997 if (sidp == NULL || cri == NULL || sc == NULL) 998 return (EINVAL); 999 1000 for (c = cri; c != NULL; c = c->cri_next) { 1001 if (c->cri_alg == CRYPTO_MD5_HMAC_96 || 1002 c->cri_alg == CRYPTO_SHA1_HMAC_96) { 1003 if (macini) 1004 return (EINVAL); 1005 macini = c; 1006 } else if (c->cri_alg == CRYPTO_DES_CBC || 1007 c->cri_alg == CRYPTO_3DES_CBC || 1008 c->cri_alg == CRYPTO_AES_CBC) { 1009 if (encini) 1010 return (EINVAL); 1011 encini = c; 1012 } else 1013 return (EINVAL); 1014 } 1015 if (encini == NULL && macini == NULL) 1016 return (EINVAL); 1017 1018 if (encini && encini->cri_alg == CRYPTO_AES_CBC) { 1019 switch (encini->cri_klen) { 1020 case 128: 1021 case 192: 1022 case 256: 1023 break; 1024 default: 1025 return (EINVAL); 1026 } 1027 } 1028 1029 if (sc->sc_sessions == NULL) { 1030 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 1031 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 1032 if (ses == NULL) 1033 return (ENOMEM); 1034 sesn = 0; 1035 sc->sc_nsessions = 1; 1036 } else { 1037 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 1038 if (sc->sc_sessions[sesn].ses_used == 0) { 1039 ses = &sc->sc_sessions[sesn]; 1040 break; 1041 } 1042 } 1043 1044 if (ses == NULL) { 1045 sesn = sc->sc_nsessions; 1046 ses = (struct ubsec_session *)malloc((sesn + 1) * 1047 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 1048 if (ses == NULL) 1049 return (ENOMEM); 1050 memcpy(ses, sc->sc_sessions, sesn * 1051 sizeof(struct ubsec_session)); 1052 memset(sc->sc_sessions, 0, sesn * 1053 sizeof(struct ubsec_session)); 1054 free(sc->sc_sessions, M_DEVBUF); 1055 sc->sc_sessions = ses; 1056 ses = &sc->sc_sessions[sesn]; 1057 sc->sc_nsessions++; 1058 } 1059 } 1060 1061 memset(ses, 0, sizeof(struct ubsec_session)); 1062 ses->ses_used = 1; 1063 if (encini) { 1064 /* get an IV, network byte order */ 1065 #ifdef __NetBSD__ 1066 cprng_fast(ses->ses_iv, sizeof(ses->ses_iv)); 1067 #else 1068 get_random_bytes(ses->ses_iv, sizeof(ses->ses_iv)); 1069 #endif 1070 1071 /* Go ahead and compute key in ubsec's byte order */ 1072 if (encini->cri_alg == CRYPTO_AES_CBC) { 1073 memcpy(ses->ses_key, encini->cri_key, 1074 encini->cri_klen / 8); 1075 } 1076 if (encini->cri_alg == CRYPTO_DES_CBC) { 1077 memcpy(&ses->ses_key[0], encini->cri_key, 8); 1078 memcpy(&ses->ses_key[2], encini->cri_key, 8); 1079 memcpy(&ses->ses_key[4], encini->cri_key, 8); 1080 } else 1081 memcpy(ses->ses_key, encini->cri_key, 24); 1082 1083 SWAP32(ses->ses_key[0]); 1084 SWAP32(ses->ses_key[1]); 1085 SWAP32(ses->ses_key[2]); 1086 SWAP32(ses->ses_key[3]); 1087 SWAP32(ses->ses_key[4]); 1088 SWAP32(ses->ses_key[5]); 1089 } 1090 1091 if (macini) { 1092 for (i = 0; i < macini->cri_klen / 8; i++) 1093 macini->cri_key[i] ^= HMAC_IPAD_VAL; 1094 1095 if (macini->cri_alg == CRYPTO_MD5_HMAC_96) { 1096 MD5Init(&md5ctx); 1097 MD5Update(&md5ctx, macini->cri_key, 1098 macini->cri_klen / 8); 1099 MD5Update(&md5ctx, hmac_ipad_buffer, 1100 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1101 memcpy(ses->ses_hminner, md5ctx.state, 1102 sizeof(md5ctx.state)); 1103 } else { 1104 SHA1Init(&sha1ctx); 1105 SHA1Update(&sha1ctx, macini->cri_key, 1106 macini->cri_klen / 8); 1107 SHA1Update(&sha1ctx, hmac_ipad_buffer, 1108 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1109 memcpy(ses->ses_hminner, sha1ctx.state, 1110 sizeof(sha1ctx.state)); 1111 } 1112 1113 for (i = 0; i < macini->cri_klen / 8; i++) 1114 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 1115 1116 if (macini->cri_alg == CRYPTO_MD5_HMAC_96) { 1117 MD5Init(&md5ctx); 1118 MD5Update(&md5ctx, macini->cri_key, 1119 macini->cri_klen / 8); 1120 MD5Update(&md5ctx, hmac_opad_buffer, 1121 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1122 memcpy(ses->ses_hmouter, md5ctx.state, 1123 sizeof(md5ctx.state)); 1124 } else { 1125 SHA1Init(&sha1ctx); 1126 SHA1Update(&sha1ctx, macini->cri_key, 1127 macini->cri_klen / 8); 1128 SHA1Update(&sha1ctx, hmac_opad_buffer, 1129 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1130 memcpy(ses->ses_hmouter, sha1ctx.state, 1131 sizeof(sha1ctx.state)); 1132 } 1133 1134 for (i = 0; i < macini->cri_klen / 8; i++) 1135 macini->cri_key[i] ^= HMAC_OPAD_VAL; 1136 } 1137 1138 *sidp = UBSEC_SID(device_unit(sc->sc_dev), sesn); 1139 return (0); 1140 } 1141 1142 /* 1143 * Deallocate a session. 1144 */ 1145 static int 1146 ubsec_freesession(void *arg, u_int64_t tid) 1147 { 1148 struct ubsec_softc *sc; 1149 int session; 1150 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 1151 1152 sc = arg; 1153 KASSERT(sc != NULL /*, ("ubsec_freesession: null softc")*/); 1154 1155 session = UBSEC_SESSION(sid); 1156 if (session >= sc->sc_nsessions) 1157 return (EINVAL); 1158 1159 memset(&sc->sc_sessions[session], 0, sizeof(sc->sc_sessions[session])); 1160 return (0); 1161 } 1162 1163 #ifdef __FreeBSD__ /* Ugly gratuitous changes to bus_dma */ 1164 static void 1165 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, 1166 int error) 1167 { 1168 struct ubsec_operand *op = arg; 1169 1170 KASSERT(nsegs <= UBS_MAX_SCATTER 1171 /*, ("Too many DMA segments returned when mapping operand")*/); 1172 #ifdef UBSEC_DEBUG 1173 if (ubsec_debug) 1174 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 1175 (u_int) mapsize, nsegs); 1176 #endif 1177 op->mapsize = mapsize; 1178 op->nsegs = nsegs; 1179 memcpy(op->segs, seg, nsegs * sizeof (seg[0])); 1180 } 1181 #endif 1182 1183 static int 1184 ubsec_process(void *arg, struct cryptop *crp, int hint) 1185 { 1186 struct ubsec_q *q = NULL; 1187 #ifdef __OpenBSD__ 1188 int card; 1189 #endif 1190 int err = 0, i, j, nicealign; 1191 struct ubsec_softc *sc; 1192 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1193 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1194 int sskip, dskip, stheend, dtheend; 1195 int16_t coffset; 1196 struct ubsec_session *ses, key; 1197 struct ubsec_dma *dmap = NULL; 1198 u_int16_t flags = 0; 1199 int ivlen = 0, keylen = 0; 1200 1201 sc = arg; 1202 KASSERT(sc != NULL /*, ("ubsec_process: null softc")*/); 1203 1204 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1205 ubsecstats.hst_invalid++; 1206 return (EINVAL); 1207 } 1208 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1209 ubsecstats.hst_badsession++; 1210 return (EINVAL); 1211 } 1212 1213 mutex_spin_enter(&sc->sc_mtx); 1214 1215 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1216 ubsecstats.hst_queuefull++; 1217 sc->sc_needwakeup |= CRYPTO_SYMQ; 1218 mutex_spin_exit(&sc->sc_mtx); 1219 return(ERESTART); 1220 } 1221 1222 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1223 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, /*q,*/ q_next); 1224 mutex_spin_exit(&sc->sc_mtx); 1225 1226 dmap = q->q_dma; /* Save dma pointer */ 1227 /* don't lose the cached dmamaps q_src_map and q_cached_dst_map */ 1228 memset(q, 0, offsetof(struct ubsec_q, q_src_map)); 1229 memset(&key, 0, sizeof(key)); 1230 1231 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1232 q->q_dma = dmap; 1233 ses = &sc->sc_sessions[q->q_sesn]; 1234 1235 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1236 q->q_src_m = (struct mbuf *)crp->crp_buf; 1237 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1238 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1239 q->q_src_io = (struct uio *)crp->crp_buf; 1240 q->q_dst_io = (struct uio *)crp->crp_buf; 1241 } else { 1242 ubsecstats.hst_badflags++; 1243 err = EINVAL; 1244 goto errout; /* XXX we don't handle contiguous blocks! */ 1245 } 1246 1247 memset(&dmap->d_dma->d_mcr, 0, sizeof(struct ubsec_mcr)); 1248 1249 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1250 dmap->d_dma->d_mcr.mcr_flags = 0; 1251 q->q_crp = crp; 1252 1253 crd1 = crp->crp_desc; 1254 if (crd1 == NULL) { 1255 ubsecstats.hst_nodesc++; 1256 err = EINVAL; 1257 goto errout; 1258 } 1259 crd2 = crd1->crd_next; 1260 1261 if (crd2 == NULL) { 1262 if (crd1->crd_alg == CRYPTO_MD5_HMAC_96 || 1263 crd1->crd_alg == CRYPTO_SHA1_HMAC_96) { 1264 maccrd = crd1; 1265 enccrd = NULL; 1266 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1267 crd1->crd_alg == CRYPTO_3DES_CBC || 1268 crd1->crd_alg == CRYPTO_AES_CBC) { 1269 maccrd = NULL; 1270 enccrd = crd1; 1271 } else { 1272 ubsecstats.hst_badalg++; 1273 err = EINVAL; 1274 goto errout; 1275 } 1276 } else { 1277 if ((crd1->crd_alg == CRYPTO_MD5_HMAC_96 || 1278 crd1->crd_alg == CRYPTO_SHA1_HMAC_96) && 1279 (crd2->crd_alg == CRYPTO_DES_CBC || 1280 crd2->crd_alg == CRYPTO_3DES_CBC || 1281 crd2->crd_alg == CRYPTO_AES_CBC) && 1282 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1283 maccrd = crd1; 1284 enccrd = crd2; 1285 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1286 crd1->crd_alg == CRYPTO_3DES_CBC || 1287 crd1->crd_alg == CRYPTO_AES_CBC) && 1288 (crd2->crd_alg == CRYPTO_MD5_HMAC_96 || 1289 crd2->crd_alg == CRYPTO_SHA1_HMAC_96) && 1290 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1291 enccrd = crd1; 1292 maccrd = crd2; 1293 } else { 1294 /* 1295 * We cannot order the ubsec as requested 1296 */ 1297 ubsecstats.hst_badalg++; 1298 err = EINVAL; 1299 goto errout; 1300 } 1301 } 1302 1303 if (enccrd) { 1304 if (enccrd->crd_alg == CRYPTO_AES_CBC) { 1305 if ((sc->sc_flags & UBS_FLAGS_AES) == 0) { 1306 /* 1307 * We cannot order the ubsec as requested 1308 */ 1309 ubsecstats.hst_badalg++; 1310 err = EINVAL; 1311 goto errout; 1312 } 1313 flags |= htole16(UBS_PKTCTX_ENC_AES); 1314 switch (enccrd->crd_klen) { 1315 case 128: 1316 case 192: 1317 case 256: 1318 keylen = enccrd->crd_klen / 8; 1319 break; 1320 default: 1321 err = EINVAL; 1322 goto errout; 1323 } 1324 ivlen = 16; 1325 } else { 1326 flags |= htole16(UBS_PKTCTX_ENC_3DES); 1327 ivlen = 8; 1328 keylen = 24; 1329 } 1330 1331 encoffset = enccrd->crd_skip; 1332 1333 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1334 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1335 1336 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1337 memcpy(key.ses_iv, enccrd->crd_iv, ivlen); 1338 else { 1339 for (i = 0; i < (ivlen / 4); i++) 1340 key.ses_iv[i] = ses->ses_iv[i]; 1341 } 1342 1343 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1344 if (crp->crp_flags & CRYPTO_F_IMBUF) 1345 m_copyback(q->q_src_m, 1346 enccrd->crd_inject, 1347 ivlen, (void *)key.ses_iv); 1348 else if (crp->crp_flags & CRYPTO_F_IOV) 1349 cuio_copyback(q->q_src_io, 1350 enccrd->crd_inject, 1351 ivlen, (void *)key.ses_iv); 1352 } 1353 } else { 1354 flags |= htole16(UBS_PKTCTX_INBOUND); 1355 1356 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1357 memcpy(key.ses_iv, enccrd->crd_iv, ivlen); 1358 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1359 m_copydata(q->q_src_m, enccrd->crd_inject, 1360 ivlen, (void *)key.ses_iv); 1361 else if (crp->crp_flags & CRYPTO_F_IOV) 1362 cuio_copydata(q->q_src_io, 1363 enccrd->crd_inject, 8, 1364 (void *)key.ses_iv); 1365 } 1366 1367 for (i = 0; i < (keylen / 4); i++) 1368 key.ses_key[i] = ses->ses_key[i]; 1369 for (i = 0; i < (ivlen / 4); i++) 1370 SWAP32(key.ses_iv[i]); 1371 } 1372 1373 if (maccrd) { 1374 macoffset = maccrd->crd_skip; 1375 1376 if (maccrd->crd_alg == CRYPTO_MD5_HMAC_96) 1377 flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1378 else 1379 flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1380 1381 for (i = 0; i < 5; i++) { 1382 key.ses_hminner[i] = ses->ses_hminner[i]; 1383 key.ses_hmouter[i] = ses->ses_hmouter[i]; 1384 1385 HTOLE32(key.ses_hminner[i]); 1386 HTOLE32(key.ses_hmouter[i]); 1387 } 1388 } 1389 1390 if (enccrd && maccrd) { 1391 /* 1392 * ubsec cannot handle packets where the end of encryption 1393 * and authentication are not the same, or where the 1394 * encrypted part begins before the authenticated part. 1395 */ 1396 if ((encoffset + enccrd->crd_len) != 1397 (macoffset + maccrd->crd_len)) { 1398 ubsecstats.hst_lenmismatch++; 1399 err = EINVAL; 1400 goto errout; 1401 } 1402 if (enccrd->crd_skip < maccrd->crd_skip) { 1403 ubsecstats.hst_skipmismatch++; 1404 err = EINVAL; 1405 goto errout; 1406 } 1407 sskip = maccrd->crd_skip; 1408 cpskip = dskip = enccrd->crd_skip; 1409 stheend = maccrd->crd_len; 1410 dtheend = enccrd->crd_len; 1411 coffset = enccrd->crd_skip - maccrd->crd_skip; 1412 cpoffset = cpskip + dtheend; 1413 #ifdef UBSEC_DEBUG 1414 if (ubsec_debug) { 1415 printf("mac: skip %d, len %d, inject %d\n", 1416 maccrd->crd_skip, maccrd->crd_len, 1417 maccrd->crd_inject); 1418 printf("enc: skip %d, len %d, inject %d\n", 1419 enccrd->crd_skip, enccrd->crd_len, 1420 enccrd->crd_inject); 1421 printf("src: skip %d, len %d\n", sskip, stheend); 1422 printf("dst: skip %d, len %d\n", dskip, dtheend); 1423 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1424 coffset, stheend, cpskip, cpoffset); 1425 } 1426 #endif 1427 } else { 1428 cpskip = dskip = sskip = macoffset + encoffset; 1429 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1430 cpoffset = cpskip + dtheend; 1431 coffset = 0; 1432 } 1433 1434 if (q->q_src_map == NULL) { 1435 /* XXX FIXME: jonathan asks, what the heck's that 0xfff0? */ 1436 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, 1437 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { 1438 err = ENOMEM; 1439 goto errout; 1440 } 1441 } 1442 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1443 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1444 q->q_src_m, BUS_DMA_NOWAIT) != 0) { 1445 ubsecstats.hst_noload++; 1446 err = ENOMEM; 1447 goto errout; 1448 } 1449 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1450 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1451 q->q_src_io, BUS_DMA_NOWAIT) != 0) { 1452 ubsecstats.hst_noload++; 1453 err = ENOMEM; 1454 goto errout; 1455 } 1456 } 1457 nicealign = ubsec_dmamap_aligned(q->q_src_map); 1458 1459 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1460 1461 #ifdef UBSEC_DEBUG 1462 if (ubsec_debug) 1463 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1464 #endif 1465 for (i = j = 0; i < q->q_src_map->dm_nsegs; i++) { 1466 struct ubsec_pktbuf *pb; 1467 bus_size_t packl = q->q_src_map->dm_segs[i].ds_len; 1468 bus_addr_t packp = q->q_src_map->dm_segs[i].ds_addr; 1469 1470 if (sskip >= packl) { 1471 sskip -= packl; 1472 continue; 1473 } 1474 1475 packl -= sskip; 1476 packp += sskip; 1477 sskip = 0; 1478 1479 if (packl > 0xfffc) { 1480 err = EIO; 1481 goto errout; 1482 } 1483 1484 if (j == 0) 1485 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1486 else 1487 pb = &dmap->d_dma->d_sbuf[j - 1]; 1488 1489 pb->pb_addr = htole32(packp); 1490 1491 if (stheend) { 1492 if (packl > stheend) { 1493 pb->pb_len = htole32(stheend); 1494 stheend = 0; 1495 } else { 1496 pb->pb_len = htole32(packl); 1497 stheend -= packl; 1498 } 1499 } else 1500 pb->pb_len = htole32(packl); 1501 1502 if ((i + 1) == q->q_src_map->dm_nsegs) 1503 pb->pb_next = 0; 1504 else 1505 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1506 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1507 j++; 1508 } 1509 1510 if (enccrd == NULL && maccrd != NULL) { 1511 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1512 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1513 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1514 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1515 #ifdef UBSEC_DEBUG 1516 if (ubsec_debug) 1517 printf("opkt: %x %x %x\n", 1518 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1519 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1520 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1521 1522 #endif 1523 } else { 1524 if (crp->crp_flags & CRYPTO_F_IOV) { 1525 if (!nicealign) { 1526 ubsecstats.hst_iovmisaligned++; 1527 err = EINVAL; 1528 goto errout; 1529 } 1530 if (q->q_dst_map == NULL) { 1531 if (q->q_cached_dst_map == NULL) { 1532 /* 1533 * XXX: ``what the heck's that'' 1534 * 0xfff0? 1535 */ 1536 if (bus_dmamap_create(sc->sc_dmat, 1537 0xfff0, UBS_MAX_SCATTER, 0xfff0, 0, 1538 BUS_DMA_NOWAIT, 1539 &q->q_cached_dst_map) != 0) { 1540 ubsecstats.hst_nomap++; 1541 err = ENOMEM; 1542 goto errout; 1543 } 1544 } 1545 q->q_dst_map = q->q_cached_dst_map; 1546 } 1547 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1548 q->q_dst_io, BUS_DMA_NOWAIT) != 0) { 1549 ubsecstats.hst_noload++; 1550 err = ENOMEM; 1551 goto errout; 1552 } 1553 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1554 if (nicealign) { 1555 q->q_dst_m = q->q_src_m; 1556 q->q_dst_map = q->q_src_map; 1557 } else { 1558 int totlen, len; 1559 struct mbuf *m, *top, **mp; 1560 1561 ubsecstats.hst_unaligned++; 1562 totlen = q->q_src_map->dm_mapsize; 1563 if (q->q_src_m->m_flags & M_PKTHDR) { 1564 len = MHLEN; 1565 MGETHDR(m, M_DONTWAIT, MT_DATA); 1566 /*XXX FIXME: m_dup_pkthdr */ 1567 if (m && 1 /*!m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)*/) { 1568 m_free(m); 1569 m = NULL; 1570 } 1571 } else { 1572 len = MLEN; 1573 MGET(m, M_DONTWAIT, MT_DATA); 1574 } 1575 if (m == NULL) { 1576 ubsecstats.hst_nombuf++; 1577 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1578 goto errout; 1579 } 1580 if (len == MHLEN) 1581 /*XXX was M_DUP_PKTHDR*/ 1582 m_copy_pkthdr(m, q->q_src_m); 1583 if (totlen >= MINCLSIZE) { 1584 MCLGET(m, M_DONTWAIT); 1585 if ((m->m_flags & M_EXT) == 0) { 1586 m_free(m); 1587 ubsecstats.hst_nomcl++; 1588 err = sc->sc_nqueue 1589 ? ERESTART : ENOMEM; 1590 goto errout; 1591 } 1592 len = MCLBYTES; 1593 } 1594 m->m_len = len; 1595 top = NULL; 1596 mp = ⊤ 1597 1598 while (totlen > 0) { 1599 if (top) { 1600 MGET(m, M_DONTWAIT, MT_DATA); 1601 if (m == NULL) { 1602 m_freem(top); 1603 ubsecstats.hst_nombuf++; 1604 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1605 goto errout; 1606 } 1607 len = MLEN; 1608 } 1609 if (top && totlen >= MINCLSIZE) { 1610 MCLGET(m, M_DONTWAIT); 1611 if ((m->m_flags & M_EXT) == 0) { 1612 *mp = m; 1613 m_freem(top); 1614 ubsecstats.hst_nomcl++; 1615 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1616 goto errout; 1617 } 1618 len = MCLBYTES; 1619 } 1620 m->m_len = len = uimin(totlen, len); 1621 totlen -= len; 1622 *mp = m; 1623 mp = &m->m_next; 1624 } 1625 q->q_dst_m = top; 1626 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1627 cpskip, cpoffset); 1628 if (q->q_dst_map == NULL) { 1629 if (q->q_cached_dst_map == NULL) { 1630 /* XXX again, what the heck is that 0xfff0? */ 1631 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, 1632 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, 1633 &q->q_cached_dst_map) != 0) { 1634 ubsecstats.hst_nomap++; 1635 err = ENOMEM; 1636 goto errout; 1637 } 1638 } 1639 q->q_dst_map = q->q_cached_dst_map; 1640 } 1641 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1642 q->q_dst_map, q->q_dst_m, 1643 BUS_DMA_NOWAIT) != 0) { 1644 ubsecstats.hst_noload++; 1645 err = ENOMEM; 1646 goto errout; 1647 } 1648 } 1649 } else { 1650 ubsecstats.hst_badflags++; 1651 err = EINVAL; 1652 goto errout; 1653 } 1654 1655 #ifdef UBSEC_DEBUG 1656 if (ubsec_debug) 1657 printf("dst skip: %d\n", dskip); 1658 #endif 1659 for (i = j = 0; i < q->q_dst_map->dm_nsegs; i++) { 1660 struct ubsec_pktbuf *pb; 1661 bus_size_t packl = q->q_dst_map->dm_segs[i].ds_len; 1662 bus_addr_t packp = q->q_dst_map->dm_segs[i].ds_addr; 1663 1664 if (dskip >= packl) { 1665 dskip -= packl; 1666 continue; 1667 } 1668 1669 packl -= dskip; 1670 packp += dskip; 1671 dskip = 0; 1672 1673 if (packl > 0xfffc) { 1674 err = EIO; 1675 goto errout; 1676 } 1677 1678 if (j == 0) 1679 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1680 else 1681 pb = &dmap->d_dma->d_dbuf[j - 1]; 1682 1683 pb->pb_addr = htole32(packp); 1684 1685 if (dtheend) { 1686 if (packl > dtheend) { 1687 pb->pb_len = htole32(dtheend); 1688 dtheend = 0; 1689 } else { 1690 pb->pb_len = htole32(packl); 1691 dtheend -= packl; 1692 } 1693 } else 1694 pb->pb_len = htole32(packl); 1695 1696 if ((i + 1) == q->q_dst_map->dm_nsegs) { 1697 if (maccrd) 1698 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1699 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1700 else 1701 pb->pb_next = 0; 1702 } else 1703 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1704 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1705 j++; 1706 } 1707 } 1708 1709 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1710 offsetof(struct ubsec_dmachunk, d_ctx)); 1711 1712 if (enccrd && enccrd->crd_alg == CRYPTO_AES_CBC) { 1713 struct ubsec_pktctx_aes128 *aes128; 1714 struct ubsec_pktctx_aes192 *aes192; 1715 struct ubsec_pktctx_aes256 *aes256; 1716 struct ubsec_pktctx_hdr *ph; 1717 u_int8_t *ctx; 1718 1719 ctx = (u_int8_t *)(dmap->d_alloc.dma_vaddr) + 1720 offsetof(struct ubsec_dmachunk, d_ctx); 1721 1722 ph = (struct ubsec_pktctx_hdr *)ctx; 1723 ph->ph_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES); 1724 ph->ph_flags = flags; 1725 ph->ph_offset = htole16(coffset >> 2); 1726 1727 switch (enccrd->crd_klen) { 1728 case 128: 1729 aes128 = (struct ubsec_pktctx_aes128 *)ctx; 1730 ph->ph_len = htole16(sizeof(*aes128)); 1731 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_128); 1732 for (i = 0; i < 4; i++) 1733 aes128->pc_aeskey[i] = key.ses_key[i]; 1734 for (i = 0; i < 5; i++) 1735 aes128->pc_hminner[i] = key.ses_hminner[i]; 1736 for (i = 0; i < 5; i++) 1737 aes128->pc_hmouter[i] = key.ses_hmouter[i]; 1738 for (i = 0; i < 4; i++) 1739 aes128->pc_iv[i] = key.ses_iv[i]; 1740 break; 1741 case 192: 1742 aes192 = (struct ubsec_pktctx_aes192 *)ctx; 1743 ph->ph_len = htole16(sizeof(*aes192)); 1744 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_192); 1745 for (i = 0; i < 6; i++) 1746 aes192->pc_aeskey[i] = key.ses_key[i]; 1747 for (i = 0; i < 5; i++) 1748 aes192->pc_hminner[i] = key.ses_hminner[i]; 1749 for (i = 0; i < 5; i++) 1750 aes192->pc_hmouter[i] = key.ses_hmouter[i]; 1751 for (i = 0; i < 4; i++) 1752 aes192->pc_iv[i] = key.ses_iv[i]; 1753 break; 1754 case 256: 1755 aes256 = (struct ubsec_pktctx_aes256 *)ctx; 1756 ph->ph_len = htole16(sizeof(*aes256)); 1757 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_256); 1758 for (i = 0; i < 8; i++) 1759 aes256->pc_aeskey[i] = key.ses_key[i]; 1760 for (i = 0; i < 5; i++) 1761 aes256->pc_hminner[i] = key.ses_hminner[i]; 1762 for (i = 0; i < 5; i++) 1763 aes256->pc_hmouter[i] = key.ses_hmouter[i]; 1764 for (i = 0; i < 4; i++) 1765 aes256->pc_iv[i] = key.ses_iv[i]; 1766 break; 1767 } 1768 } else if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1769 struct ubsec_pktctx_3des *ctx; 1770 struct ubsec_pktctx_hdr *ph; 1771 1772 ctx = (struct ubsec_pktctx_3des *) 1773 ((u_int8_t *)(dmap->d_alloc.dma_vaddr) + 1774 offsetof(struct ubsec_dmachunk, d_ctx)); 1775 1776 ph = (struct ubsec_pktctx_hdr *)ctx; 1777 ph->ph_len = htole16(sizeof(*ctx)); 1778 ph->ph_type = htole16(UBS_PKTCTX_TYPE_IPSEC_3DES); 1779 ph->ph_flags = flags; 1780 ph->ph_offset = htole16(coffset >> 2); 1781 1782 for (i = 0; i < 6; i++) 1783 ctx->pc_deskey[i] = key.ses_key[i]; 1784 for (i = 0; i < 5; i++) 1785 ctx->pc_hminner[i] = key.ses_hminner[i]; 1786 for (i = 0; i < 5; i++) 1787 ctx->pc_hmouter[i] = key.ses_hmouter[i]; 1788 for (i = 0; i < 2; i++) 1789 ctx->pc_iv[i] = key.ses_iv[i]; 1790 } else { 1791 struct ubsec_pktctx *ctx = (struct ubsec_pktctx *) 1792 ((u_int8_t *)dmap->d_alloc.dma_vaddr + 1793 offsetof(struct ubsec_dmachunk, d_ctx)); 1794 1795 ctx->pc_flags = flags; 1796 ctx->pc_offset = htole16(coffset >> 2); 1797 for (i = 0; i < 6; i++) 1798 ctx->pc_deskey[i] = key.ses_key[i]; 1799 for (i = 0; i < 5; i++) 1800 ctx->pc_hminner[i] = key.ses_hminner[i]; 1801 for (i = 0; i < 5; i++) 1802 ctx->pc_hmouter[i] = key.ses_hmouter[i]; 1803 for (i = 0; i < 2; i++) 1804 ctx->pc_iv[i] = key.ses_iv[i]; 1805 } 1806 1807 mutex_spin_enter(&sc->sc_mtx); 1808 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1809 sc->sc_nqueue++; 1810 ubsecstats.hst_ipackets++; 1811 ubsecstats.hst_ibytes += dmap->d_alloc.dma_map->dm_mapsize; 1812 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= ubsec_maxbatch) 1813 ubsec_feed(sc); 1814 mutex_spin_exit(&sc->sc_mtx); 1815 return (0); 1816 1817 errout: 1818 if (q != NULL) { 1819 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1820 m_freem(q->q_dst_m); 1821 1822 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1823 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1824 } 1825 if (q->q_src_map != NULL) { 1826 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1827 } 1828 1829 mutex_spin_enter(&sc->sc_mtx); 1830 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1831 mutex_spin_exit(&sc->sc_mtx); 1832 } 1833 #if 0 /* jonathan says: this openbsd code seems to be subsumed elsewhere */ 1834 if (err == EINVAL) 1835 ubsecstats.hst_invalid++; 1836 else 1837 ubsecstats.hst_nomem++; 1838 #endif 1839 if (err != ERESTART) { 1840 crp->crp_etype = err; 1841 crypto_done(crp); 1842 } else { 1843 sc->sc_needwakeup |= CRYPTO_SYMQ; 1844 } 1845 return (err); 1846 } 1847 1848 static void 1849 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1850 { 1851 struct cryptop *crp = (struct cryptop *)q->q_crp; 1852 struct cryptodesc *crd; 1853 struct ubsec_dma *dmap = q->q_dma; 1854 1855 ubsecstats.hst_opackets++; 1856 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1857 1858 bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, 1859 dmap->d_alloc.dma_map->dm_mapsize, 1860 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1861 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1862 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1863 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1864 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1865 } 1866 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 1867 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1868 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1869 1870 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1871 m_freem(q->q_src_m); 1872 crp->crp_buf = (void *)q->q_dst_m; 1873 } 1874 1875 /* copy out IV for future use */ 1876 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1877 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1878 if (crd->crd_alg != CRYPTO_DES_CBC && 1879 crd->crd_alg != CRYPTO_3DES_CBC && 1880 crd->crd_alg != CRYPTO_AES_CBC) 1881 continue; 1882 if (crp->crp_flags & CRYPTO_F_IMBUF) 1883 m_copydata((struct mbuf *)crp->crp_buf, 1884 crd->crd_skip + crd->crd_len - 8, 8, 1885 (void *)sc->sc_sessions[q->q_sesn].ses_iv); 1886 else if (crp->crp_flags & CRYPTO_F_IOV) { 1887 cuio_copydata((struct uio *)crp->crp_buf, 1888 crd->crd_skip + crd->crd_len - 8, 8, 1889 (void *)sc->sc_sessions[q->q_sesn].ses_iv); 1890 } 1891 break; 1892 } 1893 } 1894 1895 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1896 if (crd->crd_alg != CRYPTO_MD5_HMAC_96 && 1897 crd->crd_alg != CRYPTO_SHA1_HMAC_96) 1898 continue; 1899 if (crp->crp_flags & CRYPTO_F_IMBUF) 1900 m_copyback((struct mbuf *)crp->crp_buf, 1901 crd->crd_inject, 12, 1902 (void *)dmap->d_dma->d_macbuf); 1903 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1904 bcopy((void *)dmap->d_dma->d_macbuf, 1905 crp->crp_mac, 12); 1906 break; 1907 } 1908 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1909 crypto_done(crp); 1910 } 1911 1912 static void 1913 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1914 { 1915 int i, j, dlen, slen; 1916 char *dptr, *sptr; 1917 1918 j = 0; 1919 sptr = srcm->m_data; 1920 slen = srcm->m_len; 1921 dptr = dstm->m_data; 1922 dlen = dstm->m_len; 1923 1924 while (1) { 1925 for (i = 0; i < uimin(slen, dlen); i++) { 1926 if (j < hoffset || j >= toffset) 1927 *dptr++ = *sptr++; 1928 slen--; 1929 dlen--; 1930 j++; 1931 } 1932 if (slen == 0) { 1933 srcm = srcm->m_next; 1934 if (srcm == NULL) 1935 return; 1936 sptr = srcm->m_data; 1937 slen = srcm->m_len; 1938 } 1939 if (dlen == 0) { 1940 dstm = dstm->m_next; 1941 if (dstm == NULL) 1942 return; 1943 dptr = dstm->m_data; 1944 dlen = dstm->m_len; 1945 } 1946 } 1947 } 1948 1949 /* 1950 * feed the key generator, must be called at splnet() or higher. 1951 */ 1952 static void 1953 ubsec_feed2(struct ubsec_softc *sc) 1954 { 1955 struct ubsec_q2 *q; 1956 1957 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1958 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1959 break; 1960 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1961 1962 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1963 q->q_mcr.dma_map->dm_mapsize, 1964 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1965 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1966 q->q_ctx.dma_map->dm_mapsize, 1967 BUS_DMASYNC_PREWRITE); 1968 1969 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1970 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1971 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, /*q,*/ q_next); 1972 --sc->sc_nqueue2; 1973 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1974 } 1975 } 1976 1977 /* 1978 * feed the RNG (used instead of ubsec_feed2() on 5827+ devices) 1979 */ 1980 void 1981 ubsec_feed4(struct ubsec_softc *sc) 1982 { 1983 struct ubsec_q2 *q; 1984 1985 while (!SIMPLEQ_EMPTY(&sc->sc_queue4)) { 1986 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR4_FULL) 1987 break; 1988 q = SIMPLEQ_FIRST(&sc->sc_queue4); 1989 1990 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1991 q->q_mcr.dma_map->dm_mapsize, 1992 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1993 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1994 q->q_ctx.dma_map->dm_mapsize, 1995 BUS_DMASYNC_PREWRITE); 1996 1997 WRITE_REG(sc, BS_MCR4, q->q_mcr.dma_paddr); 1998 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue4, q_next); 1999 --sc->sc_nqueue4; 2000 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip4, q, q_next); 2001 } 2002 } 2003 2004 /* 2005 * Callback for handling random numbers 2006 */ 2007 static void 2008 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 2009 { 2010 struct cryptkop *krp; 2011 struct ubsec_ctx_keyop *ctx; 2012 2013 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 2014 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 2015 q->q_ctx.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2016 2017 switch (q->q_type) { 2018 #ifndef UBSEC_NO_RNG 2019 case UBS_CTXOP_RNGSHA1: 2020 case UBS_CTXOP_RNGBYPASS: { 2021 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 2022 u_int32_t *p; 2023 int i; 2024 2025 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 2026 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2027 p = (u_int32_t *)rng->rng_buf.dma_vaddr; 2028 #ifndef __NetBSD__ 2029 for (i = 0; i < UBSEC_RNG_BUFSIZ; p++, i++) 2030 add_true_randomness(letoh32(*p)); 2031 #else 2032 i = UBSEC_RNG_BUFSIZ * sizeof(u_int32_t); 2033 rnd_add_data(&sc->sc_rnd_source, (char *)p, i, i * NBBY); 2034 sc->sc_rng_need -= i; 2035 #endif 2036 rng->rng_used = 0; 2037 #ifdef __OpenBSD__ 2038 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 2039 #else 2040 if (sc->sc_rng_need > 0) { 2041 callout_schedule(&sc->sc_rngto, sc->sc_rnghz); 2042 } 2043 #endif 2044 break; 2045 } 2046 #endif 2047 case UBS_CTXOP_MODEXP: { 2048 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2049 u_int rlen, clen; 2050 2051 krp = me->me_krp; 2052 rlen = (me->me_modbits + 7) / 8; 2053 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 2054 2055 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2056 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2057 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2058 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2059 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2060 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2061 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2062 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2063 2064 if (clen < rlen) 2065 krp->krp_status = E2BIG; 2066 else { 2067 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 2068 memset(krp->krp_param[krp->krp_iparams].crp_p, 0, 2069 (krp->krp_param[krp->krp_iparams].crp_nbits 2070 + 7) / 8); 2071 bcopy(me->me_C.dma_vaddr, 2072 krp->krp_param[krp->krp_iparams].crp_p, 2073 (me->me_modbits + 7) / 8); 2074 } else 2075 ubsec_kshift_l(me->me_shiftbits, 2076 me->me_C.dma_vaddr, me->me_normbits, 2077 krp->krp_param[krp->krp_iparams].crp_p, 2078 krp->krp_param[krp->krp_iparams].crp_nbits); 2079 } 2080 2081 crypto_kdone(krp); 2082 2083 /* bzero all potentially sensitive data */ 2084 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2085 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2086 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2087 memset(me->me_q.q_ctx.dma_vaddr, 0, me->me_q.q_ctx.dma_size); 2088 2089 /* Can't free here, so put us on the free list. */ 2090 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 2091 break; 2092 } 2093 case UBS_CTXOP_RSAPRIV: { 2094 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2095 u_int len; 2096 2097 krp = rp->rpr_krp; 2098 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 0, 2099 rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2100 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 0, 2101 rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2102 2103 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) 2104 / 8; 2105 bcopy(rp->rpr_msgout.dma_vaddr, 2106 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 2107 2108 crypto_kdone(krp); 2109 2110 memset(rp->rpr_msgin.dma_vaddr, 0, rp->rpr_msgin.dma_size); 2111 memset(rp->rpr_msgout.dma_vaddr, 0, rp->rpr_msgout.dma_size); 2112 memset(rp->rpr_q.q_ctx.dma_vaddr, 0, rp->rpr_q.q_ctx.dma_size); 2113 2114 /* Can't free here, so put us on the free list. */ 2115 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 2116 break; 2117 } 2118 default: 2119 printf("%s: unknown ctx op: %x\n", device_xname(sc->sc_dev), 2120 letoh16(ctx->ctx_op)); 2121 break; 2122 } 2123 } 2124 2125 #ifndef UBSEC_NO_RNG 2126 2127 static void 2128 ubsec_rng_get(size_t bytes, void *vsc) 2129 { 2130 struct ubsec_softc *sc = vsc; 2131 2132 mutex_spin_enter(&sc->sc_mtx); 2133 sc->sc_rng_need = bytes; 2134 ubsec_rng_locked(sc); 2135 mutex_spin_exit(&sc->sc_mtx); 2136 2137 } 2138 2139 static void 2140 ubsec_rng(void *vsc) 2141 { 2142 struct ubsec_softc *sc = vsc; 2143 mutex_spin_enter(&sc->sc_mtx); 2144 ubsec_rng_locked(sc); 2145 mutex_spin_exit(&sc->sc_mtx); 2146 } 2147 2148 static void 2149 ubsec_rng_locked(void *vsc) 2150 { 2151 struct ubsec_softc *sc = vsc; 2152 struct ubsec_q2_rng *rng = &sc->sc_rng; 2153 struct ubsec_mcr *mcr; 2154 struct ubsec_ctx_rngbypass *ctx; 2155 int *nqueue; 2156 2157 /* Caller is responsible to lock and release sc_mtx. */ 2158 KASSERT(mutex_owned(&sc->sc_mtx)); 2159 2160 if (rng->rng_used) { 2161 return; 2162 } 2163 2164 if (sc->sc_rng_need < 1) { 2165 callout_stop(&sc->sc_rngto); 2166 return; 2167 } 2168 2169 if (sc->sc_flags & UBS_FLAGS_RNG4) 2170 nqueue = &sc->sc_nqueue4; 2171 else 2172 nqueue = &sc->sc_nqueue2; 2173 2174 (*nqueue)++; 2175 if (*nqueue >= UBS_MAX_NQUEUE) 2176 goto out; 2177 2178 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 2179 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 2180 2181 mcr->mcr_pkts = htole16(1); 2182 mcr->mcr_flags = 0; 2183 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 2184 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 2185 mcr->mcr_ipktbuf.pb_len = 0; 2186 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 2187 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 2188 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 2189 UBS_PKTBUF_LEN); 2190 mcr->mcr_opktbuf.pb_next = 0; 2191 2192 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 2193 ctx->rbp_op = htole16(UBS_CTXOP_RNGSHA1); 2194 rng->rng_q.q_type = UBS_CTXOP_RNGSHA1; 2195 2196 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 2197 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2198 2199 if (sc->sc_flags & UBS_FLAGS_RNG4) { 2200 SIMPLEQ_INSERT_TAIL(&sc->sc_queue4, &rng->rng_q, q_next); 2201 ubsec_feed4(sc); 2202 } else { 2203 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 2204 ubsec_feed2(sc); 2205 } 2206 rng->rng_used = 1; 2207 ubsecstats.hst_rng++; 2208 2209 return; 2210 2211 out: 2212 /* 2213 * Something weird happened, generate our own call back. 2214 */ 2215 (*nqueue)--; 2216 #ifdef __OpenBSD__ 2217 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 2218 #else 2219 callout_schedule(&sc->sc_rngto, sc->sc_rnghz); 2220 #endif 2221 } 2222 #endif /* UBSEC_NO_RNG */ 2223 2224 static int 2225 ubsec_dma_malloc(struct ubsec_softc *sc, bus_size_t size, 2226 struct ubsec_dma_alloc *dma,int mapflags) 2227 { 2228 int r; 2229 2230 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 2231 &dma->dma_seg, 1, &dma->dma_nseg, BUS_DMA_NOWAIT)) != 0) 2232 goto fail_0; 2233 2234 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 2235 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 2236 goto fail_1; 2237 2238 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 2239 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 2240 goto fail_2; 2241 2242 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 2243 size, NULL, BUS_DMA_NOWAIT)) != 0) 2244 goto fail_3; 2245 2246 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 2247 dma->dma_size = size; 2248 return (0); 2249 2250 fail_3: 2251 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2252 fail_2: 2253 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 2254 fail_1: 2255 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2256 fail_0: 2257 dma->dma_map = NULL; 2258 return (r); 2259 } 2260 2261 static void 2262 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 2263 { 2264 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 2265 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 2266 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2267 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2268 } 2269 2270 /* 2271 * Resets the board. Values in the regesters are left as is 2272 * from the reset (i.e. initial values are assigned elsewhere). 2273 */ 2274 static void 2275 ubsec_reset_board(struct ubsec_softc *sc) 2276 { 2277 volatile u_int32_t ctrl; 2278 2279 ctrl = READ_REG(sc, BS_CTRL); 2280 ctrl |= BS_CTRL_RESET; 2281 WRITE_REG(sc, BS_CTRL, ctrl); 2282 2283 /* 2284 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 2285 */ 2286 DELAY(10); 2287 2288 /* Enable RNG and interrupts on newer devices */ 2289 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) { 2290 #ifndef UBSEC_NO_RNG 2291 WRITE_REG(sc, BS_CFG, BS_CFG_RNG); 2292 #endif 2293 WRITE_REG(sc, BS_INT, BS_INT_DMAINT); 2294 } 2295 } 2296 2297 /* 2298 * Init Broadcom registers 2299 */ 2300 static void 2301 ubsec_init_board(struct ubsec_softc *sc) 2302 { 2303 u_int32_t ctrl; 2304 2305 ctrl = READ_REG(sc, BS_CTRL); 2306 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 2307 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 2308 2309 /* 2310 * XXX: Sam Leffler's code has (UBS_FLAGS_KEY|UBS_FLAGS_RNG)). 2311 * anyone got hw docs? 2312 */ 2313 if (sc->sc_flags & UBS_FLAGS_KEY) 2314 ctrl |= BS_CTRL_MCR2INT; 2315 else 2316 ctrl &= ~BS_CTRL_MCR2INT; 2317 2318 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2319 ctrl &= ~BS_CTRL_SWNORM; 2320 2321 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) { 2322 ctrl |= BS_CTRL_BSIZE240; 2323 ctrl &= ~BS_CTRL_MCR3INT; /* MCR3 is reserved for SSL */ 2324 2325 if (sc->sc_flags & UBS_FLAGS_RNG4) 2326 ctrl |= BS_CTRL_MCR4INT; 2327 else 2328 ctrl &= ~BS_CTRL_MCR4INT; 2329 } 2330 2331 WRITE_REG(sc, BS_CTRL, ctrl); 2332 } 2333 2334 /* 2335 * Init Broadcom PCI registers 2336 */ 2337 static void 2338 ubsec_init_pciregs(struct pci_attach_args *pa) 2339 { 2340 pci_chipset_tag_t pc = pa->pa_pc; 2341 u_int32_t misc; 2342 2343 /* 2344 * This will set the cache line size to 1, this will 2345 * force the BCM58xx chip just to do burst read/writes. 2346 * Cache line read/writes are to slow 2347 */ 2348 misc = pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 2349 misc = (misc & ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)) 2350 | ((UBS_DEF_CACHELINE & 0xff) << PCI_CACHELINE_SHIFT); 2351 pci_conf_write(pc, pa->pa_tag, PCI_BHLC_REG, misc); 2352 } 2353 2354 /* 2355 * Clean up after a chip crash. 2356 * It is assumed that the caller in splnet() 2357 */ 2358 static void 2359 ubsec_cleanchip(struct ubsec_softc *sc) 2360 { 2361 struct ubsec_q *q; 2362 2363 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 2364 q = SIMPLEQ_FIRST(&sc->sc_qchip); 2365 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 2366 ubsec_free_q(sc, q); 2367 } 2368 sc->sc_nqchip = 0; 2369 } 2370 2371 /* 2372 * free a ubsec_q 2373 * It is assumed that the caller is within splnet() 2374 */ 2375 static int 2376 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2377 { 2378 struct ubsec_q *q2; 2379 struct cryptop *crp; 2380 int npkts; 2381 int i; 2382 2383 npkts = q->q_nstacked_mcrs; 2384 2385 for (i = 0; i < npkts; i++) { 2386 if(q->q_stacked_mcr[i]) { 2387 q2 = q->q_stacked_mcr[i]; 2388 2389 if ((q2->q_dst_m != NULL) 2390 && (q2->q_src_m != q2->q_dst_m)) 2391 m_freem(q2->q_dst_m); 2392 2393 crp = (struct cryptop *)q2->q_crp; 2394 2395 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2396 2397 crp->crp_etype = EFAULT; 2398 crypto_done(crp); 2399 } else { 2400 break; 2401 } 2402 } 2403 2404 /* 2405 * Free header MCR 2406 */ 2407 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2408 m_freem(q->q_dst_m); 2409 2410 crp = (struct cryptop *)q->q_crp; 2411 2412 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2413 2414 crp->crp_etype = EFAULT; 2415 crypto_done(crp); 2416 return(0); 2417 } 2418 2419 /* 2420 * Routine to reset the chip and clean up. 2421 * It is assumed that the caller is in splnet() 2422 */ 2423 static void 2424 ubsec_totalreset(struct ubsec_softc *sc) 2425 { 2426 ubsec_reset_board(sc); 2427 ubsec_init_board(sc); 2428 ubsec_cleanchip(sc); 2429 } 2430 2431 static int 2432 ubsec_dmamap_aligned(bus_dmamap_t map) 2433 { 2434 int i; 2435 2436 for (i = 0; i < map->dm_nsegs; i++) { 2437 if (map->dm_segs[i].ds_addr & 3) 2438 return (0); 2439 if ((i != (map->dm_nsegs - 1)) && 2440 (map->dm_segs[i].ds_len & 3)) 2441 return (0); 2442 } 2443 return (1); 2444 } 2445 2446 #ifdef __OpenBSD__ 2447 struct ubsec_softc * 2448 ubsec_kfind(struct cryptkop *krp) 2449 { 2450 struct ubsec_softc *sc; 2451 int i; 2452 2453 for (i = 0; i < ubsec_cd.cd_ndevs; i++) { 2454 sc = ubsec_cd.cd_devs[i]; 2455 if (sc == NULL) 2456 continue; 2457 if (sc->sc_cid == krp->krp_hid) 2458 return (sc); 2459 } 2460 return (NULL); 2461 } 2462 #endif 2463 2464 static void 2465 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2466 { 2467 switch (q->q_type) { 2468 case UBS_CTXOP_MODEXP: { 2469 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2470 2471 ubsec_dma_free(sc, &me->me_q.q_mcr); 2472 ubsec_dma_free(sc, &me->me_q.q_ctx); 2473 ubsec_dma_free(sc, &me->me_M); 2474 ubsec_dma_free(sc, &me->me_E); 2475 ubsec_dma_free(sc, &me->me_C); 2476 ubsec_dma_free(sc, &me->me_epb); 2477 free(me, M_DEVBUF); 2478 break; 2479 } 2480 case UBS_CTXOP_RSAPRIV: { 2481 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2482 2483 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2484 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2485 ubsec_dma_free(sc, &rp->rpr_msgin); 2486 ubsec_dma_free(sc, &rp->rpr_msgout); 2487 free(rp, M_DEVBUF); 2488 break; 2489 } 2490 default: 2491 printf("%s: invalid kfree 0x%x\n", device_xname(sc->sc_dev), 2492 q->q_type); 2493 break; 2494 } 2495 } 2496 2497 static int 2498 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2499 { 2500 struct ubsec_softc *sc; 2501 int r; 2502 2503 if (krp == NULL || krp->krp_callback == NULL) 2504 return (EINVAL); 2505 #ifdef __OpenBSD__ 2506 if ((sc = ubsec_kfind(krp)) == NULL) 2507 return (EINVAL); 2508 #else 2509 sc = arg; 2510 KASSERT(sc != NULL /*, ("ubsec_kprocess: null softc")*/); 2511 #endif 2512 2513 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2514 struct ubsec_q2 *q; 2515 2516 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2517 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, /*q,*/ q_next); 2518 ubsec_kfree(sc, q); 2519 } 2520 2521 switch (krp->krp_op) { 2522 case CRK_MOD_EXP: 2523 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2524 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2525 else 2526 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2527 break; 2528 case CRK_MOD_EXP_CRT: 2529 r = ubsec_kprocess_rsapriv(sc, krp, hint); 2530 break; 2531 default: 2532 printf("%s: kprocess: invalid op 0x%x\n", 2533 device_xname(sc->sc_dev), krp->krp_op); 2534 krp->krp_status = EOPNOTSUPP; 2535 crypto_kdone(krp); 2536 r = 0; 2537 } 2538 return (r); 2539 } 2540 2541 /* 2542 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2543 */ 2544 static int 2545 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, 2546 int hint) 2547 { 2548 struct ubsec_q2_modexp *me; 2549 struct ubsec_mcr *mcr; 2550 struct ubsec_ctx_modexp *ctx; 2551 struct ubsec_pktbuf *epb; 2552 int err = 0; 2553 u_int nbits, normbits, mbits, shiftbits, ebits; 2554 2555 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2556 if (me == NULL) { 2557 err = ENOMEM; 2558 goto errout; 2559 } 2560 memset(me, 0, sizeof *me); 2561 me->me_krp = krp; 2562 me->me_q.q_type = UBS_CTXOP_MODEXP; 2563 2564 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2565 if (nbits <= 512) 2566 normbits = 512; 2567 else if (nbits <= 768) 2568 normbits = 768; 2569 else if (nbits <= 1024) 2570 normbits = 1024; 2571 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2572 normbits = 1536; 2573 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2574 normbits = 2048; 2575 else { 2576 err = E2BIG; 2577 goto errout; 2578 } 2579 2580 shiftbits = normbits - nbits; 2581 2582 me->me_modbits = nbits; 2583 me->me_shiftbits = shiftbits; 2584 me->me_normbits = normbits; 2585 2586 /* Sanity check: result bits must be >= true modulus bits. */ 2587 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2588 err = ERANGE; 2589 goto errout; 2590 } 2591 2592 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2593 &me->me_q.q_mcr, 0)) { 2594 err = ENOMEM; 2595 goto errout; 2596 } 2597 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2598 2599 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2600 &me->me_q.q_ctx, 0)) { 2601 err = ENOMEM; 2602 goto errout; 2603 } 2604 2605 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2606 if (mbits > nbits) { 2607 err = E2BIG; 2608 goto errout; 2609 } 2610 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2611 err = ENOMEM; 2612 goto errout; 2613 } 2614 ubsec_kshift_r(shiftbits, 2615 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2616 me->me_M.dma_vaddr, normbits); 2617 2618 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2619 err = ENOMEM; 2620 goto errout; 2621 } 2622 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2623 2624 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2625 if (ebits > nbits) { 2626 err = E2BIG; 2627 goto errout; 2628 } 2629 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2630 err = ENOMEM; 2631 goto errout; 2632 } 2633 ubsec_kshift_r(shiftbits, 2634 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2635 me->me_E.dma_vaddr, normbits); 2636 2637 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2638 &me->me_epb, 0)) { 2639 err = ENOMEM; 2640 goto errout; 2641 } 2642 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2643 epb->pb_addr = htole32(me->me_E.dma_paddr); 2644 epb->pb_next = 0; 2645 epb->pb_len = htole32(normbits / 8); 2646 2647 #ifdef UBSEC_DEBUG 2648 if (ubsec_debug) { 2649 printf("Epb "); 2650 ubsec_dump_pb(epb); 2651 } 2652 #endif 2653 2654 mcr->mcr_pkts = htole16(1); 2655 mcr->mcr_flags = 0; 2656 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2657 mcr->mcr_reserved = 0; 2658 mcr->mcr_pktlen = 0; 2659 2660 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2661 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2662 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2663 2664 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2665 mcr->mcr_opktbuf.pb_next = 0; 2666 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2667 2668 #ifdef DIAGNOSTIC 2669 /* Misaligned output buffer will hang the chip. */ 2670 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2671 panic("%s: modexp invalid addr 0x%x", device_xname(sc->sc_dev), 2672 letoh32(mcr->mcr_opktbuf.pb_addr)); 2673 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2674 panic("%s: modexp invalid len 0x%x", device_xname(sc->sc_dev), 2675 letoh32(mcr->mcr_opktbuf.pb_len)); 2676 #endif 2677 2678 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2679 memset(ctx, 0, sizeof(*ctx)); 2680 ubsec_kshift_r(shiftbits, 2681 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2682 ctx->me_N, normbits); 2683 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2684 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2685 ctx->me_E_len = htole16(nbits); 2686 ctx->me_N_len = htole16(nbits); 2687 2688 #ifdef UBSEC_DEBUG 2689 if (ubsec_debug) { 2690 ubsec_dump_mcr(mcr); 2691 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2692 } 2693 #endif 2694 2695 /* 2696 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2697 * everything else. 2698 */ 2699 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2700 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2701 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2702 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2703 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2704 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2705 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2706 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2707 2708 /* Enqueue and we're done... */ 2709 mutex_spin_enter(&sc->sc_mtx); 2710 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2711 ubsec_feed2(sc); 2712 ubsecstats.hst_modexp++; 2713 mutex_spin_exit(&sc->sc_mtx); 2714 2715 return (0); 2716 2717 errout: 2718 if (me != NULL) { 2719 if (me->me_q.q_mcr.dma_map != NULL) 2720 ubsec_dma_free(sc, &me->me_q.q_mcr); 2721 if (me->me_q.q_ctx.dma_map != NULL) { 2722 memset(me->me_q.q_ctx.dma_vaddr, 0, 2723 me->me_q.q_ctx.dma_size); 2724 ubsec_dma_free(sc, &me->me_q.q_ctx); 2725 } 2726 if (me->me_M.dma_map != NULL) { 2727 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2728 ubsec_dma_free(sc, &me->me_M); 2729 } 2730 if (me->me_E.dma_map != NULL) { 2731 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2732 ubsec_dma_free(sc, &me->me_E); 2733 } 2734 if (me->me_C.dma_map != NULL) { 2735 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2736 ubsec_dma_free(sc, &me->me_C); 2737 } 2738 if (me->me_epb.dma_map != NULL) 2739 ubsec_dma_free(sc, &me->me_epb); 2740 free(me, M_DEVBUF); 2741 } 2742 krp->krp_status = err; 2743 crypto_kdone(krp); 2744 return (0); 2745 } 2746 2747 /* 2748 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2749 */ 2750 static int 2751 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, 2752 int hint) 2753 { 2754 struct ubsec_q2_modexp *me; 2755 struct ubsec_mcr *mcr; 2756 struct ubsec_ctx_modexp *ctx; 2757 struct ubsec_pktbuf *epb; 2758 int err = 0; 2759 u_int nbits, normbits, mbits, shiftbits, ebits; 2760 2761 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2762 if (me == NULL) { 2763 err = ENOMEM; 2764 goto errout; 2765 } 2766 memset(me, 0, sizeof *me); 2767 me->me_krp = krp; 2768 me->me_q.q_type = UBS_CTXOP_MODEXP; 2769 2770 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2771 if (nbits <= 512) 2772 normbits = 512; 2773 else if (nbits <= 768) 2774 normbits = 768; 2775 else if (nbits <= 1024) 2776 normbits = 1024; 2777 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2778 normbits = 1536; 2779 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2780 normbits = 2048; 2781 else { 2782 err = E2BIG; 2783 goto errout; 2784 } 2785 2786 shiftbits = normbits - nbits; 2787 2788 /* XXX ??? */ 2789 me->me_modbits = nbits; 2790 me->me_shiftbits = shiftbits; 2791 me->me_normbits = normbits; 2792 2793 /* Sanity check: result bits must be >= true modulus bits. */ 2794 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2795 err = ERANGE; 2796 goto errout; 2797 } 2798 2799 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2800 &me->me_q.q_mcr, 0)) { 2801 err = ENOMEM; 2802 goto errout; 2803 } 2804 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2805 2806 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2807 &me->me_q.q_ctx, 0)) { 2808 err = ENOMEM; 2809 goto errout; 2810 } 2811 2812 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2813 if (mbits > nbits) { 2814 err = E2BIG; 2815 goto errout; 2816 } 2817 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2818 err = ENOMEM; 2819 goto errout; 2820 } 2821 memset(me->me_M.dma_vaddr, 0, normbits / 8); 2822 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2823 me->me_M.dma_vaddr, (mbits + 7) / 8); 2824 2825 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2826 err = ENOMEM; 2827 goto errout; 2828 } 2829 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2830 2831 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2832 if (ebits > nbits) { 2833 err = E2BIG; 2834 goto errout; 2835 } 2836 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2837 err = ENOMEM; 2838 goto errout; 2839 } 2840 memset(me->me_E.dma_vaddr, 0, normbits / 8); 2841 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2842 me->me_E.dma_vaddr, (ebits + 7) / 8); 2843 2844 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2845 &me->me_epb, 0)) { 2846 err = ENOMEM; 2847 goto errout; 2848 } 2849 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2850 epb->pb_addr = htole32(me->me_E.dma_paddr); 2851 epb->pb_next = 0; 2852 epb->pb_len = htole32((ebits + 7) / 8); 2853 2854 #ifdef UBSEC_DEBUG 2855 if (ubsec_debug) { 2856 printf("Epb "); 2857 ubsec_dump_pb(epb); 2858 } 2859 #endif 2860 2861 mcr->mcr_pkts = htole16(1); 2862 mcr->mcr_flags = 0; 2863 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2864 mcr->mcr_reserved = 0; 2865 mcr->mcr_pktlen = 0; 2866 2867 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2868 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2869 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2870 2871 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2872 mcr->mcr_opktbuf.pb_next = 0; 2873 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2874 2875 #ifdef DIAGNOSTIC 2876 /* Misaligned output buffer will hang the chip. */ 2877 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2878 panic("%s: modexp invalid addr 0x%x", device_xname(sc->sc_dev), 2879 letoh32(mcr->mcr_opktbuf.pb_addr)); 2880 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2881 panic("%s: modexp invalid len 0x%x", device_xname(sc->sc_dev), 2882 letoh32(mcr->mcr_opktbuf.pb_len)); 2883 #endif 2884 2885 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2886 memset(ctx, 0, sizeof(*ctx)); 2887 memcpy(ctx->me_N, krp->krp_param[UBS_MODEXP_PAR_N].crp_p, 2888 (nbits + 7) / 8); 2889 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2890 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2891 ctx->me_E_len = htole16(ebits); 2892 ctx->me_N_len = htole16(nbits); 2893 2894 #ifdef UBSEC_DEBUG 2895 if (ubsec_debug) { 2896 ubsec_dump_mcr(mcr); 2897 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2898 } 2899 #endif 2900 2901 /* 2902 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2903 * everything else. 2904 */ 2905 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2906 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2907 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2908 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2909 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2910 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2911 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2912 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2913 2914 /* Enqueue and we're done... */ 2915 mutex_spin_enter(&sc->sc_mtx); 2916 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2917 ubsec_feed2(sc); 2918 mutex_spin_exit(&sc->sc_mtx); 2919 2920 return (0); 2921 2922 errout: 2923 if (me != NULL) { 2924 if (me->me_q.q_mcr.dma_map != NULL) 2925 ubsec_dma_free(sc, &me->me_q.q_mcr); 2926 if (me->me_q.q_ctx.dma_map != NULL) { 2927 memset(me->me_q.q_ctx.dma_vaddr, 0, 2928 me->me_q.q_ctx.dma_size); 2929 ubsec_dma_free(sc, &me->me_q.q_ctx); 2930 } 2931 if (me->me_M.dma_map != NULL) { 2932 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2933 ubsec_dma_free(sc, &me->me_M); 2934 } 2935 if (me->me_E.dma_map != NULL) { 2936 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2937 ubsec_dma_free(sc, &me->me_E); 2938 } 2939 if (me->me_C.dma_map != NULL) { 2940 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2941 ubsec_dma_free(sc, &me->me_C); 2942 } 2943 if (me->me_epb.dma_map != NULL) 2944 ubsec_dma_free(sc, &me->me_epb); 2945 free(me, M_DEVBUF); 2946 } 2947 krp->krp_status = err; 2948 crypto_kdone(krp); 2949 return (0); 2950 } 2951 2952 static int 2953 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, 2954 int hint) 2955 { 2956 struct ubsec_q2_rsapriv *rp = NULL; 2957 struct ubsec_mcr *mcr; 2958 struct ubsec_ctx_rsapriv *ctx; 2959 int err = 0; 2960 u_int padlen, msglen; 2961 2962 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2963 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2964 if (msglen > padlen) 2965 padlen = msglen; 2966 2967 if (padlen <= 256) 2968 padlen = 256; 2969 else if (padlen <= 384) 2970 padlen = 384; 2971 else if (padlen <= 512) 2972 padlen = 512; 2973 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2974 padlen = 768; 2975 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2976 padlen = 1024; 2977 else { 2978 err = E2BIG; 2979 goto errout; 2980 } 2981 2982 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2983 err = E2BIG; 2984 goto errout; 2985 } 2986 2987 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2988 err = E2BIG; 2989 goto errout; 2990 } 2991 2992 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2993 err = E2BIG; 2994 goto errout; 2995 } 2996 2997 rp = malloc(sizeof *rp, M_DEVBUF, M_NOWAIT|M_ZERO); 2998 if (rp == NULL) 2999 return (ENOMEM); 3000 rp->rpr_krp = krp; 3001 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 3002 3003 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 3004 &rp->rpr_q.q_mcr, 0)) { 3005 err = ENOMEM; 3006 goto errout; 3007 } 3008 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 3009 3010 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 3011 &rp->rpr_q.q_ctx, 0)) { 3012 err = ENOMEM; 3013 goto errout; 3014 } 3015 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 3016 memset(ctx, 0, sizeof *ctx); 3017 3018 /* Copy in p */ 3019 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 3020 &ctx->rpr_buf[0 * (padlen / 8)], 3021 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 3022 3023 /* Copy in q */ 3024 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 3025 &ctx->rpr_buf[1 * (padlen / 8)], 3026 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 3027 3028 /* Copy in dp */ 3029 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 3030 &ctx->rpr_buf[2 * (padlen / 8)], 3031 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 3032 3033 /* Copy in dq */ 3034 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 3035 &ctx->rpr_buf[3 * (padlen / 8)], 3036 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 3037 3038 /* Copy in pinv */ 3039 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 3040 &ctx->rpr_buf[4 * (padlen / 8)], 3041 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 3042 3043 msglen = padlen * 2; 3044 3045 /* Copy in input message (aligned buffer/length). */ 3046 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 3047 /* Is this likely? */ 3048 err = E2BIG; 3049 goto errout; 3050 } 3051 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 3052 err = ENOMEM; 3053 goto errout; 3054 } 3055 memset(rp->rpr_msgin.dma_vaddr, 0, (msglen + 7) / 8); 3056 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 3057 rp->rpr_msgin.dma_vaddr, 3058 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 3059 3060 /* Prepare space for output message (aligned buffer/length). */ 3061 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 3062 /* Is this likely? */ 3063 err = E2BIG; 3064 goto errout; 3065 } 3066 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 3067 err = ENOMEM; 3068 goto errout; 3069 } 3070 memset(rp->rpr_msgout.dma_vaddr, 0, (msglen + 7) / 8); 3071 3072 mcr->mcr_pkts = htole16(1); 3073 mcr->mcr_flags = 0; 3074 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 3075 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 3076 mcr->mcr_ipktbuf.pb_next = 0; 3077 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 3078 mcr->mcr_reserved = 0; 3079 mcr->mcr_pktlen = htole16(msglen); 3080 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 3081 mcr->mcr_opktbuf.pb_next = 0; 3082 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 3083 3084 #ifdef DIAGNOSTIC 3085 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 3086 panic("%s: rsapriv: invalid msgin 0x%lx(0x%lx)", 3087 device_xname(sc->sc_dev), (u_long) rp->rpr_msgin.dma_paddr, 3088 (u_long) rp->rpr_msgin.dma_size); 3089 } 3090 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 3091 panic("%s: rsapriv: invalid msgout 0x%lx(0x%lx)", 3092 device_xname(sc->sc_dev), (u_long) rp->rpr_msgout.dma_paddr, 3093 (u_long) rp->rpr_msgout.dma_size); 3094 } 3095 #endif 3096 3097 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 3098 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 3099 ctx->rpr_q_len = htole16(padlen); 3100 ctx->rpr_p_len = htole16(padlen); 3101 3102 /* 3103 * ubsec_feed2 will sync mcr and ctx, we just need to sync 3104 * everything else. 3105 */ 3106 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 3107 0, rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3108 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 3109 0, rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 3110 3111 /* Enqueue and we're done... */ 3112 mutex_spin_enter(&sc->sc_mtx); 3113 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 3114 ubsec_feed2(sc); 3115 ubsecstats.hst_modexpcrt++; 3116 mutex_spin_exit(&sc->sc_mtx); 3117 return (0); 3118 3119 errout: 3120 if (rp != NULL) { 3121 if (rp->rpr_q.q_mcr.dma_map != NULL) 3122 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 3123 if (rp->rpr_msgin.dma_map != NULL) { 3124 memset(rp->rpr_msgin.dma_vaddr, 0, 3125 rp->rpr_msgin.dma_size); 3126 ubsec_dma_free(sc, &rp->rpr_msgin); 3127 } 3128 if (rp->rpr_msgout.dma_map != NULL) { 3129 memset(rp->rpr_msgout.dma_vaddr, 0, 3130 rp->rpr_msgout.dma_size); 3131 ubsec_dma_free(sc, &rp->rpr_msgout); 3132 } 3133 free(rp, M_DEVBUF); 3134 } 3135 krp->krp_status = err; 3136 crypto_kdone(krp); 3137 return (0); 3138 } 3139 3140 #ifdef UBSEC_DEBUG 3141 static void 3142 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 3143 { 3144 printf("addr 0x%x (0x%x) next 0x%x\n", 3145 pb->pb_addr, pb->pb_len, pb->pb_next); 3146 } 3147 3148 static void 3149 ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *c) 3150 { 3151 printf("CTX (0x%x):\n", c->ctx_len); 3152 switch (letoh16(c->ctx_op)) { 3153 case UBS_CTXOP_RNGBYPASS: 3154 case UBS_CTXOP_RNGSHA1: 3155 break; 3156 case UBS_CTXOP_MODEXP: 3157 { 3158 struct ubsec_ctx_modexp *cx = (void *)c; 3159 int i, len; 3160 3161 printf(" Elen %u, Nlen %u\n", 3162 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 3163 len = (cx->me_N_len + 7)/8; 3164 for (i = 0; i < len; i++) 3165 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 3166 printf("\n"); 3167 break; 3168 } 3169 default: 3170 printf("unknown context: %x\n", c->ctx_op); 3171 } 3172 printf("END CTX\n"); 3173 } 3174 3175 static void 3176 ubsec_dump_mcr(struct ubsec_mcr *mcr) 3177 { 3178 volatile struct ubsec_mcr_add *ma; 3179 int i; 3180 3181 printf("MCR:\n"); 3182 printf(" pkts: %u, flags 0x%x\n", 3183 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 3184 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 3185 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 3186 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 3187 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 3188 letoh16(ma->mcr_reserved)); 3189 printf(" %d: ipkt ", i); 3190 ubsec_dump_pb(&ma->mcr_ipktbuf); 3191 printf(" %d: opkt ", i); 3192 ubsec_dump_pb(&ma->mcr_opktbuf); 3193 ma++; 3194 } 3195 printf("END MCR\n"); 3196 } 3197 #endif /* UBSEC_DEBUG */ 3198 3199 /* 3200 * Return the number of significant bits of a big number. 3201 */ 3202 static int 3203 ubsec_ksigbits(struct crparam *cr) 3204 { 3205 u_int plen = (cr->crp_nbits + 7) / 8; 3206 int i, sig = plen * 8; 3207 u_int8_t c, *p = cr->crp_p; 3208 3209 for (i = plen - 1; i >= 0; i--) { 3210 c = p[i]; 3211 if (c != 0) { 3212 while ((c & 0x80) == 0) { 3213 sig--; 3214 c <<= 1; 3215 } 3216 break; 3217 } 3218 sig -= 8; 3219 } 3220 return (sig); 3221 } 3222 3223 static void 3224 ubsec_kshift_r(u_int shiftbits, u_int8_t *src, u_int srcbits, 3225 u_int8_t *dst, u_int dstbits) 3226 { 3227 u_int slen, dlen; 3228 int i, si, di, n; 3229 3230 slen = (srcbits + 7) / 8; 3231 dlen = (dstbits + 7) / 8; 3232 3233 for (i = 0; i < slen; i++) 3234 dst[i] = src[i]; 3235 for (i = 0; i < dlen - slen; i++) 3236 dst[slen + i] = 0; 3237 3238 n = shiftbits / 8; 3239 if (n != 0) { 3240 si = dlen - n - 1; 3241 di = dlen - 1; 3242 while (si >= 0) 3243 dst[di--] = dst[si--]; 3244 while (di >= 0) 3245 dst[di--] = 0; 3246 } 3247 3248 n = shiftbits % 8; 3249 if (n != 0) { 3250 for (i = dlen - 1; i > 0; i--) 3251 dst[i] = (dst[i] << n) | 3252 (dst[i - 1] >> (8 - n)); 3253 dst[0] = dst[0] << n; 3254 } 3255 } 3256 3257 static void 3258 ubsec_kshift_l(u_int shiftbits, u_int8_t *src, u_int srcbits, 3259 u_int8_t *dst, u_int dstbits) 3260 { 3261 int slen, dlen, i, n; 3262 3263 slen = (srcbits + 7) / 8; 3264 dlen = (dstbits + 7) / 8; 3265 3266 n = shiftbits / 8; 3267 for (i = 0; i < slen; i++) 3268 dst[i] = src[i + n]; 3269 for (i = 0; i < dlen - slen; i++) 3270 dst[slen + i] = 0; 3271 3272 n = shiftbits % 8; 3273 if (n != 0) { 3274 for (i = 0; i < (dlen - 1); i++) 3275 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 3276 dst[dlen - 1] = dst[dlen - 1] >> n; 3277 } 3278 } 3279
Indexes created Wed Oct 01 19:09:53 GMT 2025