ubsec.c revision 1.50
1 /* $NetBSD: ubsec.c,v 1.50 2020/04/30 03:40:53 riastradh Exp $ */ 2 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.6 2003/01/23 21:06:43 sam Exp $ */ 3 /* $OpenBSD: ubsec.c,v 1.143 2009/03/27 13:31:30 reyk Exp$ */ 4 5 /* 6 * Copyright (c) 2000 Jason L. Wright (jason (at) thought.net) 7 * Copyright (c) 2000 Theo de Raadt (deraadt (at) openbsd.org) 8 * Copyright (c) 2001 Patrik Lindergren (patrik (at) ipunplugged.com) 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Effort sponsored in part by the Defense Advanced Research Projects 32 * Agency (DARPA) and Air Force Research Laboratory, Air Force 33 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 34 * 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: ubsec.c,v 1.50 2020/04/30 03:40:53 riastradh Exp $"); 39 40 #undef UBSEC_DEBUG 41 42 /* 43 * uBsec 5[56]01, 58xx hardware crypto accelerator 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/proc.h> 49 #include <sys/endian.h> 50 #ifdef __NetBSD__ 51 #define UBSEC_NO_RNG /* hangs on attach */ 52 #define letoh16 htole16 53 #define letoh32 htole32 54 #endif 55 #include <sys/errno.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/mbuf.h> 59 #include <sys/device.h> 60 #include <sys/module.h> 61 #include <sys/queue.h> 62 #include <sys/sysctl.h> 63 64 #include <opencrypto/cryptodev.h> 65 #include <opencrypto/xform.h> 66 #ifdef __OpenBSD__ 67 #include <dev/rndvar.h> 68 #include <sys/md5k.h> 69 #else 70 #include <sys/cprng.h> 71 #include <sys/md5.h> 72 #include <sys/rndsource.h> 73 #endif 74 #include <sys/sha1.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/ubsecreg.h> 81 #include <dev/pci/ubsecvar.h> 82 83 /* 84 * Prototypes and count for the pci_device structure 85 */ 86 static int ubsec_probe(device_t, cfdata_t, void *); 87 static void ubsec_attach(device_t, device_t, void *); 88 static int ubsec_detach(device_t, int); 89 static void ubsec_reset_board(struct ubsec_softc *); 90 static void ubsec_init_board(struct ubsec_softc *); 91 static void ubsec_init_pciregs(struct pci_attach_args *pa); 92 static void ubsec_cleanchip(struct ubsec_softc *); 93 static void ubsec_totalreset(struct ubsec_softc *); 94 static int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); 95 96 #ifdef __OpenBSD__ 97 struct cfattach ubsec_ca = { 98 sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 99 }; 100 101 struct cfdriver ubsec_cd = { 102 0, "ubsec", DV_DULL 103 }; 104 #else 105 CFATTACH_DECL_NEW(ubsec, sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 106 ubsec_detach, NULL); 107 extern struct cfdriver ubsec_cd; 108 #endif 109 110 /* patchable */ 111 #ifdef UBSEC_DEBUG 112 extern int ubsec_debug; 113 int ubsec_debug=1; 114 #endif 115 116 static int ubsec_intr(void *); 117 static int ubsec_newsession(void*, u_int32_t *, struct cryptoini *); 118 static int ubsec_freesession(void*, u_int64_t); 119 static int ubsec_process(void*, struct cryptop *, int hint); 120 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 121 static void ubsec_feed(struct ubsec_softc *); 122 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 123 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 124 static void ubsec_feed2(struct ubsec_softc *); 125 static void ubsec_feed4(struct ubsec_softc *); 126 #ifndef UBSEC_NO_RNG 127 static void ubsec_rng(void *); 128 static void ubsec_rng_locked(void *); 129 static void ubsec_rng_get(size_t, void *); 130 #endif /* UBSEC_NO_RNG */ 131 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 132 struct ubsec_dma_alloc *, int); 133 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 134 static int ubsec_dmamap_aligned(bus_dmamap_t); 135 136 static int ubsec_kprocess(void*, struct cryptkop *, int); 137 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, 138 struct cryptkop *, int); 139 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, 140 struct cryptkop *, int); 141 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, 142 struct cryptkop *, int); 143 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 144 static int ubsec_ksigbits(struct crparam *); 145 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 146 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 147 148 #ifdef UBSEC_DEBUG 149 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 150 static void ubsec_dump_mcr(struct ubsec_mcr *); 151 static void ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *); 152 #endif 153 154 #define READ_REG(sc,r) \ 155 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 156 157 #define WRITE_REG(sc,reg,val) \ 158 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 159 160 #define SWAP32(x) (x) = htole32(ntohl((x))) 161 #ifndef HTOLE32 162 #define HTOLE32(x) (x) = htole32(x) 163 #endif 164 165 struct ubsec_stats ubsecstats; 166 167 /* 168 * ubsec_maxbatch controls the number of crypto ops to voluntarily 169 * collect into one submission to the hardware. This batching happens 170 * when ops are dispatched from the crypto subsystem with a hint that 171 * more are to follow immediately. These ops must also not be marked 172 * with a ``no delay'' flag. 173 */ 174 static int ubsec_maxbatch = 1; 175 176 /* 177 * ubsec_maxaggr controls the number of crypto ops to submit to the 178 * hardware as a unit. This aggregation reduces the number of interrupts 179 * to the host at the expense of increased latency (for all but the last 180 * operation). For network traffic setting this to one yields the highest 181 * performance but at the expense of more interrupt processing. 182 */ 183 static int ubsec_maxaggr = 1; 184 185 static const struct ubsec_product { 186 pci_vendor_id_t ubsec_vendor; 187 pci_product_id_t ubsec_product; 188 int ubsec_flags; 189 int ubsec_statmask; 190 int ubsec_maxaggr; 191 const char *ubsec_name; 192 } ubsec_products[] = { 193 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5501, 194 0, 195 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 196 UBS_MIN_AGGR, 197 "Bluesteel 5501" 198 }, 199 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5601, 200 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 201 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 202 UBS_MIN_AGGR, 203 "Bluesteel 5601" 204 }, 205 206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5801, 207 0, 208 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 209 UBS_MIN_AGGR, 210 "Broadcom BCM5801" 211 }, 212 213 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5802, 214 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 215 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 216 UBS_MIN_AGGR, 217 "Broadcom BCM5802" 218 }, 219 220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5805, 221 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 222 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 223 UBS_MIN_AGGR, 224 "Broadcom BCM5805" 225 }, 226 227 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5820, 228 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 229 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 230 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 231 UBS_MIN_AGGR, 232 "Broadcom BCM5820" 233 }, 234 235 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5821, 236 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 237 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 238 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 239 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 240 UBS_MIN_AGGR, 241 "Broadcom BCM5821" 242 }, 243 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_SCA1K, 244 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 245 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 246 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 247 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 248 UBS_MIN_AGGR, 249 "Sun Crypto Accelerator 1000" 250 }, 251 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_5821, 252 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 253 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 254 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 255 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 256 UBS_MIN_AGGR, 257 "Broadcom BCM5821 (Sun)" 258 }, 259 260 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5822, 261 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 262 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 263 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 264 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 265 UBS_MIN_AGGR, 266 "Broadcom BCM5822" 267 }, 268 269 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5823, 270 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 271 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 272 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 273 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 274 UBS_MIN_AGGR, 275 "Broadcom BCM5823" 276 }, 277 278 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5825, 279 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 280 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 281 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 282 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 283 UBS_MIN_AGGR, 284 "Broadcom BCM5825" 285 }, 286 287 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5860, 288 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 289 UBS_FLAGS_LONGCTX | 290 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 291 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 292 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 293 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 294 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 295 UBS_MAX_AGGR, 296 "Broadcom BCM5860" 297 }, 298 299 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5861, 300 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 301 UBS_FLAGS_LONGCTX | 302 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 303 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 304 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 305 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 306 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 307 UBS_MAX_AGGR, 308 "Broadcom BCM5861" 309 }, 310 311 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5862, 312 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 313 UBS_FLAGS_LONGCTX | 314 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 315 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 316 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 317 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 318 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 319 UBS_MAX_AGGR, 320 "Broadcom BCM5862" 321 }, 322 323 { 0, 0, 324 0, 325 0, 326 0, 327 NULL 328 } 329 }; 330 331 static const struct ubsec_product * 332 ubsec_lookup(const struct pci_attach_args *pa) 333 { 334 const struct ubsec_product *up; 335 336 for (up = ubsec_products; up->ubsec_name != NULL; up++) { 337 if (PCI_VENDOR(pa->pa_id) == up->ubsec_vendor && 338 PCI_PRODUCT(pa->pa_id) == up->ubsec_product) 339 return (up); 340 } 341 return (NULL); 342 } 343 344 static int 345 ubsec_probe(device_t parent, cfdata_t match, void *aux) 346 { 347 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 348 349 if (ubsec_lookup(pa) != NULL) 350 return (1); 351 352 return (0); 353 } 354 355 static void 356 ubsec_attach(device_t parent, device_t self, void *aux) 357 { 358 struct ubsec_softc *sc = device_private(self); 359 struct pci_attach_args *pa = aux; 360 const struct ubsec_product *up; 361 pci_chipset_tag_t pc = pa->pa_pc; 362 pci_intr_handle_t ih; 363 const char *intrstr = NULL; 364 pcireg_t memtype; 365 struct ubsec_dma *dmap; 366 u_int32_t cmd, i; 367 char intrbuf[PCI_INTRSTR_LEN]; 368 369 sc->sc_dev = self; 370 sc->sc_pct = pc; 371 372 up = ubsec_lookup(pa); 373 if (up == NULL) { 374 printf("\n"); 375 panic("ubsec_attach: impossible"); 376 } 377 378 pci_aprint_devinfo_fancy(pa, "Crypto processor", up->ubsec_name, 1); 379 380 SIMPLEQ_INIT(&sc->sc_queue); 381 SIMPLEQ_INIT(&sc->sc_qchip); 382 SIMPLEQ_INIT(&sc->sc_queue2); 383 SIMPLEQ_INIT(&sc->sc_qchip2); 384 SIMPLEQ_INIT(&sc->sc_queue4); 385 SIMPLEQ_INIT(&sc->sc_qchip4); 386 SIMPLEQ_INIT(&sc->sc_q2free); 387 388 sc->sc_flags = up->ubsec_flags; 389 sc->sc_statmask = up->ubsec_statmask; 390 sc->sc_maxaggr = up->ubsec_maxaggr; 391 392 cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 393 cmd |= PCI_COMMAND_MASTER_ENABLE; 394 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, cmd); 395 396 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BS_BAR); 397 if (pci_mapreg_map(pa, BS_BAR, memtype, 0, 398 &sc->sc_st, &sc->sc_sh, NULL, &sc->sc_memsize)) { 399 aprint_error_dev(self, "can't find mem space"); 400 return; 401 } 402 403 sc->sc_dmat = pa->pa_dmat; 404 405 if (pci_intr_map(pa, &ih)) { 406 aprint_error_dev(self, "couldn't map interrupt\n"); 407 return; 408 } 409 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 410 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ubsec_intr, sc, 411 device_xname(self)); 412 if (sc->sc_ih == NULL) { 413 aprint_error_dev(self, "couldn't establish interrupt"); 414 if (intrstr != NULL) 415 aprint_error(" at %s", intrstr); 416 aprint_error("\n"); 417 return; 418 } 419 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 420 421 sc->sc_cid = crypto_get_driverid(0); 422 if (sc->sc_cid < 0) { 423 aprint_error_dev(self, "couldn't get crypto driver id\n"); 424 pci_intr_disestablish(pc, sc->sc_ih); 425 return; 426 } 427 428 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_VM); 429 430 SIMPLEQ_INIT(&sc->sc_freequeue); 431 dmap = sc->sc_dmaa; 432 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 433 struct ubsec_q *q; 434 435 q = malloc(sizeof(struct ubsec_q), M_DEVBUF, M_ZERO|M_WAITOK); 436 437 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 438 &dmap->d_alloc, 0)) { 439 aprint_error_dev(self, "can't allocate dma buffers\n"); 440 free(q, M_DEVBUF); 441 break; 442 } 443 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 444 445 q->q_dma = dmap; 446 sc->sc_queuea[i] = q; 447 448 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 449 } 450 451 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 452 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 453 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 454 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 455 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC_96, 0, 0, 456 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 457 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC_96, 0, 0, 458 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 459 if (sc->sc_flags & UBS_FLAGS_AES) { 460 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 461 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 462 } 463 464 /* 465 * Reset Broadcom chip 466 */ 467 ubsec_reset_board(sc); 468 469 /* 470 * Init Broadcom specific PCI settings 471 */ 472 ubsec_init_pciregs(pa); 473 474 /* 475 * Init Broadcom chip 476 */ 477 ubsec_init_board(sc); 478 479 #ifndef UBSEC_NO_RNG 480 if (sc->sc_flags & UBS_FLAGS_RNG) { 481 if (sc->sc_flags & UBS_FLAGS_RNG4) 482 sc->sc_statmask |= BS_STAT_MCR4_DONE; 483 else 484 sc->sc_statmask |= BS_STAT_MCR2_DONE; 485 486 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 487 &sc->sc_rng.rng_q.q_mcr, 0)) 488 goto skip_rng; 489 490 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 491 &sc->sc_rng.rng_q.q_ctx, 0)) { 492 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 493 goto skip_rng; 494 } 495 496 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 497 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 498 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 499 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 500 goto skip_rng; 501 } 502 if (hz >= 100) 503 sc->sc_rnghz = hz / 100; 504 else 505 sc->sc_rnghz = 1; 506 #ifdef __OpenBSD__ 507 timeout_set(&sc->sc_rngto, ubsec_rng, sc); 508 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 509 #else 510 callout_init(&sc->sc_rngto, 0); 511 callout_setfunc(&sc->sc_rngto, ubsec_rng, sc); 512 #endif 513 rndsource_setcb(&sc->sc_rnd_source, ubsec_rng_get, sc); 514 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 515 RND_TYPE_RNG, 516 RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB); 517 518 skip_rng: 519 if (sc->sc_rnghz) 520 aprint_normal_dev(self, 521 "random number generator enabled\n"); 522 else 523 aprint_error_dev(self, 524 "WARNING: random number generator disabled\n"); 525 } 526 #endif /* UBSEC_NO_RNG */ 527 528 if (sc->sc_flags & UBS_FLAGS_KEY) { 529 sc->sc_statmask |= BS_STAT_MCR2_DONE; 530 531 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 532 ubsec_kprocess, sc); 533 #if 0 534 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 535 ubsec_kprocess, sc); 536 #endif 537 } 538 } 539 540 static int 541 ubsec_detach(device_t self, int flags) 542 { 543 struct ubsec_softc *sc = device_private(self); 544 struct ubsec_q *q, *qtmp; 545 volatile u_int32_t ctrl; 546 547 /* disable interrupts */ 548 /* XXX wait/abort current ops? where is DMAERR enabled? */ 549 ctrl = READ_REG(sc, BS_CTRL); 550 551 ctrl &= ~(BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR); 552 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) 553 ctrl &= ~BS_CTRL_MCR4INT; 554 555 WRITE_REG(sc, BS_CTRL, ctrl); 556 557 #ifndef UBSEC_NO_RNG 558 if (sc->sc_flags & UBS_FLAGS_RNG) { 559 callout_halt(&sc->sc_rngto, NULL); 560 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 561 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 562 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 563 rnd_detach_source(&sc->sc_rnd_source); 564 } 565 #endif /* UBSEC_NO_RNG */ 566 567 crypto_unregister_all(sc->sc_cid); 568 569 mutex_spin_enter(&sc->sc_mtx); 570 571 ubsec_totalreset(sc); /* XXX leaves the chip running */ 572 573 SIMPLEQ_FOREACH_SAFE(q, &sc->sc_freequeue, q_next, qtmp) { 574 ubsec_dma_free(sc, &q->q_dma->d_alloc); 575 if (q->q_src_map != NULL) 576 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 577 if (q->q_cached_dst_map != NULL) 578 bus_dmamap_destroy(sc->sc_dmat, q->q_cached_dst_map); 579 free(q, M_DEVBUF); 580 } 581 582 mutex_spin_exit(&sc->sc_mtx); 583 584 if (sc->sc_ih != NULL) { 585 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 586 sc->sc_ih = NULL; 587 } 588 589 if (sc->sc_memsize != 0) { 590 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_memsize); 591 sc->sc_memsize = 0; 592 } 593 594 return 0; 595 } 596 597 MODULE(MODULE_CLASS_DRIVER, ubsec, "pci,opencrypto"); 598 599 #ifdef _MODULE 600 #include "ioconf.c" 601 #endif 602 603 static int 604 ubsec_modcmd(modcmd_t cmd, void *data) 605 { 606 int error = 0; 607 608 switch (cmd) { 609 case MODULE_CMD_INIT: 610 #ifdef _MODULE 611 error = config_init_component(cfdriver_ioconf_ubsec, 612 cfattach_ioconf_ubsec, cfdata_ioconf_ubsec); 613 #endif 614 return error; 615 case MODULE_CMD_FINI: 616 #ifdef _MODULE 617 error = config_fini_component(cfdriver_ioconf_ubsec, 618 cfattach_ioconf_ubsec, cfdata_ioconf_ubsec); 619 #endif 620 return error; 621 default: 622 return ENOTTY; 623 } 624 } 625 626 SYSCTL_SETUP(ubsec_sysctl_init, "ubsec sysctl") 627 { 628 const struct sysctlnode *node = NULL; 629 630 sysctl_createv(clog, 0, NULL, &node, 631 CTLFLAG_PERMANENT, 632 CTLTYPE_NODE, "ubsec", 633 SYSCTL_DESCR("ubsec opetions"), 634 NULL, 0, NULL, 0, 635 CTL_HW, CTL_CREATE, CTL_EOL); 636 sysctl_createv(clog, 0, &node, NULL, 637 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 638 CTLTYPE_INT, "maxbatch", 639 SYSCTL_DESCR("max ops to batch w/o interrupt"), 640 NULL, 0, &ubsec_maxbatch, 0, 641 CTL_CREATE, CTL_EOL); 642 sysctl_createv(clog, 0, &node, NULL, 643 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 644 CTLTYPE_INT, "maxaggr", 645 SYSCTL_DESCR("max ops to aggregate under one interrupt"), 646 NULL, 0, &ubsec_maxaggr, 0, 647 CTL_CREATE, CTL_EOL); 648 649 return; 650 } 651 652 /* 653 * UBSEC Interrupt routine 654 */ 655 static int 656 ubsec_intr(void *arg) 657 { 658 struct ubsec_softc *sc = arg; 659 volatile u_int32_t stat; 660 struct ubsec_q *q; 661 struct ubsec_dma *dmap; 662 int flags; 663 int npkts = 0, i; 664 665 mutex_spin_enter(&sc->sc_mtx); 666 stat = READ_REG(sc, BS_STAT); 667 stat &= sc->sc_statmask; 668 if (stat == 0) { 669 mutex_spin_exit(&sc->sc_mtx); 670 return (0); 671 } 672 673 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 674 675 /* 676 * Check to see if we have any packets waiting for us 677 */ 678 if ((stat & BS_STAT_MCR1_DONE)) { 679 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 680 q = SIMPLEQ_FIRST(&sc->sc_qchip); 681 dmap = q->q_dma; 682 683 if ((dmap->d_dma->d_mcr.mcr_flags 684 & htole16(UBS_MCR_DONE)) == 0) 685 break; 686 687 q = SIMPLEQ_FIRST(&sc->sc_qchip); 688 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 689 690 npkts = q->q_nstacked_mcrs; 691 sc->sc_nqchip -= 1+npkts; 692 /* 693 * search for further sc_qchip ubsec_q's that share 694 * the same MCR, and complete them too, they must be 695 * at the top. 696 */ 697 for (i = 0; i < npkts; i++) { 698 if(q->q_stacked_mcr[i]) 699 ubsec_callback(sc, q->q_stacked_mcr[i]); 700 else 701 break; 702 } 703 ubsec_callback(sc, q); 704 } 705 706 /* 707 * Don't send any more packet to chip if there has been 708 * a DMAERR. 709 */ 710 if (!(stat & BS_STAT_DMAERR)) 711 ubsec_feed(sc); 712 } 713 714 /* 715 * Check to see if we have any key setups/rng's waiting for us 716 */ 717 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 718 (stat & BS_STAT_MCR2_DONE)) { 719 struct ubsec_q2 *q2; 720 struct ubsec_mcr *mcr; 721 722 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 723 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 724 725 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 726 0, q2->q_mcr.dma_map->dm_mapsize, 727 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 728 729 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 730 731 /* A bug in new devices requires to swap this field */ 732 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) 733 flags = htole16(mcr->mcr_flags); 734 else 735 flags = mcr->mcr_flags; 736 if ((flags & htole16(UBS_MCR_DONE)) == 0) { 737 bus_dmamap_sync(sc->sc_dmat, 738 q2->q_mcr.dma_map, 0, 739 q2->q_mcr.dma_map->dm_mapsize, 740 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 741 break; 742 } 743 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 744 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, /*q2,*/ q_next); 745 ubsec_callback2(sc, q2); 746 /* 747 * Don't send any more packet to chip if there has been 748 * a DMAERR. 749 */ 750 if (!(stat & BS_STAT_DMAERR)) 751 ubsec_feed2(sc); 752 } 753 } 754 if ((sc->sc_flags & UBS_FLAGS_RNG4) && (stat & BS_STAT_MCR4_DONE)) { 755 struct ubsec_q2 *q2; 756 struct ubsec_mcr *mcr; 757 758 while (!SIMPLEQ_EMPTY(&sc->sc_qchip4)) { 759 q2 = SIMPLEQ_FIRST(&sc->sc_qchip4); 760 761 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 762 0, q2->q_mcr.dma_map->dm_mapsize, 763 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 764 765 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 766 767 /* A bug in new devices requires to swap this field */ 768 flags = htole16(mcr->mcr_flags); 769 770 if ((flags & htole16(UBS_MCR_DONE)) == 0) { 771 bus_dmamap_sync(sc->sc_dmat, 772 q2->q_mcr.dma_map, 0, 773 q2->q_mcr.dma_map->dm_mapsize, 774 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 775 break; 776 } 777 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip4, q_next); 778 ubsec_callback2(sc, q2); 779 /* 780 * Don't send any more packet to chip if there has been 781 * a DMAERR. 782 */ 783 if (!(stat & BS_STAT_DMAERR)) 784 ubsec_feed4(sc); 785 } 786 } 787 788 /* 789 * Check to see if we got any DMA Error 790 */ 791 if (stat & BS_STAT_DMAERR) { 792 #ifdef UBSEC_DEBUG 793 if (ubsec_debug) { 794 volatile u_int32_t a = READ_REG(sc, BS_ERR); 795 796 printf("%s: dmaerr %s@%08x\n", device_xname(sc->sc_dev), 797 (a & BS_ERR_READ) ? "read" : "write", 798 a & BS_ERR_ADDR); 799 } 800 #endif /* UBSEC_DEBUG */ 801 ubsecstats.hst_dmaerr++; 802 ubsec_totalreset(sc); 803 ubsec_feed(sc); 804 } 805 806 if (sc->sc_needwakeup) { /* XXX check high watermark */ 807 int wkeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 808 #ifdef UBSEC_DEBUG 809 if (ubsec_debug) 810 printf("%s: wakeup crypto (%x)\n", 811 device_xname(sc->sc_dev), sc->sc_needwakeup); 812 #endif /* UBSEC_DEBUG */ 813 sc->sc_needwakeup &= ~wkeup; 814 crypto_unblock(sc->sc_cid, wkeup); 815 } 816 mutex_spin_exit(&sc->sc_mtx); 817 return (1); 818 } 819 820 /* 821 * ubsec_feed() - aggregate and post requests to chip 822 * OpenBSD comments: 823 * It is assumed that the caller set splnet() 824 */ 825 static void 826 ubsec_feed(struct ubsec_softc *sc) 827 { 828 struct ubsec_q *q, *q2; 829 int npkts, i; 830 void *v; 831 u_int32_t stat; 832 #ifdef UBSEC_DEBUG 833 static int max; 834 #endif /* UBSEC_DEBUG */ 835 836 npkts = sc->sc_nqueue; 837 if (npkts > ubsecstats.hst_maxqueue) 838 ubsecstats.hst_maxqueue = npkts; 839 if (npkts < 2) 840 goto feed1; 841 842 /* 843 * Decide how many ops to combine in a single MCR. We cannot 844 * aggregate more than UBS_MAX_AGGR because this is the number 845 * of slots defined in the data structure. Otherwise we clamp 846 * based on the tunable parameter ubsec_maxaggr. Note that 847 * aggregation can happen in two ways: either by batching ops 848 * from above or because the h/w backs up and throttles us. 849 * Aggregating ops reduces the number of interrupts to the host 850 * but also (potentially) increases the latency for processing 851 * completed ops as we only get an interrupt when all aggregated 852 * ops have completed. 853 */ 854 if (npkts > sc->sc_maxaggr) 855 npkts = sc->sc_maxaggr; 856 if (npkts > ubsec_maxaggr) 857 npkts = ubsec_maxaggr; 858 if (npkts > ubsecstats.hst_maxbatch) 859 ubsecstats.hst_maxbatch = npkts; 860 if (npkts < 2) 861 goto feed1; 862 ubsecstats.hst_totbatch += npkts-1; 863 864 if ((stat = READ_REG(sc, BS_STAT)) 865 & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 866 if (stat & BS_STAT_DMAERR) { 867 ubsec_totalreset(sc); 868 ubsecstats.hst_dmaerr++; 869 } else { 870 ubsecstats.hst_mcr1full++; 871 } 872 return; 873 } 874 875 #ifdef UBSEC_DEBUG 876 if (ubsec_debug) 877 printf("merging %d records\n", npkts); 878 /* XXX temporary aggregation statistics reporting code */ 879 if (max < npkts) { 880 max = npkts; 881 printf("%s: new max aggregate %d\n", device_xname(sc->sc_dev), 882 max); 883 } 884 #endif /* UBSEC_DEBUG */ 885 886 q = SIMPLEQ_FIRST(&sc->sc_queue); 887 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 888 --sc->sc_nqueue; 889 890 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 891 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 892 if (q->q_dst_map != NULL) 893 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 894 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 895 896 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 897 898 for (i = 0; i < q->q_nstacked_mcrs; i++) { 899 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 900 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 901 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 902 if (q2->q_dst_map != NULL) 903 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 904 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 905 q2= SIMPLEQ_FIRST(&sc->sc_queue); 906 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q2,*/ q_next); 907 --sc->sc_nqueue; 908 909 v = ((void *)&q2->q_dma->d_dma->d_mcr); 910 v = (char*)v + (sizeof(struct ubsec_mcr) - 911 sizeof(struct ubsec_mcr_add)); 912 memcpy(&q->q_dma->d_dma->d_mcradd[i], v, 913 sizeof(struct ubsec_mcr_add)); 914 q->q_stacked_mcr[i] = q2; 915 } 916 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 917 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 918 sc->sc_nqchip += npkts; 919 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 920 ubsecstats.hst_maxqchip = sc->sc_nqchip; 921 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 922 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 923 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 924 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 925 offsetof(struct ubsec_dmachunk, d_mcr)); 926 return; 927 928 feed1: 929 while (!SIMPLEQ_EMPTY(&sc->sc_queue)) { 930 if ((stat = READ_REG(sc, BS_STAT)) 931 & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 932 if (stat & BS_STAT_DMAERR) { 933 ubsec_totalreset(sc); 934 ubsecstats.hst_dmaerr++; 935 } else { 936 ubsecstats.hst_mcr1full++; 937 } 938 break; 939 } 940 941 q = SIMPLEQ_FIRST(&sc->sc_queue); 942 943 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 944 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 945 if (q->q_dst_map != NULL) 946 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 947 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 948 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 949 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 950 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 951 952 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 953 offsetof(struct ubsec_dmachunk, d_mcr)); 954 #ifdef UBSEC_DEBUG 955 if (ubsec_debug) 956 printf("feed: q->chip %p %08x stat %08x\n", 957 q, (u_int32_t)q->q_dma->d_alloc.dma_paddr, 958 stat); 959 #endif /* UBSEC_DEBUG */ 960 q = SIMPLEQ_FIRST(&sc->sc_queue); 961 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 962 --sc->sc_nqueue; 963 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 964 sc->sc_nqchip++; 965 } 966 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 967 ubsecstats.hst_maxqchip = sc->sc_nqchip; 968 } 969 970 /* 971 * Allocate a new 'session' and return an encoded session id. 'sidp' 972 * contains our registration id, and should contain an encoded session 973 * id on successful allocation. 974 */ 975 static int 976 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 977 { 978 struct cryptoini *c, *encini = NULL, *macini = NULL; 979 struct ubsec_softc *sc; 980 struct ubsec_session *ses = NULL; 981 MD5_CTX md5ctx; 982 SHA1_CTX sha1ctx; 983 int i, sesn; 984 985 sc = arg; 986 KASSERT(sc != NULL /*, ("ubsec_newsession: null softc")*/); 987 988 if (sidp == NULL || cri == NULL || sc == NULL) 989 return (EINVAL); 990 991 for (c = cri; c != NULL; c = c->cri_next) { 992 if (c->cri_alg == CRYPTO_MD5_HMAC_96 || 993 c->cri_alg == CRYPTO_SHA1_HMAC_96) { 994 if (macini) 995 return (EINVAL); 996 macini = c; 997 } else if (c->cri_alg == CRYPTO_DES_CBC || 998 c->cri_alg == CRYPTO_3DES_CBC || 999 c->cri_alg == CRYPTO_AES_CBC) { 1000 if (encini) 1001 return (EINVAL); 1002 encini = c; 1003 } else 1004 return (EINVAL); 1005 } 1006 if (encini == NULL && macini == NULL) 1007 return (EINVAL); 1008 1009 if (encini && encini->cri_alg == CRYPTO_AES_CBC) { 1010 switch (encini->cri_klen) { 1011 case 128: 1012 case 192: 1013 case 256: 1014 break; 1015 default: 1016 return (EINVAL); 1017 } 1018 } 1019 1020 if (sc->sc_sessions == NULL) { 1021 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 1022 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 1023 if (ses == NULL) 1024 return (ENOMEM); 1025 sesn = 0; 1026 sc->sc_nsessions = 1; 1027 } else { 1028 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 1029 if (sc->sc_sessions[sesn].ses_used == 0) { 1030 ses = &sc->sc_sessions[sesn]; 1031 break; 1032 } 1033 } 1034 1035 if (ses == NULL) { 1036 sesn = sc->sc_nsessions; 1037 ses = (struct ubsec_session *)malloc((sesn + 1) * 1038 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 1039 if (ses == NULL) 1040 return (ENOMEM); 1041 memcpy(ses, sc->sc_sessions, sesn * 1042 sizeof(struct ubsec_session)); 1043 memset(sc->sc_sessions, 0, sesn * 1044 sizeof(struct ubsec_session)); 1045 free(sc->sc_sessions, M_DEVBUF); 1046 sc->sc_sessions = ses; 1047 ses = &sc->sc_sessions[sesn]; 1048 sc->sc_nsessions++; 1049 } 1050 } 1051 1052 memset(ses, 0, sizeof(struct ubsec_session)); 1053 ses->ses_used = 1; 1054 if (encini) { 1055 /* get an IV, network byte order */ 1056 #ifdef __NetBSD__ 1057 cprng_fast(ses->ses_iv, sizeof(ses->ses_iv)); 1058 #else 1059 get_random_bytes(ses->ses_iv, sizeof(ses->ses_iv)); 1060 #endif 1061 1062 /* Go ahead and compute key in ubsec's byte order */ 1063 if (encini->cri_alg == CRYPTO_AES_CBC) { 1064 memcpy(ses->ses_key, encini->cri_key, 1065 encini->cri_klen / 8); 1066 } 1067 if (encini->cri_alg == CRYPTO_DES_CBC) { 1068 memcpy(&ses->ses_key[0], encini->cri_key, 8); 1069 memcpy(&ses->ses_key[2], encini->cri_key, 8); 1070 memcpy(&ses->ses_key[4], encini->cri_key, 8); 1071 } else 1072 memcpy(ses->ses_key, encini->cri_key, 24); 1073 1074 SWAP32(ses->ses_key[0]); 1075 SWAP32(ses->ses_key[1]); 1076 SWAP32(ses->ses_key[2]); 1077 SWAP32(ses->ses_key[3]); 1078 SWAP32(ses->ses_key[4]); 1079 SWAP32(ses->ses_key[5]); 1080 } 1081 1082 if (macini) { 1083 for (i = 0; i < macini->cri_klen / 8; i++) 1084 macini->cri_key[i] ^= HMAC_IPAD_VAL; 1085 1086 if (macini->cri_alg == CRYPTO_MD5_HMAC_96) { 1087 MD5Init(&md5ctx); 1088 MD5Update(&md5ctx, macini->cri_key, 1089 macini->cri_klen / 8); 1090 MD5Update(&md5ctx, hmac_ipad_buffer, 1091 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1092 memcpy(ses->ses_hminner, md5ctx.state, 1093 sizeof(md5ctx.state)); 1094 } else { 1095 SHA1Init(&sha1ctx); 1096 SHA1Update(&sha1ctx, macini->cri_key, 1097 macini->cri_klen / 8); 1098 SHA1Update(&sha1ctx, hmac_ipad_buffer, 1099 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1100 memcpy(ses->ses_hminner, sha1ctx.state, 1101 sizeof(sha1ctx.state)); 1102 } 1103 1104 for (i = 0; i < macini->cri_klen / 8; i++) 1105 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 1106 1107 if (macini->cri_alg == CRYPTO_MD5_HMAC_96) { 1108 MD5Init(&md5ctx); 1109 MD5Update(&md5ctx, macini->cri_key, 1110 macini->cri_klen / 8); 1111 MD5Update(&md5ctx, hmac_opad_buffer, 1112 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1113 memcpy(ses->ses_hmouter, md5ctx.state, 1114 sizeof(md5ctx.state)); 1115 } else { 1116 SHA1Init(&sha1ctx); 1117 SHA1Update(&sha1ctx, macini->cri_key, 1118 macini->cri_klen / 8); 1119 SHA1Update(&sha1ctx, hmac_opad_buffer, 1120 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1121 memcpy(ses->ses_hmouter, sha1ctx.state, 1122 sizeof(sha1ctx.state)); 1123 } 1124 1125 for (i = 0; i < macini->cri_klen / 8; i++) 1126 macini->cri_key[i] ^= HMAC_OPAD_VAL; 1127 } 1128 1129 *sidp = UBSEC_SID(device_unit(sc->sc_dev), sesn); 1130 return (0); 1131 } 1132 1133 /* 1134 * Deallocate a session. 1135 */ 1136 static int 1137 ubsec_freesession(void *arg, u_int64_t tid) 1138 { 1139 struct ubsec_softc *sc; 1140 int session; 1141 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 1142 1143 sc = arg; 1144 KASSERT(sc != NULL /*, ("ubsec_freesession: null softc")*/); 1145 1146 session = UBSEC_SESSION(sid); 1147 if (session >= sc->sc_nsessions) 1148 return (EINVAL); 1149 1150 memset(&sc->sc_sessions[session], 0, sizeof(sc->sc_sessions[session])); 1151 return (0); 1152 } 1153 1154 #ifdef __FreeBSD__ /* Ugly gratuitous changes to bus_dma */ 1155 static void 1156 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, 1157 int error) 1158 { 1159 struct ubsec_operand *op = arg; 1160 1161 KASSERT(nsegs <= UBS_MAX_SCATTER 1162 /*, ("Too many DMA segments returned when mapping operand")*/); 1163 #ifdef UBSEC_DEBUG 1164 if (ubsec_debug) 1165 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 1166 (u_int) mapsize, nsegs); 1167 #endif 1168 op->mapsize = mapsize; 1169 op->nsegs = nsegs; 1170 memcpy(op->segs, seg, nsegs * sizeof (seg[0])); 1171 } 1172 #endif 1173 1174 static int 1175 ubsec_process(void *arg, struct cryptop *crp, int hint) 1176 { 1177 struct ubsec_q *q = NULL; 1178 #ifdef __OpenBSD__ 1179 int card; 1180 #endif 1181 int err = 0, i, j, nicealign; 1182 struct ubsec_softc *sc; 1183 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1184 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1185 int sskip, dskip, stheend, dtheend; 1186 int16_t coffset; 1187 struct ubsec_session *ses, key; 1188 struct ubsec_dma *dmap = NULL; 1189 u_int16_t flags = 0; 1190 int ivlen = 0, keylen = 0; 1191 1192 sc = arg; 1193 KASSERT(sc != NULL /*, ("ubsec_process: null softc")*/); 1194 1195 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1196 ubsecstats.hst_invalid++; 1197 return (EINVAL); 1198 } 1199 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1200 ubsecstats.hst_badsession++; 1201 return (EINVAL); 1202 } 1203 1204 mutex_spin_enter(&sc->sc_mtx); 1205 1206 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1207 ubsecstats.hst_queuefull++; 1208 sc->sc_needwakeup |= CRYPTO_SYMQ; 1209 mutex_spin_exit(&sc->sc_mtx); 1210 return(ERESTART); 1211 } 1212 1213 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1214 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, /*q,*/ q_next); 1215 mutex_spin_exit(&sc->sc_mtx); 1216 1217 dmap = q->q_dma; /* Save dma pointer */ 1218 /* don't lose the cached dmamaps q_src_map and q_cached_dst_map */ 1219 memset(q, 0, offsetof(struct ubsec_q, q_src_map)); 1220 memset(&key, 0, sizeof(key)); 1221 1222 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1223 q->q_dma = dmap; 1224 ses = &sc->sc_sessions[q->q_sesn]; 1225 1226 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1227 q->q_src_m = (struct mbuf *)crp->crp_buf; 1228 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1229 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1230 q->q_src_io = (struct uio *)crp->crp_buf; 1231 q->q_dst_io = (struct uio *)crp->crp_buf; 1232 } else { 1233 ubsecstats.hst_badflags++; 1234 err = EINVAL; 1235 goto errout; /* XXX we don't handle contiguous blocks! */ 1236 } 1237 1238 memset(&dmap->d_dma->d_mcr, 0, sizeof(struct ubsec_mcr)); 1239 1240 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1241 dmap->d_dma->d_mcr.mcr_flags = 0; 1242 q->q_crp = crp; 1243 1244 crd1 = crp->crp_desc; 1245 if (crd1 == NULL) { 1246 ubsecstats.hst_nodesc++; 1247 err = EINVAL; 1248 goto errout; 1249 } 1250 crd2 = crd1->crd_next; 1251 1252 if (crd2 == NULL) { 1253 if (crd1->crd_alg == CRYPTO_MD5_HMAC_96 || 1254 crd1->crd_alg == CRYPTO_SHA1_HMAC_96) { 1255 maccrd = crd1; 1256 enccrd = NULL; 1257 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1258 crd1->crd_alg == CRYPTO_3DES_CBC || 1259 crd1->crd_alg == CRYPTO_AES_CBC) { 1260 maccrd = NULL; 1261 enccrd = crd1; 1262 } else { 1263 ubsecstats.hst_badalg++; 1264 err = EINVAL; 1265 goto errout; 1266 } 1267 } else { 1268 if ((crd1->crd_alg == CRYPTO_MD5_HMAC_96 || 1269 crd1->crd_alg == CRYPTO_SHA1_HMAC_96) && 1270 (crd2->crd_alg == CRYPTO_DES_CBC || 1271 crd2->crd_alg == CRYPTO_3DES_CBC || 1272 crd2->crd_alg == CRYPTO_AES_CBC) && 1273 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1274 maccrd = crd1; 1275 enccrd = crd2; 1276 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1277 crd1->crd_alg == CRYPTO_3DES_CBC || 1278 crd1->crd_alg == CRYPTO_AES_CBC) && 1279 (crd2->crd_alg == CRYPTO_MD5_HMAC_96 || 1280 crd2->crd_alg == CRYPTO_SHA1_HMAC_96) && 1281 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1282 enccrd = crd1; 1283 maccrd = crd2; 1284 } else { 1285 /* 1286 * We cannot order the ubsec as requested 1287 */ 1288 ubsecstats.hst_badalg++; 1289 err = EINVAL; 1290 goto errout; 1291 } 1292 } 1293 1294 if (enccrd) { 1295 if (enccrd->crd_alg == CRYPTO_AES_CBC) { 1296 if ((sc->sc_flags & UBS_FLAGS_AES) == 0) { 1297 /* 1298 * We cannot order the ubsec as requested 1299 */ 1300 ubsecstats.hst_badalg++; 1301 err = EINVAL; 1302 goto errout; 1303 } 1304 flags |= htole16(UBS_PKTCTX_ENC_AES); 1305 switch (enccrd->crd_klen) { 1306 case 128: 1307 case 192: 1308 case 256: 1309 keylen = enccrd->crd_klen / 8; 1310 break; 1311 default: 1312 err = EINVAL; 1313 goto errout; 1314 } 1315 ivlen = 16; 1316 } else { 1317 flags |= htole16(UBS_PKTCTX_ENC_3DES); 1318 ivlen = 8; 1319 keylen = 24; 1320 } 1321 1322 encoffset = enccrd->crd_skip; 1323 1324 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1325 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1326 1327 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1328 memcpy(key.ses_iv, enccrd->crd_iv, ivlen); 1329 else { 1330 for (i = 0; i < (ivlen / 4); i++) 1331 key.ses_iv[i] = ses->ses_iv[i]; 1332 } 1333 1334 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1335 if (crp->crp_flags & CRYPTO_F_IMBUF) 1336 m_copyback(q->q_src_m, 1337 enccrd->crd_inject, 1338 ivlen, (void *)key.ses_iv); 1339 else if (crp->crp_flags & CRYPTO_F_IOV) 1340 cuio_copyback(q->q_src_io, 1341 enccrd->crd_inject, 1342 ivlen, (void *)key.ses_iv); 1343 } 1344 } else { 1345 flags |= htole16(UBS_PKTCTX_INBOUND); 1346 1347 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1348 memcpy(key.ses_iv, enccrd->crd_iv, ivlen); 1349 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1350 m_copydata(q->q_src_m, enccrd->crd_inject, 1351 ivlen, (void *)key.ses_iv); 1352 else if (crp->crp_flags & CRYPTO_F_IOV) 1353 cuio_copydata(q->q_src_io, 1354 enccrd->crd_inject, 8, 1355 (void *)key.ses_iv); 1356 } 1357 1358 for (i = 0; i < (keylen / 4); i++) 1359 key.ses_key[i] = ses->ses_key[i]; 1360 for (i = 0; i < (ivlen / 4); i++) 1361 SWAP32(key.ses_iv[i]); 1362 } 1363 1364 if (maccrd) { 1365 macoffset = maccrd->crd_skip; 1366 1367 if (maccrd->crd_alg == CRYPTO_MD5_HMAC_96) 1368 flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1369 else 1370 flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1371 1372 for (i = 0; i < 5; i++) { 1373 key.ses_hminner[i] = ses->ses_hminner[i]; 1374 key.ses_hmouter[i] = ses->ses_hmouter[i]; 1375 1376 HTOLE32(key.ses_hminner[i]); 1377 HTOLE32(key.ses_hmouter[i]); 1378 } 1379 } 1380 1381 if (enccrd && maccrd) { 1382 /* 1383 * ubsec cannot handle packets where the end of encryption 1384 * and authentication are not the same, or where the 1385 * encrypted part begins before the authenticated part. 1386 */ 1387 if ((encoffset + enccrd->crd_len) != 1388 (macoffset + maccrd->crd_len)) { 1389 ubsecstats.hst_lenmismatch++; 1390 err = EINVAL; 1391 goto errout; 1392 } 1393 if (enccrd->crd_skip < maccrd->crd_skip) { 1394 ubsecstats.hst_skipmismatch++; 1395 err = EINVAL; 1396 goto errout; 1397 } 1398 sskip = maccrd->crd_skip; 1399 cpskip = dskip = enccrd->crd_skip; 1400 stheend = maccrd->crd_len; 1401 dtheend = enccrd->crd_len; 1402 coffset = enccrd->crd_skip - maccrd->crd_skip; 1403 cpoffset = cpskip + dtheend; 1404 #ifdef UBSEC_DEBUG 1405 if (ubsec_debug) { 1406 printf("mac: skip %d, len %d, inject %d\n", 1407 maccrd->crd_skip, maccrd->crd_len, 1408 maccrd->crd_inject); 1409 printf("enc: skip %d, len %d, inject %d\n", 1410 enccrd->crd_skip, enccrd->crd_len, 1411 enccrd->crd_inject); 1412 printf("src: skip %d, len %d\n", sskip, stheend); 1413 printf("dst: skip %d, len %d\n", dskip, dtheend); 1414 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1415 coffset, stheend, cpskip, cpoffset); 1416 } 1417 #endif 1418 } else { 1419 cpskip = dskip = sskip = macoffset + encoffset; 1420 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1421 cpoffset = cpskip + dtheend; 1422 coffset = 0; 1423 } 1424 1425 if (q->q_src_map == NULL) { 1426 /* XXX FIXME: jonathan asks, what the heck's that 0xfff0? */ 1427 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, 1428 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { 1429 err = ENOMEM; 1430 goto errout; 1431 } 1432 } 1433 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1434 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1435 q->q_src_m, BUS_DMA_NOWAIT) != 0) { 1436 ubsecstats.hst_noload++; 1437 err = ENOMEM; 1438 goto errout; 1439 } 1440 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1441 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1442 q->q_src_io, BUS_DMA_NOWAIT) != 0) { 1443 ubsecstats.hst_noload++; 1444 err = ENOMEM; 1445 goto errout; 1446 } 1447 } 1448 nicealign = ubsec_dmamap_aligned(q->q_src_map); 1449 1450 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1451 1452 #ifdef UBSEC_DEBUG 1453 if (ubsec_debug) 1454 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1455 #endif 1456 for (i = j = 0; i < q->q_src_map->dm_nsegs; i++) { 1457 struct ubsec_pktbuf *pb; 1458 bus_size_t packl = q->q_src_map->dm_segs[i].ds_len; 1459 bus_addr_t packp = q->q_src_map->dm_segs[i].ds_addr; 1460 1461 if (sskip >= packl) { 1462 sskip -= packl; 1463 continue; 1464 } 1465 1466 packl -= sskip; 1467 packp += sskip; 1468 sskip = 0; 1469 1470 if (packl > 0xfffc) { 1471 err = EIO; 1472 goto errout; 1473 } 1474 1475 if (j == 0) 1476 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1477 else 1478 pb = &dmap->d_dma->d_sbuf[j - 1]; 1479 1480 pb->pb_addr = htole32(packp); 1481 1482 if (stheend) { 1483 if (packl > stheend) { 1484 pb->pb_len = htole32(stheend); 1485 stheend = 0; 1486 } else { 1487 pb->pb_len = htole32(packl); 1488 stheend -= packl; 1489 } 1490 } else 1491 pb->pb_len = htole32(packl); 1492 1493 if ((i + 1) == q->q_src_map->dm_nsegs) 1494 pb->pb_next = 0; 1495 else 1496 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1497 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1498 j++; 1499 } 1500 1501 if (enccrd == NULL && maccrd != NULL) { 1502 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1503 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1504 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1505 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1506 #ifdef UBSEC_DEBUG 1507 if (ubsec_debug) 1508 printf("opkt: %x %x %x\n", 1509 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1510 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1511 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1512 1513 #endif 1514 } else { 1515 if (crp->crp_flags & CRYPTO_F_IOV) { 1516 if (!nicealign) { 1517 ubsecstats.hst_iovmisaligned++; 1518 err = EINVAL; 1519 goto errout; 1520 } 1521 if (q->q_dst_map == NULL) { 1522 if (q->q_cached_dst_map == NULL) { 1523 /* 1524 * XXX: ``what the heck's that'' 1525 * 0xfff0? 1526 */ 1527 if (bus_dmamap_create(sc->sc_dmat, 1528 0xfff0, UBS_MAX_SCATTER, 0xfff0, 0, 1529 BUS_DMA_NOWAIT, 1530 &q->q_cached_dst_map) != 0) { 1531 ubsecstats.hst_nomap++; 1532 err = ENOMEM; 1533 goto errout; 1534 } 1535 } 1536 q->q_dst_map = q->q_cached_dst_map; 1537 } 1538 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1539 q->q_dst_io, BUS_DMA_NOWAIT) != 0) { 1540 ubsecstats.hst_noload++; 1541 err = ENOMEM; 1542 goto errout; 1543 } 1544 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1545 if (nicealign) { 1546 q->q_dst_m = q->q_src_m; 1547 q->q_dst_map = q->q_src_map; 1548 } else { 1549 int totlen, len; 1550 struct mbuf *m, *top, **mp; 1551 1552 ubsecstats.hst_unaligned++; 1553 totlen = q->q_src_map->dm_mapsize; 1554 if (q->q_src_m->m_flags & M_PKTHDR) { 1555 len = MHLEN; 1556 MGETHDR(m, M_DONTWAIT, MT_DATA); 1557 /*XXX FIXME: m_dup_pkthdr */ 1558 if (m && 1 /*!m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)*/) { 1559 m_free(m); 1560 m = NULL; 1561 } 1562 } else { 1563 len = MLEN; 1564 MGET(m, M_DONTWAIT, MT_DATA); 1565 } 1566 if (m == NULL) { 1567 ubsecstats.hst_nombuf++; 1568 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1569 goto errout; 1570 } 1571 if (len == MHLEN) 1572 /*XXX was M_DUP_PKTHDR*/ 1573 m_copy_pkthdr(m, q->q_src_m); 1574 if (totlen >= MINCLSIZE) { 1575 MCLGET(m, M_DONTWAIT); 1576 if ((m->m_flags & M_EXT) == 0) { 1577 m_free(m); 1578 ubsecstats.hst_nomcl++; 1579 err = sc->sc_nqueue 1580 ? ERESTART : ENOMEM; 1581 goto errout; 1582 } 1583 len = MCLBYTES; 1584 } 1585 m->m_len = len; 1586 top = NULL; 1587 mp = ⊤ 1588 1589 while (totlen > 0) { 1590 if (top) { 1591 MGET(m, M_DONTWAIT, MT_DATA); 1592 if (m == NULL) { 1593 m_freem(top); 1594 ubsecstats.hst_nombuf++; 1595 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1596 goto errout; 1597 } 1598 len = MLEN; 1599 } 1600 if (top && totlen >= MINCLSIZE) { 1601 MCLGET(m, M_DONTWAIT); 1602 if ((m->m_flags & M_EXT) == 0) { 1603 *mp = m; 1604 m_freem(top); 1605 ubsecstats.hst_nomcl++; 1606 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1607 goto errout; 1608 } 1609 len = MCLBYTES; 1610 } 1611 m->m_len = len = uimin(totlen, len); 1612 totlen -= len; 1613 *mp = m; 1614 mp = &m->m_next; 1615 } 1616 q->q_dst_m = top; 1617 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1618 cpskip, cpoffset); 1619 if (q->q_dst_map == NULL) { 1620 if (q->q_cached_dst_map == NULL) { 1621 /* XXX again, what the heck is that 0xfff0? */ 1622 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, 1623 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, 1624 &q->q_cached_dst_map) != 0) { 1625 ubsecstats.hst_nomap++; 1626 err = ENOMEM; 1627 goto errout; 1628 } 1629 } 1630 q->q_dst_map = q->q_cached_dst_map; 1631 } 1632 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1633 q->q_dst_map, q->q_dst_m, 1634 BUS_DMA_NOWAIT) != 0) { 1635 ubsecstats.hst_noload++; 1636 err = ENOMEM; 1637 goto errout; 1638 } 1639 } 1640 } else { 1641 ubsecstats.hst_badflags++; 1642 err = EINVAL; 1643 goto errout; 1644 } 1645 1646 #ifdef UBSEC_DEBUG 1647 if (ubsec_debug) 1648 printf("dst skip: %d\n", dskip); 1649 #endif 1650 for (i = j = 0; i < q->q_dst_map->dm_nsegs; i++) { 1651 struct ubsec_pktbuf *pb; 1652 bus_size_t packl = q->q_dst_map->dm_segs[i].ds_len; 1653 bus_addr_t packp = q->q_dst_map->dm_segs[i].ds_addr; 1654 1655 if (dskip >= packl) { 1656 dskip -= packl; 1657 continue; 1658 } 1659 1660 packl -= dskip; 1661 packp += dskip; 1662 dskip = 0; 1663 1664 if (packl > 0xfffc) { 1665 err = EIO; 1666 goto errout; 1667 } 1668 1669 if (j == 0) 1670 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1671 else 1672 pb = &dmap->d_dma->d_dbuf[j - 1]; 1673 1674 pb->pb_addr = htole32(packp); 1675 1676 if (dtheend) { 1677 if (packl > dtheend) { 1678 pb->pb_len = htole32(dtheend); 1679 dtheend = 0; 1680 } else { 1681 pb->pb_len = htole32(packl); 1682 dtheend -= packl; 1683 } 1684 } else 1685 pb->pb_len = htole32(packl); 1686 1687 if ((i + 1) == q->q_dst_map->dm_nsegs) { 1688 if (maccrd) 1689 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1690 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1691 else 1692 pb->pb_next = 0; 1693 } else 1694 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1695 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1696 j++; 1697 } 1698 } 1699 1700 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1701 offsetof(struct ubsec_dmachunk, d_ctx)); 1702 1703 if (enccrd && enccrd->crd_alg == CRYPTO_AES_CBC) { 1704 struct ubsec_pktctx_aes128 *aes128; 1705 struct ubsec_pktctx_aes192 *aes192; 1706 struct ubsec_pktctx_aes256 *aes256; 1707 struct ubsec_pktctx_hdr *ph; 1708 u_int8_t *ctx; 1709 1710 ctx = (u_int8_t *)(dmap->d_alloc.dma_vaddr) + 1711 offsetof(struct ubsec_dmachunk, d_ctx); 1712 1713 ph = (struct ubsec_pktctx_hdr *)ctx; 1714 ph->ph_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES); 1715 ph->ph_flags = flags; 1716 ph->ph_offset = htole16(coffset >> 2); 1717 1718 switch (enccrd->crd_klen) { 1719 case 128: 1720 aes128 = (struct ubsec_pktctx_aes128 *)ctx; 1721 ph->ph_len = htole16(sizeof(*aes128)); 1722 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_128); 1723 for (i = 0; i < 4; i++) 1724 aes128->pc_aeskey[i] = key.ses_key[i]; 1725 for (i = 0; i < 5; i++) 1726 aes128->pc_hminner[i] = key.ses_hminner[i]; 1727 for (i = 0; i < 5; i++) 1728 aes128->pc_hmouter[i] = key.ses_hmouter[i]; 1729 for (i = 0; i < 4; i++) 1730 aes128->pc_iv[i] = key.ses_iv[i]; 1731 break; 1732 case 192: 1733 aes192 = (struct ubsec_pktctx_aes192 *)ctx; 1734 ph->ph_len = htole16(sizeof(*aes192)); 1735 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_192); 1736 for (i = 0; i < 6; i++) 1737 aes192->pc_aeskey[i] = key.ses_key[i]; 1738 for (i = 0; i < 5; i++) 1739 aes192->pc_hminner[i] = key.ses_hminner[i]; 1740 for (i = 0; i < 5; i++) 1741 aes192->pc_hmouter[i] = key.ses_hmouter[i]; 1742 for (i = 0; i < 4; i++) 1743 aes192->pc_iv[i] = key.ses_iv[i]; 1744 break; 1745 case 256: 1746 aes256 = (struct ubsec_pktctx_aes256 *)ctx; 1747 ph->ph_len = htole16(sizeof(*aes256)); 1748 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_256); 1749 for (i = 0; i < 8; i++) 1750 aes256->pc_aeskey[i] = key.ses_key[i]; 1751 for (i = 0; i < 5; i++) 1752 aes256->pc_hminner[i] = key.ses_hminner[i]; 1753 for (i = 0; i < 5; i++) 1754 aes256->pc_hmouter[i] = key.ses_hmouter[i]; 1755 for (i = 0; i < 4; i++) 1756 aes256->pc_iv[i] = key.ses_iv[i]; 1757 break; 1758 } 1759 } else if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1760 struct ubsec_pktctx_3des *ctx; 1761 struct ubsec_pktctx_hdr *ph; 1762 1763 ctx = (struct ubsec_pktctx_3des *) 1764 ((u_int8_t *)(dmap->d_alloc.dma_vaddr) + 1765 offsetof(struct ubsec_dmachunk, d_ctx)); 1766 1767 ph = (struct ubsec_pktctx_hdr *)ctx; 1768 ph->ph_len = htole16(sizeof(*ctx)); 1769 ph->ph_type = htole16(UBS_PKTCTX_TYPE_IPSEC_3DES); 1770 ph->ph_flags = flags; 1771 ph->ph_offset = htole16(coffset >> 2); 1772 1773 for (i = 0; i < 6; i++) 1774 ctx->pc_deskey[i] = key.ses_key[i]; 1775 for (i = 0; i < 5; i++) 1776 ctx->pc_hminner[i] = key.ses_hminner[i]; 1777 for (i = 0; i < 5; i++) 1778 ctx->pc_hmouter[i] = key.ses_hmouter[i]; 1779 for (i = 0; i < 2; i++) 1780 ctx->pc_iv[i] = key.ses_iv[i]; 1781 } else { 1782 struct ubsec_pktctx *ctx = (struct ubsec_pktctx *) 1783 ((u_int8_t *)dmap->d_alloc.dma_vaddr + 1784 offsetof(struct ubsec_dmachunk, d_ctx)); 1785 1786 ctx->pc_flags = flags; 1787 ctx->pc_offset = htole16(coffset >> 2); 1788 for (i = 0; i < 6; i++) 1789 ctx->pc_deskey[i] = key.ses_key[i]; 1790 for (i = 0; i < 5; i++) 1791 ctx->pc_hminner[i] = key.ses_hminner[i]; 1792 for (i = 0; i < 5; i++) 1793 ctx->pc_hmouter[i] = key.ses_hmouter[i]; 1794 for (i = 0; i < 2; i++) 1795 ctx->pc_iv[i] = key.ses_iv[i]; 1796 } 1797 1798 mutex_spin_enter(&sc->sc_mtx); 1799 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1800 sc->sc_nqueue++; 1801 ubsecstats.hst_ipackets++; 1802 ubsecstats.hst_ibytes += dmap->d_alloc.dma_map->dm_mapsize; 1803 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= ubsec_maxbatch) 1804 ubsec_feed(sc); 1805 mutex_spin_exit(&sc->sc_mtx); 1806 return (0); 1807 1808 errout: 1809 if (q != NULL) { 1810 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1811 m_freem(q->q_dst_m); 1812 1813 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1814 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1815 } 1816 if (q->q_src_map != NULL) { 1817 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1818 } 1819 1820 mutex_spin_enter(&sc->sc_mtx); 1821 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1822 mutex_spin_exit(&sc->sc_mtx); 1823 } 1824 #if 0 /* jonathan says: this openbsd code seems to be subsumed elsewhere */ 1825 if (err == EINVAL) 1826 ubsecstats.hst_invalid++; 1827 else 1828 ubsecstats.hst_nomem++; 1829 #endif 1830 if (err != ERESTART) { 1831 crp->crp_etype = err; 1832 crypto_done(crp); 1833 } else { 1834 sc->sc_needwakeup |= CRYPTO_SYMQ; 1835 } 1836 return (err); 1837 } 1838 1839 static void 1840 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1841 { 1842 struct cryptop *crp = (struct cryptop *)q->q_crp; 1843 struct cryptodesc *crd; 1844 struct ubsec_dma *dmap = q->q_dma; 1845 1846 ubsecstats.hst_opackets++; 1847 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1848 1849 bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, 1850 dmap->d_alloc.dma_map->dm_mapsize, 1851 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1852 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1853 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1854 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1855 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1856 } 1857 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 1858 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1859 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1860 1861 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1862 m_freem(q->q_src_m); 1863 crp->crp_buf = (void *)q->q_dst_m; 1864 } 1865 1866 /* copy out IV for future use */ 1867 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1868 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1869 if (crd->crd_alg != CRYPTO_DES_CBC && 1870 crd->crd_alg != CRYPTO_3DES_CBC && 1871 crd->crd_alg != CRYPTO_AES_CBC) 1872 continue; 1873 if (crp->crp_flags & CRYPTO_F_IMBUF) 1874 m_copydata((struct mbuf *)crp->crp_buf, 1875 crd->crd_skip + crd->crd_len - 8, 8, 1876 (void *)sc->sc_sessions[q->q_sesn].ses_iv); 1877 else if (crp->crp_flags & CRYPTO_F_IOV) { 1878 cuio_copydata((struct uio *)crp->crp_buf, 1879 crd->crd_skip + crd->crd_len - 8, 8, 1880 (void *)sc->sc_sessions[q->q_sesn].ses_iv); 1881 } 1882 break; 1883 } 1884 } 1885 1886 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1887 if (crd->crd_alg != CRYPTO_MD5_HMAC_96 && 1888 crd->crd_alg != CRYPTO_SHA1_HMAC_96) 1889 continue; 1890 if (crp->crp_flags & CRYPTO_F_IMBUF) 1891 m_copyback((struct mbuf *)crp->crp_buf, 1892 crd->crd_inject, 12, 1893 (void *)dmap->d_dma->d_macbuf); 1894 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1895 bcopy((void *)dmap->d_dma->d_macbuf, 1896 crp->crp_mac, 12); 1897 break; 1898 } 1899 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1900 crypto_done(crp); 1901 } 1902 1903 static void 1904 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1905 { 1906 int i, j, dlen, slen; 1907 char *dptr, *sptr; 1908 1909 j = 0; 1910 sptr = srcm->m_data; 1911 slen = srcm->m_len; 1912 dptr = dstm->m_data; 1913 dlen = dstm->m_len; 1914 1915 while (1) { 1916 for (i = 0; i < uimin(slen, dlen); i++) { 1917 if (j < hoffset || j >= toffset) 1918 *dptr++ = *sptr++; 1919 slen--; 1920 dlen--; 1921 j++; 1922 } 1923 if (slen == 0) { 1924 srcm = srcm->m_next; 1925 if (srcm == NULL) 1926 return; 1927 sptr = srcm->m_data; 1928 slen = srcm->m_len; 1929 } 1930 if (dlen == 0) { 1931 dstm = dstm->m_next; 1932 if (dstm == NULL) 1933 return; 1934 dptr = dstm->m_data; 1935 dlen = dstm->m_len; 1936 } 1937 } 1938 } 1939 1940 /* 1941 * feed the key generator, must be called at splnet() or higher. 1942 */ 1943 static void 1944 ubsec_feed2(struct ubsec_softc *sc) 1945 { 1946 struct ubsec_q2 *q; 1947 1948 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1949 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1950 break; 1951 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1952 1953 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1954 q->q_mcr.dma_map->dm_mapsize, 1955 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1956 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1957 q->q_ctx.dma_map->dm_mapsize, 1958 BUS_DMASYNC_PREWRITE); 1959 1960 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1961 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1962 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, /*q,*/ q_next); 1963 --sc->sc_nqueue2; 1964 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1965 } 1966 } 1967 1968 /* 1969 * feed the RNG (used instead of ubsec_feed2() on 5827+ devices) 1970 */ 1971 void 1972 ubsec_feed4(struct ubsec_softc *sc) 1973 { 1974 struct ubsec_q2 *q; 1975 1976 while (!SIMPLEQ_EMPTY(&sc->sc_queue4)) { 1977 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR4_FULL) 1978 break; 1979 q = SIMPLEQ_FIRST(&sc->sc_queue4); 1980 1981 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1982 q->q_mcr.dma_map->dm_mapsize, 1983 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1984 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1985 q->q_ctx.dma_map->dm_mapsize, 1986 BUS_DMASYNC_PREWRITE); 1987 1988 WRITE_REG(sc, BS_MCR4, q->q_mcr.dma_paddr); 1989 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue4, q_next); 1990 --sc->sc_nqueue4; 1991 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip4, q, q_next); 1992 } 1993 } 1994 1995 /* 1996 * Callback for handling random numbers 1997 */ 1998 static void 1999 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 2000 { 2001 struct cryptkop *krp; 2002 struct ubsec_ctx_keyop *ctx; 2003 2004 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 2005 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 2006 q->q_ctx.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2007 2008 switch (q->q_type) { 2009 #ifndef UBSEC_NO_RNG 2010 case UBS_CTXOP_RNGSHA1: 2011 case UBS_CTXOP_RNGBYPASS: { 2012 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 2013 u_int32_t *p; 2014 int i; 2015 2016 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 2017 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2018 p = (u_int32_t *)rng->rng_buf.dma_vaddr; 2019 #ifndef __NetBSD__ 2020 for (i = 0; i < UBSEC_RNG_BUFSIZ; p++, i++) 2021 add_true_randomness(letoh32(*p)); 2022 #else 2023 i = UBSEC_RNG_BUFSIZ * sizeof(u_int32_t); 2024 rnd_add_data(&sc->sc_rnd_source, (char *)p, i, i * NBBY); 2025 sc->sc_rng_need -= i; 2026 #endif 2027 rng->rng_used = 0; 2028 #ifdef __OpenBSD__ 2029 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 2030 #else 2031 if (sc->sc_rng_need > 0) { 2032 callout_schedule(&sc->sc_rngto, sc->sc_rnghz); 2033 } 2034 #endif 2035 break; 2036 } 2037 #endif 2038 case UBS_CTXOP_MODEXP: { 2039 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2040 u_int rlen, clen; 2041 2042 krp = me->me_krp; 2043 rlen = (me->me_modbits + 7) / 8; 2044 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 2045 2046 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2047 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2048 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2049 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2050 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2051 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2052 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2053 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2054 2055 if (clen < rlen) 2056 krp->krp_status = E2BIG; 2057 else { 2058 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 2059 memset(krp->krp_param[krp->krp_iparams].crp_p, 0, 2060 (krp->krp_param[krp->krp_iparams].crp_nbits 2061 + 7) / 8); 2062 bcopy(me->me_C.dma_vaddr, 2063 krp->krp_param[krp->krp_iparams].crp_p, 2064 (me->me_modbits + 7) / 8); 2065 } else 2066 ubsec_kshift_l(me->me_shiftbits, 2067 me->me_C.dma_vaddr, me->me_normbits, 2068 krp->krp_param[krp->krp_iparams].crp_p, 2069 krp->krp_param[krp->krp_iparams].crp_nbits); 2070 } 2071 2072 crypto_kdone(krp); 2073 2074 /* bzero all potentially sensitive data */ 2075 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2076 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2077 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2078 memset(me->me_q.q_ctx.dma_vaddr, 0, me->me_q.q_ctx.dma_size); 2079 2080 /* Can't free here, so put us on the free list. */ 2081 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 2082 break; 2083 } 2084 case UBS_CTXOP_RSAPRIV: { 2085 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2086 u_int len; 2087 2088 krp = rp->rpr_krp; 2089 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 0, 2090 rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2091 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 0, 2092 rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2093 2094 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) 2095 / 8; 2096 bcopy(rp->rpr_msgout.dma_vaddr, 2097 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 2098 2099 crypto_kdone(krp); 2100 2101 memset(rp->rpr_msgin.dma_vaddr, 0, rp->rpr_msgin.dma_size); 2102 memset(rp->rpr_msgout.dma_vaddr, 0, rp->rpr_msgout.dma_size); 2103 memset(rp->rpr_q.q_ctx.dma_vaddr, 0, rp->rpr_q.q_ctx.dma_size); 2104 2105 /* Can't free here, so put us on the free list. */ 2106 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 2107 break; 2108 } 2109 default: 2110 printf("%s: unknown ctx op: %x\n", device_xname(sc->sc_dev), 2111 letoh16(ctx->ctx_op)); 2112 break; 2113 } 2114 } 2115 2116 #ifndef UBSEC_NO_RNG 2117 2118 static void 2119 ubsec_rng_get(size_t bytes, void *vsc) 2120 { 2121 struct ubsec_softc *sc = vsc; 2122 2123 mutex_spin_enter(&sc->sc_mtx); 2124 sc->sc_rng_need = bytes; 2125 ubsec_rng_locked(sc); 2126 mutex_spin_exit(&sc->sc_mtx); 2127 2128 } 2129 2130 static void 2131 ubsec_rng(void *vsc) 2132 { 2133 struct ubsec_softc *sc = vsc; 2134 mutex_spin_enter(&sc->sc_mtx); 2135 ubsec_rng_locked(sc); 2136 mutex_spin_exit(&sc->sc_mtx); 2137 } 2138 2139 static void 2140 ubsec_rng_locked(void *vsc) 2141 { 2142 struct ubsec_softc *sc = vsc; 2143 struct ubsec_q2_rng *rng = &sc->sc_rng; 2144 struct ubsec_mcr *mcr; 2145 struct ubsec_ctx_rngbypass *ctx; 2146 int *nqueue; 2147 2148 /* Caller is responsible to lock and release sc_mtx. */ 2149 KASSERT(mutex_owned(&sc->sc_mtx)); 2150 2151 if (rng->rng_used) { 2152 return; 2153 } 2154 2155 if (sc->sc_rng_need < 1) { 2156 callout_stop(&sc->sc_rngto); 2157 return; 2158 } 2159 2160 if (sc->sc_flags & UBS_FLAGS_RNG4) 2161 nqueue = &sc->sc_nqueue4; 2162 else 2163 nqueue = &sc->sc_nqueue2; 2164 2165 (*nqueue)++; 2166 if (*nqueue >= UBS_MAX_NQUEUE) 2167 goto out; 2168 2169 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 2170 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 2171 2172 mcr->mcr_pkts = htole16(1); 2173 mcr->mcr_flags = 0; 2174 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 2175 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 2176 mcr->mcr_ipktbuf.pb_len = 0; 2177 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 2178 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 2179 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 2180 UBS_PKTBUF_LEN); 2181 mcr->mcr_opktbuf.pb_next = 0; 2182 2183 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 2184 ctx->rbp_op = htole16(UBS_CTXOP_RNGSHA1); 2185 rng->rng_q.q_type = UBS_CTXOP_RNGSHA1; 2186 2187 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 2188 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2189 2190 if (sc->sc_flags & UBS_FLAGS_RNG4) { 2191 SIMPLEQ_INSERT_TAIL(&sc->sc_queue4, &rng->rng_q, q_next); 2192 ubsec_feed4(sc); 2193 } else { 2194 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 2195 ubsec_feed2(sc); 2196 } 2197 rng->rng_used = 1; 2198 ubsecstats.hst_rng++; 2199 2200 return; 2201 2202 out: 2203 /* 2204 * Something weird happened, generate our own call back. 2205 */ 2206 (*nqueue)--; 2207 #ifdef __OpenBSD__ 2208 timeout_add(&sc->sc_rngto, sc->sc_rnghz); 2209 #else 2210 callout_schedule(&sc->sc_rngto, sc->sc_rnghz); 2211 #endif 2212 } 2213 #endif /* UBSEC_NO_RNG */ 2214 2215 static int 2216 ubsec_dma_malloc(struct ubsec_softc *sc, bus_size_t size, 2217 struct ubsec_dma_alloc *dma,int mapflags) 2218 { 2219 int r; 2220 2221 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 2222 &dma->dma_seg, 1, &dma->dma_nseg, BUS_DMA_NOWAIT)) != 0) 2223 goto fail_0; 2224 2225 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 2226 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 2227 goto fail_1; 2228 2229 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 2230 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 2231 goto fail_2; 2232 2233 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 2234 size, NULL, BUS_DMA_NOWAIT)) != 0) 2235 goto fail_3; 2236 2237 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 2238 dma->dma_size = size; 2239 return (0); 2240 2241 fail_3: 2242 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2243 fail_2: 2244 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 2245 fail_1: 2246 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2247 fail_0: 2248 dma->dma_map = NULL; 2249 return (r); 2250 } 2251 2252 static void 2253 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 2254 { 2255 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 2256 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 2257 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2258 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2259 } 2260 2261 /* 2262 * Resets the board. Values in the regesters are left as is 2263 * from the reset (i.e. initial values are assigned elsewhere). 2264 */ 2265 static void 2266 ubsec_reset_board(struct ubsec_softc *sc) 2267 { 2268 volatile u_int32_t ctrl; 2269 2270 ctrl = READ_REG(sc, BS_CTRL); 2271 ctrl |= BS_CTRL_RESET; 2272 WRITE_REG(sc, BS_CTRL, ctrl); 2273 2274 /* 2275 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 2276 */ 2277 DELAY(10); 2278 2279 /* Enable RNG and interrupts on newer devices */ 2280 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) { 2281 #ifndef UBSEC_NO_RNG 2282 WRITE_REG(sc, BS_CFG, BS_CFG_RNG); 2283 #endif 2284 WRITE_REG(sc, BS_INT, BS_INT_DMAINT); 2285 } 2286 } 2287 2288 /* 2289 * Init Broadcom registers 2290 */ 2291 static void 2292 ubsec_init_board(struct ubsec_softc *sc) 2293 { 2294 u_int32_t ctrl; 2295 2296 ctrl = READ_REG(sc, BS_CTRL); 2297 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 2298 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 2299 2300 /* 2301 * XXX: Sam Leffler's code has (UBS_FLAGS_KEY|UBS_FLAGS_RNG)). 2302 * anyone got hw docs? 2303 */ 2304 if (sc->sc_flags & UBS_FLAGS_KEY) 2305 ctrl |= BS_CTRL_MCR2INT; 2306 else 2307 ctrl &= ~BS_CTRL_MCR2INT; 2308 2309 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2310 ctrl &= ~BS_CTRL_SWNORM; 2311 2312 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) { 2313 ctrl |= BS_CTRL_BSIZE240; 2314 ctrl &= ~BS_CTRL_MCR3INT; /* MCR3 is reserved for SSL */ 2315 2316 if (sc->sc_flags & UBS_FLAGS_RNG4) 2317 ctrl |= BS_CTRL_MCR4INT; 2318 else 2319 ctrl &= ~BS_CTRL_MCR4INT; 2320 } 2321 2322 WRITE_REG(sc, BS_CTRL, ctrl); 2323 } 2324 2325 /* 2326 * Init Broadcom PCI registers 2327 */ 2328 static void 2329 ubsec_init_pciregs(struct pci_attach_args *pa) 2330 { 2331 pci_chipset_tag_t pc = pa->pa_pc; 2332 u_int32_t misc; 2333 2334 /* 2335 * This will set the cache line size to 1, this will 2336 * force the BCM58xx chip just to do burst read/writes. 2337 * Cache line read/writes are to slow 2338 */ 2339 misc = pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 2340 misc = (misc & ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)) 2341 | ((UBS_DEF_CACHELINE & 0xff) << PCI_CACHELINE_SHIFT); 2342 pci_conf_write(pc, pa->pa_tag, PCI_BHLC_REG, misc); 2343 } 2344 2345 /* 2346 * Clean up after a chip crash. 2347 * It is assumed that the caller in splnet() 2348 */ 2349 static void 2350 ubsec_cleanchip(struct ubsec_softc *sc) 2351 { 2352 struct ubsec_q *q; 2353 2354 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 2355 q = SIMPLEQ_FIRST(&sc->sc_qchip); 2356 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 2357 ubsec_free_q(sc, q); 2358 } 2359 sc->sc_nqchip = 0; 2360 } 2361 2362 /* 2363 * free a ubsec_q 2364 * It is assumed that the caller is within splnet() 2365 */ 2366 static int 2367 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2368 { 2369 struct ubsec_q *q2; 2370 struct cryptop *crp; 2371 int npkts; 2372 int i; 2373 2374 npkts = q->q_nstacked_mcrs; 2375 2376 for (i = 0; i < npkts; i++) { 2377 if(q->q_stacked_mcr[i]) { 2378 q2 = q->q_stacked_mcr[i]; 2379 2380 if ((q2->q_dst_m != NULL) 2381 && (q2->q_src_m != q2->q_dst_m)) 2382 m_freem(q2->q_dst_m); 2383 2384 crp = (struct cryptop *)q2->q_crp; 2385 2386 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2387 2388 crp->crp_etype = EFAULT; 2389 crypto_done(crp); 2390 } else { 2391 break; 2392 } 2393 } 2394 2395 /* 2396 * Free header MCR 2397 */ 2398 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2399 m_freem(q->q_dst_m); 2400 2401 crp = (struct cryptop *)q->q_crp; 2402 2403 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2404 2405 crp->crp_etype = EFAULT; 2406 crypto_done(crp); 2407 return(0); 2408 } 2409 2410 /* 2411 * Routine to reset the chip and clean up. 2412 * It is assumed that the caller is in splnet() 2413 */ 2414 static void 2415 ubsec_totalreset(struct ubsec_softc *sc) 2416 { 2417 ubsec_reset_board(sc); 2418 ubsec_init_board(sc); 2419 ubsec_cleanchip(sc); 2420 } 2421 2422 static int 2423 ubsec_dmamap_aligned(bus_dmamap_t map) 2424 { 2425 int i; 2426 2427 for (i = 0; i < map->dm_nsegs; i++) { 2428 if (map->dm_segs[i].ds_addr & 3) 2429 return (0); 2430 if ((i != (map->dm_nsegs - 1)) && 2431 (map->dm_segs[i].ds_len & 3)) 2432 return (0); 2433 } 2434 return (1); 2435 } 2436 2437 #ifdef __OpenBSD__ 2438 struct ubsec_softc * 2439 ubsec_kfind(struct cryptkop *krp) 2440 { 2441 struct ubsec_softc *sc; 2442 int i; 2443 2444 for (i = 0; i < ubsec_cd.cd_ndevs; i++) { 2445 sc = ubsec_cd.cd_devs[i]; 2446 if (sc == NULL) 2447 continue; 2448 if (sc->sc_cid == krp->krp_hid) 2449 return (sc); 2450 } 2451 return (NULL); 2452 } 2453 #endif 2454 2455 static void 2456 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2457 { 2458 switch (q->q_type) { 2459 case UBS_CTXOP_MODEXP: { 2460 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2461 2462 ubsec_dma_free(sc, &me->me_q.q_mcr); 2463 ubsec_dma_free(sc, &me->me_q.q_ctx); 2464 ubsec_dma_free(sc, &me->me_M); 2465 ubsec_dma_free(sc, &me->me_E); 2466 ubsec_dma_free(sc, &me->me_C); 2467 ubsec_dma_free(sc, &me->me_epb); 2468 free(me, M_DEVBUF); 2469 break; 2470 } 2471 case UBS_CTXOP_RSAPRIV: { 2472 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2473 2474 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2475 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2476 ubsec_dma_free(sc, &rp->rpr_msgin); 2477 ubsec_dma_free(sc, &rp->rpr_msgout); 2478 free(rp, M_DEVBUF); 2479 break; 2480 } 2481 default: 2482 printf("%s: invalid kfree 0x%x\n", device_xname(sc->sc_dev), 2483 q->q_type); 2484 break; 2485 } 2486 } 2487 2488 static int 2489 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2490 { 2491 struct ubsec_softc *sc; 2492 int r; 2493 2494 if (krp == NULL || krp->krp_callback == NULL) 2495 return (EINVAL); 2496 #ifdef __OpenBSD__ 2497 if ((sc = ubsec_kfind(krp)) == NULL) 2498 return (EINVAL); 2499 #else 2500 sc = arg; 2501 KASSERT(sc != NULL /*, ("ubsec_kprocess: null softc")*/); 2502 #endif 2503 2504 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2505 struct ubsec_q2 *q; 2506 2507 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2508 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, /*q,*/ q_next); 2509 ubsec_kfree(sc, q); 2510 } 2511 2512 switch (krp->krp_op) { 2513 case CRK_MOD_EXP: 2514 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2515 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2516 else 2517 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2518 break; 2519 case CRK_MOD_EXP_CRT: 2520 r = ubsec_kprocess_rsapriv(sc, krp, hint); 2521 break; 2522 default: 2523 printf("%s: kprocess: invalid op 0x%x\n", 2524 device_xname(sc->sc_dev), krp->krp_op); 2525 krp->krp_status = EOPNOTSUPP; 2526 crypto_kdone(krp); 2527 r = 0; 2528 } 2529 return (r); 2530 } 2531 2532 /* 2533 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2534 */ 2535 static int 2536 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, 2537 int hint) 2538 { 2539 struct ubsec_q2_modexp *me; 2540 struct ubsec_mcr *mcr; 2541 struct ubsec_ctx_modexp *ctx; 2542 struct ubsec_pktbuf *epb; 2543 int err = 0; 2544 u_int nbits, normbits, mbits, shiftbits, ebits; 2545 2546 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2547 if (me == NULL) { 2548 err = ENOMEM; 2549 goto errout; 2550 } 2551 memset(me, 0, sizeof *me); 2552 me->me_krp = krp; 2553 me->me_q.q_type = UBS_CTXOP_MODEXP; 2554 2555 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2556 if (nbits <= 512) 2557 normbits = 512; 2558 else if (nbits <= 768) 2559 normbits = 768; 2560 else if (nbits <= 1024) 2561 normbits = 1024; 2562 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2563 normbits = 1536; 2564 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2565 normbits = 2048; 2566 else { 2567 err = E2BIG; 2568 goto errout; 2569 } 2570 2571 shiftbits = normbits - nbits; 2572 2573 me->me_modbits = nbits; 2574 me->me_shiftbits = shiftbits; 2575 me->me_normbits = normbits; 2576 2577 /* Sanity check: result bits must be >= true modulus bits. */ 2578 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2579 err = ERANGE; 2580 goto errout; 2581 } 2582 2583 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2584 &me->me_q.q_mcr, 0)) { 2585 err = ENOMEM; 2586 goto errout; 2587 } 2588 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2589 2590 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2591 &me->me_q.q_ctx, 0)) { 2592 err = ENOMEM; 2593 goto errout; 2594 } 2595 2596 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2597 if (mbits > nbits) { 2598 err = E2BIG; 2599 goto errout; 2600 } 2601 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2602 err = ENOMEM; 2603 goto errout; 2604 } 2605 ubsec_kshift_r(shiftbits, 2606 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2607 me->me_M.dma_vaddr, normbits); 2608 2609 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2610 err = ENOMEM; 2611 goto errout; 2612 } 2613 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2614 2615 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2616 if (ebits > nbits) { 2617 err = E2BIG; 2618 goto errout; 2619 } 2620 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2621 err = ENOMEM; 2622 goto errout; 2623 } 2624 ubsec_kshift_r(shiftbits, 2625 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2626 me->me_E.dma_vaddr, normbits); 2627 2628 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2629 &me->me_epb, 0)) { 2630 err = ENOMEM; 2631 goto errout; 2632 } 2633 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2634 epb->pb_addr = htole32(me->me_E.dma_paddr); 2635 epb->pb_next = 0; 2636 epb->pb_len = htole32(normbits / 8); 2637 2638 #ifdef UBSEC_DEBUG 2639 if (ubsec_debug) { 2640 printf("Epb "); 2641 ubsec_dump_pb(epb); 2642 } 2643 #endif 2644 2645 mcr->mcr_pkts = htole16(1); 2646 mcr->mcr_flags = 0; 2647 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2648 mcr->mcr_reserved = 0; 2649 mcr->mcr_pktlen = 0; 2650 2651 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2652 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2653 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2654 2655 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2656 mcr->mcr_opktbuf.pb_next = 0; 2657 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2658 2659 #ifdef DIAGNOSTIC 2660 /* Misaligned output buffer will hang the chip. */ 2661 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2662 panic("%s: modexp invalid addr 0x%x", device_xname(sc->sc_dev), 2663 letoh32(mcr->mcr_opktbuf.pb_addr)); 2664 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2665 panic("%s: modexp invalid len 0x%x", device_xname(sc->sc_dev), 2666 letoh32(mcr->mcr_opktbuf.pb_len)); 2667 #endif 2668 2669 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2670 memset(ctx, 0, sizeof(*ctx)); 2671 ubsec_kshift_r(shiftbits, 2672 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2673 ctx->me_N, normbits); 2674 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2675 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2676 ctx->me_E_len = htole16(nbits); 2677 ctx->me_N_len = htole16(nbits); 2678 2679 #ifdef UBSEC_DEBUG 2680 if (ubsec_debug) { 2681 ubsec_dump_mcr(mcr); 2682 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2683 } 2684 #endif 2685 2686 /* 2687 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2688 * everything else. 2689 */ 2690 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2691 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2692 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2693 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2694 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2695 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2696 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2697 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2698 2699 /* Enqueue and we're done... */ 2700 mutex_spin_enter(&sc->sc_mtx); 2701 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2702 ubsec_feed2(sc); 2703 ubsecstats.hst_modexp++; 2704 mutex_spin_exit(&sc->sc_mtx); 2705 2706 return (0); 2707 2708 errout: 2709 if (me != NULL) { 2710 if (me->me_q.q_mcr.dma_map != NULL) 2711 ubsec_dma_free(sc, &me->me_q.q_mcr); 2712 if (me->me_q.q_ctx.dma_map != NULL) { 2713 memset(me->me_q.q_ctx.dma_vaddr, 0, 2714 me->me_q.q_ctx.dma_size); 2715 ubsec_dma_free(sc, &me->me_q.q_ctx); 2716 } 2717 if (me->me_M.dma_map != NULL) { 2718 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2719 ubsec_dma_free(sc, &me->me_M); 2720 } 2721 if (me->me_E.dma_map != NULL) { 2722 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2723 ubsec_dma_free(sc, &me->me_E); 2724 } 2725 if (me->me_C.dma_map != NULL) { 2726 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2727 ubsec_dma_free(sc, &me->me_C); 2728 } 2729 if (me->me_epb.dma_map != NULL) 2730 ubsec_dma_free(sc, &me->me_epb); 2731 free(me, M_DEVBUF); 2732 } 2733 krp->krp_status = err; 2734 crypto_kdone(krp); 2735 return (0); 2736 } 2737 2738 /* 2739 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2740 */ 2741 static int 2742 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, 2743 int hint) 2744 { 2745 struct ubsec_q2_modexp *me; 2746 struct ubsec_mcr *mcr; 2747 struct ubsec_ctx_modexp *ctx; 2748 struct ubsec_pktbuf *epb; 2749 int err = 0; 2750 u_int nbits, normbits, mbits, shiftbits, ebits; 2751 2752 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2753 if (me == NULL) { 2754 err = ENOMEM; 2755 goto errout; 2756 } 2757 memset(me, 0, sizeof *me); 2758 me->me_krp = krp; 2759 me->me_q.q_type = UBS_CTXOP_MODEXP; 2760 2761 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2762 if (nbits <= 512) 2763 normbits = 512; 2764 else if (nbits <= 768) 2765 normbits = 768; 2766 else if (nbits <= 1024) 2767 normbits = 1024; 2768 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2769 normbits = 1536; 2770 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2771 normbits = 2048; 2772 else { 2773 err = E2BIG; 2774 goto errout; 2775 } 2776 2777 shiftbits = normbits - nbits; 2778 2779 /* XXX ??? */ 2780 me->me_modbits = nbits; 2781 me->me_shiftbits = shiftbits; 2782 me->me_normbits = normbits; 2783 2784 /* Sanity check: result bits must be >= true modulus bits. */ 2785 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2786 err = ERANGE; 2787 goto errout; 2788 } 2789 2790 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2791 &me->me_q.q_mcr, 0)) { 2792 err = ENOMEM; 2793 goto errout; 2794 } 2795 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2796 2797 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2798 &me->me_q.q_ctx, 0)) { 2799 err = ENOMEM; 2800 goto errout; 2801 } 2802 2803 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2804 if (mbits > nbits) { 2805 err = E2BIG; 2806 goto errout; 2807 } 2808 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2809 err = ENOMEM; 2810 goto errout; 2811 } 2812 memset(me->me_M.dma_vaddr, 0, normbits / 8); 2813 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2814 me->me_M.dma_vaddr, (mbits + 7) / 8); 2815 2816 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2817 err = ENOMEM; 2818 goto errout; 2819 } 2820 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2821 2822 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2823 if (ebits > nbits) { 2824 err = E2BIG; 2825 goto errout; 2826 } 2827 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2828 err = ENOMEM; 2829 goto errout; 2830 } 2831 memset(me->me_E.dma_vaddr, 0, normbits / 8); 2832 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2833 me->me_E.dma_vaddr, (ebits + 7) / 8); 2834 2835 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2836 &me->me_epb, 0)) { 2837 err = ENOMEM; 2838 goto errout; 2839 } 2840 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2841 epb->pb_addr = htole32(me->me_E.dma_paddr); 2842 epb->pb_next = 0; 2843 epb->pb_len = htole32((ebits + 7) / 8); 2844 2845 #ifdef UBSEC_DEBUG 2846 if (ubsec_debug) { 2847 printf("Epb "); 2848 ubsec_dump_pb(epb); 2849 } 2850 #endif 2851 2852 mcr->mcr_pkts = htole16(1); 2853 mcr->mcr_flags = 0; 2854 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2855 mcr->mcr_reserved = 0; 2856 mcr->mcr_pktlen = 0; 2857 2858 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2859 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2860 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2861 2862 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2863 mcr->mcr_opktbuf.pb_next = 0; 2864 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2865 2866 #ifdef DIAGNOSTIC 2867 /* Misaligned output buffer will hang the chip. */ 2868 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2869 panic("%s: modexp invalid addr 0x%x", device_xname(sc->sc_dev), 2870 letoh32(mcr->mcr_opktbuf.pb_addr)); 2871 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2872 panic("%s: modexp invalid len 0x%x", device_xname(sc->sc_dev), 2873 letoh32(mcr->mcr_opktbuf.pb_len)); 2874 #endif 2875 2876 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2877 memset(ctx, 0, sizeof(*ctx)); 2878 memcpy(ctx->me_N, krp->krp_param[UBS_MODEXP_PAR_N].crp_p, 2879 (nbits + 7) / 8); 2880 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2881 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2882 ctx->me_E_len = htole16(ebits); 2883 ctx->me_N_len = htole16(nbits); 2884 2885 #ifdef UBSEC_DEBUG 2886 if (ubsec_debug) { 2887 ubsec_dump_mcr(mcr); 2888 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2889 } 2890 #endif 2891 2892 /* 2893 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2894 * everything else. 2895 */ 2896 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2897 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2898 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2899 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2900 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2901 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2902 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2903 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2904 2905 /* Enqueue and we're done... */ 2906 mutex_spin_enter(&sc->sc_mtx); 2907 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2908 ubsec_feed2(sc); 2909 mutex_spin_exit(&sc->sc_mtx); 2910 2911 return (0); 2912 2913 errout: 2914 if (me != NULL) { 2915 if (me->me_q.q_mcr.dma_map != NULL) 2916 ubsec_dma_free(sc, &me->me_q.q_mcr); 2917 if (me->me_q.q_ctx.dma_map != NULL) { 2918 memset(me->me_q.q_ctx.dma_vaddr, 0, 2919 me->me_q.q_ctx.dma_size); 2920 ubsec_dma_free(sc, &me->me_q.q_ctx); 2921 } 2922 if (me->me_M.dma_map != NULL) { 2923 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2924 ubsec_dma_free(sc, &me->me_M); 2925 } 2926 if (me->me_E.dma_map != NULL) { 2927 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2928 ubsec_dma_free(sc, &me->me_E); 2929 } 2930 if (me->me_C.dma_map != NULL) { 2931 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2932 ubsec_dma_free(sc, &me->me_C); 2933 } 2934 if (me->me_epb.dma_map != NULL) 2935 ubsec_dma_free(sc, &me->me_epb); 2936 free(me, M_DEVBUF); 2937 } 2938 krp->krp_status = err; 2939 crypto_kdone(krp); 2940 return (0); 2941 } 2942 2943 static int 2944 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, 2945 int hint) 2946 { 2947 struct ubsec_q2_rsapriv *rp = NULL; 2948 struct ubsec_mcr *mcr; 2949 struct ubsec_ctx_rsapriv *ctx; 2950 int err = 0; 2951 u_int padlen, msglen; 2952 2953 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2954 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2955 if (msglen > padlen) 2956 padlen = msglen; 2957 2958 if (padlen <= 256) 2959 padlen = 256; 2960 else if (padlen <= 384) 2961 padlen = 384; 2962 else if (padlen <= 512) 2963 padlen = 512; 2964 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2965 padlen = 768; 2966 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2967 padlen = 1024; 2968 else { 2969 err = E2BIG; 2970 goto errout; 2971 } 2972 2973 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2974 err = E2BIG; 2975 goto errout; 2976 } 2977 2978 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2979 err = E2BIG; 2980 goto errout; 2981 } 2982 2983 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2984 err = E2BIG; 2985 goto errout; 2986 } 2987 2988 rp = malloc(sizeof *rp, M_DEVBUF, M_NOWAIT|M_ZERO); 2989 if (rp == NULL) 2990 return (ENOMEM); 2991 rp->rpr_krp = krp; 2992 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2993 2994 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2995 &rp->rpr_q.q_mcr, 0)) { 2996 err = ENOMEM; 2997 goto errout; 2998 } 2999 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 3000 3001 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 3002 &rp->rpr_q.q_ctx, 0)) { 3003 err = ENOMEM; 3004 goto errout; 3005 } 3006 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 3007 memset(ctx, 0, sizeof *ctx); 3008 3009 /* Copy in p */ 3010 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 3011 &ctx->rpr_buf[0 * (padlen / 8)], 3012 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 3013 3014 /* Copy in q */ 3015 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 3016 &ctx->rpr_buf[1 * (padlen / 8)], 3017 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 3018 3019 /* Copy in dp */ 3020 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 3021 &ctx->rpr_buf[2 * (padlen / 8)], 3022 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 3023 3024 /* Copy in dq */ 3025 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 3026 &ctx->rpr_buf[3 * (padlen / 8)], 3027 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 3028 3029 /* Copy in pinv */ 3030 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 3031 &ctx->rpr_buf[4 * (padlen / 8)], 3032 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 3033 3034 msglen = padlen * 2; 3035 3036 /* Copy in input message (aligned buffer/length). */ 3037 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 3038 /* Is this likely? */ 3039 err = E2BIG; 3040 goto errout; 3041 } 3042 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 3043 err = ENOMEM; 3044 goto errout; 3045 } 3046 memset(rp->rpr_msgin.dma_vaddr, 0, (msglen + 7) / 8); 3047 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 3048 rp->rpr_msgin.dma_vaddr, 3049 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 3050 3051 /* Prepare space for output message (aligned buffer/length). */ 3052 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 3053 /* Is this likely? */ 3054 err = E2BIG; 3055 goto errout; 3056 } 3057 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 3058 err = ENOMEM; 3059 goto errout; 3060 } 3061 memset(rp->rpr_msgout.dma_vaddr, 0, (msglen + 7) / 8); 3062 3063 mcr->mcr_pkts = htole16(1); 3064 mcr->mcr_flags = 0; 3065 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 3066 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 3067 mcr->mcr_ipktbuf.pb_next = 0; 3068 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 3069 mcr->mcr_reserved = 0; 3070 mcr->mcr_pktlen = htole16(msglen); 3071 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 3072 mcr->mcr_opktbuf.pb_next = 0; 3073 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 3074 3075 #ifdef DIAGNOSTIC 3076 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 3077 panic("%s: rsapriv: invalid msgin 0x%lx(0x%lx)", 3078 device_xname(sc->sc_dev), (u_long) rp->rpr_msgin.dma_paddr, 3079 (u_long) rp->rpr_msgin.dma_size); 3080 } 3081 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 3082 panic("%s: rsapriv: invalid msgout 0x%lx(0x%lx)", 3083 device_xname(sc->sc_dev), (u_long) rp->rpr_msgout.dma_paddr, 3084 (u_long) rp->rpr_msgout.dma_size); 3085 } 3086 #endif 3087 3088 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 3089 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 3090 ctx->rpr_q_len = htole16(padlen); 3091 ctx->rpr_p_len = htole16(padlen); 3092 3093 /* 3094 * ubsec_feed2 will sync mcr and ctx, we just need to sync 3095 * everything else. 3096 */ 3097 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 3098 0, rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3099 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 3100 0, rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 3101 3102 /* Enqueue and we're done... */ 3103 mutex_spin_enter(&sc->sc_mtx); 3104 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 3105 ubsec_feed2(sc); 3106 ubsecstats.hst_modexpcrt++; 3107 mutex_spin_exit(&sc->sc_mtx); 3108 return (0); 3109 3110 errout: 3111 if (rp != NULL) { 3112 if (rp->rpr_q.q_mcr.dma_map != NULL) 3113 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 3114 if (rp->rpr_msgin.dma_map != NULL) { 3115 memset(rp->rpr_msgin.dma_vaddr, 0, 3116 rp->rpr_msgin.dma_size); 3117 ubsec_dma_free(sc, &rp->rpr_msgin); 3118 } 3119 if (rp->rpr_msgout.dma_map != NULL) { 3120 memset(rp->rpr_msgout.dma_vaddr, 0, 3121 rp->rpr_msgout.dma_size); 3122 ubsec_dma_free(sc, &rp->rpr_msgout); 3123 } 3124 free(rp, M_DEVBUF); 3125 } 3126 krp->krp_status = err; 3127 crypto_kdone(krp); 3128 return (0); 3129 } 3130 3131 #ifdef UBSEC_DEBUG 3132 static void 3133 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 3134 { 3135 printf("addr 0x%x (0x%x) next 0x%x\n", 3136 pb->pb_addr, pb->pb_len, pb->pb_next); 3137 } 3138 3139 static void 3140 ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *c) 3141 { 3142 printf("CTX (0x%x):\n", c->ctx_len); 3143 switch (letoh16(c->ctx_op)) { 3144 case UBS_CTXOP_RNGBYPASS: 3145 case UBS_CTXOP_RNGSHA1: 3146 break; 3147 case UBS_CTXOP_MODEXP: 3148 { 3149 struct ubsec_ctx_modexp *cx = (void *)c; 3150 int i, len; 3151 3152 printf(" Elen %u, Nlen %u\n", 3153 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 3154 len = (cx->me_N_len + 7)/8; 3155 for (i = 0; i < len; i++) 3156 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 3157 printf("\n"); 3158 break; 3159 } 3160 default: 3161 printf("unknown context: %x\n", c->ctx_op); 3162 } 3163 printf("END CTX\n"); 3164 } 3165 3166 static void 3167 ubsec_dump_mcr(struct ubsec_mcr *mcr) 3168 { 3169 volatile struct ubsec_mcr_add *ma; 3170 int i; 3171 3172 printf("MCR:\n"); 3173 printf(" pkts: %u, flags 0x%x\n", 3174 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 3175 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 3176 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 3177 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 3178 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 3179 letoh16(ma->mcr_reserved)); 3180 printf(" %d: ipkt ", i); 3181 ubsec_dump_pb(&ma->mcr_ipktbuf); 3182 printf(" %d: opkt ", i); 3183 ubsec_dump_pb(&ma->mcr_opktbuf); 3184 ma++; 3185 } 3186 printf("END MCR\n"); 3187 } 3188 #endif /* UBSEC_DEBUG */ 3189 3190 /* 3191 * Return the number of significant bits of a big number. 3192 */ 3193 static int 3194 ubsec_ksigbits(struct crparam *cr) 3195 { 3196 u_int plen = (cr->crp_nbits + 7) / 8; 3197 int i, sig = plen * 8; 3198 u_int8_t c, *p = cr->crp_p; 3199 3200 for (i = plen - 1; i >= 0; i--) { 3201 c = p[i]; 3202 if (c != 0) { 3203 while ((c & 0x80) == 0) { 3204 sig--; 3205 c <<= 1; 3206 } 3207 break; 3208 } 3209 sig -= 8; 3210 } 3211 return (sig); 3212 } 3213 3214 static void 3215 ubsec_kshift_r(u_int shiftbits, u_int8_t *src, u_int srcbits, 3216 u_int8_t *dst, u_int dstbits) 3217 { 3218 u_int slen, dlen; 3219 int i, si, di, n; 3220 3221 slen = (srcbits + 7) / 8; 3222 dlen = (dstbits + 7) / 8; 3223 3224 for (i = 0; i < slen; i++) 3225 dst[i] = src[i]; 3226 for (i = 0; i < dlen - slen; i++) 3227 dst[slen + i] = 0; 3228 3229 n = shiftbits / 8; 3230 if (n != 0) { 3231 si = dlen - n - 1; 3232 di = dlen - 1; 3233 while (si >= 0) 3234 dst[di--] = dst[si--]; 3235 while (di >= 0) 3236 dst[di--] = 0; 3237 } 3238 3239 n = shiftbits % 8; 3240 if (n != 0) { 3241 for (i = dlen - 1; i > 0; i--) 3242 dst[i] = (dst[i] << n) | 3243 (dst[i - 1] >> (8 - n)); 3244 dst[0] = dst[0] << n; 3245 } 3246 } 3247 3248 static void 3249 ubsec_kshift_l(u_int shiftbits, u_int8_t *src, u_int srcbits, 3250 u_int8_t *dst, u_int dstbits) 3251 { 3252 int slen, dlen, i, n; 3253 3254 slen = (srcbits + 7) / 8; 3255 dlen = (dstbits + 7) / 8; 3256 3257 n = shiftbits / 8; 3258 for (i = 0; i < slen; i++) 3259 dst[i] = src[i + n]; 3260 for (i = 0; i < dlen - slen; i++) 3261 dst[slen + i] = 0; 3262 3263 n = shiftbits % 8; 3264 if (n != 0) { 3265 for (i = 0; i < (dlen - 1); i++) 3266 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 3267 dst[dlen - 1] = dst[dlen - 1] >> n; 3268 } 3269 } 3270
Indexes created Wed Oct 01 19:09:53 GMT 2025