ubsec.c revision 1.51
1 /* $NetBSD: ubsec.c,v 1.51 2020/05/25 19:13:28 thorpej Exp $ */ 2 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.6 2003/01/23 21:06:43 sam Exp $ */ 3 /* $OpenBSD: ubsec.c,v 1.143 2009/03/27 13:31:30 reyk Exp$ */ 4 5 /* 6 * Copyright (c) 2000 Jason L. Wright (jason (at) thought.net) 7 * Copyright (c) 2000 Theo de Raadt (deraadt (at) openbsd.org) 8 * Copyright (c) 2001 Patrik Lindergren (patrik (at) ipunplugged.com) 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Effort sponsored in part by the Defense Advanced Research Projects 32 * Agency (DARPA) and Air Force Research Laboratory, Air Force 33 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 34 * 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: ubsec.c,v 1.51 2020/05/25 19:13:28 thorpej Exp $"); 39 40 #undef UBSEC_DEBUG 41 42 /* 43 * uBsec 5[56]01, 58xx hardware crypto accelerator 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/proc.h> 49 #include <sys/endian.h> 50 #include <sys/errno.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/mbuf.h> 54 #include <sys/device.h> 55 #include <sys/module.h> 56 #include <sys/queue.h> 57 #include <sys/sysctl.h> 58 59 #include <opencrypto/cryptodev.h> 60 #include <opencrypto/xform.h> 61 #include <sys/cprng.h> 62 #include <sys/md5.h> 63 #include <sys/rndsource.h> 64 #include <sys/sha1.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/pci/ubsecreg.h> 71 #include <dev/pci/ubsecvar.h> 72 73 #define UBSEC_NO_RNG /* hangs on attach */ 74 #define letoh16 htole16 75 #define letoh32 htole32 76 77 /* 78 * Prototypes and count for the pci_device structure 79 */ 80 static int ubsec_probe(device_t, cfdata_t, void *); 81 static void ubsec_attach(device_t, device_t, void *); 82 static int ubsec_detach(device_t, int); 83 static void ubsec_reset_board(struct ubsec_softc *); 84 static void ubsec_init_board(struct ubsec_softc *); 85 static void ubsec_init_pciregs(struct pci_attach_args *pa); 86 static void ubsec_cleanchip(struct ubsec_softc *); 87 static void ubsec_totalreset(struct ubsec_softc *); 88 static int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); 89 90 CFATTACH_DECL_NEW(ubsec, sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 91 ubsec_detach, NULL); 92 extern struct cfdriver ubsec_cd; 93 94 /* patchable */ 95 #ifdef UBSEC_DEBUG 96 extern int ubsec_debug; 97 int ubsec_debug=1; 98 #endif 99 100 static int ubsec_intr(void *); 101 static int ubsec_newsession(void*, u_int32_t *, struct cryptoini *); 102 static int ubsec_freesession(void*, u_int64_t); 103 static int ubsec_process(void*, struct cryptop *, int hint); 104 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 105 static void ubsec_feed(struct ubsec_softc *); 106 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 107 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 108 static void ubsec_feed2(struct ubsec_softc *); 109 static void ubsec_feed4(struct ubsec_softc *); 110 #ifndef UBSEC_NO_RNG 111 static void ubsec_rng(void *); 112 static void ubsec_rng_locked(void *); 113 static void ubsec_rng_get(size_t, void *); 114 #endif /* UBSEC_NO_RNG */ 115 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 116 struct ubsec_dma_alloc *, int); 117 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 118 static int ubsec_dmamap_aligned(bus_dmamap_t); 119 120 static int ubsec_kprocess(void*, struct cryptkop *, int); 121 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, 122 struct cryptkop *, int); 123 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, 124 struct cryptkop *, int); 125 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, 126 struct cryptkop *, int); 127 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 128 static int ubsec_ksigbits(struct crparam *); 129 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 130 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 131 132 #ifdef UBSEC_DEBUG 133 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 134 static void ubsec_dump_mcr(struct ubsec_mcr *); 135 static void ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *); 136 #endif 137 138 #define READ_REG(sc,r) \ 139 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 140 141 #define WRITE_REG(sc,reg,val) \ 142 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 143 144 #define SWAP32(x) (x) = htole32(ntohl((x))) 145 #ifndef HTOLE32 146 #define HTOLE32(x) (x) = htole32(x) 147 #endif 148 149 struct ubsec_stats ubsecstats; 150 151 /* 152 * ubsec_maxbatch controls the number of crypto ops to voluntarily 153 * collect into one submission to the hardware. This batching happens 154 * when ops are dispatched from the crypto subsystem with a hint that 155 * more are to follow immediately. These ops must also not be marked 156 * with a ``no delay'' flag. 157 */ 158 static int ubsec_maxbatch = 1; 159 160 /* 161 * ubsec_maxaggr controls the number of crypto ops to submit to the 162 * hardware as a unit. This aggregation reduces the number of interrupts 163 * to the host at the expense of increased latency (for all but the last 164 * operation). For network traffic setting this to one yields the highest 165 * performance but at the expense of more interrupt processing. 166 */ 167 static int ubsec_maxaggr = 1; 168 169 static const struct ubsec_product { 170 pci_vendor_id_t ubsec_vendor; 171 pci_product_id_t ubsec_product; 172 int ubsec_flags; 173 int ubsec_statmask; 174 int ubsec_maxaggr; 175 const char *ubsec_name; 176 } ubsec_products[] = { 177 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5501, 178 0, 179 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 180 UBS_MIN_AGGR, 181 "Bluesteel 5501" 182 }, 183 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5601, 184 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 185 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 186 UBS_MIN_AGGR, 187 "Bluesteel 5601" 188 }, 189 190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5801, 191 0, 192 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 193 UBS_MIN_AGGR, 194 "Broadcom BCM5801" 195 }, 196 197 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5802, 198 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 199 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 200 UBS_MIN_AGGR, 201 "Broadcom BCM5802" 202 }, 203 204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5805, 205 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 206 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 207 UBS_MIN_AGGR, 208 "Broadcom BCM5805" 209 }, 210 211 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5820, 212 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 213 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 214 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 215 UBS_MIN_AGGR, 216 "Broadcom BCM5820" 217 }, 218 219 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5821, 220 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 221 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 222 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 223 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 224 UBS_MIN_AGGR, 225 "Broadcom BCM5821" 226 }, 227 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_SCA1K, 228 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 229 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 230 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 231 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 232 UBS_MIN_AGGR, 233 "Sun Crypto Accelerator 1000" 234 }, 235 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_5821, 236 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 237 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 238 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 239 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 240 UBS_MIN_AGGR, 241 "Broadcom BCM5821 (Sun)" 242 }, 243 244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5822, 245 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 246 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 247 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 248 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 249 UBS_MIN_AGGR, 250 "Broadcom BCM5822" 251 }, 252 253 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5823, 254 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 255 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 256 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 257 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 258 UBS_MIN_AGGR, 259 "Broadcom BCM5823" 260 }, 261 262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5825, 263 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 264 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 265 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 266 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 267 UBS_MIN_AGGR, 268 "Broadcom BCM5825" 269 }, 270 271 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5860, 272 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 273 UBS_FLAGS_LONGCTX | 274 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 275 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 276 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 277 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 278 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 279 UBS_MAX_AGGR, 280 "Broadcom BCM5860" 281 }, 282 283 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5861, 284 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 285 UBS_FLAGS_LONGCTX | 286 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 287 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 288 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 289 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 290 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 291 UBS_MAX_AGGR, 292 "Broadcom BCM5861" 293 }, 294 295 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5862, 296 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 297 UBS_FLAGS_LONGCTX | 298 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 299 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 300 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 301 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 302 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 303 UBS_MAX_AGGR, 304 "Broadcom BCM5862" 305 }, 306 307 { 0, 0, 308 0, 309 0, 310 0, 311 NULL 312 } 313 }; 314 315 static const struct ubsec_product * 316 ubsec_lookup(const struct pci_attach_args *pa) 317 { 318 const struct ubsec_product *up; 319 320 for (up = ubsec_products; up->ubsec_name != NULL; up++) { 321 if (PCI_VENDOR(pa->pa_id) == up->ubsec_vendor && 322 PCI_PRODUCT(pa->pa_id) == up->ubsec_product) 323 return (up); 324 } 325 return (NULL); 326 } 327 328 static int 329 ubsec_probe(device_t parent, cfdata_t match, void *aux) 330 { 331 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 332 333 if (ubsec_lookup(pa) != NULL) 334 return (1); 335 336 return (0); 337 } 338 339 static void 340 ubsec_attach(device_t parent, device_t self, void *aux) 341 { 342 struct ubsec_softc *sc = device_private(self); 343 struct pci_attach_args *pa = aux; 344 const struct ubsec_product *up; 345 pci_chipset_tag_t pc = pa->pa_pc; 346 pci_intr_handle_t ih; 347 const char *intrstr = NULL; 348 pcireg_t memtype; 349 struct ubsec_dma *dmap; 350 u_int32_t cmd, i; 351 char intrbuf[PCI_INTRSTR_LEN]; 352 353 sc->sc_dev = self; 354 sc->sc_pct = pc; 355 356 up = ubsec_lookup(pa); 357 if (up == NULL) { 358 printf("\n"); 359 panic("ubsec_attach: impossible"); 360 } 361 362 pci_aprint_devinfo_fancy(pa, "Crypto processor", up->ubsec_name, 1); 363 364 SIMPLEQ_INIT(&sc->sc_queue); 365 SIMPLEQ_INIT(&sc->sc_qchip); 366 SIMPLEQ_INIT(&sc->sc_queue2); 367 SIMPLEQ_INIT(&sc->sc_qchip2); 368 SIMPLEQ_INIT(&sc->sc_queue4); 369 SIMPLEQ_INIT(&sc->sc_qchip4); 370 SIMPLEQ_INIT(&sc->sc_q2free); 371 372 sc->sc_flags = up->ubsec_flags; 373 sc->sc_statmask = up->ubsec_statmask; 374 sc->sc_maxaggr = up->ubsec_maxaggr; 375 376 cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 377 cmd |= PCI_COMMAND_MASTER_ENABLE; 378 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, cmd); 379 380 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BS_BAR); 381 if (pci_mapreg_map(pa, BS_BAR, memtype, 0, 382 &sc->sc_st, &sc->sc_sh, NULL, &sc->sc_memsize)) { 383 aprint_error_dev(self, "can't find mem space"); 384 return; 385 } 386 387 sc->sc_dmat = pa->pa_dmat; 388 389 if (pci_intr_map(pa, &ih)) { 390 aprint_error_dev(self, "couldn't map interrupt\n"); 391 return; 392 } 393 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 394 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ubsec_intr, sc, 395 device_xname(self)); 396 if (sc->sc_ih == NULL) { 397 aprint_error_dev(self, "couldn't establish interrupt"); 398 if (intrstr != NULL) 399 aprint_error(" at %s", intrstr); 400 aprint_error("\n"); 401 return; 402 } 403 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 404 405 sc->sc_cid = crypto_get_driverid(0); 406 if (sc->sc_cid < 0) { 407 aprint_error_dev(self, "couldn't get crypto driver id\n"); 408 pci_intr_disestablish(pc, sc->sc_ih); 409 return; 410 } 411 412 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_VM); 413 414 SIMPLEQ_INIT(&sc->sc_freequeue); 415 dmap = sc->sc_dmaa; 416 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 417 struct ubsec_q *q; 418 419 q = malloc(sizeof(struct ubsec_q), M_DEVBUF, M_ZERO|M_WAITOK); 420 421 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 422 &dmap->d_alloc, 0)) { 423 aprint_error_dev(self, "can't allocate dma buffers\n"); 424 free(q, M_DEVBUF); 425 break; 426 } 427 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 428 429 q->q_dma = dmap; 430 sc->sc_queuea[i] = q; 431 432 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 433 } 434 435 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 436 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 437 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 438 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 439 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC_96, 0, 0, 440 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 441 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC_96, 0, 0, 442 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 443 if (sc->sc_flags & UBS_FLAGS_AES) { 444 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 445 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 446 } 447 448 /* 449 * Reset Broadcom chip 450 */ 451 ubsec_reset_board(sc); 452 453 /* 454 * Init Broadcom specific PCI settings 455 */ 456 ubsec_init_pciregs(pa); 457 458 /* 459 * Init Broadcom chip 460 */ 461 ubsec_init_board(sc); 462 463 #ifndef UBSEC_NO_RNG 464 if (sc->sc_flags & UBS_FLAGS_RNG) { 465 if (sc->sc_flags & UBS_FLAGS_RNG4) 466 sc->sc_statmask |= BS_STAT_MCR4_DONE; 467 else 468 sc->sc_statmask |= BS_STAT_MCR2_DONE; 469 470 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 471 &sc->sc_rng.rng_q.q_mcr, 0)) 472 goto skip_rng; 473 474 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 475 &sc->sc_rng.rng_q.q_ctx, 0)) { 476 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 477 goto skip_rng; 478 } 479 480 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 481 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 482 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 483 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 484 goto skip_rng; 485 } 486 if (hz >= 100) 487 sc->sc_rnghz = hz / 100; 488 else 489 sc->sc_rnghz = 1; 490 callout_init(&sc->sc_rngto, 0); 491 callout_setfunc(&sc->sc_rngto, ubsec_rng, sc); 492 rndsource_setcb(&sc->sc_rnd_source, ubsec_rng_get, sc); 493 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 494 RND_TYPE_RNG, 495 RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB); 496 497 skip_rng: 498 if (sc->sc_rnghz) 499 aprint_normal_dev(self, 500 "random number generator enabled\n"); 501 else 502 aprint_error_dev(self, 503 "WARNING: random number generator disabled\n"); 504 } 505 #endif /* UBSEC_NO_RNG */ 506 507 if (sc->sc_flags & UBS_FLAGS_KEY) { 508 sc->sc_statmask |= BS_STAT_MCR2_DONE; 509 510 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 511 ubsec_kprocess, sc); 512 #if 0 513 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 514 ubsec_kprocess, sc); 515 #endif 516 } 517 } 518 519 static int 520 ubsec_detach(device_t self, int flags) 521 { 522 struct ubsec_softc *sc = device_private(self); 523 struct ubsec_q *q, *qtmp; 524 volatile u_int32_t ctrl; 525 526 /* disable interrupts */ 527 /* XXX wait/abort current ops? where is DMAERR enabled? */ 528 ctrl = READ_REG(sc, BS_CTRL); 529 530 ctrl &= ~(BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR); 531 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) 532 ctrl &= ~BS_CTRL_MCR4INT; 533 534 WRITE_REG(sc, BS_CTRL, ctrl); 535 536 #ifndef UBSEC_NO_RNG 537 if (sc->sc_flags & UBS_FLAGS_RNG) { 538 callout_halt(&sc->sc_rngto, NULL); 539 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 540 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 541 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 542 rnd_detach_source(&sc->sc_rnd_source); 543 } 544 #endif /* UBSEC_NO_RNG */ 545 546 crypto_unregister_all(sc->sc_cid); 547 548 mutex_spin_enter(&sc->sc_mtx); 549 550 ubsec_totalreset(sc); /* XXX leaves the chip running */ 551 552 SIMPLEQ_FOREACH_SAFE(q, &sc->sc_freequeue, q_next, qtmp) { 553 ubsec_dma_free(sc, &q->q_dma->d_alloc); 554 if (q->q_src_map != NULL) 555 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 556 if (q->q_cached_dst_map != NULL) 557 bus_dmamap_destroy(sc->sc_dmat, q->q_cached_dst_map); 558 free(q, M_DEVBUF); 559 } 560 561 mutex_spin_exit(&sc->sc_mtx); 562 563 if (sc->sc_ih != NULL) { 564 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 565 sc->sc_ih = NULL; 566 } 567 568 if (sc->sc_memsize != 0) { 569 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_memsize); 570 sc->sc_memsize = 0; 571 } 572 573 return 0; 574 } 575 576 MODULE(MODULE_CLASS_DRIVER, ubsec, "pci,opencrypto"); 577 578 #ifdef _MODULE 579 #include "ioconf.c" 580 #endif 581 582 static int 583 ubsec_modcmd(modcmd_t cmd, void *data) 584 { 585 int error = 0; 586 587 switch (cmd) { 588 case MODULE_CMD_INIT: 589 #ifdef _MODULE 590 error = config_init_component(cfdriver_ioconf_ubsec, 591 cfattach_ioconf_ubsec, cfdata_ioconf_ubsec); 592 #endif 593 return error; 594 case MODULE_CMD_FINI: 595 #ifdef _MODULE 596 error = config_fini_component(cfdriver_ioconf_ubsec, 597 cfattach_ioconf_ubsec, cfdata_ioconf_ubsec); 598 #endif 599 return error; 600 default: 601 return ENOTTY; 602 } 603 } 604 605 SYSCTL_SETUP(ubsec_sysctl_init, "ubsec sysctl") 606 { 607 const struct sysctlnode *node = NULL; 608 609 sysctl_createv(clog, 0, NULL, &node, 610 CTLFLAG_PERMANENT, 611 CTLTYPE_NODE, "ubsec", 612 SYSCTL_DESCR("ubsec opetions"), 613 NULL, 0, NULL, 0, 614 CTL_HW, CTL_CREATE, CTL_EOL); 615 sysctl_createv(clog, 0, &node, NULL, 616 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 617 CTLTYPE_INT, "maxbatch", 618 SYSCTL_DESCR("max ops to batch w/o interrupt"), 619 NULL, 0, &ubsec_maxbatch, 0, 620 CTL_CREATE, CTL_EOL); 621 sysctl_createv(clog, 0, &node, NULL, 622 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 623 CTLTYPE_INT, "maxaggr", 624 SYSCTL_DESCR("max ops to aggregate under one interrupt"), 625 NULL, 0, &ubsec_maxaggr, 0, 626 CTL_CREATE, CTL_EOL); 627 628 return; 629 } 630 631 /* 632 * UBSEC Interrupt routine 633 */ 634 static int 635 ubsec_intr(void *arg) 636 { 637 struct ubsec_softc *sc = arg; 638 volatile u_int32_t stat; 639 struct ubsec_q *q; 640 struct ubsec_dma *dmap; 641 int flags; 642 int npkts = 0, i; 643 644 mutex_spin_enter(&sc->sc_mtx); 645 stat = READ_REG(sc, BS_STAT); 646 stat &= sc->sc_statmask; 647 if (stat == 0) { 648 mutex_spin_exit(&sc->sc_mtx); 649 return (0); 650 } 651 652 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 653 654 /* 655 * Check to see if we have any packets waiting for us 656 */ 657 if ((stat & BS_STAT_MCR1_DONE)) { 658 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 659 q = SIMPLEQ_FIRST(&sc->sc_qchip); 660 dmap = q->q_dma; 661 662 if ((dmap->d_dma->d_mcr.mcr_flags 663 & htole16(UBS_MCR_DONE)) == 0) 664 break; 665 666 q = SIMPLEQ_FIRST(&sc->sc_qchip); 667 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 668 669 npkts = q->q_nstacked_mcrs; 670 sc->sc_nqchip -= 1+npkts; 671 /* 672 * search for further sc_qchip ubsec_q's that share 673 * the same MCR, and complete them too, they must be 674 * at the top. 675 */ 676 for (i = 0; i < npkts; i++) { 677 if(q->q_stacked_mcr[i]) 678 ubsec_callback(sc, q->q_stacked_mcr[i]); 679 else 680 break; 681 } 682 ubsec_callback(sc, q); 683 } 684 685 /* 686 * Don't send any more packet to chip if there has been 687 * a DMAERR. 688 */ 689 if (!(stat & BS_STAT_DMAERR)) 690 ubsec_feed(sc); 691 } 692 693 /* 694 * Check to see if we have any key setups/rng's waiting for us 695 */ 696 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 697 (stat & BS_STAT_MCR2_DONE)) { 698 struct ubsec_q2 *q2; 699 struct ubsec_mcr *mcr; 700 701 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 702 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 703 704 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 705 0, q2->q_mcr.dma_map->dm_mapsize, 706 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 707 708 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 709 710 /* A bug in new devices requires to swap this field */ 711 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) 712 flags = htole16(mcr->mcr_flags); 713 else 714 flags = mcr->mcr_flags; 715 if ((flags & htole16(UBS_MCR_DONE)) == 0) { 716 bus_dmamap_sync(sc->sc_dmat, 717 q2->q_mcr.dma_map, 0, 718 q2->q_mcr.dma_map->dm_mapsize, 719 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 720 break; 721 } 722 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 723 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, /*q2,*/ q_next); 724 ubsec_callback2(sc, q2); 725 /* 726 * Don't send any more packet to chip if there has been 727 * a DMAERR. 728 */ 729 if (!(stat & BS_STAT_DMAERR)) 730 ubsec_feed2(sc); 731 } 732 } 733 if ((sc->sc_flags & UBS_FLAGS_RNG4) && (stat & BS_STAT_MCR4_DONE)) { 734 struct ubsec_q2 *q2; 735 struct ubsec_mcr *mcr; 736 737 while (!SIMPLEQ_EMPTY(&sc->sc_qchip4)) { 738 q2 = SIMPLEQ_FIRST(&sc->sc_qchip4); 739 740 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 741 0, q2->q_mcr.dma_map->dm_mapsize, 742 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 743 744 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 745 746 /* A bug in new devices requires to swap this field */ 747 flags = htole16(mcr->mcr_flags); 748 749 if ((flags & htole16(UBS_MCR_DONE)) == 0) { 750 bus_dmamap_sync(sc->sc_dmat, 751 q2->q_mcr.dma_map, 0, 752 q2->q_mcr.dma_map->dm_mapsize, 753 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 754 break; 755 } 756 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip4, q_next); 757 ubsec_callback2(sc, q2); 758 /* 759 * Don't send any more packet to chip if there has been 760 * a DMAERR. 761 */ 762 if (!(stat & BS_STAT_DMAERR)) 763 ubsec_feed4(sc); 764 } 765 } 766 767 /* 768 * Check to see if we got any DMA Error 769 */ 770 if (stat & BS_STAT_DMAERR) { 771 #ifdef UBSEC_DEBUG 772 if (ubsec_debug) { 773 volatile u_int32_t a = READ_REG(sc, BS_ERR); 774 775 printf("%s: dmaerr %s@%08x\n", device_xname(sc->sc_dev), 776 (a & BS_ERR_READ) ? "read" : "write", 777 a & BS_ERR_ADDR); 778 } 779 #endif /* UBSEC_DEBUG */ 780 ubsecstats.hst_dmaerr++; 781 ubsec_totalreset(sc); 782 ubsec_feed(sc); 783 } 784 785 if (sc->sc_needwakeup) { /* XXX check high watermark */ 786 int wkeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 787 #ifdef UBSEC_DEBUG 788 if (ubsec_debug) 789 printf("%s: wakeup crypto (%x)\n", 790 device_xname(sc->sc_dev), sc->sc_needwakeup); 791 #endif /* UBSEC_DEBUG */ 792 sc->sc_needwakeup &= ~wkeup; 793 crypto_unblock(sc->sc_cid, wkeup); 794 } 795 mutex_spin_exit(&sc->sc_mtx); 796 return (1); 797 } 798 799 /* 800 * ubsec_feed() - aggregate and post requests to chip 801 * OpenBSD comments: 802 * It is assumed that the caller set splnet() 803 */ 804 static void 805 ubsec_feed(struct ubsec_softc *sc) 806 { 807 struct ubsec_q *q, *q2; 808 int npkts, i; 809 void *v; 810 u_int32_t stat; 811 #ifdef UBSEC_DEBUG 812 static int max; 813 #endif /* UBSEC_DEBUG */ 814 815 npkts = sc->sc_nqueue; 816 if (npkts > ubsecstats.hst_maxqueue) 817 ubsecstats.hst_maxqueue = npkts; 818 if (npkts < 2) 819 goto feed1; 820 821 /* 822 * Decide how many ops to combine in a single MCR. We cannot 823 * aggregate more than UBS_MAX_AGGR because this is the number 824 * of slots defined in the data structure. Otherwise we clamp 825 * based on the tunable parameter ubsec_maxaggr. Note that 826 * aggregation can happen in two ways: either by batching ops 827 * from above or because the h/w backs up and throttles us. 828 * Aggregating ops reduces the number of interrupts to the host 829 * but also (potentially) increases the latency for processing 830 * completed ops as we only get an interrupt when all aggregated 831 * ops have completed. 832 */ 833 if (npkts > sc->sc_maxaggr) 834 npkts = sc->sc_maxaggr; 835 if (npkts > ubsec_maxaggr) 836 npkts = ubsec_maxaggr; 837 if (npkts > ubsecstats.hst_maxbatch) 838 ubsecstats.hst_maxbatch = npkts; 839 if (npkts < 2) 840 goto feed1; 841 ubsecstats.hst_totbatch += npkts-1; 842 843 if ((stat = READ_REG(sc, BS_STAT)) 844 & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 845 if (stat & BS_STAT_DMAERR) { 846 ubsec_totalreset(sc); 847 ubsecstats.hst_dmaerr++; 848 } else { 849 ubsecstats.hst_mcr1full++; 850 } 851 return; 852 } 853 854 #ifdef UBSEC_DEBUG 855 if (ubsec_debug) 856 printf("merging %d records\n", npkts); 857 /* XXX temporary aggregation statistics reporting code */ 858 if (max < npkts) { 859 max = npkts; 860 printf("%s: new max aggregate %d\n", device_xname(sc->sc_dev), 861 max); 862 } 863 #endif /* UBSEC_DEBUG */ 864 865 q = SIMPLEQ_FIRST(&sc->sc_queue); 866 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 867 --sc->sc_nqueue; 868 869 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 870 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 871 if (q->q_dst_map != NULL) 872 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 873 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 874 875 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 876 877 for (i = 0; i < q->q_nstacked_mcrs; i++) { 878 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 879 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 880 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 881 if (q2->q_dst_map != NULL) 882 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 883 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 884 q2= SIMPLEQ_FIRST(&sc->sc_queue); 885 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q2,*/ q_next); 886 --sc->sc_nqueue; 887 888 v = ((void *)&q2->q_dma->d_dma->d_mcr); 889 v = (char*)v + (sizeof(struct ubsec_mcr) - 890 sizeof(struct ubsec_mcr_add)); 891 memcpy(&q->q_dma->d_dma->d_mcradd[i], v, 892 sizeof(struct ubsec_mcr_add)); 893 q->q_stacked_mcr[i] = q2; 894 } 895 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 896 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 897 sc->sc_nqchip += npkts; 898 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 899 ubsecstats.hst_maxqchip = sc->sc_nqchip; 900 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 901 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 902 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 903 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 904 offsetof(struct ubsec_dmachunk, d_mcr)); 905 return; 906 907 feed1: 908 while (!SIMPLEQ_EMPTY(&sc->sc_queue)) { 909 if ((stat = READ_REG(sc, BS_STAT)) 910 & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 911 if (stat & BS_STAT_DMAERR) { 912 ubsec_totalreset(sc); 913 ubsecstats.hst_dmaerr++; 914 } else { 915 ubsecstats.hst_mcr1full++; 916 } 917 break; 918 } 919 920 q = SIMPLEQ_FIRST(&sc->sc_queue); 921 922 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 923 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 924 if (q->q_dst_map != NULL) 925 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 926 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 927 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 928 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 929 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 930 931 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 932 offsetof(struct ubsec_dmachunk, d_mcr)); 933 #ifdef UBSEC_DEBUG 934 if (ubsec_debug) 935 printf("feed: q->chip %p %08x stat %08x\n", 936 q, (u_int32_t)q->q_dma->d_alloc.dma_paddr, 937 stat); 938 #endif /* UBSEC_DEBUG */ 939 q = SIMPLEQ_FIRST(&sc->sc_queue); 940 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 941 --sc->sc_nqueue; 942 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 943 sc->sc_nqchip++; 944 } 945 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 946 ubsecstats.hst_maxqchip = sc->sc_nqchip; 947 } 948 949 /* 950 * Allocate a new 'session' and return an encoded session id. 'sidp' 951 * contains our registration id, and should contain an encoded session 952 * id on successful allocation. 953 */ 954 static int 955 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 956 { 957 struct cryptoini *c, *encini = NULL, *macini = NULL; 958 struct ubsec_softc *sc; 959 struct ubsec_session *ses = NULL; 960 MD5_CTX md5ctx; 961 SHA1_CTX sha1ctx; 962 int i, sesn; 963 964 sc = arg; 965 KASSERT(sc != NULL /*, ("ubsec_newsession: null softc")*/); 966 967 if (sidp == NULL || cri == NULL || sc == NULL) 968 return (EINVAL); 969 970 for (c = cri; c != NULL; c = c->cri_next) { 971 if (c->cri_alg == CRYPTO_MD5_HMAC_96 || 972 c->cri_alg == CRYPTO_SHA1_HMAC_96) { 973 if (macini) 974 return (EINVAL); 975 macini = c; 976 } else if (c->cri_alg == CRYPTO_DES_CBC || 977 c->cri_alg == CRYPTO_3DES_CBC || 978 c->cri_alg == CRYPTO_AES_CBC) { 979 if (encini) 980 return (EINVAL); 981 encini = c; 982 } else 983 return (EINVAL); 984 } 985 if (encini == NULL && macini == NULL) 986 return (EINVAL); 987 988 if (encini && encini->cri_alg == CRYPTO_AES_CBC) { 989 switch (encini->cri_klen) { 990 case 128: 991 case 192: 992 case 256: 993 break; 994 default: 995 return (EINVAL); 996 } 997 } 998 999 if (sc->sc_sessions == NULL) { 1000 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 1001 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 1002 if (ses == NULL) 1003 return (ENOMEM); 1004 sesn = 0; 1005 sc->sc_nsessions = 1; 1006 } else { 1007 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 1008 if (sc->sc_sessions[sesn].ses_used == 0) { 1009 ses = &sc->sc_sessions[sesn]; 1010 break; 1011 } 1012 } 1013 1014 if (ses == NULL) { 1015 sesn = sc->sc_nsessions; 1016 ses = (struct ubsec_session *)malloc((sesn + 1) * 1017 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 1018 if (ses == NULL) 1019 return (ENOMEM); 1020 memcpy(ses, sc->sc_sessions, sesn * 1021 sizeof(struct ubsec_session)); 1022 memset(sc->sc_sessions, 0, sesn * 1023 sizeof(struct ubsec_session)); 1024 free(sc->sc_sessions, M_DEVBUF); 1025 sc->sc_sessions = ses; 1026 ses = &sc->sc_sessions[sesn]; 1027 sc->sc_nsessions++; 1028 } 1029 } 1030 1031 memset(ses, 0, sizeof(struct ubsec_session)); 1032 ses->ses_used = 1; 1033 if (encini) { 1034 /* get an IV, network byte order */ 1035 cprng_fast(ses->ses_iv, sizeof(ses->ses_iv)); 1036 1037 /* Go ahead and compute key in ubsec's byte order */ 1038 if (encini->cri_alg == CRYPTO_AES_CBC) { 1039 memcpy(ses->ses_key, encini->cri_key, 1040 encini->cri_klen / 8); 1041 } 1042 if (encini->cri_alg == CRYPTO_DES_CBC) { 1043 memcpy(&ses->ses_key[0], encini->cri_key, 8); 1044 memcpy(&ses->ses_key[2], encini->cri_key, 8); 1045 memcpy(&ses->ses_key[4], encini->cri_key, 8); 1046 } else 1047 memcpy(ses->ses_key, encini->cri_key, 24); 1048 1049 SWAP32(ses->ses_key[0]); 1050 SWAP32(ses->ses_key[1]); 1051 SWAP32(ses->ses_key[2]); 1052 SWAP32(ses->ses_key[3]); 1053 SWAP32(ses->ses_key[4]); 1054 SWAP32(ses->ses_key[5]); 1055 } 1056 1057 if (macini) { 1058 for (i = 0; i < macini->cri_klen / 8; i++) 1059 macini->cri_key[i] ^= HMAC_IPAD_VAL; 1060 1061 if (macini->cri_alg == CRYPTO_MD5_HMAC_96) { 1062 MD5Init(&md5ctx); 1063 MD5Update(&md5ctx, macini->cri_key, 1064 macini->cri_klen / 8); 1065 MD5Update(&md5ctx, hmac_ipad_buffer, 1066 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1067 memcpy(ses->ses_hminner, md5ctx.state, 1068 sizeof(md5ctx.state)); 1069 } else { 1070 SHA1Init(&sha1ctx); 1071 SHA1Update(&sha1ctx, macini->cri_key, 1072 macini->cri_klen / 8); 1073 SHA1Update(&sha1ctx, hmac_ipad_buffer, 1074 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1075 memcpy(ses->ses_hminner, sha1ctx.state, 1076 sizeof(sha1ctx.state)); 1077 } 1078 1079 for (i = 0; i < macini->cri_klen / 8; i++) 1080 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 1081 1082 if (macini->cri_alg == CRYPTO_MD5_HMAC_96) { 1083 MD5Init(&md5ctx); 1084 MD5Update(&md5ctx, macini->cri_key, 1085 macini->cri_klen / 8); 1086 MD5Update(&md5ctx, hmac_opad_buffer, 1087 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1088 memcpy(ses->ses_hmouter, md5ctx.state, 1089 sizeof(md5ctx.state)); 1090 } else { 1091 SHA1Init(&sha1ctx); 1092 SHA1Update(&sha1ctx, macini->cri_key, 1093 macini->cri_klen / 8); 1094 SHA1Update(&sha1ctx, hmac_opad_buffer, 1095 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1096 memcpy(ses->ses_hmouter, sha1ctx.state, 1097 sizeof(sha1ctx.state)); 1098 } 1099 1100 for (i = 0; i < macini->cri_klen / 8; i++) 1101 macini->cri_key[i] ^= HMAC_OPAD_VAL; 1102 } 1103 1104 *sidp = UBSEC_SID(device_unit(sc->sc_dev), sesn); 1105 return (0); 1106 } 1107 1108 /* 1109 * Deallocate a session. 1110 */ 1111 static int 1112 ubsec_freesession(void *arg, u_int64_t tid) 1113 { 1114 struct ubsec_softc *sc; 1115 int session; 1116 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 1117 1118 sc = arg; 1119 KASSERT(sc != NULL /*, ("ubsec_freesession: null softc")*/); 1120 1121 session = UBSEC_SESSION(sid); 1122 if (session >= sc->sc_nsessions) 1123 return (EINVAL); 1124 1125 memset(&sc->sc_sessions[session], 0, sizeof(sc->sc_sessions[session])); 1126 return (0); 1127 } 1128 1129 #ifdef __FreeBSD__ /* Ugly gratuitous changes to bus_dma */ 1130 static void 1131 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, 1132 int error) 1133 { 1134 struct ubsec_operand *op = arg; 1135 1136 KASSERT(nsegs <= UBS_MAX_SCATTER 1137 /*, ("Too many DMA segments returned when mapping operand")*/); 1138 #ifdef UBSEC_DEBUG 1139 if (ubsec_debug) 1140 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 1141 (u_int) mapsize, nsegs); 1142 #endif 1143 op->mapsize = mapsize; 1144 op->nsegs = nsegs; 1145 memcpy(op->segs, seg, nsegs * sizeof (seg[0])); 1146 } 1147 #endif 1148 1149 static int 1150 ubsec_process(void *arg, struct cryptop *crp, int hint) 1151 { 1152 struct ubsec_q *q = NULL; 1153 int err = 0, i, j, nicealign; 1154 struct ubsec_softc *sc; 1155 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1156 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1157 int sskip, dskip, stheend, dtheend; 1158 int16_t coffset; 1159 struct ubsec_session *ses, key; 1160 struct ubsec_dma *dmap = NULL; 1161 u_int16_t flags = 0; 1162 int ivlen = 0, keylen = 0; 1163 1164 sc = arg; 1165 KASSERT(sc != NULL /*, ("ubsec_process: null softc")*/); 1166 1167 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1168 ubsecstats.hst_invalid++; 1169 return (EINVAL); 1170 } 1171 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1172 ubsecstats.hst_badsession++; 1173 return (EINVAL); 1174 } 1175 1176 mutex_spin_enter(&sc->sc_mtx); 1177 1178 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1179 ubsecstats.hst_queuefull++; 1180 sc->sc_needwakeup |= CRYPTO_SYMQ; 1181 mutex_spin_exit(&sc->sc_mtx); 1182 return(ERESTART); 1183 } 1184 1185 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1186 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, /*q,*/ q_next); 1187 mutex_spin_exit(&sc->sc_mtx); 1188 1189 dmap = q->q_dma; /* Save dma pointer */ 1190 /* don't lose the cached dmamaps q_src_map and q_cached_dst_map */ 1191 memset(q, 0, offsetof(struct ubsec_q, q_src_map)); 1192 memset(&key, 0, sizeof(key)); 1193 1194 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1195 q->q_dma = dmap; 1196 ses = &sc->sc_sessions[q->q_sesn]; 1197 1198 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1199 q->q_src_m = (struct mbuf *)crp->crp_buf; 1200 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1201 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1202 q->q_src_io = (struct uio *)crp->crp_buf; 1203 q->q_dst_io = (struct uio *)crp->crp_buf; 1204 } else { 1205 ubsecstats.hst_badflags++; 1206 err = EINVAL; 1207 goto errout; /* XXX we don't handle contiguous blocks! */ 1208 } 1209 1210 memset(&dmap->d_dma->d_mcr, 0, sizeof(struct ubsec_mcr)); 1211 1212 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1213 dmap->d_dma->d_mcr.mcr_flags = 0; 1214 q->q_crp = crp; 1215 1216 crd1 = crp->crp_desc; 1217 if (crd1 == NULL) { 1218 ubsecstats.hst_nodesc++; 1219 err = EINVAL; 1220 goto errout; 1221 } 1222 crd2 = crd1->crd_next; 1223 1224 if (crd2 == NULL) { 1225 if (crd1->crd_alg == CRYPTO_MD5_HMAC_96 || 1226 crd1->crd_alg == CRYPTO_SHA1_HMAC_96) { 1227 maccrd = crd1; 1228 enccrd = NULL; 1229 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1230 crd1->crd_alg == CRYPTO_3DES_CBC || 1231 crd1->crd_alg == CRYPTO_AES_CBC) { 1232 maccrd = NULL; 1233 enccrd = crd1; 1234 } else { 1235 ubsecstats.hst_badalg++; 1236 err = EINVAL; 1237 goto errout; 1238 } 1239 } else { 1240 if ((crd1->crd_alg == CRYPTO_MD5_HMAC_96 || 1241 crd1->crd_alg == CRYPTO_SHA1_HMAC_96) && 1242 (crd2->crd_alg == CRYPTO_DES_CBC || 1243 crd2->crd_alg == CRYPTO_3DES_CBC || 1244 crd2->crd_alg == CRYPTO_AES_CBC) && 1245 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1246 maccrd = crd1; 1247 enccrd = crd2; 1248 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1249 crd1->crd_alg == CRYPTO_3DES_CBC || 1250 crd1->crd_alg == CRYPTO_AES_CBC) && 1251 (crd2->crd_alg == CRYPTO_MD5_HMAC_96 || 1252 crd2->crd_alg == CRYPTO_SHA1_HMAC_96) && 1253 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1254 enccrd = crd1; 1255 maccrd = crd2; 1256 } else { 1257 /* 1258 * We cannot order the ubsec as requested 1259 */ 1260 ubsecstats.hst_badalg++; 1261 err = EINVAL; 1262 goto errout; 1263 } 1264 } 1265 1266 if (enccrd) { 1267 if (enccrd->crd_alg == CRYPTO_AES_CBC) { 1268 if ((sc->sc_flags & UBS_FLAGS_AES) == 0) { 1269 /* 1270 * We cannot order the ubsec as requested 1271 */ 1272 ubsecstats.hst_badalg++; 1273 err = EINVAL; 1274 goto errout; 1275 } 1276 flags |= htole16(UBS_PKTCTX_ENC_AES); 1277 switch (enccrd->crd_klen) { 1278 case 128: 1279 case 192: 1280 case 256: 1281 keylen = enccrd->crd_klen / 8; 1282 break; 1283 default: 1284 err = EINVAL; 1285 goto errout; 1286 } 1287 ivlen = 16; 1288 } else { 1289 flags |= htole16(UBS_PKTCTX_ENC_3DES); 1290 ivlen = 8; 1291 keylen = 24; 1292 } 1293 1294 encoffset = enccrd->crd_skip; 1295 1296 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1297 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1298 1299 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1300 memcpy(key.ses_iv, enccrd->crd_iv, ivlen); 1301 else { 1302 for (i = 0; i < (ivlen / 4); i++) 1303 key.ses_iv[i] = ses->ses_iv[i]; 1304 } 1305 1306 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1307 if (crp->crp_flags & CRYPTO_F_IMBUF) 1308 m_copyback(q->q_src_m, 1309 enccrd->crd_inject, 1310 ivlen, (void *)key.ses_iv); 1311 else if (crp->crp_flags & CRYPTO_F_IOV) 1312 cuio_copyback(q->q_src_io, 1313 enccrd->crd_inject, 1314 ivlen, (void *)key.ses_iv); 1315 } 1316 } else { 1317 flags |= htole16(UBS_PKTCTX_INBOUND); 1318 1319 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1320 memcpy(key.ses_iv, enccrd->crd_iv, ivlen); 1321 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1322 m_copydata(q->q_src_m, enccrd->crd_inject, 1323 ivlen, (void *)key.ses_iv); 1324 else if (crp->crp_flags & CRYPTO_F_IOV) 1325 cuio_copydata(q->q_src_io, 1326 enccrd->crd_inject, 8, 1327 (void *)key.ses_iv); 1328 } 1329 1330 for (i = 0; i < (keylen / 4); i++) 1331 key.ses_key[i] = ses->ses_key[i]; 1332 for (i = 0; i < (ivlen / 4); i++) 1333 SWAP32(key.ses_iv[i]); 1334 } 1335 1336 if (maccrd) { 1337 macoffset = maccrd->crd_skip; 1338 1339 if (maccrd->crd_alg == CRYPTO_MD5_HMAC_96) 1340 flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1341 else 1342 flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1343 1344 for (i = 0; i < 5; i++) { 1345 key.ses_hminner[i] = ses->ses_hminner[i]; 1346 key.ses_hmouter[i] = ses->ses_hmouter[i]; 1347 1348 HTOLE32(key.ses_hminner[i]); 1349 HTOLE32(key.ses_hmouter[i]); 1350 } 1351 } 1352 1353 if (enccrd && maccrd) { 1354 /* 1355 * ubsec cannot handle packets where the end of encryption 1356 * and authentication are not the same, or where the 1357 * encrypted part begins before the authenticated part. 1358 */ 1359 if ((encoffset + enccrd->crd_len) != 1360 (macoffset + maccrd->crd_len)) { 1361 ubsecstats.hst_lenmismatch++; 1362 err = EINVAL; 1363 goto errout; 1364 } 1365 if (enccrd->crd_skip < maccrd->crd_skip) { 1366 ubsecstats.hst_skipmismatch++; 1367 err = EINVAL; 1368 goto errout; 1369 } 1370 sskip = maccrd->crd_skip; 1371 cpskip = dskip = enccrd->crd_skip; 1372 stheend = maccrd->crd_len; 1373 dtheend = enccrd->crd_len; 1374 coffset = enccrd->crd_skip - maccrd->crd_skip; 1375 cpoffset = cpskip + dtheend; 1376 #ifdef UBSEC_DEBUG 1377 if (ubsec_debug) { 1378 printf("mac: skip %d, len %d, inject %d\n", 1379 maccrd->crd_skip, maccrd->crd_len, 1380 maccrd->crd_inject); 1381 printf("enc: skip %d, len %d, inject %d\n", 1382 enccrd->crd_skip, enccrd->crd_len, 1383 enccrd->crd_inject); 1384 printf("src: skip %d, len %d\n", sskip, stheend); 1385 printf("dst: skip %d, len %d\n", dskip, dtheend); 1386 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1387 coffset, stheend, cpskip, cpoffset); 1388 } 1389 #endif 1390 } else { 1391 cpskip = dskip = sskip = macoffset + encoffset; 1392 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1393 cpoffset = cpskip + dtheend; 1394 coffset = 0; 1395 } 1396 1397 if (q->q_src_map == NULL) { 1398 /* XXX FIXME: jonathan asks, what the heck's that 0xfff0? */ 1399 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, 1400 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { 1401 err = ENOMEM; 1402 goto errout; 1403 } 1404 } 1405 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1406 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1407 q->q_src_m, BUS_DMA_NOWAIT) != 0) { 1408 ubsecstats.hst_noload++; 1409 err = ENOMEM; 1410 goto errout; 1411 } 1412 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1413 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1414 q->q_src_io, BUS_DMA_NOWAIT) != 0) { 1415 ubsecstats.hst_noload++; 1416 err = ENOMEM; 1417 goto errout; 1418 } 1419 } 1420 nicealign = ubsec_dmamap_aligned(q->q_src_map); 1421 1422 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1423 1424 #ifdef UBSEC_DEBUG 1425 if (ubsec_debug) 1426 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1427 #endif 1428 for (i = j = 0; i < q->q_src_map->dm_nsegs; i++) { 1429 struct ubsec_pktbuf *pb; 1430 bus_size_t packl = q->q_src_map->dm_segs[i].ds_len; 1431 bus_addr_t packp = q->q_src_map->dm_segs[i].ds_addr; 1432 1433 if (sskip >= packl) { 1434 sskip -= packl; 1435 continue; 1436 } 1437 1438 packl -= sskip; 1439 packp += sskip; 1440 sskip = 0; 1441 1442 if (packl > 0xfffc) { 1443 err = EIO; 1444 goto errout; 1445 } 1446 1447 if (j == 0) 1448 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1449 else 1450 pb = &dmap->d_dma->d_sbuf[j - 1]; 1451 1452 pb->pb_addr = htole32(packp); 1453 1454 if (stheend) { 1455 if (packl > stheend) { 1456 pb->pb_len = htole32(stheend); 1457 stheend = 0; 1458 } else { 1459 pb->pb_len = htole32(packl); 1460 stheend -= packl; 1461 } 1462 } else 1463 pb->pb_len = htole32(packl); 1464 1465 if ((i + 1) == q->q_src_map->dm_nsegs) 1466 pb->pb_next = 0; 1467 else 1468 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1469 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1470 j++; 1471 } 1472 1473 if (enccrd == NULL && maccrd != NULL) { 1474 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1475 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1476 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1477 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1478 #ifdef UBSEC_DEBUG 1479 if (ubsec_debug) 1480 printf("opkt: %x %x %x\n", 1481 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1482 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1483 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1484 1485 #endif 1486 } else { 1487 if (crp->crp_flags & CRYPTO_F_IOV) { 1488 if (!nicealign) { 1489 ubsecstats.hst_iovmisaligned++; 1490 err = EINVAL; 1491 goto errout; 1492 } 1493 if (q->q_dst_map == NULL) { 1494 if (q->q_cached_dst_map == NULL) { 1495 /* 1496 * XXX: ``what the heck's that'' 1497 * 0xfff0? 1498 */ 1499 if (bus_dmamap_create(sc->sc_dmat, 1500 0xfff0, UBS_MAX_SCATTER, 0xfff0, 0, 1501 BUS_DMA_NOWAIT, 1502 &q->q_cached_dst_map) != 0) { 1503 ubsecstats.hst_nomap++; 1504 err = ENOMEM; 1505 goto errout; 1506 } 1507 } 1508 q->q_dst_map = q->q_cached_dst_map; 1509 } 1510 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1511 q->q_dst_io, BUS_DMA_NOWAIT) != 0) { 1512 ubsecstats.hst_noload++; 1513 err = ENOMEM; 1514 goto errout; 1515 } 1516 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1517 if (nicealign) { 1518 q->q_dst_m = q->q_src_m; 1519 q->q_dst_map = q->q_src_map; 1520 } else { 1521 int totlen, len; 1522 struct mbuf *m, *top, **mp; 1523 1524 ubsecstats.hst_unaligned++; 1525 totlen = q->q_src_map->dm_mapsize; 1526 if (q->q_src_m->m_flags & M_PKTHDR) { 1527 len = MHLEN; 1528 MGETHDR(m, M_DONTWAIT, MT_DATA); 1529 /*XXX FIXME: m_dup_pkthdr */ 1530 if (m && 1 /*!m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)*/) { 1531 m_free(m); 1532 m = NULL; 1533 } 1534 } else { 1535 len = MLEN; 1536 MGET(m, M_DONTWAIT, MT_DATA); 1537 } 1538 if (m == NULL) { 1539 ubsecstats.hst_nombuf++; 1540 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1541 goto errout; 1542 } 1543 if (len == MHLEN) 1544 /*XXX was M_DUP_PKTHDR*/ 1545 m_copy_pkthdr(m, q->q_src_m); 1546 if (totlen >= MINCLSIZE) { 1547 MCLGET(m, M_DONTWAIT); 1548 if ((m->m_flags & M_EXT) == 0) { 1549 m_free(m); 1550 ubsecstats.hst_nomcl++; 1551 err = sc->sc_nqueue 1552 ? ERESTART : ENOMEM; 1553 goto errout; 1554 } 1555 len = MCLBYTES; 1556 } 1557 m->m_len = len; 1558 top = NULL; 1559 mp = ⊤ 1560 1561 while (totlen > 0) { 1562 if (top) { 1563 MGET(m, M_DONTWAIT, MT_DATA); 1564 if (m == NULL) { 1565 m_freem(top); 1566 ubsecstats.hst_nombuf++; 1567 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1568 goto errout; 1569 } 1570 len = MLEN; 1571 } 1572 if (top && totlen >= MINCLSIZE) { 1573 MCLGET(m, M_DONTWAIT); 1574 if ((m->m_flags & M_EXT) == 0) { 1575 *mp = m; 1576 m_freem(top); 1577 ubsecstats.hst_nomcl++; 1578 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1579 goto errout; 1580 } 1581 len = MCLBYTES; 1582 } 1583 m->m_len = len = uimin(totlen, len); 1584 totlen -= len; 1585 *mp = m; 1586 mp = &m->m_next; 1587 } 1588 q->q_dst_m = top; 1589 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1590 cpskip, cpoffset); 1591 if (q->q_dst_map == NULL) { 1592 if (q->q_cached_dst_map == NULL) { 1593 /* XXX again, what the heck is that 0xfff0? */ 1594 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, 1595 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, 1596 &q->q_cached_dst_map) != 0) { 1597 ubsecstats.hst_nomap++; 1598 err = ENOMEM; 1599 goto errout; 1600 } 1601 } 1602 q->q_dst_map = q->q_cached_dst_map; 1603 } 1604 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1605 q->q_dst_map, q->q_dst_m, 1606 BUS_DMA_NOWAIT) != 0) { 1607 ubsecstats.hst_noload++; 1608 err = ENOMEM; 1609 goto errout; 1610 } 1611 } 1612 } else { 1613 ubsecstats.hst_badflags++; 1614 err = EINVAL; 1615 goto errout; 1616 } 1617 1618 #ifdef UBSEC_DEBUG 1619 if (ubsec_debug) 1620 printf("dst skip: %d\n", dskip); 1621 #endif 1622 for (i = j = 0; i < q->q_dst_map->dm_nsegs; i++) { 1623 struct ubsec_pktbuf *pb; 1624 bus_size_t packl = q->q_dst_map->dm_segs[i].ds_len; 1625 bus_addr_t packp = q->q_dst_map->dm_segs[i].ds_addr; 1626 1627 if (dskip >= packl) { 1628 dskip -= packl; 1629 continue; 1630 } 1631 1632 packl -= dskip; 1633 packp += dskip; 1634 dskip = 0; 1635 1636 if (packl > 0xfffc) { 1637 err = EIO; 1638 goto errout; 1639 } 1640 1641 if (j == 0) 1642 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1643 else 1644 pb = &dmap->d_dma->d_dbuf[j - 1]; 1645 1646 pb->pb_addr = htole32(packp); 1647 1648 if (dtheend) { 1649 if (packl > dtheend) { 1650 pb->pb_len = htole32(dtheend); 1651 dtheend = 0; 1652 } else { 1653 pb->pb_len = htole32(packl); 1654 dtheend -= packl; 1655 } 1656 } else 1657 pb->pb_len = htole32(packl); 1658 1659 if ((i + 1) == q->q_dst_map->dm_nsegs) { 1660 if (maccrd) 1661 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1662 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1663 else 1664 pb->pb_next = 0; 1665 } else 1666 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1667 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1668 j++; 1669 } 1670 } 1671 1672 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1673 offsetof(struct ubsec_dmachunk, d_ctx)); 1674 1675 if (enccrd && enccrd->crd_alg == CRYPTO_AES_CBC) { 1676 struct ubsec_pktctx_aes128 *aes128; 1677 struct ubsec_pktctx_aes192 *aes192; 1678 struct ubsec_pktctx_aes256 *aes256; 1679 struct ubsec_pktctx_hdr *ph; 1680 u_int8_t *ctx; 1681 1682 ctx = (u_int8_t *)(dmap->d_alloc.dma_vaddr) + 1683 offsetof(struct ubsec_dmachunk, d_ctx); 1684 1685 ph = (struct ubsec_pktctx_hdr *)ctx; 1686 ph->ph_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES); 1687 ph->ph_flags = flags; 1688 ph->ph_offset = htole16(coffset >> 2); 1689 1690 switch (enccrd->crd_klen) { 1691 case 128: 1692 aes128 = (struct ubsec_pktctx_aes128 *)ctx; 1693 ph->ph_len = htole16(sizeof(*aes128)); 1694 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_128); 1695 for (i = 0; i < 4; i++) 1696 aes128->pc_aeskey[i] = key.ses_key[i]; 1697 for (i = 0; i < 5; i++) 1698 aes128->pc_hminner[i] = key.ses_hminner[i]; 1699 for (i = 0; i < 5; i++) 1700 aes128->pc_hmouter[i] = key.ses_hmouter[i]; 1701 for (i = 0; i < 4; i++) 1702 aes128->pc_iv[i] = key.ses_iv[i]; 1703 break; 1704 case 192: 1705 aes192 = (struct ubsec_pktctx_aes192 *)ctx; 1706 ph->ph_len = htole16(sizeof(*aes192)); 1707 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_192); 1708 for (i = 0; i < 6; i++) 1709 aes192->pc_aeskey[i] = key.ses_key[i]; 1710 for (i = 0; i < 5; i++) 1711 aes192->pc_hminner[i] = key.ses_hminner[i]; 1712 for (i = 0; i < 5; i++) 1713 aes192->pc_hmouter[i] = key.ses_hmouter[i]; 1714 for (i = 0; i < 4; i++) 1715 aes192->pc_iv[i] = key.ses_iv[i]; 1716 break; 1717 case 256: 1718 aes256 = (struct ubsec_pktctx_aes256 *)ctx; 1719 ph->ph_len = htole16(sizeof(*aes256)); 1720 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_256); 1721 for (i = 0; i < 8; i++) 1722 aes256->pc_aeskey[i] = key.ses_key[i]; 1723 for (i = 0; i < 5; i++) 1724 aes256->pc_hminner[i] = key.ses_hminner[i]; 1725 for (i = 0; i < 5; i++) 1726 aes256->pc_hmouter[i] = key.ses_hmouter[i]; 1727 for (i = 0; i < 4; i++) 1728 aes256->pc_iv[i] = key.ses_iv[i]; 1729 break; 1730 } 1731 } else if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1732 struct ubsec_pktctx_3des *ctx; 1733 struct ubsec_pktctx_hdr *ph; 1734 1735 ctx = (struct ubsec_pktctx_3des *) 1736 ((u_int8_t *)(dmap->d_alloc.dma_vaddr) + 1737 offsetof(struct ubsec_dmachunk, d_ctx)); 1738 1739 ph = (struct ubsec_pktctx_hdr *)ctx; 1740 ph->ph_len = htole16(sizeof(*ctx)); 1741 ph->ph_type = htole16(UBS_PKTCTX_TYPE_IPSEC_3DES); 1742 ph->ph_flags = flags; 1743 ph->ph_offset = htole16(coffset >> 2); 1744 1745 for (i = 0; i < 6; i++) 1746 ctx->pc_deskey[i] = key.ses_key[i]; 1747 for (i = 0; i < 5; i++) 1748 ctx->pc_hminner[i] = key.ses_hminner[i]; 1749 for (i = 0; i < 5; i++) 1750 ctx->pc_hmouter[i] = key.ses_hmouter[i]; 1751 for (i = 0; i < 2; i++) 1752 ctx->pc_iv[i] = key.ses_iv[i]; 1753 } else { 1754 struct ubsec_pktctx *ctx = (struct ubsec_pktctx *) 1755 ((u_int8_t *)dmap->d_alloc.dma_vaddr + 1756 offsetof(struct ubsec_dmachunk, d_ctx)); 1757 1758 ctx->pc_flags = flags; 1759 ctx->pc_offset = htole16(coffset >> 2); 1760 for (i = 0; i < 6; i++) 1761 ctx->pc_deskey[i] = key.ses_key[i]; 1762 for (i = 0; i < 5; i++) 1763 ctx->pc_hminner[i] = key.ses_hminner[i]; 1764 for (i = 0; i < 5; i++) 1765 ctx->pc_hmouter[i] = key.ses_hmouter[i]; 1766 for (i = 0; i < 2; i++) 1767 ctx->pc_iv[i] = key.ses_iv[i]; 1768 } 1769 1770 mutex_spin_enter(&sc->sc_mtx); 1771 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1772 sc->sc_nqueue++; 1773 ubsecstats.hst_ipackets++; 1774 ubsecstats.hst_ibytes += dmap->d_alloc.dma_map->dm_mapsize; 1775 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= ubsec_maxbatch) 1776 ubsec_feed(sc); 1777 mutex_spin_exit(&sc->sc_mtx); 1778 return (0); 1779 1780 errout: 1781 if (q != NULL) { 1782 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1783 m_freem(q->q_dst_m); 1784 1785 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1786 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1787 } 1788 if (q->q_src_map != NULL) { 1789 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1790 } 1791 1792 mutex_spin_enter(&sc->sc_mtx); 1793 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1794 mutex_spin_exit(&sc->sc_mtx); 1795 } 1796 #if 0 /* jonathan says: this openbsd code seems to be subsumed elsewhere */ 1797 if (err == EINVAL) 1798 ubsecstats.hst_invalid++; 1799 else 1800 ubsecstats.hst_nomem++; 1801 #endif 1802 if (err != ERESTART) { 1803 crp->crp_etype = err; 1804 crypto_done(crp); 1805 } else { 1806 sc->sc_needwakeup |= CRYPTO_SYMQ; 1807 } 1808 return (err); 1809 } 1810 1811 static void 1812 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1813 { 1814 struct cryptop *crp = (struct cryptop *)q->q_crp; 1815 struct cryptodesc *crd; 1816 struct ubsec_dma *dmap = q->q_dma; 1817 1818 ubsecstats.hst_opackets++; 1819 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1820 1821 bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, 1822 dmap->d_alloc.dma_map->dm_mapsize, 1823 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1824 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1825 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1826 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1827 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1828 } 1829 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 1830 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1831 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1832 1833 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1834 m_freem(q->q_src_m); 1835 crp->crp_buf = (void *)q->q_dst_m; 1836 } 1837 1838 /* copy out IV for future use */ 1839 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1840 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1841 if (crd->crd_alg != CRYPTO_DES_CBC && 1842 crd->crd_alg != CRYPTO_3DES_CBC && 1843 crd->crd_alg != CRYPTO_AES_CBC) 1844 continue; 1845 if (crp->crp_flags & CRYPTO_F_IMBUF) 1846 m_copydata((struct mbuf *)crp->crp_buf, 1847 crd->crd_skip + crd->crd_len - 8, 8, 1848 (void *)sc->sc_sessions[q->q_sesn].ses_iv); 1849 else if (crp->crp_flags & CRYPTO_F_IOV) { 1850 cuio_copydata((struct uio *)crp->crp_buf, 1851 crd->crd_skip + crd->crd_len - 8, 8, 1852 (void *)sc->sc_sessions[q->q_sesn].ses_iv); 1853 } 1854 break; 1855 } 1856 } 1857 1858 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1859 if (crd->crd_alg != CRYPTO_MD5_HMAC_96 && 1860 crd->crd_alg != CRYPTO_SHA1_HMAC_96) 1861 continue; 1862 if (crp->crp_flags & CRYPTO_F_IMBUF) 1863 m_copyback((struct mbuf *)crp->crp_buf, 1864 crd->crd_inject, 12, 1865 (void *)dmap->d_dma->d_macbuf); 1866 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1867 bcopy((void *)dmap->d_dma->d_macbuf, 1868 crp->crp_mac, 12); 1869 break; 1870 } 1871 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1872 crypto_done(crp); 1873 } 1874 1875 static void 1876 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1877 { 1878 int i, j, dlen, slen; 1879 char *dptr, *sptr; 1880 1881 j = 0; 1882 sptr = srcm->m_data; 1883 slen = srcm->m_len; 1884 dptr = dstm->m_data; 1885 dlen = dstm->m_len; 1886 1887 while (1) { 1888 for (i = 0; i < uimin(slen, dlen); i++) { 1889 if (j < hoffset || j >= toffset) 1890 *dptr++ = *sptr++; 1891 slen--; 1892 dlen--; 1893 j++; 1894 } 1895 if (slen == 0) { 1896 srcm = srcm->m_next; 1897 if (srcm == NULL) 1898 return; 1899 sptr = srcm->m_data; 1900 slen = srcm->m_len; 1901 } 1902 if (dlen == 0) { 1903 dstm = dstm->m_next; 1904 if (dstm == NULL) 1905 return; 1906 dptr = dstm->m_data; 1907 dlen = dstm->m_len; 1908 } 1909 } 1910 } 1911 1912 /* 1913 * feed the key generator, must be called at splnet() or higher. 1914 */ 1915 static void 1916 ubsec_feed2(struct ubsec_softc *sc) 1917 { 1918 struct ubsec_q2 *q; 1919 1920 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1921 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1922 break; 1923 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1924 1925 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1926 q->q_mcr.dma_map->dm_mapsize, 1927 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1928 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1929 q->q_ctx.dma_map->dm_mapsize, 1930 BUS_DMASYNC_PREWRITE); 1931 1932 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1933 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1934 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, /*q,*/ q_next); 1935 --sc->sc_nqueue2; 1936 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1937 } 1938 } 1939 1940 /* 1941 * feed the RNG (used instead of ubsec_feed2() on 5827+ devices) 1942 */ 1943 void 1944 ubsec_feed4(struct ubsec_softc *sc) 1945 { 1946 struct ubsec_q2 *q; 1947 1948 while (!SIMPLEQ_EMPTY(&sc->sc_queue4)) { 1949 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR4_FULL) 1950 break; 1951 q = SIMPLEQ_FIRST(&sc->sc_queue4); 1952 1953 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1954 q->q_mcr.dma_map->dm_mapsize, 1955 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1956 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1957 q->q_ctx.dma_map->dm_mapsize, 1958 BUS_DMASYNC_PREWRITE); 1959 1960 WRITE_REG(sc, BS_MCR4, q->q_mcr.dma_paddr); 1961 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue4, q_next); 1962 --sc->sc_nqueue4; 1963 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip4, q, q_next); 1964 } 1965 } 1966 1967 /* 1968 * Callback for handling random numbers 1969 */ 1970 static void 1971 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1972 { 1973 struct cryptkop *krp; 1974 struct ubsec_ctx_keyop *ctx; 1975 1976 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1977 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1978 q->q_ctx.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1979 1980 switch (q->q_type) { 1981 #ifndef UBSEC_NO_RNG 1982 case UBS_CTXOP_RNGSHA1: 1983 case UBS_CTXOP_RNGBYPASS: { 1984 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1985 u_int32_t *p; 1986 int i; 1987 1988 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 1989 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1990 p = (u_int32_t *)rng->rng_buf.dma_vaddr; 1991 i = UBSEC_RNG_BUFSIZ * sizeof(u_int32_t); 1992 rnd_add_data(&sc->sc_rnd_source, (char *)p, i, i * NBBY); 1993 sc->sc_rng_need -= i; 1994 rng->rng_used = 0; 1995 if (sc->sc_rng_need > 0) { 1996 callout_schedule(&sc->sc_rngto, sc->sc_rnghz); 1997 } 1998 break; 1999 } 2000 #endif 2001 case UBS_CTXOP_MODEXP: { 2002 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2003 u_int rlen, clen; 2004 2005 krp = me->me_krp; 2006 rlen = (me->me_modbits + 7) / 8; 2007 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 2008 2009 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2010 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2011 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2012 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2013 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2014 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2015 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2016 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2017 2018 if (clen < rlen) 2019 krp->krp_status = E2BIG; 2020 else { 2021 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 2022 memset(krp->krp_param[krp->krp_iparams].crp_p, 0, 2023 (krp->krp_param[krp->krp_iparams].crp_nbits 2024 + 7) / 8); 2025 bcopy(me->me_C.dma_vaddr, 2026 krp->krp_param[krp->krp_iparams].crp_p, 2027 (me->me_modbits + 7) / 8); 2028 } else 2029 ubsec_kshift_l(me->me_shiftbits, 2030 me->me_C.dma_vaddr, me->me_normbits, 2031 krp->krp_param[krp->krp_iparams].crp_p, 2032 krp->krp_param[krp->krp_iparams].crp_nbits); 2033 } 2034 2035 crypto_kdone(krp); 2036 2037 /* bzero all potentially sensitive data */ 2038 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2039 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2040 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2041 memset(me->me_q.q_ctx.dma_vaddr, 0, me->me_q.q_ctx.dma_size); 2042 2043 /* Can't free here, so put us on the free list. */ 2044 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 2045 break; 2046 } 2047 case UBS_CTXOP_RSAPRIV: { 2048 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2049 u_int len; 2050 2051 krp = rp->rpr_krp; 2052 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 0, 2053 rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2054 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 0, 2055 rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2056 2057 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) 2058 / 8; 2059 bcopy(rp->rpr_msgout.dma_vaddr, 2060 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 2061 2062 crypto_kdone(krp); 2063 2064 memset(rp->rpr_msgin.dma_vaddr, 0, rp->rpr_msgin.dma_size); 2065 memset(rp->rpr_msgout.dma_vaddr, 0, rp->rpr_msgout.dma_size); 2066 memset(rp->rpr_q.q_ctx.dma_vaddr, 0, rp->rpr_q.q_ctx.dma_size); 2067 2068 /* Can't free here, so put us on the free list. */ 2069 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 2070 break; 2071 } 2072 default: 2073 printf("%s: unknown ctx op: %x\n", device_xname(sc->sc_dev), 2074 letoh16(ctx->ctx_op)); 2075 break; 2076 } 2077 } 2078 2079 #ifndef UBSEC_NO_RNG 2080 2081 static void 2082 ubsec_rng_get(size_t bytes, void *vsc) 2083 { 2084 struct ubsec_softc *sc = vsc; 2085 2086 mutex_spin_enter(&sc->sc_mtx); 2087 sc->sc_rng_need = bytes; 2088 ubsec_rng_locked(sc); 2089 mutex_spin_exit(&sc->sc_mtx); 2090 2091 } 2092 2093 static void 2094 ubsec_rng(void *vsc) 2095 { 2096 struct ubsec_softc *sc = vsc; 2097 mutex_spin_enter(&sc->sc_mtx); 2098 ubsec_rng_locked(sc); 2099 mutex_spin_exit(&sc->sc_mtx); 2100 } 2101 2102 static void 2103 ubsec_rng_locked(void *vsc) 2104 { 2105 struct ubsec_softc *sc = vsc; 2106 struct ubsec_q2_rng *rng = &sc->sc_rng; 2107 struct ubsec_mcr *mcr; 2108 struct ubsec_ctx_rngbypass *ctx; 2109 int *nqueue; 2110 2111 /* Caller is responsible to lock and release sc_mtx. */ 2112 KASSERT(mutex_owned(&sc->sc_mtx)); 2113 2114 if (rng->rng_used) { 2115 return; 2116 } 2117 2118 if (sc->sc_rng_need < 1) { 2119 callout_stop(&sc->sc_rngto); 2120 return; 2121 } 2122 2123 if (sc->sc_flags & UBS_FLAGS_RNG4) 2124 nqueue = &sc->sc_nqueue4; 2125 else 2126 nqueue = &sc->sc_nqueue2; 2127 2128 (*nqueue)++; 2129 if (*nqueue >= UBS_MAX_NQUEUE) 2130 goto out; 2131 2132 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 2133 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 2134 2135 mcr->mcr_pkts = htole16(1); 2136 mcr->mcr_flags = 0; 2137 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 2138 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 2139 mcr->mcr_ipktbuf.pb_len = 0; 2140 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 2141 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 2142 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 2143 UBS_PKTBUF_LEN); 2144 mcr->mcr_opktbuf.pb_next = 0; 2145 2146 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 2147 ctx->rbp_op = htole16(UBS_CTXOP_RNGSHA1); 2148 rng->rng_q.q_type = UBS_CTXOP_RNGSHA1; 2149 2150 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 2151 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2152 2153 if (sc->sc_flags & UBS_FLAGS_RNG4) { 2154 SIMPLEQ_INSERT_TAIL(&sc->sc_queue4, &rng->rng_q, q_next); 2155 ubsec_feed4(sc); 2156 } else { 2157 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 2158 ubsec_feed2(sc); 2159 } 2160 rng->rng_used = 1; 2161 ubsecstats.hst_rng++; 2162 2163 return; 2164 2165 out: 2166 /* 2167 * Something weird happened, generate our own call back. 2168 */ 2169 (*nqueue)--; 2170 callout_schedule(&sc->sc_rngto, sc->sc_rnghz); 2171 } 2172 #endif /* UBSEC_NO_RNG */ 2173 2174 static int 2175 ubsec_dma_malloc(struct ubsec_softc *sc, bus_size_t size, 2176 struct ubsec_dma_alloc *dma,int mapflags) 2177 { 2178 int r; 2179 2180 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 2181 &dma->dma_seg, 1, &dma->dma_nseg, BUS_DMA_NOWAIT)) != 0) 2182 goto fail_0; 2183 2184 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 2185 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 2186 goto fail_1; 2187 2188 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 2189 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 2190 goto fail_2; 2191 2192 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 2193 size, NULL, BUS_DMA_NOWAIT)) != 0) 2194 goto fail_3; 2195 2196 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 2197 dma->dma_size = size; 2198 return (0); 2199 2200 fail_3: 2201 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2202 fail_2: 2203 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 2204 fail_1: 2205 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2206 fail_0: 2207 dma->dma_map = NULL; 2208 return (r); 2209 } 2210 2211 static void 2212 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 2213 { 2214 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 2215 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 2216 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2217 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2218 } 2219 2220 /* 2221 * Resets the board. Values in the regesters are left as is 2222 * from the reset (i.e. initial values are assigned elsewhere). 2223 */ 2224 static void 2225 ubsec_reset_board(struct ubsec_softc *sc) 2226 { 2227 volatile u_int32_t ctrl; 2228 2229 ctrl = READ_REG(sc, BS_CTRL); 2230 ctrl |= BS_CTRL_RESET; 2231 WRITE_REG(sc, BS_CTRL, ctrl); 2232 2233 /* 2234 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 2235 */ 2236 DELAY(10); 2237 2238 /* Enable RNG and interrupts on newer devices */ 2239 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) { 2240 #ifndef UBSEC_NO_RNG 2241 WRITE_REG(sc, BS_CFG, BS_CFG_RNG); 2242 #endif 2243 WRITE_REG(sc, BS_INT, BS_INT_DMAINT); 2244 } 2245 } 2246 2247 /* 2248 * Init Broadcom registers 2249 */ 2250 static void 2251 ubsec_init_board(struct ubsec_softc *sc) 2252 { 2253 u_int32_t ctrl; 2254 2255 ctrl = READ_REG(sc, BS_CTRL); 2256 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 2257 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 2258 2259 /* 2260 * XXX: Sam Leffler's code has (UBS_FLAGS_KEY|UBS_FLAGS_RNG)). 2261 * anyone got hw docs? 2262 */ 2263 if (sc->sc_flags & UBS_FLAGS_KEY) 2264 ctrl |= BS_CTRL_MCR2INT; 2265 else 2266 ctrl &= ~BS_CTRL_MCR2INT; 2267 2268 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2269 ctrl &= ~BS_CTRL_SWNORM; 2270 2271 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) { 2272 ctrl |= BS_CTRL_BSIZE240; 2273 ctrl &= ~BS_CTRL_MCR3INT; /* MCR3 is reserved for SSL */ 2274 2275 if (sc->sc_flags & UBS_FLAGS_RNG4) 2276 ctrl |= BS_CTRL_MCR4INT; 2277 else 2278 ctrl &= ~BS_CTRL_MCR4INT; 2279 } 2280 2281 WRITE_REG(sc, BS_CTRL, ctrl); 2282 } 2283 2284 /* 2285 * Init Broadcom PCI registers 2286 */ 2287 static void 2288 ubsec_init_pciregs(struct pci_attach_args *pa) 2289 { 2290 pci_chipset_tag_t pc = pa->pa_pc; 2291 u_int32_t misc; 2292 2293 /* 2294 * This will set the cache line size to 1, this will 2295 * force the BCM58xx chip just to do burst read/writes. 2296 * Cache line read/writes are to slow 2297 */ 2298 misc = pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 2299 misc = (misc & ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)) 2300 | ((UBS_DEF_CACHELINE & 0xff) << PCI_CACHELINE_SHIFT); 2301 pci_conf_write(pc, pa->pa_tag, PCI_BHLC_REG, misc); 2302 } 2303 2304 /* 2305 * Clean up after a chip crash. 2306 * It is assumed that the caller in splnet() 2307 */ 2308 static void 2309 ubsec_cleanchip(struct ubsec_softc *sc) 2310 { 2311 struct ubsec_q *q; 2312 2313 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 2314 q = SIMPLEQ_FIRST(&sc->sc_qchip); 2315 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 2316 ubsec_free_q(sc, q); 2317 } 2318 sc->sc_nqchip = 0; 2319 } 2320 2321 /* 2322 * free a ubsec_q 2323 * It is assumed that the caller is within splnet() 2324 */ 2325 static int 2326 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2327 { 2328 struct ubsec_q *q2; 2329 struct cryptop *crp; 2330 int npkts; 2331 int i; 2332 2333 npkts = q->q_nstacked_mcrs; 2334 2335 for (i = 0; i < npkts; i++) { 2336 if(q->q_stacked_mcr[i]) { 2337 q2 = q->q_stacked_mcr[i]; 2338 2339 if ((q2->q_dst_m != NULL) 2340 && (q2->q_src_m != q2->q_dst_m)) 2341 m_freem(q2->q_dst_m); 2342 2343 crp = (struct cryptop *)q2->q_crp; 2344 2345 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2346 2347 crp->crp_etype = EFAULT; 2348 crypto_done(crp); 2349 } else { 2350 break; 2351 } 2352 } 2353 2354 /* 2355 * Free header MCR 2356 */ 2357 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2358 m_freem(q->q_dst_m); 2359 2360 crp = (struct cryptop *)q->q_crp; 2361 2362 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2363 2364 crp->crp_etype = EFAULT; 2365 crypto_done(crp); 2366 return(0); 2367 } 2368 2369 /* 2370 * Routine to reset the chip and clean up. 2371 * It is assumed that the caller is in splnet() 2372 */ 2373 static void 2374 ubsec_totalreset(struct ubsec_softc *sc) 2375 { 2376 ubsec_reset_board(sc); 2377 ubsec_init_board(sc); 2378 ubsec_cleanchip(sc); 2379 } 2380 2381 static int 2382 ubsec_dmamap_aligned(bus_dmamap_t map) 2383 { 2384 int i; 2385 2386 for (i = 0; i < map->dm_nsegs; i++) { 2387 if (map->dm_segs[i].ds_addr & 3) 2388 return (0); 2389 if ((i != (map->dm_nsegs - 1)) && 2390 (map->dm_segs[i].ds_len & 3)) 2391 return (0); 2392 } 2393 return (1); 2394 } 2395 2396 static void 2397 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2398 { 2399 switch (q->q_type) { 2400 case UBS_CTXOP_MODEXP: { 2401 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2402 2403 ubsec_dma_free(sc, &me->me_q.q_mcr); 2404 ubsec_dma_free(sc, &me->me_q.q_ctx); 2405 ubsec_dma_free(sc, &me->me_M); 2406 ubsec_dma_free(sc, &me->me_E); 2407 ubsec_dma_free(sc, &me->me_C); 2408 ubsec_dma_free(sc, &me->me_epb); 2409 free(me, M_DEVBUF); 2410 break; 2411 } 2412 case UBS_CTXOP_RSAPRIV: { 2413 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2414 2415 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2416 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2417 ubsec_dma_free(sc, &rp->rpr_msgin); 2418 ubsec_dma_free(sc, &rp->rpr_msgout); 2419 free(rp, M_DEVBUF); 2420 break; 2421 } 2422 default: 2423 printf("%s: invalid kfree 0x%x\n", device_xname(sc->sc_dev), 2424 q->q_type); 2425 break; 2426 } 2427 } 2428 2429 static int 2430 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2431 { 2432 struct ubsec_softc *sc; 2433 int r; 2434 2435 if (krp == NULL || krp->krp_callback == NULL) 2436 return (EINVAL); 2437 sc = arg; 2438 KASSERT(sc != NULL /*, ("ubsec_kprocess: null softc")*/); 2439 2440 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2441 struct ubsec_q2 *q; 2442 2443 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2444 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, /*q,*/ q_next); 2445 ubsec_kfree(sc, q); 2446 } 2447 2448 switch (krp->krp_op) { 2449 case CRK_MOD_EXP: 2450 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2451 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2452 else 2453 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2454 break; 2455 case CRK_MOD_EXP_CRT: 2456 r = ubsec_kprocess_rsapriv(sc, krp, hint); 2457 break; 2458 default: 2459 printf("%s: kprocess: invalid op 0x%x\n", 2460 device_xname(sc->sc_dev), krp->krp_op); 2461 krp->krp_status = EOPNOTSUPP; 2462 crypto_kdone(krp); 2463 r = 0; 2464 } 2465 return (r); 2466 } 2467 2468 /* 2469 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2470 */ 2471 static int 2472 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, 2473 int hint) 2474 { 2475 struct ubsec_q2_modexp *me; 2476 struct ubsec_mcr *mcr; 2477 struct ubsec_ctx_modexp *ctx; 2478 struct ubsec_pktbuf *epb; 2479 int err = 0; 2480 u_int nbits, normbits, mbits, shiftbits, ebits; 2481 2482 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2483 if (me == NULL) { 2484 err = ENOMEM; 2485 goto errout; 2486 } 2487 memset(me, 0, sizeof *me); 2488 me->me_krp = krp; 2489 me->me_q.q_type = UBS_CTXOP_MODEXP; 2490 2491 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2492 if (nbits <= 512) 2493 normbits = 512; 2494 else if (nbits <= 768) 2495 normbits = 768; 2496 else if (nbits <= 1024) 2497 normbits = 1024; 2498 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2499 normbits = 1536; 2500 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2501 normbits = 2048; 2502 else { 2503 err = E2BIG; 2504 goto errout; 2505 } 2506 2507 shiftbits = normbits - nbits; 2508 2509 me->me_modbits = nbits; 2510 me->me_shiftbits = shiftbits; 2511 me->me_normbits = normbits; 2512 2513 /* Sanity check: result bits must be >= true modulus bits. */ 2514 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2515 err = ERANGE; 2516 goto errout; 2517 } 2518 2519 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2520 &me->me_q.q_mcr, 0)) { 2521 err = ENOMEM; 2522 goto errout; 2523 } 2524 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2525 2526 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2527 &me->me_q.q_ctx, 0)) { 2528 err = ENOMEM; 2529 goto errout; 2530 } 2531 2532 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2533 if (mbits > nbits) { 2534 err = E2BIG; 2535 goto errout; 2536 } 2537 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2538 err = ENOMEM; 2539 goto errout; 2540 } 2541 ubsec_kshift_r(shiftbits, 2542 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2543 me->me_M.dma_vaddr, normbits); 2544 2545 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2546 err = ENOMEM; 2547 goto errout; 2548 } 2549 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2550 2551 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2552 if (ebits > nbits) { 2553 err = E2BIG; 2554 goto errout; 2555 } 2556 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2557 err = ENOMEM; 2558 goto errout; 2559 } 2560 ubsec_kshift_r(shiftbits, 2561 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2562 me->me_E.dma_vaddr, normbits); 2563 2564 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2565 &me->me_epb, 0)) { 2566 err = ENOMEM; 2567 goto errout; 2568 } 2569 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2570 epb->pb_addr = htole32(me->me_E.dma_paddr); 2571 epb->pb_next = 0; 2572 epb->pb_len = htole32(normbits / 8); 2573 2574 #ifdef UBSEC_DEBUG 2575 if (ubsec_debug) { 2576 printf("Epb "); 2577 ubsec_dump_pb(epb); 2578 } 2579 #endif 2580 2581 mcr->mcr_pkts = htole16(1); 2582 mcr->mcr_flags = 0; 2583 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2584 mcr->mcr_reserved = 0; 2585 mcr->mcr_pktlen = 0; 2586 2587 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2588 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2589 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2590 2591 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2592 mcr->mcr_opktbuf.pb_next = 0; 2593 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2594 2595 #ifdef DIAGNOSTIC 2596 /* Misaligned output buffer will hang the chip. */ 2597 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2598 panic("%s: modexp invalid addr 0x%x", device_xname(sc->sc_dev), 2599 letoh32(mcr->mcr_opktbuf.pb_addr)); 2600 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2601 panic("%s: modexp invalid len 0x%x", device_xname(sc->sc_dev), 2602 letoh32(mcr->mcr_opktbuf.pb_len)); 2603 #endif 2604 2605 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2606 memset(ctx, 0, sizeof(*ctx)); 2607 ubsec_kshift_r(shiftbits, 2608 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2609 ctx->me_N, normbits); 2610 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2611 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2612 ctx->me_E_len = htole16(nbits); 2613 ctx->me_N_len = htole16(nbits); 2614 2615 #ifdef UBSEC_DEBUG 2616 if (ubsec_debug) { 2617 ubsec_dump_mcr(mcr); 2618 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2619 } 2620 #endif 2621 2622 /* 2623 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2624 * everything else. 2625 */ 2626 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2627 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2628 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2629 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2630 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2631 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2632 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2633 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2634 2635 /* Enqueue and we're done... */ 2636 mutex_spin_enter(&sc->sc_mtx); 2637 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2638 ubsec_feed2(sc); 2639 ubsecstats.hst_modexp++; 2640 mutex_spin_exit(&sc->sc_mtx); 2641 2642 return (0); 2643 2644 errout: 2645 if (me != NULL) { 2646 if (me->me_q.q_mcr.dma_map != NULL) 2647 ubsec_dma_free(sc, &me->me_q.q_mcr); 2648 if (me->me_q.q_ctx.dma_map != NULL) { 2649 memset(me->me_q.q_ctx.dma_vaddr, 0, 2650 me->me_q.q_ctx.dma_size); 2651 ubsec_dma_free(sc, &me->me_q.q_ctx); 2652 } 2653 if (me->me_M.dma_map != NULL) { 2654 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2655 ubsec_dma_free(sc, &me->me_M); 2656 } 2657 if (me->me_E.dma_map != NULL) { 2658 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2659 ubsec_dma_free(sc, &me->me_E); 2660 } 2661 if (me->me_C.dma_map != NULL) { 2662 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2663 ubsec_dma_free(sc, &me->me_C); 2664 } 2665 if (me->me_epb.dma_map != NULL) 2666 ubsec_dma_free(sc, &me->me_epb); 2667 free(me, M_DEVBUF); 2668 } 2669 krp->krp_status = err; 2670 crypto_kdone(krp); 2671 return (0); 2672 } 2673 2674 /* 2675 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2676 */ 2677 static int 2678 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, 2679 int hint) 2680 { 2681 struct ubsec_q2_modexp *me; 2682 struct ubsec_mcr *mcr; 2683 struct ubsec_ctx_modexp *ctx; 2684 struct ubsec_pktbuf *epb; 2685 int err = 0; 2686 u_int nbits, normbits, mbits, shiftbits, ebits; 2687 2688 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2689 if (me == NULL) { 2690 err = ENOMEM; 2691 goto errout; 2692 } 2693 memset(me, 0, sizeof *me); 2694 me->me_krp = krp; 2695 me->me_q.q_type = UBS_CTXOP_MODEXP; 2696 2697 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2698 if (nbits <= 512) 2699 normbits = 512; 2700 else if (nbits <= 768) 2701 normbits = 768; 2702 else if (nbits <= 1024) 2703 normbits = 1024; 2704 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2705 normbits = 1536; 2706 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2707 normbits = 2048; 2708 else { 2709 err = E2BIG; 2710 goto errout; 2711 } 2712 2713 shiftbits = normbits - nbits; 2714 2715 /* XXX ??? */ 2716 me->me_modbits = nbits; 2717 me->me_shiftbits = shiftbits; 2718 me->me_normbits = normbits; 2719 2720 /* Sanity check: result bits must be >= true modulus bits. */ 2721 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2722 err = ERANGE; 2723 goto errout; 2724 } 2725 2726 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2727 &me->me_q.q_mcr, 0)) { 2728 err = ENOMEM; 2729 goto errout; 2730 } 2731 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2732 2733 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2734 &me->me_q.q_ctx, 0)) { 2735 err = ENOMEM; 2736 goto errout; 2737 } 2738 2739 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2740 if (mbits > nbits) { 2741 err = E2BIG; 2742 goto errout; 2743 } 2744 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2745 err = ENOMEM; 2746 goto errout; 2747 } 2748 memset(me->me_M.dma_vaddr, 0, normbits / 8); 2749 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2750 me->me_M.dma_vaddr, (mbits + 7) / 8); 2751 2752 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2753 err = ENOMEM; 2754 goto errout; 2755 } 2756 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2757 2758 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2759 if (ebits > nbits) { 2760 err = E2BIG; 2761 goto errout; 2762 } 2763 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2764 err = ENOMEM; 2765 goto errout; 2766 } 2767 memset(me->me_E.dma_vaddr, 0, normbits / 8); 2768 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2769 me->me_E.dma_vaddr, (ebits + 7) / 8); 2770 2771 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2772 &me->me_epb, 0)) { 2773 err = ENOMEM; 2774 goto errout; 2775 } 2776 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2777 epb->pb_addr = htole32(me->me_E.dma_paddr); 2778 epb->pb_next = 0; 2779 epb->pb_len = htole32((ebits + 7) / 8); 2780 2781 #ifdef UBSEC_DEBUG 2782 if (ubsec_debug) { 2783 printf("Epb "); 2784 ubsec_dump_pb(epb); 2785 } 2786 #endif 2787 2788 mcr->mcr_pkts = htole16(1); 2789 mcr->mcr_flags = 0; 2790 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2791 mcr->mcr_reserved = 0; 2792 mcr->mcr_pktlen = 0; 2793 2794 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2795 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2796 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2797 2798 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2799 mcr->mcr_opktbuf.pb_next = 0; 2800 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2801 2802 #ifdef DIAGNOSTIC 2803 /* Misaligned output buffer will hang the chip. */ 2804 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2805 panic("%s: modexp invalid addr 0x%x", device_xname(sc->sc_dev), 2806 letoh32(mcr->mcr_opktbuf.pb_addr)); 2807 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2808 panic("%s: modexp invalid len 0x%x", device_xname(sc->sc_dev), 2809 letoh32(mcr->mcr_opktbuf.pb_len)); 2810 #endif 2811 2812 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2813 memset(ctx, 0, sizeof(*ctx)); 2814 memcpy(ctx->me_N, krp->krp_param[UBS_MODEXP_PAR_N].crp_p, 2815 (nbits + 7) / 8); 2816 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2817 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2818 ctx->me_E_len = htole16(ebits); 2819 ctx->me_N_len = htole16(nbits); 2820 2821 #ifdef UBSEC_DEBUG 2822 if (ubsec_debug) { 2823 ubsec_dump_mcr(mcr); 2824 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2825 } 2826 #endif 2827 2828 /* 2829 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2830 * everything else. 2831 */ 2832 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2833 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2834 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2835 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2836 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2837 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2838 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2839 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2840 2841 /* Enqueue and we're done... */ 2842 mutex_spin_enter(&sc->sc_mtx); 2843 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2844 ubsec_feed2(sc); 2845 mutex_spin_exit(&sc->sc_mtx); 2846 2847 return (0); 2848 2849 errout: 2850 if (me != NULL) { 2851 if (me->me_q.q_mcr.dma_map != NULL) 2852 ubsec_dma_free(sc, &me->me_q.q_mcr); 2853 if (me->me_q.q_ctx.dma_map != NULL) { 2854 memset(me->me_q.q_ctx.dma_vaddr, 0, 2855 me->me_q.q_ctx.dma_size); 2856 ubsec_dma_free(sc, &me->me_q.q_ctx); 2857 } 2858 if (me->me_M.dma_map != NULL) { 2859 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2860 ubsec_dma_free(sc, &me->me_M); 2861 } 2862 if (me->me_E.dma_map != NULL) { 2863 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2864 ubsec_dma_free(sc, &me->me_E); 2865 } 2866 if (me->me_C.dma_map != NULL) { 2867 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2868 ubsec_dma_free(sc, &me->me_C); 2869 } 2870 if (me->me_epb.dma_map != NULL) 2871 ubsec_dma_free(sc, &me->me_epb); 2872 free(me, M_DEVBUF); 2873 } 2874 krp->krp_status = err; 2875 crypto_kdone(krp); 2876 return (0); 2877 } 2878 2879 static int 2880 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, 2881 int hint) 2882 { 2883 struct ubsec_q2_rsapriv *rp = NULL; 2884 struct ubsec_mcr *mcr; 2885 struct ubsec_ctx_rsapriv *ctx; 2886 int err = 0; 2887 u_int padlen, msglen; 2888 2889 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2890 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2891 if (msglen > padlen) 2892 padlen = msglen; 2893 2894 if (padlen <= 256) 2895 padlen = 256; 2896 else if (padlen <= 384) 2897 padlen = 384; 2898 else if (padlen <= 512) 2899 padlen = 512; 2900 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2901 padlen = 768; 2902 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2903 padlen = 1024; 2904 else { 2905 err = E2BIG; 2906 goto errout; 2907 } 2908 2909 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2910 err = E2BIG; 2911 goto errout; 2912 } 2913 2914 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2915 err = E2BIG; 2916 goto errout; 2917 } 2918 2919 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2920 err = E2BIG; 2921 goto errout; 2922 } 2923 2924 rp = malloc(sizeof *rp, M_DEVBUF, M_NOWAIT|M_ZERO); 2925 if (rp == NULL) 2926 return (ENOMEM); 2927 rp->rpr_krp = krp; 2928 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2929 2930 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2931 &rp->rpr_q.q_mcr, 0)) { 2932 err = ENOMEM; 2933 goto errout; 2934 } 2935 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2936 2937 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2938 &rp->rpr_q.q_ctx, 0)) { 2939 err = ENOMEM; 2940 goto errout; 2941 } 2942 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2943 memset(ctx, 0, sizeof *ctx); 2944 2945 /* Copy in p */ 2946 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2947 &ctx->rpr_buf[0 * (padlen / 8)], 2948 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2949 2950 /* Copy in q */ 2951 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2952 &ctx->rpr_buf[1 * (padlen / 8)], 2953 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2954 2955 /* Copy in dp */ 2956 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2957 &ctx->rpr_buf[2 * (padlen / 8)], 2958 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2959 2960 /* Copy in dq */ 2961 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2962 &ctx->rpr_buf[3 * (padlen / 8)], 2963 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2964 2965 /* Copy in pinv */ 2966 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2967 &ctx->rpr_buf[4 * (padlen / 8)], 2968 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2969 2970 msglen = padlen * 2; 2971 2972 /* Copy in input message (aligned buffer/length). */ 2973 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2974 /* Is this likely? */ 2975 err = E2BIG; 2976 goto errout; 2977 } 2978 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2979 err = ENOMEM; 2980 goto errout; 2981 } 2982 memset(rp->rpr_msgin.dma_vaddr, 0, (msglen + 7) / 8); 2983 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2984 rp->rpr_msgin.dma_vaddr, 2985 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2986 2987 /* Prepare space for output message (aligned buffer/length). */ 2988 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2989 /* Is this likely? */ 2990 err = E2BIG; 2991 goto errout; 2992 } 2993 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2994 err = ENOMEM; 2995 goto errout; 2996 } 2997 memset(rp->rpr_msgout.dma_vaddr, 0, (msglen + 7) / 8); 2998 2999 mcr->mcr_pkts = htole16(1); 3000 mcr->mcr_flags = 0; 3001 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 3002 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 3003 mcr->mcr_ipktbuf.pb_next = 0; 3004 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 3005 mcr->mcr_reserved = 0; 3006 mcr->mcr_pktlen = htole16(msglen); 3007 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 3008 mcr->mcr_opktbuf.pb_next = 0; 3009 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 3010 3011 #ifdef DIAGNOSTIC 3012 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 3013 panic("%s: rsapriv: invalid msgin 0x%lx(0x%lx)", 3014 device_xname(sc->sc_dev), (u_long) rp->rpr_msgin.dma_paddr, 3015 (u_long) rp->rpr_msgin.dma_size); 3016 } 3017 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 3018 panic("%s: rsapriv: invalid msgout 0x%lx(0x%lx)", 3019 device_xname(sc->sc_dev), (u_long) rp->rpr_msgout.dma_paddr, 3020 (u_long) rp->rpr_msgout.dma_size); 3021 } 3022 #endif 3023 3024 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 3025 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 3026 ctx->rpr_q_len = htole16(padlen); 3027 ctx->rpr_p_len = htole16(padlen); 3028 3029 /* 3030 * ubsec_feed2 will sync mcr and ctx, we just need to sync 3031 * everything else. 3032 */ 3033 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 3034 0, rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3035 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 3036 0, rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 3037 3038 /* Enqueue and we're done... */ 3039 mutex_spin_enter(&sc->sc_mtx); 3040 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 3041 ubsec_feed2(sc); 3042 ubsecstats.hst_modexpcrt++; 3043 mutex_spin_exit(&sc->sc_mtx); 3044 return (0); 3045 3046 errout: 3047 if (rp != NULL) { 3048 if (rp->rpr_q.q_mcr.dma_map != NULL) 3049 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 3050 if (rp->rpr_msgin.dma_map != NULL) { 3051 memset(rp->rpr_msgin.dma_vaddr, 0, 3052 rp->rpr_msgin.dma_size); 3053 ubsec_dma_free(sc, &rp->rpr_msgin); 3054 } 3055 if (rp->rpr_msgout.dma_map != NULL) { 3056 memset(rp->rpr_msgout.dma_vaddr, 0, 3057 rp->rpr_msgout.dma_size); 3058 ubsec_dma_free(sc, &rp->rpr_msgout); 3059 } 3060 free(rp, M_DEVBUF); 3061 } 3062 krp->krp_status = err; 3063 crypto_kdone(krp); 3064 return (0); 3065 } 3066 3067 #ifdef UBSEC_DEBUG 3068 static void 3069 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 3070 { 3071 printf("addr 0x%x (0x%x) next 0x%x\n", 3072 pb->pb_addr, pb->pb_len, pb->pb_next); 3073 } 3074 3075 static void 3076 ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *c) 3077 { 3078 printf("CTX (0x%x):\n", c->ctx_len); 3079 switch (letoh16(c->ctx_op)) { 3080 case UBS_CTXOP_RNGBYPASS: 3081 case UBS_CTXOP_RNGSHA1: 3082 break; 3083 case UBS_CTXOP_MODEXP: 3084 { 3085 struct ubsec_ctx_modexp *cx = (void *)c; 3086 int i, len; 3087 3088 printf(" Elen %u, Nlen %u\n", 3089 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 3090 len = (cx->me_N_len + 7)/8; 3091 for (i = 0; i < len; i++) 3092 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 3093 printf("\n"); 3094 break; 3095 } 3096 default: 3097 printf("unknown context: %x\n", c->ctx_op); 3098 } 3099 printf("END CTX\n"); 3100 } 3101 3102 static void 3103 ubsec_dump_mcr(struct ubsec_mcr *mcr) 3104 { 3105 volatile struct ubsec_mcr_add *ma; 3106 int i; 3107 3108 printf("MCR:\n"); 3109 printf(" pkts: %u, flags 0x%x\n", 3110 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 3111 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 3112 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 3113 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 3114 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 3115 letoh16(ma->mcr_reserved)); 3116 printf(" %d: ipkt ", i); 3117 ubsec_dump_pb(&ma->mcr_ipktbuf); 3118 printf(" %d: opkt ", i); 3119 ubsec_dump_pb(&ma->mcr_opktbuf); 3120 ma++; 3121 } 3122 printf("END MCR\n"); 3123 } 3124 #endif /* UBSEC_DEBUG */ 3125 3126 /* 3127 * Return the number of significant bits of a big number. 3128 */ 3129 static int 3130 ubsec_ksigbits(struct crparam *cr) 3131 { 3132 u_int plen = (cr->crp_nbits + 7) / 8; 3133 int i, sig = plen * 8; 3134 u_int8_t c, *p = cr->crp_p; 3135 3136 for (i = plen - 1; i >= 0; i--) { 3137 c = p[i]; 3138 if (c != 0) { 3139 while ((c & 0x80) == 0) { 3140 sig--; 3141 c <<= 1; 3142 } 3143 break; 3144 } 3145 sig -= 8; 3146 } 3147 return (sig); 3148 } 3149 3150 static void 3151 ubsec_kshift_r(u_int shiftbits, u_int8_t *src, u_int srcbits, 3152 u_int8_t *dst, u_int dstbits) 3153 { 3154 u_int slen, dlen; 3155 int i, si, di, n; 3156 3157 slen = (srcbits + 7) / 8; 3158 dlen = (dstbits + 7) / 8; 3159 3160 for (i = 0; i < slen; i++) 3161 dst[i] = src[i]; 3162 for (i = 0; i < dlen - slen; i++) 3163 dst[slen + i] = 0; 3164 3165 n = shiftbits / 8; 3166 if (n != 0) { 3167 si = dlen - n - 1; 3168 di = dlen - 1; 3169 while (si >= 0) 3170 dst[di--] = dst[si--]; 3171 while (di >= 0) 3172 dst[di--] = 0; 3173 } 3174 3175 n = shiftbits % 8; 3176 if (n != 0) { 3177 for (i = dlen - 1; i > 0; i--) 3178 dst[i] = (dst[i] << n) | 3179 (dst[i - 1] >> (8 - n)); 3180 dst[0] = dst[0] << n; 3181 } 3182 } 3183 3184 static void 3185 ubsec_kshift_l(u_int shiftbits, u_int8_t *src, u_int srcbits, 3186 u_int8_t *dst, u_int dstbits) 3187 { 3188 int slen, dlen, i, n; 3189 3190 slen = (srcbits + 7) / 8; 3191 dlen = (dstbits + 7) / 8; 3192 3193 n = shiftbits / 8; 3194 for (i = 0; i < slen; i++) 3195 dst[i] = src[i + n]; 3196 for (i = 0; i < dlen - slen; i++) 3197 dst[slen + i] = 0; 3198 3199 n = shiftbits % 8; 3200 if (n != 0) { 3201 for (i = 0; i < (dlen - 1); i++) 3202 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 3203 dst[dlen - 1] = dst[dlen - 1] >> n; 3204 } 3205 } 3206
Indexes created Sun Sep 21 20:09:37 GMT 2025