ubsec.c revision 1.56
1 /* $NetBSD: ubsec.c,v 1.56 2022/05/22 11:35:05 riastradh Exp $ */ 2 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.6 2003/01/23 21:06:43 sam Exp $ */ 3 /* $OpenBSD: ubsec.c,v 1.143 2009/03/27 13:31:30 reyk Exp$ */ 4 5 /* 6 * Copyright (c) 2000 Jason L. Wright (jason (at) thought.net) 7 * Copyright (c) 2000 Theo de Raadt (deraadt (at) openbsd.org) 8 * Copyright (c) 2001 Patrik Lindergren (patrik (at) ipunplugged.com) 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Effort sponsored in part by the Defense Advanced Research Projects 32 * Agency (DARPA) and Air Force Research Laboratory, Air Force 33 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 34 * 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: ubsec.c,v 1.56 2022/05/22 11:35:05 riastradh Exp $"); 39 40 #undef UBSEC_DEBUG 41 42 /* 43 * uBsec 5[56]01, 58xx hardware crypto accelerator 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/proc.h> 49 #include <sys/endian.h> 50 #include <sys/errno.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/mbuf.h> 54 #include <sys/device.h> 55 #include <sys/module.h> 56 #include <sys/queue.h> 57 #include <sys/sysctl.h> 58 59 #include <opencrypto/cryptodev.h> 60 #include <opencrypto/xform.h> 61 #include <sys/cprng.h> 62 #include <sys/md5.h> 63 #include <sys/rndsource.h> 64 #include <sys/sha1.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/pci/ubsecreg.h> 71 #include <dev/pci/ubsecvar.h> 72 73 #define UBSEC_NO_RNG /* hangs on attach */ 74 #define letoh16 htole16 75 #define letoh32 htole32 76 77 /* 78 * Prototypes and count for the pci_device structure 79 */ 80 static int ubsec_probe(device_t, cfdata_t, void *); 81 static void ubsec_attach(device_t, device_t, void *); 82 static int ubsec_detach(device_t, int); 83 static void ubsec_reset_board(struct ubsec_softc *); 84 static void ubsec_init_board(struct ubsec_softc *); 85 static void ubsec_init_pciregs(struct pci_attach_args *pa); 86 static void ubsec_cleanchip(struct ubsec_softc *); 87 static void ubsec_totalreset(struct ubsec_softc *); 88 static int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); 89 90 CFATTACH_DECL_NEW(ubsec, sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach, 91 ubsec_detach, NULL); 92 extern struct cfdriver ubsec_cd; 93 94 /* patchable */ 95 #ifdef UBSEC_DEBUG 96 extern int ubsec_debug; 97 int ubsec_debug=1; 98 #endif 99 100 static int ubsec_intr(void *); 101 static int ubsec_newsession(void*, u_int32_t *, struct cryptoini *); 102 static int ubsec_freesession(void*, u_int64_t); 103 static int ubsec_process(void*, struct cryptop *, int hint); 104 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 105 static void ubsec_feed(struct ubsec_softc *); 106 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 107 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 108 static void ubsec_feed2(struct ubsec_softc *); 109 static void ubsec_feed4(struct ubsec_softc *); 110 #ifndef UBSEC_NO_RNG 111 static void ubsec_rng(void *); 112 static void ubsec_rng_locked(void *); 113 static void ubsec_rng_get(size_t, void *); 114 #endif /* UBSEC_NO_RNG */ 115 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 116 struct ubsec_dma_alloc *, int); 117 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 118 static int ubsec_dmamap_aligned(bus_dmamap_t); 119 120 static int ubsec_kprocess(void*, struct cryptkop *, int); 121 static void ubsec_kprocess_modexp_sw(struct ubsec_softc *, 122 struct cryptkop *, int); 123 static void ubsec_kprocess_modexp_hw(struct ubsec_softc *, 124 struct cryptkop *, int); 125 static void ubsec_kprocess_rsapriv(struct ubsec_softc *, 126 struct cryptkop *, int); 127 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 128 static int ubsec_ksigbits(struct crparam *); 129 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 130 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 131 132 #ifdef UBSEC_DEBUG 133 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 134 static void ubsec_dump_mcr(struct ubsec_mcr *); 135 static void ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *); 136 #endif 137 138 #define READ_REG(sc,r) \ 139 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 140 141 #define WRITE_REG(sc,reg,val) \ 142 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 143 144 #define SWAP32(x) (x) = htole32(ntohl((x))) 145 #ifndef HTOLE32 146 #define HTOLE32(x) (x) = htole32(x) 147 #endif 148 149 struct ubsec_stats ubsecstats; 150 151 /* 152 * ubsec_maxbatch controls the number of crypto ops to voluntarily 153 * collect into one submission to the hardware. This batching happens 154 * when ops are dispatched from the crypto subsystem with a hint that 155 * more are to follow immediately. These ops must also not be marked 156 * with a ``no delay'' flag. 157 */ 158 static int ubsec_maxbatch = 1; 159 160 /* 161 * ubsec_maxaggr controls the number of crypto ops to submit to the 162 * hardware as a unit. This aggregation reduces the number of interrupts 163 * to the host at the expense of increased latency (for all but the last 164 * operation). For network traffic setting this to one yields the highest 165 * performance but at the expense of more interrupt processing. 166 */ 167 static int ubsec_maxaggr = 1; 168 169 static const struct ubsec_product { 170 pci_vendor_id_t ubsec_vendor; 171 pci_product_id_t ubsec_product; 172 int ubsec_flags; 173 int ubsec_statmask; 174 int ubsec_maxaggr; 175 const char *ubsec_name; 176 } ubsec_products[] = { 177 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5501, 178 0, 179 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 180 UBS_MIN_AGGR, 181 "Bluesteel 5501" 182 }, 183 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5601, 184 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 185 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 186 UBS_MIN_AGGR, 187 "Bluesteel 5601" 188 }, 189 190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5801, 191 0, 192 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 193 UBS_MIN_AGGR, 194 "Broadcom BCM5801" 195 }, 196 197 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5802, 198 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 199 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 200 UBS_MIN_AGGR, 201 "Broadcom BCM5802" 202 }, 203 204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5805, 205 UBS_FLAGS_KEY | UBS_FLAGS_RNG, 206 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 207 UBS_MIN_AGGR, 208 "Broadcom BCM5805" 209 }, 210 211 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5820, 212 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 213 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 214 BS_STAT_MCR1_DONE | BS_STAT_DMAERR, 215 UBS_MIN_AGGR, 216 "Broadcom BCM5820" 217 }, 218 219 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5821, 220 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 221 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 222 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 223 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 224 UBS_MIN_AGGR, 225 "Broadcom BCM5821" 226 }, 227 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_SCA1K, 228 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 229 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 230 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 231 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 232 UBS_MIN_AGGR, 233 "Sun Crypto Accelerator 1000" 234 }, 235 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_5821, 236 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 237 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 238 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 239 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 240 UBS_MIN_AGGR, 241 "Broadcom BCM5821 (Sun)" 242 }, 243 244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5822, 245 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 246 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY, 247 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 248 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 249 UBS_MIN_AGGR, 250 "Broadcom BCM5822" 251 }, 252 253 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5823, 254 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 255 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 256 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 257 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 258 UBS_MIN_AGGR, 259 "Broadcom BCM5823" 260 }, 261 262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5825, 263 UBS_FLAGS_KEY | UBS_FLAGS_RNG | UBS_FLAGS_LONGCTX | 264 UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 265 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 266 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY, 267 UBS_MIN_AGGR, 268 "Broadcom BCM5825" 269 }, 270 271 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5860, 272 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 273 UBS_FLAGS_LONGCTX | 274 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 275 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 276 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 277 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 278 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 279 UBS_MAX_AGGR, 280 "Broadcom BCM5860" 281 }, 282 283 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5861, 284 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 285 UBS_FLAGS_LONGCTX | 286 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 287 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 288 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 289 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 290 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 291 UBS_MAX_AGGR, 292 "Broadcom BCM5861" 293 }, 294 295 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5862, 296 UBS_FLAGS_MULTIMCR | UBS_FLAGS_HWNORM | 297 UBS_FLAGS_LONGCTX | 298 UBS_FLAGS_RNG | UBS_FLAGS_RNG4 | 299 UBS_FLAGS_KEY | UBS_FLAGS_BIGKEY | UBS_FLAGS_AES, 300 BS_STAT_MCR1_DONE | BS_STAT_DMAERR | 301 BS_STAT_MCR1_ALLEMPTY | BS_STAT_MCR2_ALLEMPTY | 302 BS_STAT_MCR3_ALLEMPTY | BS_STAT_MCR4_ALLEMPTY, 303 UBS_MAX_AGGR, 304 "Broadcom BCM5862" 305 }, 306 307 { 0, 0, 308 0, 309 0, 310 0, 311 NULL 312 } 313 }; 314 315 static const struct ubsec_product * 316 ubsec_lookup(const struct pci_attach_args *pa) 317 { 318 const struct ubsec_product *up; 319 320 for (up = ubsec_products; up->ubsec_name != NULL; up++) { 321 if (PCI_VENDOR(pa->pa_id) == up->ubsec_vendor && 322 PCI_PRODUCT(pa->pa_id) == up->ubsec_product) 323 return (up); 324 } 325 return (NULL); 326 } 327 328 static int 329 ubsec_probe(device_t parent, cfdata_t match, void *aux) 330 { 331 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 332 333 if (ubsec_lookup(pa) != NULL) 334 return (1); 335 336 return (0); 337 } 338 339 static void 340 ubsec_attach(device_t parent, device_t self, void *aux) 341 { 342 struct ubsec_softc *sc = device_private(self); 343 struct pci_attach_args *pa = aux; 344 const struct ubsec_product *up; 345 pci_chipset_tag_t pc = pa->pa_pc; 346 pci_intr_handle_t ih; 347 const char *intrstr = NULL; 348 pcireg_t memtype; 349 struct ubsec_dma *dmap; 350 u_int32_t cmd, i; 351 char intrbuf[PCI_INTRSTR_LEN]; 352 353 sc->sc_dev = self; 354 sc->sc_pct = pc; 355 356 up = ubsec_lookup(pa); 357 if (up == NULL) { 358 printf("\n"); 359 panic("ubsec_attach: impossible"); 360 } 361 362 pci_aprint_devinfo_fancy(pa, "Crypto processor", up->ubsec_name, 1); 363 364 SIMPLEQ_INIT(&sc->sc_queue); 365 SIMPLEQ_INIT(&sc->sc_qchip); 366 SIMPLEQ_INIT(&sc->sc_queue2); 367 SIMPLEQ_INIT(&sc->sc_qchip2); 368 SIMPLEQ_INIT(&sc->sc_queue4); 369 SIMPLEQ_INIT(&sc->sc_qchip4); 370 SIMPLEQ_INIT(&sc->sc_q2free); 371 372 sc->sc_flags = up->ubsec_flags; 373 sc->sc_statmask = up->ubsec_statmask; 374 sc->sc_maxaggr = up->ubsec_maxaggr; 375 376 cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 377 cmd |= PCI_COMMAND_MASTER_ENABLE; 378 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, cmd); 379 380 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BS_BAR); 381 if (pci_mapreg_map(pa, BS_BAR, memtype, 0, 382 &sc->sc_st, &sc->sc_sh, NULL, &sc->sc_memsize)) { 383 aprint_error_dev(self, "can't find mem space"); 384 return; 385 } 386 387 sc->sc_dmat = pa->pa_dmat; 388 389 if (pci_intr_map(pa, &ih)) { 390 aprint_error_dev(self, "couldn't map interrupt\n"); 391 return; 392 } 393 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 394 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ubsec_intr, sc, 395 device_xname(self)); 396 if (sc->sc_ih == NULL) { 397 aprint_error_dev(self, "couldn't establish interrupt"); 398 if (intrstr != NULL) 399 aprint_error(" at %s", intrstr); 400 aprint_error("\n"); 401 return; 402 } 403 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 404 405 sc->sc_cid = crypto_get_driverid(0); 406 if (sc->sc_cid < 0) { 407 aprint_error_dev(self, "couldn't get crypto driver id\n"); 408 pci_intr_disestablish(pc, sc->sc_ih); 409 return; 410 } 411 412 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_VM); 413 414 SIMPLEQ_INIT(&sc->sc_freequeue); 415 dmap = sc->sc_dmaa; 416 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 417 struct ubsec_q *q; 418 419 q = malloc(sizeof(struct ubsec_q), M_DEVBUF, M_ZERO|M_WAITOK); 420 421 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 422 &dmap->d_alloc, 0)) { 423 aprint_error_dev(self, "can't allocate dma buffers\n"); 424 free(q, M_DEVBUF); 425 break; 426 } 427 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 428 429 q->q_dma = dmap; 430 sc->sc_queuea[i] = q; 431 432 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 433 } 434 435 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 436 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 437 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 438 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 439 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC_96, 0, 0, 440 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 441 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC_96, 0, 0, 442 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 443 if (sc->sc_flags & UBS_FLAGS_AES) { 444 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 445 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 446 } 447 448 /* 449 * Reset Broadcom chip 450 */ 451 ubsec_reset_board(sc); 452 453 /* 454 * Init Broadcom specific PCI settings 455 */ 456 ubsec_init_pciregs(pa); 457 458 /* 459 * Init Broadcom chip 460 */ 461 ubsec_init_board(sc); 462 463 #ifndef UBSEC_NO_RNG 464 if (sc->sc_flags & UBS_FLAGS_RNG) { 465 if (sc->sc_flags & UBS_FLAGS_RNG4) 466 sc->sc_statmask |= BS_STAT_MCR4_DONE; 467 else 468 sc->sc_statmask |= BS_STAT_MCR2_DONE; 469 470 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 471 &sc->sc_rng.rng_q.q_mcr, 0)) 472 goto skip_rng; 473 474 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 475 &sc->sc_rng.rng_q.q_ctx, 0)) { 476 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 477 goto skip_rng; 478 } 479 480 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 481 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 482 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 483 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 484 goto skip_rng; 485 } 486 if (hz >= 100) 487 sc->sc_rnghz = hz / 100; 488 else 489 sc->sc_rnghz = 1; 490 callout_init(&sc->sc_rngto, 0); 491 callout_setfunc(&sc->sc_rngto, ubsec_rng, sc); 492 rndsource_setcb(&sc->sc_rnd_source, ubsec_rng_get, sc); 493 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 494 RND_TYPE_RNG, 495 RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB); 496 497 skip_rng: 498 if (sc->sc_rnghz) 499 aprint_normal_dev(self, 500 "random number generator enabled\n"); 501 else 502 aprint_error_dev(self, 503 "WARNING: random number generator disabled\n"); 504 } 505 #endif /* UBSEC_NO_RNG */ 506 507 if (sc->sc_flags & UBS_FLAGS_KEY) { 508 sc->sc_statmask |= BS_STAT_MCR2_DONE; 509 510 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 511 ubsec_kprocess, sc); 512 #if 0 513 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 514 ubsec_kprocess, sc); 515 #endif 516 } 517 } 518 519 static int 520 ubsec_detach(device_t self, int flags) 521 { 522 struct ubsec_softc *sc = device_private(self); 523 struct ubsec_q *q, *qtmp; 524 volatile u_int32_t ctrl; 525 526 /* disable interrupts */ 527 /* XXX wait/abort current ops? where is DMAERR enabled? */ 528 ctrl = READ_REG(sc, BS_CTRL); 529 530 ctrl &= ~(BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR); 531 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) 532 ctrl &= ~BS_CTRL_MCR4INT; 533 534 WRITE_REG(sc, BS_CTRL, ctrl); 535 536 #ifndef UBSEC_NO_RNG 537 if (sc->sc_flags & UBS_FLAGS_RNG) { 538 callout_halt(&sc->sc_rngto, NULL); 539 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 540 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 541 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 542 rnd_detach_source(&sc->sc_rnd_source); 543 } 544 #endif /* UBSEC_NO_RNG */ 545 546 crypto_unregister_all(sc->sc_cid); 547 548 mutex_spin_enter(&sc->sc_mtx); 549 550 ubsec_totalreset(sc); /* XXX leaves the chip running */ 551 552 SIMPLEQ_FOREACH_SAFE(q, &sc->sc_freequeue, q_next, qtmp) { 553 ubsec_dma_free(sc, &q->q_dma->d_alloc); 554 if (q->q_src_map != NULL) 555 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 556 if (q->q_cached_dst_map != NULL) 557 bus_dmamap_destroy(sc->sc_dmat, q->q_cached_dst_map); 558 free(q, M_DEVBUF); 559 } 560 561 mutex_spin_exit(&sc->sc_mtx); 562 563 if (sc->sc_ih != NULL) { 564 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 565 sc->sc_ih = NULL; 566 } 567 568 if (sc->sc_memsize != 0) { 569 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_memsize); 570 sc->sc_memsize = 0; 571 } 572 573 return 0; 574 } 575 576 MODULE(MODULE_CLASS_DRIVER, ubsec, "pci,opencrypto"); 577 578 #ifdef _MODULE 579 #include "ioconf.c" 580 #endif 581 582 static int 583 ubsec_modcmd(modcmd_t cmd, void *data) 584 { 585 int error = 0; 586 587 switch (cmd) { 588 case MODULE_CMD_INIT: 589 #ifdef _MODULE 590 error = config_init_component(cfdriver_ioconf_ubsec, 591 cfattach_ioconf_ubsec, cfdata_ioconf_ubsec); 592 #endif 593 return error; 594 case MODULE_CMD_FINI: 595 #ifdef _MODULE 596 error = config_fini_component(cfdriver_ioconf_ubsec, 597 cfattach_ioconf_ubsec, cfdata_ioconf_ubsec); 598 #endif 599 return error; 600 default: 601 return ENOTTY; 602 } 603 } 604 605 SYSCTL_SETUP(ubsec_sysctl_init, "ubsec sysctl") 606 { 607 const struct sysctlnode *node = NULL; 608 609 sysctl_createv(clog, 0, NULL, &node, 610 CTLFLAG_PERMANENT, 611 CTLTYPE_NODE, "ubsec", 612 SYSCTL_DESCR("ubsec opetions"), 613 NULL, 0, NULL, 0, 614 CTL_HW, CTL_CREATE, CTL_EOL); 615 sysctl_createv(clog, 0, &node, NULL, 616 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 617 CTLTYPE_INT, "maxbatch", 618 SYSCTL_DESCR("max ops to batch w/o interrupt"), 619 NULL, 0, &ubsec_maxbatch, 0, 620 CTL_CREATE, CTL_EOL); 621 sysctl_createv(clog, 0, &node, NULL, 622 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 623 CTLTYPE_INT, "maxaggr", 624 SYSCTL_DESCR("max ops to aggregate under one interrupt"), 625 NULL, 0, &ubsec_maxaggr, 0, 626 CTL_CREATE, CTL_EOL); 627 628 return; 629 } 630 631 /* 632 * UBSEC Interrupt routine 633 */ 634 static int 635 ubsec_intr(void *arg) 636 { 637 struct ubsec_softc *sc = arg; 638 volatile u_int32_t stat; 639 struct ubsec_q *q; 640 struct ubsec_dma *dmap; 641 int flags; 642 int npkts = 0, i; 643 644 mutex_spin_enter(&sc->sc_mtx); 645 stat = READ_REG(sc, BS_STAT); 646 stat &= sc->sc_statmask; 647 if (stat == 0) { 648 mutex_spin_exit(&sc->sc_mtx); 649 return (0); 650 } 651 652 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 653 654 /* 655 * Check to see if we have any packets waiting for us 656 */ 657 if ((stat & BS_STAT_MCR1_DONE)) { 658 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 659 q = SIMPLEQ_FIRST(&sc->sc_qchip); 660 dmap = q->q_dma; 661 662 if ((dmap->d_dma->d_mcr.mcr_flags 663 & htole16(UBS_MCR_DONE)) == 0) 664 break; 665 666 q = SIMPLEQ_FIRST(&sc->sc_qchip); 667 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 668 669 npkts = q->q_nstacked_mcrs; 670 sc->sc_nqchip -= 1+npkts; 671 /* 672 * search for further sc_qchip ubsec_q's that share 673 * the same MCR, and complete them too, they must be 674 * at the top. 675 */ 676 for (i = 0; i < npkts; i++) { 677 if(q->q_stacked_mcr[i]) 678 ubsec_callback(sc, q->q_stacked_mcr[i]); 679 else 680 break; 681 } 682 ubsec_callback(sc, q); 683 } 684 685 /* 686 * Don't send any more packet to chip if there has been 687 * a DMAERR. 688 */ 689 if (!(stat & BS_STAT_DMAERR)) 690 ubsec_feed(sc); 691 } 692 693 /* 694 * Check to see if we have any key setups/rng's waiting for us 695 */ 696 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 697 (stat & BS_STAT_MCR2_DONE)) { 698 struct ubsec_q2 *q2; 699 struct ubsec_mcr *mcr; 700 701 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 702 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 703 704 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 705 0, q2->q_mcr.dma_map->dm_mapsize, 706 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 707 708 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 709 710 /* A bug in new devices requires to swap this field */ 711 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) 712 flags = htole16(mcr->mcr_flags); 713 else 714 flags = mcr->mcr_flags; 715 if ((flags & htole16(UBS_MCR_DONE)) == 0) { 716 bus_dmamap_sync(sc->sc_dmat, 717 q2->q_mcr.dma_map, 0, 718 q2->q_mcr.dma_map->dm_mapsize, 719 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 720 break; 721 } 722 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 723 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, /*q2,*/ q_next); 724 ubsec_callback2(sc, q2); 725 /* 726 * Don't send any more packet to chip if there has been 727 * a DMAERR. 728 */ 729 if (!(stat & BS_STAT_DMAERR)) 730 ubsec_feed2(sc); 731 } 732 } 733 if ((sc->sc_flags & UBS_FLAGS_RNG4) && (stat & BS_STAT_MCR4_DONE)) { 734 struct ubsec_q2 *q2; 735 struct ubsec_mcr *mcr; 736 737 while (!SIMPLEQ_EMPTY(&sc->sc_qchip4)) { 738 q2 = SIMPLEQ_FIRST(&sc->sc_qchip4); 739 740 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 741 0, q2->q_mcr.dma_map->dm_mapsize, 742 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 743 744 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 745 746 /* A bug in new devices requires to swap this field */ 747 flags = htole16(mcr->mcr_flags); 748 749 if ((flags & htole16(UBS_MCR_DONE)) == 0) { 750 bus_dmamap_sync(sc->sc_dmat, 751 q2->q_mcr.dma_map, 0, 752 q2->q_mcr.dma_map->dm_mapsize, 753 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 754 break; 755 } 756 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip4, q_next); 757 ubsec_callback2(sc, q2); 758 /* 759 * Don't send any more packet to chip if there has been 760 * a DMAERR. 761 */ 762 if (!(stat & BS_STAT_DMAERR)) 763 ubsec_feed4(sc); 764 } 765 } 766 767 /* 768 * Check to see if we got any DMA Error 769 */ 770 if (stat & BS_STAT_DMAERR) { 771 #ifdef UBSEC_DEBUG 772 if (ubsec_debug) { 773 volatile u_int32_t a = READ_REG(sc, BS_ERR); 774 775 printf("%s: dmaerr %s@%08x\n", device_xname(sc->sc_dev), 776 (a & BS_ERR_READ) ? "read" : "write", 777 a & BS_ERR_ADDR); 778 } 779 #endif /* UBSEC_DEBUG */ 780 ubsecstats.hst_dmaerr++; 781 ubsec_totalreset(sc); 782 ubsec_feed(sc); 783 } 784 785 if (sc->sc_needwakeup) { /* XXX check high watermark */ 786 int wkeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 787 #ifdef UBSEC_DEBUG 788 if (ubsec_debug) 789 printf("%s: wakeup crypto (%x)\n", 790 device_xname(sc->sc_dev), sc->sc_needwakeup); 791 #endif /* UBSEC_DEBUG */ 792 sc->sc_needwakeup &= ~wkeup; 793 crypto_unblock(sc->sc_cid, wkeup); 794 } 795 mutex_spin_exit(&sc->sc_mtx); 796 return (1); 797 } 798 799 /* 800 * ubsec_feed() - aggregate and post requests to chip 801 * OpenBSD comments: 802 * It is assumed that the caller set splnet() 803 */ 804 static void 805 ubsec_feed(struct ubsec_softc *sc) 806 { 807 struct ubsec_q *q, *q2; 808 int npkts, i; 809 void *v; 810 u_int32_t stat; 811 #ifdef UBSEC_DEBUG 812 static int max; 813 #endif /* UBSEC_DEBUG */ 814 815 npkts = sc->sc_nqueue; 816 if (npkts > ubsecstats.hst_maxqueue) 817 ubsecstats.hst_maxqueue = npkts; 818 if (npkts < 2) 819 goto feed1; 820 821 /* 822 * Decide how many ops to combine in a single MCR. We cannot 823 * aggregate more than UBS_MAX_AGGR because this is the number 824 * of slots defined in the data structure. Otherwise we clamp 825 * based on the tunable parameter ubsec_maxaggr. Note that 826 * aggregation can happen in two ways: either by batching ops 827 * from above or because the h/w backs up and throttles us. 828 * Aggregating ops reduces the number of interrupts to the host 829 * but also (potentially) increases the latency for processing 830 * completed ops as we only get an interrupt when all aggregated 831 * ops have completed. 832 */ 833 if (npkts > sc->sc_maxaggr) 834 npkts = sc->sc_maxaggr; 835 if (npkts > ubsec_maxaggr) 836 npkts = ubsec_maxaggr; 837 if (npkts > ubsecstats.hst_maxbatch) 838 ubsecstats.hst_maxbatch = npkts; 839 if (npkts < 2) 840 goto feed1; 841 ubsecstats.hst_totbatch += npkts-1; 842 843 if ((stat = READ_REG(sc, BS_STAT)) 844 & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 845 if (stat & BS_STAT_DMAERR) { 846 ubsec_totalreset(sc); 847 ubsecstats.hst_dmaerr++; 848 } else { 849 ubsecstats.hst_mcr1full++; 850 } 851 return; 852 } 853 854 #ifdef UBSEC_DEBUG 855 if (ubsec_debug) 856 printf("merging %d records\n", npkts); 857 /* XXX temporary aggregation statistics reporting code */ 858 if (max < npkts) { 859 max = npkts; 860 printf("%s: new max aggregate %d\n", device_xname(sc->sc_dev), 861 max); 862 } 863 #endif /* UBSEC_DEBUG */ 864 865 q = SIMPLEQ_FIRST(&sc->sc_queue); 866 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 867 --sc->sc_nqueue; 868 869 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 870 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 871 if (q->q_dst_map != NULL) 872 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 873 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 874 875 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 876 877 for (i = 0; i < q->q_nstacked_mcrs; i++) { 878 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 879 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 880 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 881 if (q2->q_dst_map != NULL) 882 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 883 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 884 q2= SIMPLEQ_FIRST(&sc->sc_queue); 885 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q2,*/ q_next); 886 --sc->sc_nqueue; 887 888 v = ((void *)&q2->q_dma->d_dma->d_mcr); 889 v = (char*)v + (sizeof(struct ubsec_mcr) - 890 sizeof(struct ubsec_mcr_add)); 891 memcpy(&q->q_dma->d_dma->d_mcradd[i], v, 892 sizeof(struct ubsec_mcr_add)); 893 q->q_stacked_mcr[i] = q2; 894 } 895 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 896 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 897 sc->sc_nqchip += npkts; 898 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 899 ubsecstats.hst_maxqchip = sc->sc_nqchip; 900 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 901 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 902 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 903 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 904 offsetof(struct ubsec_dmachunk, d_mcr)); 905 return; 906 907 feed1: 908 while (!SIMPLEQ_EMPTY(&sc->sc_queue)) { 909 if ((stat = READ_REG(sc, BS_STAT)) 910 & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 911 if (stat & BS_STAT_DMAERR) { 912 ubsec_totalreset(sc); 913 ubsecstats.hst_dmaerr++; 914 } else { 915 ubsecstats.hst_mcr1full++; 916 } 917 break; 918 } 919 920 q = SIMPLEQ_FIRST(&sc->sc_queue); 921 922 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 923 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 924 if (q->q_dst_map != NULL) 925 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 926 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); 927 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 928 0, q->q_dma->d_alloc.dma_map->dm_mapsize, 929 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 930 931 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 932 offsetof(struct ubsec_dmachunk, d_mcr)); 933 #ifdef UBSEC_DEBUG 934 if (ubsec_debug) 935 printf("feed: q->chip %p %08x stat %08x\n", 936 q, (u_int32_t)q->q_dma->d_alloc.dma_paddr, 937 stat); 938 #endif /* UBSEC_DEBUG */ 939 q = SIMPLEQ_FIRST(&sc->sc_queue); 940 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, /*q,*/ q_next); 941 --sc->sc_nqueue; 942 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 943 sc->sc_nqchip++; 944 } 945 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 946 ubsecstats.hst_maxqchip = sc->sc_nqchip; 947 } 948 949 /* 950 * Allocate a new 'session' and return an encoded session id. 'sidp' 951 * contains our registration id, and should contain an encoded session 952 * id on successful allocation. 953 */ 954 static int 955 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 956 { 957 struct cryptoini *c, *encini = NULL, *macini = NULL; 958 struct ubsec_softc *sc; 959 struct ubsec_session *ses = NULL; 960 MD5_CTX md5ctx; 961 SHA1_CTX sha1ctx; 962 int i, sesn; 963 964 sc = arg; 965 KASSERT(sc != NULL /*, ("ubsec_newsession: null softc")*/); 966 967 if (sidp == NULL || cri == NULL || sc == NULL) 968 return (EINVAL); 969 970 for (c = cri; c != NULL; c = c->cri_next) { 971 if (c->cri_alg == CRYPTO_MD5_HMAC_96 || 972 c->cri_alg == CRYPTO_SHA1_HMAC_96) { 973 if (macini) 974 return (EINVAL); 975 macini = c; 976 } else if (c->cri_alg == CRYPTO_DES_CBC || 977 c->cri_alg == CRYPTO_3DES_CBC || 978 c->cri_alg == CRYPTO_AES_CBC) { 979 if (encini) 980 return (EINVAL); 981 encini = c; 982 } else 983 return (EINVAL); 984 } 985 if (encini == NULL && macini == NULL) 986 return (EINVAL); 987 988 if (encini && encini->cri_alg == CRYPTO_AES_CBC) { 989 switch (encini->cri_klen) { 990 case 128: 991 case 192: 992 case 256: 993 break; 994 default: 995 return (EINVAL); 996 } 997 } 998 999 if (sc->sc_sessions == NULL) { 1000 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 1001 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 1002 if (ses == NULL) 1003 return (ENOMEM); 1004 sesn = 0; 1005 sc->sc_nsessions = 1; 1006 } else { 1007 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 1008 if (sc->sc_sessions[sesn].ses_used == 0) { 1009 ses = &sc->sc_sessions[sesn]; 1010 break; 1011 } 1012 } 1013 1014 if (ses == NULL) { 1015 sesn = sc->sc_nsessions; 1016 ses = (struct ubsec_session *)malloc((sesn + 1) * 1017 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 1018 if (ses == NULL) 1019 return (ENOMEM); 1020 memcpy(ses, sc->sc_sessions, sesn * 1021 sizeof(struct ubsec_session)); 1022 memset(sc->sc_sessions, 0, sesn * 1023 sizeof(struct ubsec_session)); 1024 free(sc->sc_sessions, M_DEVBUF); 1025 sc->sc_sessions = ses; 1026 ses = &sc->sc_sessions[sesn]; 1027 sc->sc_nsessions++; 1028 } 1029 } 1030 1031 memset(ses, 0, sizeof(struct ubsec_session)); 1032 ses->ses_used = 1; 1033 if (encini) { 1034 /* Go ahead and compute key in ubsec's byte order */ 1035 if (encini->cri_alg == CRYPTO_AES_CBC) { 1036 memcpy(ses->ses_key, encini->cri_key, 1037 encini->cri_klen / 8); 1038 } 1039 if (encini->cri_alg == CRYPTO_DES_CBC) { 1040 memcpy(&ses->ses_key[0], encini->cri_key, 8); 1041 memcpy(&ses->ses_key[2], encini->cri_key, 8); 1042 memcpy(&ses->ses_key[4], encini->cri_key, 8); 1043 } else 1044 memcpy(ses->ses_key, encini->cri_key, 24); 1045 1046 SWAP32(ses->ses_key[0]); 1047 SWAP32(ses->ses_key[1]); 1048 SWAP32(ses->ses_key[2]); 1049 SWAP32(ses->ses_key[3]); 1050 SWAP32(ses->ses_key[4]); 1051 SWAP32(ses->ses_key[5]); 1052 } 1053 1054 if (macini) { 1055 for (i = 0; i < macini->cri_klen / 8; i++) 1056 macini->cri_key[i] ^= HMAC_IPAD_VAL; 1057 1058 if (macini->cri_alg == CRYPTO_MD5_HMAC_96) { 1059 MD5Init(&md5ctx); 1060 MD5Update(&md5ctx, macini->cri_key, 1061 macini->cri_klen / 8); 1062 MD5Update(&md5ctx, hmac_ipad_buffer, 1063 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1064 memcpy(ses->ses_hminner, md5ctx.state, 1065 sizeof(md5ctx.state)); 1066 } else { 1067 SHA1Init(&sha1ctx); 1068 SHA1Update(&sha1ctx, macini->cri_key, 1069 macini->cri_klen / 8); 1070 SHA1Update(&sha1ctx, hmac_ipad_buffer, 1071 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1072 memcpy(ses->ses_hminner, sha1ctx.state, 1073 sizeof(sha1ctx.state)); 1074 } 1075 1076 for (i = 0; i < macini->cri_klen / 8; i++) 1077 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 1078 1079 if (macini->cri_alg == CRYPTO_MD5_HMAC_96) { 1080 MD5Init(&md5ctx); 1081 MD5Update(&md5ctx, macini->cri_key, 1082 macini->cri_klen / 8); 1083 MD5Update(&md5ctx, hmac_opad_buffer, 1084 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1085 memcpy(ses->ses_hmouter, md5ctx.state, 1086 sizeof(md5ctx.state)); 1087 } else { 1088 SHA1Init(&sha1ctx); 1089 SHA1Update(&sha1ctx, macini->cri_key, 1090 macini->cri_klen / 8); 1091 SHA1Update(&sha1ctx, hmac_opad_buffer, 1092 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1093 memcpy(ses->ses_hmouter, sha1ctx.state, 1094 sizeof(sha1ctx.state)); 1095 } 1096 1097 for (i = 0; i < macini->cri_klen / 8; i++) 1098 macini->cri_key[i] ^= HMAC_OPAD_VAL; 1099 } 1100 1101 *sidp = UBSEC_SID(device_unit(sc->sc_dev), sesn); 1102 return (0); 1103 } 1104 1105 /* 1106 * Deallocate a session. 1107 */ 1108 static int 1109 ubsec_freesession(void *arg, u_int64_t tid) 1110 { 1111 struct ubsec_softc *sc; 1112 int session; 1113 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 1114 1115 sc = arg; 1116 KASSERT(sc != NULL /*, ("ubsec_freesession: null softc")*/); 1117 1118 session = UBSEC_SESSION(sid); 1119 if (session >= sc->sc_nsessions) 1120 return (EINVAL); 1121 1122 memset(&sc->sc_sessions[session], 0, sizeof(sc->sc_sessions[session])); 1123 return (0); 1124 } 1125 1126 #ifdef __FreeBSD__ /* Ugly gratuitous changes to bus_dma */ 1127 static void 1128 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, 1129 int error) 1130 { 1131 struct ubsec_operand *op = arg; 1132 1133 KASSERT(nsegs <= UBS_MAX_SCATTER 1134 /*, ("Too many DMA segments returned when mapping operand")*/); 1135 #ifdef UBSEC_DEBUG 1136 if (ubsec_debug) 1137 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 1138 (u_int) mapsize, nsegs); 1139 #endif 1140 op->mapsize = mapsize; 1141 op->nsegs = nsegs; 1142 memcpy(op->segs, seg, nsegs * sizeof (seg[0])); 1143 } 1144 #endif 1145 1146 static int 1147 ubsec_process(void *arg, struct cryptop *crp, int hint) 1148 { 1149 struct ubsec_q *q = NULL; 1150 int err = 0, i, j, nicealign; 1151 struct ubsec_softc *sc = arg; 1152 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1153 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1154 int sskip, dskip, stheend, dtheend; 1155 int16_t coffset; 1156 struct ubsec_session *ses, key; 1157 struct ubsec_dma *dmap = NULL; 1158 u_int16_t flags = 0; 1159 int ivlen = 0, keylen = 0; 1160 1161 KASSERTMSG(UBSEC_SESSION(crp->crp_sid) < sc->sc_nsessions, 1162 "invalid session id 0x%"PRIx64", nsessions=%d", 1163 crp->crp_sid, sc->sc_nsessions); 1164 1165 mutex_spin_enter(&sc->sc_mtx); 1166 1167 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1168 ubsecstats.hst_queuefull++; 1169 sc->sc_needwakeup |= CRYPTO_SYMQ; 1170 mutex_spin_exit(&sc->sc_mtx); 1171 return(ERESTART); 1172 } 1173 1174 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1175 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, /*q,*/ q_next); 1176 mutex_spin_exit(&sc->sc_mtx); 1177 1178 dmap = q->q_dma; /* Save dma pointer */ 1179 /* don't lose the cached dmamaps q_src_map and q_cached_dst_map */ 1180 memset(q, 0, offsetof(struct ubsec_q, q_src_map)); 1181 memset(&key, 0, sizeof(key)); 1182 1183 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1184 q->q_dma = dmap; 1185 ses = &sc->sc_sessions[q->q_sesn]; 1186 1187 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1188 q->q_src_m = (struct mbuf *)crp->crp_buf; 1189 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1190 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1191 q->q_src_io = (struct uio *)crp->crp_buf; 1192 q->q_dst_io = (struct uio *)crp->crp_buf; 1193 } else { 1194 ubsecstats.hst_badflags++; 1195 err = EINVAL; 1196 goto errout; /* XXX we don't handle contiguous blocks! */ 1197 } 1198 1199 memset(&dmap->d_dma->d_mcr, 0, sizeof(struct ubsec_mcr)); 1200 1201 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1202 dmap->d_dma->d_mcr.mcr_flags = 0; 1203 q->q_crp = crp; 1204 1205 crd1 = crp->crp_desc; 1206 if (crd1 == NULL) { 1207 ubsecstats.hst_nodesc++; 1208 err = EINVAL; 1209 goto errout; 1210 } 1211 crd2 = crd1->crd_next; 1212 1213 if (crd2 == NULL) { 1214 if (crd1->crd_alg == CRYPTO_MD5_HMAC_96 || 1215 crd1->crd_alg == CRYPTO_SHA1_HMAC_96) { 1216 maccrd = crd1; 1217 enccrd = NULL; 1218 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1219 crd1->crd_alg == CRYPTO_3DES_CBC || 1220 crd1->crd_alg == CRYPTO_AES_CBC) { 1221 maccrd = NULL; 1222 enccrd = crd1; 1223 } else { 1224 ubsecstats.hst_badalg++; 1225 err = EINVAL; 1226 goto errout; 1227 } 1228 } else { 1229 if ((crd1->crd_alg == CRYPTO_MD5_HMAC_96 || 1230 crd1->crd_alg == CRYPTO_SHA1_HMAC_96) && 1231 (crd2->crd_alg == CRYPTO_DES_CBC || 1232 crd2->crd_alg == CRYPTO_3DES_CBC || 1233 crd2->crd_alg == CRYPTO_AES_CBC) && 1234 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1235 maccrd = crd1; 1236 enccrd = crd2; 1237 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1238 crd1->crd_alg == CRYPTO_3DES_CBC || 1239 crd1->crd_alg == CRYPTO_AES_CBC) && 1240 (crd2->crd_alg == CRYPTO_MD5_HMAC_96 || 1241 crd2->crd_alg == CRYPTO_SHA1_HMAC_96) && 1242 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1243 enccrd = crd1; 1244 maccrd = crd2; 1245 } else { 1246 /* 1247 * We cannot order the ubsec as requested 1248 */ 1249 ubsecstats.hst_badalg++; 1250 err = EINVAL; 1251 goto errout; 1252 } 1253 } 1254 1255 if (enccrd) { 1256 if (enccrd->crd_alg == CRYPTO_AES_CBC) { 1257 if ((sc->sc_flags & UBS_FLAGS_AES) == 0) { 1258 /* 1259 * We cannot order the ubsec as requested 1260 */ 1261 ubsecstats.hst_badalg++; 1262 err = EINVAL; 1263 goto errout; 1264 } 1265 flags |= htole16(UBS_PKTCTX_ENC_AES); 1266 switch (enccrd->crd_klen) { 1267 case 128: 1268 case 192: 1269 case 256: 1270 keylen = enccrd->crd_klen / 8; 1271 break; 1272 default: 1273 err = EINVAL; 1274 goto errout; 1275 } 1276 ivlen = 16; 1277 } else { 1278 flags |= htole16(UBS_PKTCTX_ENC_3DES); 1279 ivlen = 8; 1280 keylen = 24; 1281 } 1282 1283 encoffset = enccrd->crd_skip; 1284 1285 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1286 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1287 memcpy(key.ses_iv, enccrd->crd_iv, ivlen); 1288 else 1289 cprng_fast(key.ses_iv, ivlen); 1290 1291 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1292 if (crp->crp_flags & CRYPTO_F_IMBUF) 1293 m_copyback(q->q_src_m, 1294 enccrd->crd_inject, 1295 ivlen, (void *)key.ses_iv); 1296 else if (crp->crp_flags & CRYPTO_F_IOV) 1297 cuio_copyback(q->q_src_io, 1298 enccrd->crd_inject, 1299 ivlen, (void *)key.ses_iv); 1300 } 1301 } else { 1302 flags |= htole16(UBS_PKTCTX_INBOUND); 1303 1304 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1305 memcpy(key.ses_iv, enccrd->crd_iv, ivlen); 1306 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1307 m_copydata(q->q_src_m, enccrd->crd_inject, 1308 ivlen, (void *)key.ses_iv); 1309 else if (crp->crp_flags & CRYPTO_F_IOV) 1310 cuio_copydata(q->q_src_io, 1311 enccrd->crd_inject, 8, 1312 (void *)key.ses_iv); 1313 } 1314 1315 for (i = 0; i < (keylen / 4); i++) 1316 key.ses_key[i] = ses->ses_key[i]; 1317 for (i = 0; i < (ivlen / 4); i++) 1318 SWAP32(key.ses_iv[i]); 1319 } 1320 1321 if (maccrd) { 1322 macoffset = maccrd->crd_skip; 1323 1324 if (maccrd->crd_alg == CRYPTO_MD5_HMAC_96) 1325 flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1326 else 1327 flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1328 1329 for (i = 0; i < 5; i++) { 1330 key.ses_hminner[i] = ses->ses_hminner[i]; 1331 key.ses_hmouter[i] = ses->ses_hmouter[i]; 1332 1333 HTOLE32(key.ses_hminner[i]); 1334 HTOLE32(key.ses_hmouter[i]); 1335 } 1336 } 1337 1338 if (enccrd && maccrd) { 1339 /* 1340 * ubsec cannot handle packets where the end of encryption 1341 * and authentication are not the same, or where the 1342 * encrypted part begins before the authenticated part. 1343 */ 1344 if ((encoffset + enccrd->crd_len) != 1345 (macoffset + maccrd->crd_len)) { 1346 ubsecstats.hst_lenmismatch++; 1347 err = EINVAL; 1348 goto errout; 1349 } 1350 if (enccrd->crd_skip < maccrd->crd_skip) { 1351 ubsecstats.hst_skipmismatch++; 1352 err = EINVAL; 1353 goto errout; 1354 } 1355 sskip = maccrd->crd_skip; 1356 cpskip = dskip = enccrd->crd_skip; 1357 stheend = maccrd->crd_len; 1358 dtheend = enccrd->crd_len; 1359 coffset = enccrd->crd_skip - maccrd->crd_skip; 1360 cpoffset = cpskip + dtheend; 1361 #ifdef UBSEC_DEBUG 1362 if (ubsec_debug) { 1363 printf("mac: skip %d, len %d, inject %d\n", 1364 maccrd->crd_skip, maccrd->crd_len, 1365 maccrd->crd_inject); 1366 printf("enc: skip %d, len %d, inject %d\n", 1367 enccrd->crd_skip, enccrd->crd_len, 1368 enccrd->crd_inject); 1369 printf("src: skip %d, len %d\n", sskip, stheend); 1370 printf("dst: skip %d, len %d\n", dskip, dtheend); 1371 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1372 coffset, stheend, cpskip, cpoffset); 1373 } 1374 #endif 1375 } else { 1376 cpskip = dskip = sskip = macoffset + encoffset; 1377 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1378 cpoffset = cpskip + dtheend; 1379 coffset = 0; 1380 } 1381 1382 if (q->q_src_map == NULL) { 1383 /* XXX FIXME: jonathan asks, what the heck's that 0xfff0? */ 1384 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, 1385 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { 1386 err = ENOMEM; 1387 goto errout; 1388 } 1389 } 1390 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1391 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1392 q->q_src_m, BUS_DMA_NOWAIT) != 0) { 1393 ubsecstats.hst_noload++; 1394 err = ENOMEM; 1395 goto errout; 1396 } 1397 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1398 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1399 q->q_src_io, BUS_DMA_NOWAIT) != 0) { 1400 ubsecstats.hst_noload++; 1401 err = ENOMEM; 1402 goto errout; 1403 } 1404 } 1405 nicealign = ubsec_dmamap_aligned(q->q_src_map); 1406 1407 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1408 1409 #ifdef UBSEC_DEBUG 1410 if (ubsec_debug) 1411 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1412 #endif 1413 for (i = j = 0; i < q->q_src_map->dm_nsegs; i++) { 1414 struct ubsec_pktbuf *pb; 1415 bus_size_t packl = q->q_src_map->dm_segs[i].ds_len; 1416 bus_addr_t packp = q->q_src_map->dm_segs[i].ds_addr; 1417 1418 if (sskip >= packl) { 1419 sskip -= packl; 1420 continue; 1421 } 1422 1423 packl -= sskip; 1424 packp += sskip; 1425 sskip = 0; 1426 1427 if (packl > 0xfffc) { 1428 err = EIO; 1429 goto errout; 1430 } 1431 1432 if (j == 0) 1433 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1434 else 1435 pb = &dmap->d_dma->d_sbuf[j - 1]; 1436 1437 pb->pb_addr = htole32(packp); 1438 1439 if (stheend) { 1440 if (packl > stheend) { 1441 pb->pb_len = htole32(stheend); 1442 stheend = 0; 1443 } else { 1444 pb->pb_len = htole32(packl); 1445 stheend -= packl; 1446 } 1447 } else 1448 pb->pb_len = htole32(packl); 1449 1450 if ((i + 1) == q->q_src_map->dm_nsegs) 1451 pb->pb_next = 0; 1452 else 1453 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1454 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1455 j++; 1456 } 1457 1458 if (enccrd == NULL && maccrd != NULL) { 1459 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1460 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1461 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1462 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1463 #ifdef UBSEC_DEBUG 1464 if (ubsec_debug) 1465 printf("opkt: %x %x %x\n", 1466 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1467 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1468 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1469 1470 #endif 1471 } else { 1472 if (crp->crp_flags & CRYPTO_F_IOV) { 1473 if (!nicealign) { 1474 ubsecstats.hst_iovmisaligned++; 1475 err = EINVAL; 1476 goto errout; 1477 } 1478 if (q->q_dst_map == NULL) { 1479 if (q->q_cached_dst_map == NULL) { 1480 /* 1481 * XXX: ``what the heck's that'' 1482 * 0xfff0? 1483 */ 1484 if (bus_dmamap_create(sc->sc_dmat, 1485 0xfff0, UBS_MAX_SCATTER, 0xfff0, 0, 1486 BUS_DMA_NOWAIT, 1487 &q->q_cached_dst_map) != 0) { 1488 ubsecstats.hst_nomap++; 1489 err = ENOMEM; 1490 goto errout; 1491 } 1492 } 1493 q->q_dst_map = q->q_cached_dst_map; 1494 } 1495 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1496 q->q_dst_io, BUS_DMA_NOWAIT) != 0) { 1497 ubsecstats.hst_noload++; 1498 err = ENOMEM; 1499 goto errout; 1500 } 1501 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1502 if (nicealign) { 1503 q->q_dst_m = q->q_src_m; 1504 q->q_dst_map = q->q_src_map; 1505 } else { 1506 int totlen, len; 1507 struct mbuf *m, *top, **mp; 1508 1509 ubsecstats.hst_unaligned++; 1510 totlen = q->q_src_map->dm_mapsize; 1511 if (q->q_src_m->m_flags & M_PKTHDR) { 1512 len = MHLEN; 1513 MGETHDR(m, M_DONTWAIT, MT_DATA); 1514 /*XXX FIXME: m_dup_pkthdr */ 1515 if (m && 1 /*!m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)*/) { 1516 m_free(m); 1517 m = NULL; 1518 } 1519 } else { 1520 len = MLEN; 1521 MGET(m, M_DONTWAIT, MT_DATA); 1522 } 1523 if (m == NULL) { 1524 ubsecstats.hst_nombuf++; 1525 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1526 goto errout; 1527 } 1528 if (len == MHLEN) 1529 /*XXX was M_DUP_PKTHDR*/ 1530 m_copy_pkthdr(m, q->q_src_m); 1531 if (totlen >= MINCLSIZE) { 1532 MCLGET(m, M_DONTWAIT); 1533 if ((m->m_flags & M_EXT) == 0) { 1534 m_free(m); 1535 ubsecstats.hst_nomcl++; 1536 err = sc->sc_nqueue 1537 ? ERESTART : ENOMEM; 1538 goto errout; 1539 } 1540 len = MCLBYTES; 1541 } 1542 m->m_len = len; 1543 top = NULL; 1544 mp = ⊤ 1545 1546 while (totlen > 0) { 1547 if (top) { 1548 MGET(m, M_DONTWAIT, MT_DATA); 1549 if (m == NULL) { 1550 m_freem(top); 1551 ubsecstats.hst_nombuf++; 1552 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1553 goto errout; 1554 } 1555 len = MLEN; 1556 } 1557 if (top && totlen >= MINCLSIZE) { 1558 MCLGET(m, M_DONTWAIT); 1559 if ((m->m_flags & M_EXT) == 0) { 1560 *mp = m; 1561 m_freem(top); 1562 ubsecstats.hst_nomcl++; 1563 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1564 goto errout; 1565 } 1566 len = MCLBYTES; 1567 } 1568 m->m_len = len = uimin(totlen, len); 1569 totlen -= len; 1570 *mp = m; 1571 mp = &m->m_next; 1572 } 1573 q->q_dst_m = top; 1574 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1575 cpskip, cpoffset); 1576 if (q->q_dst_map == NULL) { 1577 if (q->q_cached_dst_map == NULL) { 1578 /* XXX again, what the heck is that 0xfff0? */ 1579 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, 1580 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, 1581 &q->q_cached_dst_map) != 0) { 1582 ubsecstats.hst_nomap++; 1583 err = ENOMEM; 1584 goto errout; 1585 } 1586 } 1587 q->q_dst_map = q->q_cached_dst_map; 1588 } 1589 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1590 q->q_dst_map, q->q_dst_m, 1591 BUS_DMA_NOWAIT) != 0) { 1592 ubsecstats.hst_noload++; 1593 err = ENOMEM; 1594 goto errout; 1595 } 1596 } 1597 } else { 1598 ubsecstats.hst_badflags++; 1599 err = EINVAL; 1600 goto errout; 1601 } 1602 1603 #ifdef UBSEC_DEBUG 1604 if (ubsec_debug) 1605 printf("dst skip: %d\n", dskip); 1606 #endif 1607 for (i = j = 0; i < q->q_dst_map->dm_nsegs; i++) { 1608 struct ubsec_pktbuf *pb; 1609 bus_size_t packl = q->q_dst_map->dm_segs[i].ds_len; 1610 bus_addr_t packp = q->q_dst_map->dm_segs[i].ds_addr; 1611 1612 if (dskip >= packl) { 1613 dskip -= packl; 1614 continue; 1615 } 1616 1617 packl -= dskip; 1618 packp += dskip; 1619 dskip = 0; 1620 1621 if (packl > 0xfffc) { 1622 err = EIO; 1623 goto errout; 1624 } 1625 1626 if (j == 0) 1627 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1628 else 1629 pb = &dmap->d_dma->d_dbuf[j - 1]; 1630 1631 pb->pb_addr = htole32(packp); 1632 1633 if (dtheend) { 1634 if (packl > dtheend) { 1635 pb->pb_len = htole32(dtheend); 1636 dtheend = 0; 1637 } else { 1638 pb->pb_len = htole32(packl); 1639 dtheend -= packl; 1640 } 1641 } else 1642 pb->pb_len = htole32(packl); 1643 1644 if ((i + 1) == q->q_dst_map->dm_nsegs) { 1645 if (maccrd) 1646 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1647 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1648 else 1649 pb->pb_next = 0; 1650 } else 1651 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1652 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1653 j++; 1654 } 1655 } 1656 1657 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1658 offsetof(struct ubsec_dmachunk, d_ctx)); 1659 1660 if (enccrd && enccrd->crd_alg == CRYPTO_AES_CBC) { 1661 struct ubsec_pktctx_aes128 *aes128; 1662 struct ubsec_pktctx_aes192 *aes192; 1663 struct ubsec_pktctx_aes256 *aes256; 1664 struct ubsec_pktctx_hdr *ph; 1665 u_int8_t *ctx; 1666 1667 ctx = (u_int8_t *)(dmap->d_alloc.dma_vaddr) + 1668 offsetof(struct ubsec_dmachunk, d_ctx); 1669 1670 ph = (struct ubsec_pktctx_hdr *)ctx; 1671 ph->ph_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES); 1672 ph->ph_flags = flags; 1673 ph->ph_offset = htole16(coffset >> 2); 1674 1675 switch (enccrd->crd_klen) { 1676 case 128: 1677 aes128 = (struct ubsec_pktctx_aes128 *)ctx; 1678 ph->ph_len = htole16(sizeof(*aes128)); 1679 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_128); 1680 for (i = 0; i < 4; i++) 1681 aes128->pc_aeskey[i] = key.ses_key[i]; 1682 for (i = 0; i < 5; i++) 1683 aes128->pc_hminner[i] = key.ses_hminner[i]; 1684 for (i = 0; i < 5; i++) 1685 aes128->pc_hmouter[i] = key.ses_hmouter[i]; 1686 for (i = 0; i < 4; i++) 1687 aes128->pc_iv[i] = key.ses_iv[i]; 1688 break; 1689 case 192: 1690 aes192 = (struct ubsec_pktctx_aes192 *)ctx; 1691 ph->ph_len = htole16(sizeof(*aes192)); 1692 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_192); 1693 for (i = 0; i < 6; i++) 1694 aes192->pc_aeskey[i] = key.ses_key[i]; 1695 for (i = 0; i < 5; i++) 1696 aes192->pc_hminner[i] = key.ses_hminner[i]; 1697 for (i = 0; i < 5; i++) 1698 aes192->pc_hmouter[i] = key.ses_hmouter[i]; 1699 for (i = 0; i < 4; i++) 1700 aes192->pc_iv[i] = key.ses_iv[i]; 1701 break; 1702 case 256: 1703 aes256 = (struct ubsec_pktctx_aes256 *)ctx; 1704 ph->ph_len = htole16(sizeof(*aes256)); 1705 ph->ph_flags |= htole16(UBS_PKTCTX_KEYSIZE_256); 1706 for (i = 0; i < 8; i++) 1707 aes256->pc_aeskey[i] = key.ses_key[i]; 1708 for (i = 0; i < 5; i++) 1709 aes256->pc_hminner[i] = key.ses_hminner[i]; 1710 for (i = 0; i < 5; i++) 1711 aes256->pc_hmouter[i] = key.ses_hmouter[i]; 1712 for (i = 0; i < 4; i++) 1713 aes256->pc_iv[i] = key.ses_iv[i]; 1714 break; 1715 } 1716 } else if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1717 struct ubsec_pktctx_3des *ctx; 1718 struct ubsec_pktctx_hdr *ph; 1719 1720 ctx = (struct ubsec_pktctx_3des *) 1721 ((u_int8_t *)(dmap->d_alloc.dma_vaddr) + 1722 offsetof(struct ubsec_dmachunk, d_ctx)); 1723 1724 ph = (struct ubsec_pktctx_hdr *)ctx; 1725 ph->ph_len = htole16(sizeof(*ctx)); 1726 ph->ph_type = htole16(UBS_PKTCTX_TYPE_IPSEC_3DES); 1727 ph->ph_flags = flags; 1728 ph->ph_offset = htole16(coffset >> 2); 1729 1730 for (i = 0; i < 6; i++) 1731 ctx->pc_deskey[i] = key.ses_key[i]; 1732 for (i = 0; i < 5; i++) 1733 ctx->pc_hminner[i] = key.ses_hminner[i]; 1734 for (i = 0; i < 5; i++) 1735 ctx->pc_hmouter[i] = key.ses_hmouter[i]; 1736 for (i = 0; i < 2; i++) 1737 ctx->pc_iv[i] = key.ses_iv[i]; 1738 } else { 1739 struct ubsec_pktctx *ctx = (struct ubsec_pktctx *) 1740 ((u_int8_t *)dmap->d_alloc.dma_vaddr + 1741 offsetof(struct ubsec_dmachunk, d_ctx)); 1742 1743 ctx->pc_flags = flags; 1744 ctx->pc_offset = htole16(coffset >> 2); 1745 for (i = 0; i < 6; i++) 1746 ctx->pc_deskey[i] = key.ses_key[i]; 1747 for (i = 0; i < 5; i++) 1748 ctx->pc_hminner[i] = key.ses_hminner[i]; 1749 for (i = 0; i < 5; i++) 1750 ctx->pc_hmouter[i] = key.ses_hmouter[i]; 1751 for (i = 0; i < 2; i++) 1752 ctx->pc_iv[i] = key.ses_iv[i]; 1753 } 1754 1755 mutex_spin_enter(&sc->sc_mtx); 1756 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1757 sc->sc_nqueue++; 1758 ubsecstats.hst_ipackets++; 1759 ubsecstats.hst_ibytes += dmap->d_alloc.dma_map->dm_mapsize; 1760 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= ubsec_maxbatch) 1761 ubsec_feed(sc); 1762 mutex_spin_exit(&sc->sc_mtx); 1763 return (0); 1764 1765 errout: 1766 if (q != NULL) { 1767 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1768 m_freem(q->q_dst_m); 1769 1770 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1771 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1772 } 1773 if (q->q_src_map != NULL) { 1774 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1775 } 1776 1777 mutex_spin_enter(&sc->sc_mtx); 1778 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1779 mutex_spin_exit(&sc->sc_mtx); 1780 } 1781 #if 0 /* jonathan says: this openbsd code seems to be subsumed elsewhere */ 1782 if (err == EINVAL) 1783 ubsecstats.hst_invalid++; 1784 else 1785 ubsecstats.hst_nomem++; 1786 #endif 1787 if (err != ERESTART) { 1788 crp->crp_etype = err; 1789 crypto_done(crp); 1790 } else { 1791 sc->sc_needwakeup |= CRYPTO_SYMQ; 1792 } 1793 return (err); 1794 } 1795 1796 static void 1797 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1798 { 1799 struct cryptop *crp = (struct cryptop *)q->q_crp; 1800 struct cryptodesc *crd; 1801 struct ubsec_dma *dmap = q->q_dma; 1802 1803 ubsecstats.hst_opackets++; 1804 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1805 1806 bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, 1807 dmap->d_alloc.dma_map->dm_mapsize, 1808 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1809 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1810 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1811 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1812 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1813 } 1814 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 1815 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1816 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1817 1818 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1819 m_freem(q->q_src_m); 1820 crp->crp_buf = (void *)q->q_dst_m; 1821 } 1822 1823 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1824 if (crd->crd_alg != CRYPTO_MD5_HMAC_96 && 1825 crd->crd_alg != CRYPTO_SHA1_HMAC_96) 1826 continue; 1827 if (crp->crp_flags & CRYPTO_F_IMBUF) 1828 m_copyback((struct mbuf *)crp->crp_buf, 1829 crd->crd_inject, 12, 1830 (void *)dmap->d_dma->d_macbuf); 1831 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1832 bcopy((void *)dmap->d_dma->d_macbuf, 1833 crp->crp_mac, 12); 1834 break; 1835 } 1836 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1837 crypto_done(crp); 1838 } 1839 1840 static void 1841 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1842 { 1843 int i, j, dlen, slen; 1844 char *dptr, *sptr; 1845 1846 j = 0; 1847 sptr = srcm->m_data; 1848 slen = srcm->m_len; 1849 dptr = dstm->m_data; 1850 dlen = dstm->m_len; 1851 1852 while (1) { 1853 for (i = 0; i < uimin(slen, dlen); i++) { 1854 if (j < hoffset || j >= toffset) 1855 *dptr++ = *sptr++; 1856 slen--; 1857 dlen--; 1858 j++; 1859 } 1860 if (slen == 0) { 1861 srcm = srcm->m_next; 1862 if (srcm == NULL) 1863 return; 1864 sptr = srcm->m_data; 1865 slen = srcm->m_len; 1866 } 1867 if (dlen == 0) { 1868 dstm = dstm->m_next; 1869 if (dstm == NULL) 1870 return; 1871 dptr = dstm->m_data; 1872 dlen = dstm->m_len; 1873 } 1874 } 1875 } 1876 1877 /* 1878 * feed the key generator, must be called at splnet() or higher. 1879 */ 1880 static void 1881 ubsec_feed2(struct ubsec_softc *sc) 1882 { 1883 struct ubsec_q2 *q; 1884 1885 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1886 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1887 break; 1888 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1889 1890 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1891 q->q_mcr.dma_map->dm_mapsize, 1892 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1893 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1894 q->q_ctx.dma_map->dm_mapsize, 1895 BUS_DMASYNC_PREWRITE); 1896 1897 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1898 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1899 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, /*q,*/ q_next); 1900 --sc->sc_nqueue2; 1901 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1902 } 1903 } 1904 1905 /* 1906 * feed the RNG (used instead of ubsec_feed2() on 5827+ devices) 1907 */ 1908 void 1909 ubsec_feed4(struct ubsec_softc *sc) 1910 { 1911 struct ubsec_q2 *q; 1912 1913 while (!SIMPLEQ_EMPTY(&sc->sc_queue4)) { 1914 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR4_FULL) 1915 break; 1916 q = SIMPLEQ_FIRST(&sc->sc_queue4); 1917 1918 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0, 1919 q->q_mcr.dma_map->dm_mapsize, 1920 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1921 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1922 q->q_ctx.dma_map->dm_mapsize, 1923 BUS_DMASYNC_PREWRITE); 1924 1925 WRITE_REG(sc, BS_MCR4, q->q_mcr.dma_paddr); 1926 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue4, q_next); 1927 --sc->sc_nqueue4; 1928 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip4, q, q_next); 1929 } 1930 } 1931 1932 /* 1933 * Callback for handling random numbers 1934 */ 1935 static void 1936 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1937 { 1938 struct cryptkop *krp; 1939 struct ubsec_ctx_keyop *ctx; 1940 1941 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1942 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0, 1943 q->q_ctx.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1944 1945 switch (q->q_type) { 1946 #ifndef UBSEC_NO_RNG 1947 case UBS_CTXOP_RNGSHA1: 1948 case UBS_CTXOP_RNGBYPASS: { 1949 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1950 u_int32_t *p; 1951 int i; 1952 1953 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 1954 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1955 p = (u_int32_t *)rng->rng_buf.dma_vaddr; 1956 i = UBSEC_RNG_BUFSIZ * sizeof(u_int32_t); 1957 rnd_add_data(&sc->sc_rnd_source, (char *)p, i, i * NBBY); 1958 sc->sc_rng_need -= i; 1959 rng->rng_used = 0; 1960 if (sc->sc_rng_need > 0) { 1961 callout_schedule(&sc->sc_rngto, sc->sc_rnghz); 1962 } 1963 break; 1964 } 1965 #endif 1966 case UBS_CTXOP_MODEXP: { 1967 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1968 u_int rlen, clen; 1969 1970 krp = me->me_krp; 1971 rlen = (me->me_modbits + 7) / 8; 1972 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1973 1974 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 1975 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1976 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 1977 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1978 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 1979 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1980 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 1981 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1982 1983 if (clen < rlen) 1984 krp->krp_status = E2BIG; 1985 else { 1986 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1987 memset(krp->krp_param[krp->krp_iparams].crp_p, 0, 1988 (krp->krp_param[krp->krp_iparams].crp_nbits 1989 + 7) / 8); 1990 bcopy(me->me_C.dma_vaddr, 1991 krp->krp_param[krp->krp_iparams].crp_p, 1992 (me->me_modbits + 7) / 8); 1993 } else 1994 ubsec_kshift_l(me->me_shiftbits, 1995 me->me_C.dma_vaddr, me->me_normbits, 1996 krp->krp_param[krp->krp_iparams].crp_p, 1997 krp->krp_param[krp->krp_iparams].crp_nbits); 1998 } 1999 2000 crypto_kdone(krp); 2001 2002 /* bzero all potentially sensitive data */ 2003 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2004 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2005 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2006 memset(me->me_q.q_ctx.dma_vaddr, 0, me->me_q.q_ctx.dma_size); 2007 2008 /* Can't free here, so put us on the free list. */ 2009 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 2010 break; 2011 } 2012 case UBS_CTXOP_RSAPRIV: { 2013 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2014 u_int len; 2015 2016 krp = rp->rpr_krp; 2017 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 0, 2018 rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2019 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 0, 2020 rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2021 2022 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) 2023 / 8; 2024 bcopy(rp->rpr_msgout.dma_vaddr, 2025 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 2026 2027 crypto_kdone(krp); 2028 2029 memset(rp->rpr_msgin.dma_vaddr, 0, rp->rpr_msgin.dma_size); 2030 memset(rp->rpr_msgout.dma_vaddr, 0, rp->rpr_msgout.dma_size); 2031 memset(rp->rpr_q.q_ctx.dma_vaddr, 0, rp->rpr_q.q_ctx.dma_size); 2032 2033 /* Can't free here, so put us on the free list. */ 2034 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 2035 break; 2036 } 2037 default: 2038 printf("%s: unknown ctx op: %x\n", device_xname(sc->sc_dev), 2039 letoh16(ctx->ctx_op)); 2040 break; 2041 } 2042 } 2043 2044 #ifndef UBSEC_NO_RNG 2045 2046 static void 2047 ubsec_rng_get(size_t bytes, void *vsc) 2048 { 2049 struct ubsec_softc *sc = vsc; 2050 2051 mutex_spin_enter(&sc->sc_mtx); 2052 sc->sc_rng_need = bytes; 2053 ubsec_rng_locked(sc); 2054 mutex_spin_exit(&sc->sc_mtx); 2055 2056 } 2057 2058 static void 2059 ubsec_rng(void *vsc) 2060 { 2061 struct ubsec_softc *sc = vsc; 2062 mutex_spin_enter(&sc->sc_mtx); 2063 ubsec_rng_locked(sc); 2064 mutex_spin_exit(&sc->sc_mtx); 2065 } 2066 2067 static void 2068 ubsec_rng_locked(void *vsc) 2069 { 2070 struct ubsec_softc *sc = vsc; 2071 struct ubsec_q2_rng *rng = &sc->sc_rng; 2072 struct ubsec_mcr *mcr; 2073 struct ubsec_ctx_rngbypass *ctx; 2074 int *nqueue; 2075 2076 /* Caller is responsible to lock and release sc_mtx. */ 2077 KASSERT(mutex_owned(&sc->sc_mtx)); 2078 2079 if (rng->rng_used) { 2080 return; 2081 } 2082 2083 if (sc->sc_rng_need < 1) { 2084 callout_stop(&sc->sc_rngto); 2085 return; 2086 } 2087 2088 if (sc->sc_flags & UBS_FLAGS_RNG4) 2089 nqueue = &sc->sc_nqueue4; 2090 else 2091 nqueue = &sc->sc_nqueue2; 2092 2093 (*nqueue)++; 2094 if (*nqueue >= UBS_MAX_NQUEUE) 2095 goto out; 2096 2097 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 2098 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 2099 2100 mcr->mcr_pkts = htole16(1); 2101 mcr->mcr_flags = 0; 2102 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 2103 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 2104 mcr->mcr_ipktbuf.pb_len = 0; 2105 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 2106 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 2107 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 2108 UBS_PKTBUF_LEN); 2109 mcr->mcr_opktbuf.pb_next = 0; 2110 2111 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 2112 ctx->rbp_op = htole16(UBS_CTXOP_RNGSHA1); 2113 rng->rng_q.q_type = UBS_CTXOP_RNGSHA1; 2114 2115 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0, 2116 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2117 2118 if (sc->sc_flags & UBS_FLAGS_RNG4) { 2119 SIMPLEQ_INSERT_TAIL(&sc->sc_queue4, &rng->rng_q, q_next); 2120 ubsec_feed4(sc); 2121 } else { 2122 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 2123 ubsec_feed2(sc); 2124 } 2125 rng->rng_used = 1; 2126 ubsecstats.hst_rng++; 2127 2128 return; 2129 2130 out: 2131 /* 2132 * Something weird happened, generate our own call back. 2133 */ 2134 (*nqueue)--; 2135 callout_schedule(&sc->sc_rngto, sc->sc_rnghz); 2136 } 2137 #endif /* UBSEC_NO_RNG */ 2138 2139 static int 2140 ubsec_dma_malloc(struct ubsec_softc *sc, bus_size_t size, 2141 struct ubsec_dma_alloc *dma,int mapflags) 2142 { 2143 int r; 2144 2145 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 2146 &dma->dma_seg, 1, &dma->dma_nseg, BUS_DMA_NOWAIT)) != 0) 2147 goto fail_0; 2148 2149 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 2150 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 2151 goto fail_1; 2152 2153 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 2154 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 2155 goto fail_2; 2156 2157 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 2158 size, NULL, BUS_DMA_NOWAIT)) != 0) 2159 goto fail_3; 2160 2161 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 2162 dma->dma_size = size; 2163 return (0); 2164 2165 fail_3: 2166 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2167 fail_2: 2168 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 2169 fail_1: 2170 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2171 fail_0: 2172 dma->dma_map = NULL; 2173 return (r); 2174 } 2175 2176 static void 2177 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 2178 { 2179 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 2180 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 2181 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2182 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2183 } 2184 2185 /* 2186 * Resets the board. Values in the regesters are left as is 2187 * from the reset (i.e. initial values are assigned elsewhere). 2188 */ 2189 static void 2190 ubsec_reset_board(struct ubsec_softc *sc) 2191 { 2192 volatile u_int32_t ctrl; 2193 2194 ctrl = READ_REG(sc, BS_CTRL); 2195 ctrl |= BS_CTRL_RESET; 2196 WRITE_REG(sc, BS_CTRL, ctrl); 2197 2198 /* 2199 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 2200 */ 2201 DELAY(10); 2202 2203 /* Enable RNG and interrupts on newer devices */ 2204 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) { 2205 #ifndef UBSEC_NO_RNG 2206 WRITE_REG(sc, BS_CFG, BS_CFG_RNG); 2207 #endif 2208 WRITE_REG(sc, BS_INT, BS_INT_DMAINT); 2209 } 2210 } 2211 2212 /* 2213 * Init Broadcom registers 2214 */ 2215 static void 2216 ubsec_init_board(struct ubsec_softc *sc) 2217 { 2218 u_int32_t ctrl; 2219 2220 ctrl = READ_REG(sc, BS_CTRL); 2221 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 2222 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 2223 2224 /* 2225 * XXX: Sam Leffler's code has (UBS_FLAGS_KEY|UBS_FLAGS_RNG)). 2226 * anyone got hw docs? 2227 */ 2228 if (sc->sc_flags & UBS_FLAGS_KEY) 2229 ctrl |= BS_CTRL_MCR2INT; 2230 else 2231 ctrl &= ~BS_CTRL_MCR2INT; 2232 2233 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2234 ctrl &= ~BS_CTRL_SWNORM; 2235 2236 if (sc->sc_flags & UBS_FLAGS_MULTIMCR) { 2237 ctrl |= BS_CTRL_BSIZE240; 2238 ctrl &= ~BS_CTRL_MCR3INT; /* MCR3 is reserved for SSL */ 2239 2240 if (sc->sc_flags & UBS_FLAGS_RNG4) 2241 ctrl |= BS_CTRL_MCR4INT; 2242 else 2243 ctrl &= ~BS_CTRL_MCR4INT; 2244 } 2245 2246 WRITE_REG(sc, BS_CTRL, ctrl); 2247 } 2248 2249 /* 2250 * Init Broadcom PCI registers 2251 */ 2252 static void 2253 ubsec_init_pciregs(struct pci_attach_args *pa) 2254 { 2255 pci_chipset_tag_t pc = pa->pa_pc; 2256 u_int32_t misc; 2257 2258 /* 2259 * This will set the cache line size to 1, this will 2260 * force the BCM58xx chip just to do burst read/writes. 2261 * Cache line read/writes are to slow 2262 */ 2263 misc = pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 2264 misc = (misc & ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)) 2265 | ((UBS_DEF_CACHELINE & 0xff) << PCI_CACHELINE_SHIFT); 2266 pci_conf_write(pc, pa->pa_tag, PCI_BHLC_REG, misc); 2267 } 2268 2269 /* 2270 * Clean up after a chip crash. 2271 * It is assumed that the caller in splnet() 2272 */ 2273 static void 2274 ubsec_cleanchip(struct ubsec_softc *sc) 2275 { 2276 struct ubsec_q *q; 2277 2278 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 2279 q = SIMPLEQ_FIRST(&sc->sc_qchip); 2280 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, /*q,*/ q_next); 2281 ubsec_free_q(sc, q); 2282 } 2283 sc->sc_nqchip = 0; 2284 } 2285 2286 /* 2287 * free a ubsec_q 2288 * It is assumed that the caller is within splnet() 2289 */ 2290 static int 2291 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2292 { 2293 struct ubsec_q *q2; 2294 struct cryptop *crp; 2295 int npkts; 2296 int i; 2297 2298 npkts = q->q_nstacked_mcrs; 2299 2300 for (i = 0; i < npkts; i++) { 2301 if(q->q_stacked_mcr[i]) { 2302 q2 = q->q_stacked_mcr[i]; 2303 2304 if ((q2->q_dst_m != NULL) 2305 && (q2->q_src_m != q2->q_dst_m)) 2306 m_freem(q2->q_dst_m); 2307 2308 crp = (struct cryptop *)q2->q_crp; 2309 2310 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2311 2312 crp->crp_etype = EFAULT; 2313 crypto_done(crp); 2314 } else { 2315 break; 2316 } 2317 } 2318 2319 /* 2320 * Free header MCR 2321 */ 2322 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2323 m_freem(q->q_dst_m); 2324 2325 crp = (struct cryptop *)q->q_crp; 2326 2327 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2328 2329 crp->crp_etype = EFAULT; 2330 crypto_done(crp); 2331 return(0); 2332 } 2333 2334 /* 2335 * Routine to reset the chip and clean up. 2336 * It is assumed that the caller is in splnet() 2337 */ 2338 static void 2339 ubsec_totalreset(struct ubsec_softc *sc) 2340 { 2341 ubsec_reset_board(sc); 2342 ubsec_init_board(sc); 2343 ubsec_cleanchip(sc); 2344 } 2345 2346 static int 2347 ubsec_dmamap_aligned(bus_dmamap_t map) 2348 { 2349 int i; 2350 2351 for (i = 0; i < map->dm_nsegs; i++) { 2352 if (map->dm_segs[i].ds_addr & 3) 2353 return (0); 2354 if ((i != (map->dm_nsegs - 1)) && 2355 (map->dm_segs[i].ds_len & 3)) 2356 return (0); 2357 } 2358 return (1); 2359 } 2360 2361 static void 2362 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2363 { 2364 switch (q->q_type) { 2365 case UBS_CTXOP_MODEXP: { 2366 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2367 2368 ubsec_dma_free(sc, &me->me_q.q_mcr); 2369 ubsec_dma_free(sc, &me->me_q.q_ctx); 2370 ubsec_dma_free(sc, &me->me_M); 2371 ubsec_dma_free(sc, &me->me_E); 2372 ubsec_dma_free(sc, &me->me_C); 2373 ubsec_dma_free(sc, &me->me_epb); 2374 free(me, M_DEVBUF); 2375 break; 2376 } 2377 case UBS_CTXOP_RSAPRIV: { 2378 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2379 2380 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2381 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2382 ubsec_dma_free(sc, &rp->rpr_msgin); 2383 ubsec_dma_free(sc, &rp->rpr_msgout); 2384 free(rp, M_DEVBUF); 2385 break; 2386 } 2387 default: 2388 printf("%s: invalid kfree 0x%x\n", device_xname(sc->sc_dev), 2389 q->q_type); 2390 break; 2391 } 2392 } 2393 2394 static int 2395 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2396 { 2397 struct ubsec_softc *sc = arg; 2398 2399 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2400 struct ubsec_q2 *q; 2401 2402 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2403 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, /*q,*/ q_next); 2404 ubsec_kfree(sc, q); 2405 } 2406 2407 switch (krp->krp_op) { 2408 case CRK_MOD_EXP: 2409 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2410 ubsec_kprocess_modexp_hw(sc, krp, hint); 2411 else 2412 ubsec_kprocess_modexp_sw(sc, krp, hint); 2413 break; 2414 case CRK_MOD_EXP_CRT: 2415 ubsec_kprocess_rsapriv(sc, krp, hint); 2416 break; 2417 default: 2418 printf("%s: kprocess: invalid op 0x%x\n", 2419 device_xname(sc->sc_dev), krp->krp_op); 2420 krp->krp_status = EOPNOTSUPP; 2421 crypto_kdone(krp); 2422 } 2423 return 0; 2424 } 2425 2426 /* 2427 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2428 */ 2429 static void 2430 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, 2431 int hint) 2432 { 2433 struct ubsec_q2_modexp *me; 2434 struct ubsec_mcr *mcr; 2435 struct ubsec_ctx_modexp *ctx; 2436 struct ubsec_pktbuf *epb; 2437 int err = 0; 2438 u_int nbits, normbits, mbits, shiftbits, ebits; 2439 2440 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2441 if (me == NULL) { 2442 err = ENOMEM; 2443 goto errout; 2444 } 2445 memset(me, 0, sizeof *me); 2446 me->me_krp = krp; 2447 me->me_q.q_type = UBS_CTXOP_MODEXP; 2448 2449 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2450 if (nbits <= 512) 2451 normbits = 512; 2452 else if (nbits <= 768) 2453 normbits = 768; 2454 else if (nbits <= 1024) 2455 normbits = 1024; 2456 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2457 normbits = 1536; 2458 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2459 normbits = 2048; 2460 else { 2461 err = E2BIG; 2462 goto errout; 2463 } 2464 2465 shiftbits = normbits - nbits; 2466 2467 me->me_modbits = nbits; 2468 me->me_shiftbits = shiftbits; 2469 me->me_normbits = normbits; 2470 2471 /* Sanity check: result bits must be >= true modulus bits. */ 2472 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2473 err = ERANGE; 2474 goto errout; 2475 } 2476 2477 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2478 &me->me_q.q_mcr, 0)) { 2479 err = ENOMEM; 2480 goto errout; 2481 } 2482 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2483 2484 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2485 &me->me_q.q_ctx, 0)) { 2486 err = ENOMEM; 2487 goto errout; 2488 } 2489 2490 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2491 if (mbits > nbits) { 2492 err = E2BIG; 2493 goto errout; 2494 } 2495 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2496 err = ENOMEM; 2497 goto errout; 2498 } 2499 ubsec_kshift_r(shiftbits, 2500 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2501 me->me_M.dma_vaddr, normbits); 2502 2503 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2504 err = ENOMEM; 2505 goto errout; 2506 } 2507 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2508 2509 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2510 if (ebits > nbits) { 2511 err = E2BIG; 2512 goto errout; 2513 } 2514 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2515 err = ENOMEM; 2516 goto errout; 2517 } 2518 ubsec_kshift_r(shiftbits, 2519 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2520 me->me_E.dma_vaddr, normbits); 2521 2522 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2523 &me->me_epb, 0)) { 2524 err = ENOMEM; 2525 goto errout; 2526 } 2527 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2528 epb->pb_addr = htole32(me->me_E.dma_paddr); 2529 epb->pb_next = 0; 2530 epb->pb_len = htole32(normbits / 8); 2531 2532 #ifdef UBSEC_DEBUG 2533 if (ubsec_debug) { 2534 printf("Epb "); 2535 ubsec_dump_pb(epb); 2536 } 2537 #endif 2538 2539 mcr->mcr_pkts = htole16(1); 2540 mcr->mcr_flags = 0; 2541 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2542 mcr->mcr_reserved = 0; 2543 mcr->mcr_pktlen = 0; 2544 2545 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2546 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2547 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2548 2549 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2550 mcr->mcr_opktbuf.pb_next = 0; 2551 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2552 2553 #ifdef DIAGNOSTIC 2554 /* Misaligned output buffer will hang the chip. */ 2555 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2556 panic("%s: modexp invalid addr 0x%x", device_xname(sc->sc_dev), 2557 letoh32(mcr->mcr_opktbuf.pb_addr)); 2558 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2559 panic("%s: modexp invalid len 0x%x", device_xname(sc->sc_dev), 2560 letoh32(mcr->mcr_opktbuf.pb_len)); 2561 #endif 2562 2563 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2564 memset(ctx, 0, sizeof(*ctx)); 2565 ubsec_kshift_r(shiftbits, 2566 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2567 ctx->me_N, normbits); 2568 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2569 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2570 ctx->me_E_len = htole16(nbits); 2571 ctx->me_N_len = htole16(nbits); 2572 2573 #ifdef UBSEC_DEBUG 2574 if (ubsec_debug) { 2575 ubsec_dump_mcr(mcr); 2576 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2577 } 2578 #endif 2579 2580 /* 2581 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2582 * everything else. 2583 */ 2584 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2585 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2586 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2587 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2588 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2589 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2590 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2591 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2592 2593 /* Enqueue and we're done... */ 2594 mutex_spin_enter(&sc->sc_mtx); 2595 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2596 ubsec_feed2(sc); 2597 ubsecstats.hst_modexp++; 2598 mutex_spin_exit(&sc->sc_mtx); 2599 2600 return; 2601 2602 errout: 2603 if (me != NULL) { 2604 if (me->me_q.q_mcr.dma_map != NULL) 2605 ubsec_dma_free(sc, &me->me_q.q_mcr); 2606 if (me->me_q.q_ctx.dma_map != NULL) { 2607 memset(me->me_q.q_ctx.dma_vaddr, 0, 2608 me->me_q.q_ctx.dma_size); 2609 ubsec_dma_free(sc, &me->me_q.q_ctx); 2610 } 2611 if (me->me_M.dma_map != NULL) { 2612 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2613 ubsec_dma_free(sc, &me->me_M); 2614 } 2615 if (me->me_E.dma_map != NULL) { 2616 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2617 ubsec_dma_free(sc, &me->me_E); 2618 } 2619 if (me->me_C.dma_map != NULL) { 2620 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2621 ubsec_dma_free(sc, &me->me_C); 2622 } 2623 if (me->me_epb.dma_map != NULL) 2624 ubsec_dma_free(sc, &me->me_epb); 2625 free(me, M_DEVBUF); 2626 } 2627 krp->krp_status = err; 2628 crypto_kdone(krp); 2629 } 2630 2631 /* 2632 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2633 */ 2634 static void 2635 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, 2636 int hint) 2637 { 2638 struct ubsec_q2_modexp *me; 2639 struct ubsec_mcr *mcr; 2640 struct ubsec_ctx_modexp *ctx; 2641 struct ubsec_pktbuf *epb; 2642 int err = 0; 2643 u_int nbits, normbits, mbits, shiftbits, ebits; 2644 2645 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2646 if (me == NULL) { 2647 err = ENOMEM; 2648 goto errout; 2649 } 2650 memset(me, 0, sizeof *me); 2651 me->me_krp = krp; 2652 me->me_q.q_type = UBS_CTXOP_MODEXP; 2653 2654 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2655 if (nbits <= 512) 2656 normbits = 512; 2657 else if (nbits <= 768) 2658 normbits = 768; 2659 else if (nbits <= 1024) 2660 normbits = 1024; 2661 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2662 normbits = 1536; 2663 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2664 normbits = 2048; 2665 else { 2666 err = E2BIG; 2667 goto errout; 2668 } 2669 2670 shiftbits = normbits - nbits; 2671 2672 /* XXX ??? */ 2673 me->me_modbits = nbits; 2674 me->me_shiftbits = shiftbits; 2675 me->me_normbits = normbits; 2676 2677 /* Sanity check: result bits must be >= true modulus bits. */ 2678 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2679 err = ERANGE; 2680 goto errout; 2681 } 2682 2683 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2684 &me->me_q.q_mcr, 0)) { 2685 err = ENOMEM; 2686 goto errout; 2687 } 2688 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2689 2690 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2691 &me->me_q.q_ctx, 0)) { 2692 err = ENOMEM; 2693 goto errout; 2694 } 2695 2696 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2697 if (mbits > nbits) { 2698 err = E2BIG; 2699 goto errout; 2700 } 2701 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2702 err = ENOMEM; 2703 goto errout; 2704 } 2705 memset(me->me_M.dma_vaddr, 0, normbits / 8); 2706 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2707 me->me_M.dma_vaddr, (mbits + 7) / 8); 2708 2709 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2710 err = ENOMEM; 2711 goto errout; 2712 } 2713 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2714 2715 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2716 if (ebits > nbits) { 2717 err = E2BIG; 2718 goto errout; 2719 } 2720 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2721 err = ENOMEM; 2722 goto errout; 2723 } 2724 memset(me->me_E.dma_vaddr, 0, normbits / 8); 2725 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2726 me->me_E.dma_vaddr, (ebits + 7) / 8); 2727 2728 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2729 &me->me_epb, 0)) { 2730 err = ENOMEM; 2731 goto errout; 2732 } 2733 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2734 epb->pb_addr = htole32(me->me_E.dma_paddr); 2735 epb->pb_next = 0; 2736 epb->pb_len = htole32((ebits + 7) / 8); 2737 2738 #ifdef UBSEC_DEBUG 2739 if (ubsec_debug) { 2740 printf("Epb "); 2741 ubsec_dump_pb(epb); 2742 } 2743 #endif 2744 2745 mcr->mcr_pkts = htole16(1); 2746 mcr->mcr_flags = 0; 2747 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2748 mcr->mcr_reserved = 0; 2749 mcr->mcr_pktlen = 0; 2750 2751 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2752 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2753 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2754 2755 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2756 mcr->mcr_opktbuf.pb_next = 0; 2757 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2758 2759 #ifdef DIAGNOSTIC 2760 /* Misaligned output buffer will hang the chip. */ 2761 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2762 panic("%s: modexp invalid addr 0x%x", device_xname(sc->sc_dev), 2763 letoh32(mcr->mcr_opktbuf.pb_addr)); 2764 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2765 panic("%s: modexp invalid len 0x%x", device_xname(sc->sc_dev), 2766 letoh32(mcr->mcr_opktbuf.pb_len)); 2767 #endif 2768 2769 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2770 memset(ctx, 0, sizeof(*ctx)); 2771 memcpy(ctx->me_N, krp->krp_param[UBS_MODEXP_PAR_N].crp_p, 2772 (nbits + 7) / 8); 2773 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2774 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2775 ctx->me_E_len = htole16(ebits); 2776 ctx->me_N_len = htole16(nbits); 2777 2778 #ifdef UBSEC_DEBUG 2779 if (ubsec_debug) { 2780 ubsec_dump_mcr(mcr); 2781 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2782 } 2783 #endif 2784 2785 /* 2786 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2787 * everything else. 2788 */ 2789 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 2790 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2791 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 2792 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2793 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 2794 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2795 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 2796 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2797 2798 /* Enqueue and we're done... */ 2799 mutex_spin_enter(&sc->sc_mtx); 2800 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2801 ubsec_feed2(sc); 2802 mutex_spin_exit(&sc->sc_mtx); 2803 2804 return; 2805 2806 errout: 2807 if (me != NULL) { 2808 if (me->me_q.q_mcr.dma_map != NULL) 2809 ubsec_dma_free(sc, &me->me_q.q_mcr); 2810 if (me->me_q.q_ctx.dma_map != NULL) { 2811 memset(me->me_q.q_ctx.dma_vaddr, 0, 2812 me->me_q.q_ctx.dma_size); 2813 ubsec_dma_free(sc, &me->me_q.q_ctx); 2814 } 2815 if (me->me_M.dma_map != NULL) { 2816 memset(me->me_M.dma_vaddr, 0, me->me_M.dma_size); 2817 ubsec_dma_free(sc, &me->me_M); 2818 } 2819 if (me->me_E.dma_map != NULL) { 2820 memset(me->me_E.dma_vaddr, 0, me->me_E.dma_size); 2821 ubsec_dma_free(sc, &me->me_E); 2822 } 2823 if (me->me_C.dma_map != NULL) { 2824 memset(me->me_C.dma_vaddr, 0, me->me_C.dma_size); 2825 ubsec_dma_free(sc, &me->me_C); 2826 } 2827 if (me->me_epb.dma_map != NULL) 2828 ubsec_dma_free(sc, &me->me_epb); 2829 free(me, M_DEVBUF); 2830 } 2831 krp->krp_status = err; 2832 crypto_kdone(krp); 2833 } 2834 2835 static void 2836 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, 2837 int hint) 2838 { 2839 struct ubsec_q2_rsapriv *rp = NULL; 2840 struct ubsec_mcr *mcr; 2841 struct ubsec_ctx_rsapriv *ctx; 2842 int err = 0; 2843 u_int padlen, msglen; 2844 2845 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2846 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2847 if (msglen > padlen) 2848 padlen = msglen; 2849 2850 if (padlen <= 256) 2851 padlen = 256; 2852 else if (padlen <= 384) 2853 padlen = 384; 2854 else if (padlen <= 512) 2855 padlen = 512; 2856 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2857 padlen = 768; 2858 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2859 padlen = 1024; 2860 else { 2861 err = E2BIG; 2862 goto errout; 2863 } 2864 2865 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2866 err = E2BIG; 2867 goto errout; 2868 } 2869 2870 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2871 err = E2BIG; 2872 goto errout; 2873 } 2874 2875 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2876 err = E2BIG; 2877 goto errout; 2878 } 2879 2880 rp = malloc(sizeof *rp, M_DEVBUF, M_NOWAIT|M_ZERO); 2881 if (rp == NULL) { 2882 err = ENOMEM; 2883 goto errout; 2884 } 2885 rp->rpr_krp = krp; 2886 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2887 2888 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2889 &rp->rpr_q.q_mcr, 0)) { 2890 err = ENOMEM; 2891 goto errout; 2892 } 2893 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2894 2895 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2896 &rp->rpr_q.q_ctx, 0)) { 2897 err = ENOMEM; 2898 goto errout; 2899 } 2900 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2901 memset(ctx, 0, sizeof *ctx); 2902 2903 /* Copy in p */ 2904 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2905 &ctx->rpr_buf[0 * (padlen / 8)], 2906 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2907 2908 /* Copy in q */ 2909 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2910 &ctx->rpr_buf[1 * (padlen / 8)], 2911 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2912 2913 /* Copy in dp */ 2914 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2915 &ctx->rpr_buf[2 * (padlen / 8)], 2916 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2917 2918 /* Copy in dq */ 2919 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2920 &ctx->rpr_buf[3 * (padlen / 8)], 2921 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2922 2923 /* Copy in pinv */ 2924 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2925 &ctx->rpr_buf[4 * (padlen / 8)], 2926 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2927 2928 msglen = padlen * 2; 2929 2930 /* Copy in input message (aligned buffer/length). */ 2931 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2932 /* Is this likely? */ 2933 err = E2BIG; 2934 goto errout; 2935 } 2936 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2937 err = ENOMEM; 2938 goto errout; 2939 } 2940 memset(rp->rpr_msgin.dma_vaddr, 0, (msglen + 7) / 8); 2941 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2942 rp->rpr_msgin.dma_vaddr, 2943 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2944 2945 /* Prepare space for output message (aligned buffer/length). */ 2946 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2947 /* Is this likely? */ 2948 err = E2BIG; 2949 goto errout; 2950 } 2951 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2952 err = ENOMEM; 2953 goto errout; 2954 } 2955 memset(rp->rpr_msgout.dma_vaddr, 0, (msglen + 7) / 8); 2956 2957 mcr->mcr_pkts = htole16(1); 2958 mcr->mcr_flags = 0; 2959 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2960 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2961 mcr->mcr_ipktbuf.pb_next = 0; 2962 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2963 mcr->mcr_reserved = 0; 2964 mcr->mcr_pktlen = htole16(msglen); 2965 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2966 mcr->mcr_opktbuf.pb_next = 0; 2967 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2968 2969 #ifdef DIAGNOSTIC 2970 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2971 panic("%s: rsapriv: invalid msgin 0x%lx(0x%lx)", 2972 device_xname(sc->sc_dev), (u_long) rp->rpr_msgin.dma_paddr, 2973 (u_long) rp->rpr_msgin.dma_size); 2974 } 2975 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2976 panic("%s: rsapriv: invalid msgout 0x%lx(0x%lx)", 2977 device_xname(sc->sc_dev), (u_long) rp->rpr_msgout.dma_paddr, 2978 (u_long) rp->rpr_msgout.dma_size); 2979 } 2980 #endif 2981 2982 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2983 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2984 ctx->rpr_q_len = htole16(padlen); 2985 ctx->rpr_p_len = htole16(padlen); 2986 2987 /* 2988 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2989 * everything else. 2990 */ 2991 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 2992 0, rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2993 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 2994 0, rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2995 2996 /* Enqueue and we're done... */ 2997 mutex_spin_enter(&sc->sc_mtx); 2998 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2999 ubsec_feed2(sc); 3000 ubsecstats.hst_modexpcrt++; 3001 mutex_spin_exit(&sc->sc_mtx); 3002 return; 3003 3004 errout: 3005 if (rp != NULL) { 3006 if (rp->rpr_q.q_mcr.dma_map != NULL) 3007 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 3008 if (rp->rpr_msgin.dma_map != NULL) { 3009 memset(rp->rpr_msgin.dma_vaddr, 0, 3010 rp->rpr_msgin.dma_size); 3011 ubsec_dma_free(sc, &rp->rpr_msgin); 3012 } 3013 if (rp->rpr_msgout.dma_map != NULL) { 3014 memset(rp->rpr_msgout.dma_vaddr, 0, 3015 rp->rpr_msgout.dma_size); 3016 ubsec_dma_free(sc, &rp->rpr_msgout); 3017 } 3018 free(rp, M_DEVBUF); 3019 } 3020 krp->krp_status = err; 3021 crypto_kdone(krp); 3022 } 3023 3024 #ifdef UBSEC_DEBUG 3025 static void 3026 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 3027 { 3028 printf("addr 0x%x (0x%x) next 0x%x\n", 3029 pb->pb_addr, pb->pb_len, pb->pb_next); 3030 } 3031 3032 static void 3033 ubsec_dump_ctx2(volatile struct ubsec_ctx_keyop *c) 3034 { 3035 printf("CTX (0x%x):\n", c->ctx_len); 3036 switch (letoh16(c->ctx_op)) { 3037 case UBS_CTXOP_RNGBYPASS: 3038 case UBS_CTXOP_RNGSHA1: 3039 break; 3040 case UBS_CTXOP_MODEXP: 3041 { 3042 struct ubsec_ctx_modexp *cx = (void *)c; 3043 int i, len; 3044 3045 printf(" Elen %u, Nlen %u\n", 3046 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 3047 len = (cx->me_N_len + 7)/8; 3048 for (i = 0; i < len; i++) 3049 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 3050 printf("\n"); 3051 break; 3052 } 3053 default: 3054 printf("unknown context: %x\n", c->ctx_op); 3055 } 3056 printf("END CTX\n"); 3057 } 3058 3059 static void 3060 ubsec_dump_mcr(struct ubsec_mcr *mcr) 3061 { 3062 volatile struct ubsec_mcr_add *ma; 3063 int i; 3064 3065 printf("MCR:\n"); 3066 printf(" pkts: %u, flags 0x%x\n", 3067 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 3068 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 3069 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 3070 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 3071 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 3072 letoh16(ma->mcr_reserved)); 3073 printf(" %d: ipkt ", i); 3074 ubsec_dump_pb(&ma->mcr_ipktbuf); 3075 printf(" %d: opkt ", i); 3076 ubsec_dump_pb(&ma->mcr_opktbuf); 3077 ma++; 3078 } 3079 printf("END MCR\n"); 3080 } 3081 #endif /* UBSEC_DEBUG */ 3082 3083 /* 3084 * Return the number of significant bits of a big number. 3085 */ 3086 static int 3087 ubsec_ksigbits(struct crparam *cr) 3088 { 3089 u_int plen = (cr->crp_nbits + 7) / 8; 3090 int i, sig = plen * 8; 3091 u_int8_t c, *p = cr->crp_p; 3092 3093 for (i = plen - 1; i >= 0; i--) { 3094 c = p[i]; 3095 if (c != 0) { 3096 while ((c & 0x80) == 0) { 3097 sig--; 3098 c <<= 1; 3099 } 3100 break; 3101 } 3102 sig -= 8; 3103 } 3104 return (sig); 3105 } 3106 3107 static void 3108 ubsec_kshift_r(u_int shiftbits, u_int8_t *src, u_int srcbits, 3109 u_int8_t *dst, u_int dstbits) 3110 { 3111 u_int slen, dlen; 3112 int i, si, di, n; 3113 3114 slen = (srcbits + 7) / 8; 3115 dlen = (dstbits + 7) / 8; 3116 3117 for (i = 0; i < slen; i++) 3118 dst[i] = src[i]; 3119 for (i = 0; i < dlen - slen; i++) 3120 dst[slen + i] = 0; 3121 3122 n = shiftbits / 8; 3123 if (n != 0) { 3124 si = dlen - n - 1; 3125 di = dlen - 1; 3126 while (si >= 0) 3127 dst[di--] = dst[si--]; 3128 while (di >= 0) 3129 dst[di--] = 0; 3130 } 3131 3132 n = shiftbits % 8; 3133 if (n != 0) { 3134 for (i = dlen - 1; i > 0; i--) 3135 dst[i] = (dst[i] << n) | 3136 (dst[i - 1] >> (8 - n)); 3137 dst[0] = dst[0] << n; 3138 } 3139 } 3140 3141 static void 3142 ubsec_kshift_l(u_int shiftbits, u_int8_t *src, u_int srcbits, 3143 u_int8_t *dst, u_int dstbits) 3144 { 3145 int slen, dlen, i, n; 3146 3147 slen = (srcbits + 7) / 8; 3148 dlen = (dstbits + 7) / 8; 3149 3150 n = shiftbits / 8; 3151 for (i = 0; i < slen; i++) 3152 dst[i] = src[i + n]; 3153 for (i = 0; i < dlen - slen; i++) 3154 dst[slen + i] = 0; 3155 3156 n = shiftbits % 8; 3157 if (n != 0) { 3158 for (i = 0; i < (dlen - 1); i++) 3159 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 3160 dst[dlen - 1] = dst[dlen - 1] >> n; 3161 } 3162 } 3163
Indexes created Tue Sep 23 02:09:52 GMT 2025