ubsecvar.h revision 1.9
1 /* $NetBSD: ubsecvar.h,v 1.9 2014/04/19 12:29:24 bad Exp $ */ 2 /* $OpenBSD: ubsecvar.h,v 1.38 2009/03/27 13:31:30 reyk Exp $ */ 3 4 /* 5 * Copyright (c) 2000 Theo de Raadt 6 * Copyright (c) 2001 Patrik Lindergren (patrik (at) ipunplugged.com) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Effort sponsored in part by the Defense Advanced Research Projects 30 * Agency (DARPA) and Air Force Research Laboratory, Air Force 31 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 32 * 33 */ 34 35 /* Maximum queue length */ 36 #ifndef UBS_MAX_NQUEUE 37 #define UBS_MAX_NQUEUE 60 38 #endif 39 40 #define UBS_MAX_SCATTER 64 /* Maximum scatter/gather depth */ 41 42 #ifndef UBS_MAX_AGGR 43 #define UBS_MAX_AGGR 17 /* Maximum aggregation count */ 44 #endif 45 46 #ifndef UBS_MIN_AGGR 47 #define UBS_MIN_AGGR 5 /* < 5827, Maximum aggregation count */ 48 #endif 49 50 #define UBSEC_CARD(sid) (((sid) & 0xf0000000) >> 28) 51 #define UBSEC_SESSION(sid) ( (sid) & 0x0fffffff) 52 #define UBSEC_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) 53 54 #define UBS_DEF_RTY 0xff /* PCI Retry Timeout */ 55 #define UBS_DEF_TOUT 0xff /* PCI TRDY Timeout */ 56 #define UBS_DEF_CACHELINE 0x01 /* Cache Line setting */ 57 58 struct ubsec_dma_alloc { 59 u_int32_t dma_paddr; 60 void * dma_vaddr; 61 bus_dmamap_t dma_map; 62 bus_dma_segment_t dma_seg; 63 bus_size_t dma_size; 64 int dma_nseg; 65 }; 66 67 struct ubsec_q2 { 68 SIMPLEQ_ENTRY(ubsec_q2) q_next; 69 struct ubsec_dma_alloc q_mcr; 70 struct ubsec_dma_alloc q_ctx; 71 u_int q_type; 72 }; 73 74 struct ubsec_q2_rng { 75 struct ubsec_q2 rng_q; 76 struct ubsec_dma_alloc rng_buf; 77 int rng_used; 78 }; 79 80 /* C = (M ^ E) mod N */ 81 #define UBS_MODEXP_PAR_M 0 82 #define UBS_MODEXP_PAR_E 1 83 #define UBS_MODEXP_PAR_N 2 84 struct ubsec_q2_modexp { 85 struct ubsec_q2 me_q; 86 struct cryptkop * me_krp; 87 struct ubsec_dma_alloc me_M; 88 struct ubsec_dma_alloc me_E; 89 struct ubsec_dma_alloc me_C; 90 struct ubsec_dma_alloc me_epb; 91 int me_modbits; 92 int me_shiftbits; 93 int me_normbits; 94 }; 95 96 #define UBS_RSAPRIV_PAR_P 0 97 #define UBS_RSAPRIV_PAR_Q 1 98 #define UBS_RSAPRIV_PAR_DP 2 99 #define UBS_RSAPRIV_PAR_DQ 3 100 #define UBS_RSAPRIV_PAR_PINV 4 101 #define UBS_RSAPRIV_PAR_MSGIN 5 102 #define UBS_RSAPRIV_PAR_MSGOUT 6 103 struct ubsec_q2_rsapriv { 104 struct ubsec_q2 rpr_q; 105 struct cryptkop * rpr_krp; 106 struct ubsec_dma_alloc rpr_msgin; 107 struct ubsec_dma_alloc rpr_msgout; 108 }; 109 110 #define UBSEC_RNG_BUFSIZ 16 /* measured in 32bit words */ 111 112 struct ubsec_dmachunk { 113 struct ubsec_mcr d_mcr; 114 struct ubsec_mcr_add d_mcradd[UBS_MAX_AGGR-1]; 115 struct ubsec_pktbuf d_sbuf[UBS_MAX_SCATTER-1]; 116 struct ubsec_pktbuf d_dbuf[UBS_MAX_SCATTER-1]; 117 u_int32_t d_macbuf[5]; 118 union { 119 struct ubsec_pktctx_aes256 ctx_aes256; 120 struct ubsec_pktctx_aes192 ctx_aes192; 121 struct ubsec_pktctx_aes128 ctx_aes128; 122 struct ubsec_pktctx_3des ctx_3des; 123 struct ubsec_pktctx ctx; 124 } d_ctx; 125 }; 126 127 struct ubsec_dma { 128 SIMPLEQ_ENTRY(ubsec_dma) d_next; 129 struct ubsec_dmachunk *d_dma; 130 struct ubsec_dma_alloc d_alloc; 131 }; 132 133 #define UBS_FLAGS_KEY 0x01 /* has key accelerator */ 134 #define UBS_FLAGS_LONGCTX 0x02 /* uses long ipsec ctx */ 135 #define UBS_FLAGS_BIGKEY 0x04 /* 2048bit keys */ 136 #define UBS_FLAGS_HWNORM 0x08 /* hardware normalization */ 137 #define UBS_FLAGS_RNG 0x10 /* hardware rng */ 138 #define UBS_FLAGS_AES 0x20 /* supports AES */ 139 #define UBS_FLAGS_MULTIMCR 0x40 /* 5827+ with 4 MCRs */ 140 #define UBS_FLAGS_RNG4 0x80 /* 5827+ RNG on MCR4 */ 141 142 struct ubsec_q { 143 SIMPLEQ_ENTRY(ubsec_q) q_next; 144 int q_nstacked_mcrs; 145 struct ubsec_q *q_stacked_mcr[UBS_MAX_AGGR-1]; 146 struct cryptop *q_crp; 147 struct ubsec_dma *q_dma; 148 149 struct mbuf *q_src_m, *q_dst_m; 150 struct uio *q_src_io, *q_dst_io; 151 152 int q_sesn; 153 int q_flags; 154 155 bus_dmamap_t q_dst_map; 156 bus_dmamap_t q_src_map; /* cached src_map */ 157 bus_dmamap_t q_cached_dst_map; /* cached dst_map */ 158 }; 159 160 struct ubsec_softc { 161 device_t sc_dev; /* generic device */ 162 void *sc_ih; /* interrupt handler cookie */ 163 kmutex_t sc_mtx; 164 pci_chipset_tag_t sc_pct; /* pci chipset tag */ 165 bus_space_handle_t sc_sh; /* memory handle */ 166 bus_space_tag_t sc_st; /* memory tag */ 167 bus_dma_tag_t sc_dmat; /* dma tag */ 168 int sc_flags; /* device specific flags */ 169 int sc_suspended; 170 int sc_needwakeup; /* notify crypto layer */ 171 u_int32_t sc_statmask; /* interrupt status mask */ 172 int32_t sc_cid; /* crypto tag */ 173 int sc_maxaggr; /* max pkt aggregation */ 174 SIMPLEQ_HEAD(,ubsec_q) sc_queue; /* packet queue, mcr1 */ 175 int sc_nqueue; /* count enqueued, mcr1 */ 176 SIMPLEQ_HEAD(,ubsec_q) sc_qchip; /* on chip, mcr1 */ 177 int sc_nqchip; /* count on chip, mcr1 */ 178 SIMPLEQ_HEAD(,ubsec_q) sc_freequeue; /* list of free queue elements */ 179 SIMPLEQ_HEAD(,ubsec_q2) sc_queue2; /* packet queue, mcr2 */ 180 int sc_nqueue2; /* count enqueued, mcr2 */ 181 SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2; /* on chip, mcr2 */ 182 SIMPLEQ_HEAD(,ubsec_q2) sc_queue4; /* packet queue, mcr4 */ 183 int sc_nqueue4; /* count enqueued, mcr4 */ 184 SIMPLEQ_HEAD(,ubsec_q2) sc_qchip4; /* on chip, mcr4 */ 185 int sc_nsessions; /* # of sessions */ 186 struct ubsec_session *sc_sessions; /* sessions */ 187 struct callout sc_rngto; /* rng timeout */ 188 int sc_rnghz; /* rng poll time */ 189 struct ubsec_q2_rng sc_rng; 190 krndsource_t sc_rnd_source; 191 int sc_rng_need; /* how many bytes wanted */ 192 struct ubsec_dma sc_dmaa[UBS_MAX_NQUEUE]; 193 struct ubsec_q *sc_queuea[UBS_MAX_NQUEUE]; 194 SIMPLEQ_HEAD(,ubsec_q2) sc_q2free; /* free list */ 195 bus_size_t sc_memsize; /* size mapped by sc_sh */ 196 }; 197 198 #define UBSEC_QFLAGS_COPYOUTIV 0x1 199 200 struct ubsec_session { 201 u_int32_t ses_used; 202 u_int32_t ses_key[8]; /* 3DES/AES key */ 203 u_int32_t ses_hminner[5]; /* hmac inner state */ 204 u_int32_t ses_hmouter[5]; /* hmac outer state */ 205 u_int32_t ses_iv[4]; /* [3]DES iv or AES iv/icv */ 206 }; 207 208 struct ubsec_stats { 209 u_int64_t hst_ibytes; 210 u_int64_t hst_obytes; 211 u_int32_t hst_ipackets; 212 u_int32_t hst_opackets; 213 u_int32_t hst_invalid; /* invalid argument */ 214 u_int32_t hst_badsession; /* invalid session id */ 215 u_int32_t hst_badflags; /* flags indicate !(mbuf | uio) */ 216 u_int32_t hst_nodesc; /* op submitted w/o descriptors */ 217 u_int32_t hst_badalg; /* unsupported algorithm */ 218 219 u_int32_t hst_nomem; 220 u_int32_t hst_queuefull; 221 u_int32_t hst_dmaerr; 222 u_int32_t hst_mcrerr; 223 u_int32_t hst_nodmafree; 224 225 u_int32_t hst_lenmismatch; /* enc/auth lengths different */ 226 u_int32_t hst_skipmismatch; /* enc part begins before auth part */ 227 u_int32_t hst_iovmisaligned; /* iov op not aligned */ 228 u_int32_t hst_noirq; /* IRQ for no reason */ 229 u_int32_t hst_unaligned; /* unaligned src caused copy */ 230 u_int32_t hst_nomap; /* bus_dmamap_create failed */ 231 u_int32_t hst_noload; /* bus_dmamap_load_* failed */ 232 u_int32_t hst_nombuf; /* MGET* failed */ 233 u_int32_t hst_nomcl; /* MCLGET* failed */ 234 u_int32_t hst_totbatch; /* ops submitted w/o interrupt */ 235 u_int32_t hst_maxbatch; /* max ops submitted together */ 236 u_int32_t hst_maxqueue; /* max ops queued for submission */ 237 u_int32_t hst_maxqchip; /* max mcr1 ops out for processing */ 238 u_int32_t hst_mcr1full; /* MCR1 too busy to take ops */ 239 u_int32_t hst_rng; /* RNG requests */ 240 u_int32_t hst_modexp; /* MOD EXP requests */ 241 u_int32_t hst_modexpcrt; /* MOD EXP CRT requests */ 242 }; 243
Indexes created Mon Sep 22 13:09:51 GMT 2025