uhci_pci.c revision 1.62
1/* $NetBSD: uhci_pci.c,v 1.62 2018/04/09 16:21:10 jakllsch Exp $ */ 2 3/* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net) at 9 * Carlstedt Research & Technology. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__KERNEL_RCSID(0, "$NetBSD: uhci_pci.c,v 1.62 2018/04/09 16:21:10 jakllsch Exp $"); 35 36#include "ehci.h" 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/kernel.h> 41#include <sys/device.h> 42#include <sys/proc.h> 43#include <sys/queue.h> 44 45#include <sys/bus.h> 46 47#include <dev/pci/pcivar.h> 48#include <dev/pci/usb_pci.h> 49 50#include <dev/usb/usb.h> 51#include <dev/usb/usbdi.h> 52#include <dev/usb/usbdivar.h> 53#include <dev/usb/usb_mem.h> 54 55#include <dev/usb/uhcireg.h> 56#include <dev/usb/uhcivar.h> 57 58static bool uhci_pci_resume(device_t, const pmf_qual_t *); 59 60struct uhci_pci_softc { 61 uhci_softc_t sc; 62#if NEHCI > 0 63 struct usb_pci sc_pci; 64#endif 65 pci_chipset_tag_t sc_pc; 66 pcitag_t sc_tag; 67 void *sc_ih; /* interrupt vectoring */ 68 unsigned sc_initialized; 69#define SC_INIT_UHCI 1 70#define SC_INIT_PMF 2 71}; 72 73static int 74uhci_pci_match(device_t parent, cfdata_t match, void *aux) 75{ 76 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 77 78 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 79 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 80 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_UHCI) 81 return 1; 82 83 return 0; 84} 85 86static void 87uhci_pci_attach(device_t parent, device_t self, void *aux) 88{ 89 struct uhci_pci_softc *sc = device_private(self); 90 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 91 pci_chipset_tag_t pc = pa->pa_pc; 92 pcitag_t tag = pa->pa_tag; 93 char const *intrstr; 94 pci_intr_handle_t ih; 95 pcireg_t csr; 96 int s; 97 char intrbuf[PCI_INTRSTR_LEN]; 98 99 sc->sc.sc_dev = self; 100 sc->sc.sc_bus.ub_hcpriv = sc; 101 102 pci_aprint_devinfo(pa, NULL); 103 104 /* Map I/O registers */ 105 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 106 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 107 aprint_error_dev(self, "can't map i/o space\n"); 108 return; 109 } 110 111 /* 112 * Disable interrupts, so we don't get any spurious ones. 113 * Acknowledge all pending interrupts. 114 */ 115 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); 116 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_STS, 117 bus_space_read_2(sc->sc.iot, sc->sc.ioh, UHCI_STS)); 118 119 sc->sc_pc = pc; 120 sc->sc_tag = tag; 121 sc->sc.sc_bus.ub_dmatag = pa->pa_dmat; 122 123 /* Enable the device. */ 124 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 125 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 126 csr | PCI_COMMAND_MASTER_ENABLE); 127 128 /* Map and establish the interrupt. */ 129 if (pci_intr_map(pa, &ih)) { 130 aprint_error_dev(self, "couldn't map interrupt\n"); 131 return; 132 } 133 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 134 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_USB, uhci_intr, sc, 135 device_xname(self)); 136 if (sc->sc_ih == NULL) { 137 aprint_error_dev(self, "couldn't establish interrupt"); 138 if (intrstr != NULL) 139 aprint_error(" at %s", intrstr); 140 aprint_error("\n"); 141 return; 142 } 143 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 144 145 /* 146 * Set LEGSUP register to its default value. 147 * This can re-enable or trigger interrupts, so protect against 148 * them and explicitly disable and ACK them afterwards. 149 */ 150 s = splhardusb(); 151 pci_conf_write(pc, tag, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN); 152 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); 153 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_STS, 154 bus_space_read_2(sc->sc.iot, sc->sc.ioh, UHCI_STS)); 155 splx(s); 156 157 switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 158 case PCI_USBREV_PRE_1_0: 159 sc->sc.sc_bus.ub_revision = USBREV_PRE_1_0; 160 break; 161 case PCI_USBREV_1_0: 162 sc->sc.sc_bus.ub_revision = USBREV_1_0; 163 break; 164 case PCI_USBREV_1_1: 165 sc->sc.sc_bus.ub_revision = USBREV_1_1; 166 break; 167 default: 168 sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN; 169 break; 170 } 171 172 int err = uhci_init(&sc->sc); 173 if (err) { 174 aprint_error_dev(self, "init failed, error=%d\n", err); 175 return; 176 } 177 sc->sc_initialized = SC_INIT_UHCI; 178 179#if NEHCI > 0 180 usb_pci_add(&sc->sc_pci, pa, self); 181#endif 182 183 if (!pmf_device_register(self, uhci_suspend, uhci_pci_resume)) 184 aprint_error_dev(self, "couldn't establish power handler\n"); 185 else 186 sc->sc_initialized |= SC_INIT_PMF; 187 188 /* Attach usb device. */ 189 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 190} 191 192static int 193uhci_pci_detach(device_t self, int flags) 194{ 195 struct uhci_pci_softc *sc = device_private(self); 196 int rv; 197 198 if (sc->sc_initialized & SC_INIT_UHCI) { 199 rv = uhci_detach(&sc->sc, flags); 200 if (rv) 201 return rv; 202 } 203 204 if (sc->sc_initialized & SC_INIT_PMF) 205 pmf_device_deregister(self); 206 207 /* disable interrupts and acknowledge any pending */ 208 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); 209 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_STS, 210 bus_space_read_2(sc->sc.iot, sc->sc.ioh, UHCI_STS)); 211 212 if (sc->sc_ih != NULL) { 213 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 214 sc->sc_ih = NULL; 215 } 216 if (sc->sc.sc_size) { 217 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 218 sc->sc.sc_size = 0; 219 } 220#if NEHCI > 0 221 usb_pci_rem(&sc->sc_pci); 222#endif 223 return 0; 224} 225 226static bool 227uhci_pci_resume(device_t dv, const pmf_qual_t *qual) 228{ 229 struct uhci_pci_softc *sc = device_private(dv); 230 231 /* Set LEGSUP register to its default value. */ 232 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_LEGSUP, 233 PCI_LEGSUP_USBPIRQDEN); 234 235 return uhci_resume(dv, qual); 236} 237 238CFATTACH_DECL3_NEW(uhci_pci, sizeof(struct uhci_pci_softc), 239 uhci_pci_match, uhci_pci_attach, uhci_pci_detach, uhci_activate, 240 NULL, uhci_childdet, DVF_DETACH_SHUTDOWN); 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