unichromeconfig.h revision 1.2.4.2
1 1.2.4.2 rpaulo /* $NetBSD: unichromeconfig.h,v 1.2.4.2 2006/09/09 02:52:19 rpaulo Exp $ */ 2 1.2.4.2 rpaulo 3 1.2.4.2 rpaulo /* 4 1.2.4.2 rpaulo * Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved. 5 1.2.4.2 rpaulo * Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved. 6 1.2.4.2 rpaulo * 7 1.2.4.2 rpaulo * Permission is hereby granted, free of charge, to any person obtaining a 8 1.2.4.2 rpaulo * copy of this software and associated documentation files (the "Software"), 9 1.2.4.2 rpaulo * to deal in the Software without restriction, including without limitation 10 1.2.4.2 rpaulo * the rights to use, copy, modify, merge, publish, distribute, sub license, 11 1.2.4.2 rpaulo * and/or sell copies of the Software, and to permit persons to whom the 12 1.2.4.2 rpaulo * Software is furnished to do so, subject to the following conditions: 13 1.2.4.2 rpaulo * 14 1.2.4.2 rpaulo * The above copyright notice and this permission notice (including the 15 1.2.4.2 rpaulo * next paragraph) shall be included in all copies or substantial portions 16 1.2.4.2 rpaulo * of the Software. 17 1.2.4.2 rpaulo * 18 1.2.4.2 rpaulo * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 1.2.4.2 rpaulo * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 1.2.4.2 rpaulo * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 1.2.4.2 rpaulo * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 1.2.4.2 rpaulo * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 1.2.4.2 rpaulo * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 1.2.4.2 rpaulo * DEALINGS IN THE SOFTWARE. 25 1.2.4.2 rpaulo */ 26 1.2.4.2 rpaulo 27 1.2.4.2 rpaulo #ifndef _DEV_PCI_UNICHROMECONFIG_H 28 1.2.4.2 rpaulo #define _DEV_PCI_UNICHROMECONFIG_H 29 1.2.4.2 rpaulo 30 1.2.4.2 rpaulo static struct pll_map pll_value[] = { 31 1.2.4.2 rpaulo {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M, CX700_25_175M}, 32 1.2.4.2 rpaulo {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M, CX700_29_581M}, 33 1.2.4.2 rpaulo {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M, CX700_26_880M}, 34 1.2.4.2 rpaulo {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M, CX700_31_490M}, 35 1.2.4.2 rpaulo {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M, CX700_31_500M}, 36 1.2.4.2 rpaulo {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M, CX700_31_728M}, 37 1.2.4.2 rpaulo {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M, CX700_32_668M}, 38 1.2.4.2 rpaulo {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M, CX700_36_000M}, 39 1.2.4.2 rpaulo {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M, CX700_40_000M}, 40 1.2.4.2 rpaulo {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M, CX700_41_291M}, 41 1.2.4.2 rpaulo {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M, CX700_43_163M}, 42 1.2.4.2 rpaulo {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M, CX700_49_500M}, 43 1.2.4.2 rpaulo {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M, CX700_52_406M}, 44 1.2.4.2 rpaulo {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M, CX700_56_250M}, 45 1.2.4.2 rpaulo {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M, CX700_65_000M}, 46 1.2.4.2 rpaulo {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M, CX700_68_179M}, 47 1.2.4.2 rpaulo {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M, CX700_78_750M}, 48 1.2.4.2 rpaulo {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M, CX700_80_136M}, 49 1.2.4.2 rpaulo {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M, CX700_83_950M}, 50 1.2.4.2 rpaulo {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M, CX700_85_860M}, 51 1.2.4.2 rpaulo {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M, CX700_94_500M}, 52 1.2.4.2 rpaulo {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M, CX700_108_000M}, 53 1.2.4.2 rpaulo {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M, CX700_125_104M}, 54 1.2.4.2 rpaulo {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M, CX700_133_308M}, 55 1.2.4.2 rpaulo {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M, CX700_135_000M}, 56 1.2.4.2 rpaulo {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M, CX700_157_500M}, 57 1.2.4.2 rpaulo {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M, CX700_162_000M}, 58 1.2.4.2 rpaulo {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M, CX700_202_500M}, 59 1.2.4.2 rpaulo {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M, CX700_234_000M}, 60 1.2.4.2 rpaulo {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M, CX700_297_500M}, 61 1.2.4.2 rpaulo {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M, CX700_74_481M}, 62 1.2.4.2 rpaulo {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M, CX700_172_798M} 63 1.2.4.2 rpaulo }; 64 1.2.4.2 rpaulo 65 1.2.4.2 rpaulo #define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value) 66 1.2.4.2 rpaulo 67 1.2.4.2 rpaulo static struct fifo_depth_select display_fifo_depth_reg= { 68 1.2.4.2 rpaulo // IGA1 FIFO Depth_Select 69 1.2.4.2 rpaulo {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17,0,7}}}, 70 1.2.4.2 rpaulo // IGA2 FIFO Depth_Select 71 1.2.4.2 rpaulo {IGA2_FIFO_DEPTH_SELECT_REG_NUM, {{CR68,4,7}, {CR94,7,7}, {CR95,7,7}}} 72 1.2.4.2 rpaulo }; 73 1.2.4.2 rpaulo 74 1.2.4.2 rpaulo static struct fifo_threshold_select fifo_threshold_select_reg= { 75 1.2.4.2 rpaulo // IGA1 FIFO Threshold Select 76 1.2.4.2 rpaulo {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16,0,5},{SR16,7,7}}}, 77 1.2.4.2 rpaulo // IGA2 FIFO Threshold Select 78 1.2.4.2 rpaulo {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68,0,3}, {CR95,4,6}}} 79 1.2.4.2 rpaulo }; 80 1.2.4.2 rpaulo 81 1.2.4.2 rpaulo static struct fifo_high_threshold_select fifo_high_threshold_select_reg= { 82 1.2.4.2 rpaulo // IGA1 FIFO High Threshold Select 83 1.2.4.2 rpaulo {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18,0,5},{SR18,7,7}}}, 84 1.2.4.2 rpaulo // IGA2 FIFO High Threshold Select 85 1.2.4.2 rpaulo {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92,0,3}, {CR95,0,2}}} 86 1.2.4.2 rpaulo }; 87 1.2.4.2 rpaulo 88 1.2.4.2 rpaulo static struct display_queue_expire_num display_queue_expire_num_reg= { 89 1.2.4.2 rpaulo // IGA1 Display Queue Expire Num 90 1.2.4.2 rpaulo {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22,0,4}}}, 91 1.2.4.2 rpaulo // IGA2 Display Queue Expire Num 92 1.2.4.2 rpaulo {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94,0,6}}} 93 1.2.4.2 rpaulo }; 94 1.2.4.2 rpaulo 95 1.2.4.2 rpaulo // Definition Offset Registers 96 1.2.4.2 rpaulo static struct offset offset_reg = { 97 1.2.4.2 rpaulo // IGA1 Offset Register 98 1.2.4.2 rpaulo {IGA1_OFFSET_REG_NUM, {{CR13,0,7},{CR35,5,7}}}, 99 1.2.4.2 rpaulo // IGA2 Offset Register 100 1.2.4.2 rpaulo {IGA2_OFFSET_REG_NUM, {{CR66,0,7},{CR67,0,1}}} 101 1.2.4.2 rpaulo }; 102 1.2.4.2 rpaulo 103 1.2.4.2 rpaulo // Definition Fetch Count Registers 104 1.2.4.2 rpaulo static struct fetch_count fetch_count_reg = { 105 1.2.4.2 rpaulo // IGA1 Fetch Count Register 106 1.2.4.2 rpaulo {IGA1_FETCH_COUNT_REG_NUM, {{SR1C,0,7},{SR1D,0,1}}}, 107 1.2.4.2 rpaulo // IGA2 Fetch Count Register 108 1.2.4.2 rpaulo {IGA2_FETCH_COUNT_REG_NUM, {{CR65,0,7},{CR67,2,3}}} 109 1.2.4.2 rpaulo }; 110 1.2.4.2 rpaulo 111 1.2.4.2 rpaulo // Definition Starting Address Registers 112 1.2.4.2 rpaulo /*static static struct starting_addr starting_addr_reg = { 113 1.2.4.2 rpaulo // IGA1 Starting Address Register 114 1.2.4.2 rpaulo {IGA1_STARTING_ADDR_REG_NUM, {{CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1}}}, 115 1.2.4.2 rpaulo // IGA2 Starting Address Register 116 1.2.4.2 rpaulo {IGA2_STARTING_ADDR_REG_NUM, {{CR62,1,7},{CR63,0,7},{CR64,0,7}}} 117 1.2.4.2 rpaulo };*/ 118 1.2.4.2 rpaulo 119 1.2.4.2 rpaulo #define IGA1_STARTING_ADDR_REG_NUM 4 // location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} 120 1.2.4.2 rpaulo #define IGA2_STARTING_ADDR_REG_NUM 3 // location: {CR62,1,7},{CR63,0,7},{CR64,0,7} 121 1.2.4.2 rpaulo 122 1.2.4.2 rpaulo static struct iga1_crtc_timing iga1_crtc_reg = { 123 1.2.4.2 rpaulo // IGA1 Horizontal Total 124 1.2.4.2 rpaulo {IGA1_HOR_TOTAL_REG_NUM, {{CR00,0,7}, {CR36,3,3}}}, 125 1.2.4.2 rpaulo // IGA1 Horizontal Addressable Video 126 1.2.4.2 rpaulo {IGA1_HOR_ADDR_REG_NUM, {{CR01,0,7}}}, 127 1.2.4.2 rpaulo // IGA1 Horizontal Blank Start 128 1.2.4.2 rpaulo {IGA1_HOR_BLANK_START_REG_NUM, {{CR02,0,7}}}, 129 1.2.4.2 rpaulo // IGA1 Horizontal Blank End 130 1.2.4.2 rpaulo {IGA1_HOR_BLANK_END_REG_NUM, {{CR03,0,4}, {CR05,7,7}, {CR33,5,5}}}, 131 1.2.4.2 rpaulo // IGA1 Horizontal Sync Start 132 1.2.4.2 rpaulo {IGA1_HOR_SYNC_START_REG_NUM, {{CR04,0,7}, {CR33,4,4}}}, 133 1.2.4.2 rpaulo // IGA1 Horizontal Sync End 134 1.2.4.2 rpaulo {IGA1_HOR_SYNC_END_REG_NUM, {{CR05,0,4}}}, 135 1.2.4.2 rpaulo // IGA1 Vertical Total 136 1.2.4.2 rpaulo {IGA1_VER_TOTAL_REG_NUM, {{CR06,0,7}, {CR07,0,0}, {CR07,5,5}, {CR35,0,0}}}, 137 1.2.4.2 rpaulo // IGA1 Vertical Addressable Video 138 1.2.4.2 rpaulo {IGA1_VER_ADDR_REG_NUM, {{CR12,0,7}, {CR07,1,1}, {CR07,6,6}, {CR35,2,2}}}, 139 1.2.4.2 rpaulo // IGA1 Vertical Blank Start 140 1.2.4.2 rpaulo {IGA1_VER_BLANK_START_REG_NUM, {{CR15,0,7}, {CR07,3,3}, {CR09,5,5}, {CR35,3,3}}}, 141 1.2.4.2 rpaulo // IGA1 Vertical Blank End 142 1.2.4.2 rpaulo {IGA1_VER_BLANK_END_REG_NUM, {{CR16,0,7}}}, 143 1.2.4.2 rpaulo // IGA1 Vertical Sync Start 144 1.2.4.2 rpaulo {IGA1_VER_SYNC_START_REG_NUM, {{CR10,0,7}, {CR07,2,2}, {CR07,7,7}, {CR35,1,1}}}, 145 1.2.4.2 rpaulo // IGA1 Vertical Sync End 146 1.2.4.2 rpaulo {IGA1_VER_SYNC_END_REG_NUM, {{CR11,0,3}}} 147 1.2.4.2 rpaulo }; 148 1.2.4.2 rpaulo 149 1.2.4.2 rpaulo #if notyet 150 1.2.4.2 rpaulo static struct iga2_shadow_crtc_timing iga2_shadow_crtc_reg = { 151 1.2.4.2 rpaulo // IGA2 Shadow Horizontal Total 152 1.2.4.2 rpaulo {IGA2_SHADOW_HOR_TOTAL_REG_NUM, {{CR6D,0,7}, {CR71,3,3}}}, 153 1.2.4.2 rpaulo // IGA2 Shadow Horizontal Blank End 154 1.2.4.2 rpaulo {IGA2_SHADOW_HOR_BLANK_END_REG_NUM, {{CR6E,0,7}}}, 155 1.2.4.2 rpaulo // IGA2 Shadow Vertical Total 156 1.2.4.2 rpaulo {IGA2_SHADOW_VER_TOTAL_REG_NUM, {{CR6F,0,7}, {CR71,0,2}}}, 157 1.2.4.2 rpaulo // IGA2 Shadow Vertical Addressable Video 158 1.2.4.2 rpaulo {IGA2_SHADOW_VER_ADDR_REG_NUM, {{CR70,0,7}, {CR71,4,6}}}, 159 1.2.4.2 rpaulo // IGA2 Shadow Vertical Blank Start 160 1.2.4.2 rpaulo {IGA2_SHADOW_VER_BLANK_START_REG_NUM, {{CR72,0,7}, {CR74,4,6}}}, 161 1.2.4.2 rpaulo // IGA2 Shadow Vertical Blank End 162 1.2.4.2 rpaulo {IGA2_SHADOW_VER_BLANK_END_REG_NUM, {{CR73,0,7}, {CR74,0,2}}}, 163 1.2.4.2 rpaulo // IGA2 Shadow Vertical Sync Start 164 1.2.4.2 rpaulo {IGA2_SHADOW_VER_SYNC_START_REG_NUM, {{CR75,0,7}, {CR76,4,6}}}, 165 1.2.4.2 rpaulo // IGA2 Shadow Vertical Sync End 166 1.2.4.2 rpaulo {IGA2_SHADOW_VER_SYNC_END_REG_NUM, {{CR76,0,3}}} 167 1.2.4.2 rpaulo }; 168 1.2.4.2 rpaulo 169 1.2.4.2 rpaulo static struct iga2_crtc_timing iga2_crtc_reg = { 170 1.2.4.2 rpaulo // IGA2 Horizontal Total 171 1.2.4.2 rpaulo {IGA2_HOR_TOTAL_REG_NUM, {{CR50,0,7}, {CR55,0,3}}}, 172 1.2.4.2 rpaulo // IGA2 Horizontal Addressable Video 173 1.2.4.2 rpaulo {IGA2_HOR_ADDR_REG_NUM, {{CR51,0,7}, {CR55,4,6}}}, 174 1.2.4.2 rpaulo // IGA2 Horizontal Blank Start 175 1.2.4.2 rpaulo {IGA2_HOR_BLANK_START_REG_NUM, {{CR52,0,7}, {CR54,0,2}}}, 176 1.2.4.2 rpaulo // IGA2 Horizontal Blank End 177 1.2.4.2 rpaulo {IGA2_HOR_BLANK_END_REG_NUM, {{CR53,0,7}, {CR54,3,5}, {CR5D,6,6}}}, 178 1.2.4.2 rpaulo // IGA2 Horizontal Sync Start 179 1.2.4.2 rpaulo {IGA2_HOR_SYNC_START_REG_NUM, {{CR56,0,7}, {CR54,6,7}, {CR5C,7,7}}}, 180 1.2.4.2 rpaulo // IGA2 Horizontal Sync End 181 1.2.4.2 rpaulo {IGA2_HOR_SYNC_END_REG_NUM, {{CR57,0,7}, {CR5C,6,6}}}, 182 1.2.4.2 rpaulo // IGA2 Vertical Total 183 1.2.4.2 rpaulo {IGA2_VER_TOTAL_REG_NUM, {{CR58,0,7}, {CR5D,0,2}}}, 184 1.2.4.2 rpaulo // IGA2 Vertical Addressable Video 185 1.2.4.2 rpaulo {IGA2_VER_ADDR_REG_NUM, {{CR59,0,7}, {CR5D,3,5}}}, 186 1.2.4.2 rpaulo // IGA2 Vertical Blank Start 187 1.2.4.2 rpaulo {IGA2_VER_BLANK_START_REG_NUM, {{CR5A,0,7}, {CR5C,0,2}}}, 188 1.2.4.2 rpaulo // IGA2 Vertical Blank End 189 1.2.4.2 rpaulo {IGA2_VER_BLANK_END_REG_NUM, {{CR5B,0,7}, {CR5C,3,5}}}, 190 1.2.4.2 rpaulo // IGA2 Vertical Sync Start 191 1.2.4.2 rpaulo {IGA2_VER_SYNC_START_REG_NUM, {{CR5E,0,7}, {CR5F,5,7}}}, 192 1.2.4.2 rpaulo // IGA2 Vertical Sync End 193 1.2.4.2 rpaulo {IGA2_VER_SYNC_END_REG_NUM, {{CR5F,0,4}}} 194 1.2.4.2 rpaulo }; 195 1.2.4.2 rpaulo 196 1.2.4.2 rpaulo /*static static struct _lcd_pwd_seq_timer lcd_pwd_seq_timer = { 197 1.2.4.2 rpaulo // LCD Power Sequence TD0 198 1.2.4.2 rpaulo {LCD_POWER_SEQ_TD0_REG_NUM, {{CR8B,0,7}, {CR8F,0,3}}}, 199 1.2.4.2 rpaulo // LCD Power Sequence TD1 200 1.2.4.2 rpaulo {LCD_POWER_SEQ_TD1_REG_NUM, {{CR8C,0,7}, {CR8F,4,7}}}, 201 1.2.4.2 rpaulo // LCD Power Sequence TD2 202 1.2.4.2 rpaulo {LCD_POWER_SEQ_TD2_REG_NUM, {{CR8D,0,7}, {CR90,0,3}}}, 203 1.2.4.2 rpaulo // LCD Power Sequence TD3 204 1.2.4.2 rpaulo {LCD_POWER_SEQ_TD3_REG_NUM, {{CR8E,0,7}, {CR90,4,7}}} 205 1.2.4.2 rpaulo 206 1.2.4.2 rpaulo };*/ 207 1.2.4.2 rpaulo 208 1.2.4.2 rpaulo static struct _lcd_scaling_factor lcd_scaling_factor = { 209 1.2.4.2 rpaulo // LCD Horizontal Scaling Factor Register 210 1.2.4.2 rpaulo {LCD_HOR_SCALING_FACTOR_REG_NUM, {{CR9F,0,1}, {CR77,0,7}, {CR79,4,5}}}, 211 1.2.4.2 rpaulo // LCD Vertical Scaling Factor Register 212 1.2.4.2 rpaulo {LCD_VER_SCALING_FACTOR_REG_NUM, {{CR79,3,3}, {CR78,0,7}, {CR79,6,7}}} 213 1.2.4.2 rpaulo }; 214 1.2.4.2 rpaulo static struct _lcd_scaling_factor lcd_scaling_factor_CLE = { 215 1.2.4.2 rpaulo /* LCD Horizontal Scaling Factor Register */ 216 1.2.4.2 rpaulo {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77,0,7}, {CR79,4,5}}}, 217 1.2.4.2 rpaulo /* LCD Vertical Scaling Factor Register */ 218 1.2.4.2 rpaulo {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78,0,7}, {CR79,6,7}}} 219 1.2.4.2 rpaulo }; 220 1.2.4.2 rpaulo #endif 221 1.2.4.2 rpaulo 222 1.2.4.2 rpaulo static struct rgbLUT palLUT_table[]= { 223 1.2.4.2 rpaulo // {R,G,B} 224 1.2.4.2 rpaulo // Index 0x00~0x03 225 1.2.4.2 rpaulo {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00, 0x2A, 0x2A}, 226 1.2.4.2 rpaulo // Index 0x04~0x07 227 1.2.4.2 rpaulo {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A, 0x2A, 0x2A}, 228 1.2.4.2 rpaulo // Index 0x08~0x0B 229 1.2.4.2 rpaulo {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15, 0x3F, 0x3F}, 230 1.2.4.2 rpaulo // Index 0x0C~0x0F 231 1.2.4.2 rpaulo {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F, 0x3F, 0x3F}, 232 1.2.4.2 rpaulo // Index 0x10~0x13 233 1.2.4.2 rpaulo {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B, 0x0B, 0x0B}, 234 1.2.4.2 rpaulo // Index 0x14~0x17 235 1.2.4.2 rpaulo {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18, 0x18, 0x18}, 236 1.2.4.2 rpaulo // Index 0x18~0x1B 237 1.2.4.2 rpaulo {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28, 0x28, 0x28}, 238 1.2.4.2 rpaulo // Index 0x1C~0x1F 239 1.2.4.2 rpaulo {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F, 0x3F, 0x3F}, 240 1.2.4.2 rpaulo // Index 0x20~0x23 241 1.2.4.2 rpaulo {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F, 0x00, 0x3F}, 242 1.2.4.2 rpaulo // Index 0x24~0x27 243 1.2.4.2 rpaulo {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F, 0x00, 0x10}, 244 1.2.4.2 rpaulo // Index 0x28~0x2B 245 1.2.4.2 rpaulo {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F, 0x2F, 0x00}, 246 1.2.4.2 rpaulo // Index 0x2C~0x2F 247 1.2.4.2 rpaulo {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10, 0x3F, 0x00}, 248 1.2.4.2 rpaulo // Index 0x30~0x33 249 1.2.4.2 rpaulo {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00, 0x3F, 0x2F}, 250 1.2.4.2 rpaulo // Index 0x34~0x37 251 1.2.4.2 rpaulo {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00, 0x10, 0x3F}, 252 1.2.4.2 rpaulo // Index 0x38~0x3B 253 1.2.4.2 rpaulo {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37, 0x1F, 0x3F}, 254 1.2.4.2 rpaulo // Index 0x3C~0x3F 255 1.2.4.2 rpaulo {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F, 0x1F, 0x27}, 256 1.2.4.2 rpaulo // Index 0x40~0x43 257 1.2.4.2 rpaulo {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F, 0x3F, 0x1F}, 258 1.2.4.2 rpaulo // Index 0x44~0x47 259 1.2.4.2 rpaulo {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27, 0x3F, 0x1F}, 260 1.2.4.2 rpaulo // Index 0x48~0x4B 261 1.2.4.2 rpaulo {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F, 0x3F, 0x37}, 262 1.2.4.2 rpaulo // Index 0x4C~0x4F 263 1.2.4.2 rpaulo {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F, 0x27, 0x3F}, 264 1.2.4.2 rpaulo // Index 0x50~0x53 265 1.2.4.2 rpaulo {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A, 0x2D, 0x3F}, 266 1.2.4.2 rpaulo // Index 0x54~0x57 267 1.2.4.2 rpaulo {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F, 0x2D, 0x31}, 268 1.2.4.2 rpaulo // Index 0x58~0x5B 269 1.2.4.2 rpaulo {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F, 0x3A, 0x2D}, 270 1.2.4.2 rpaulo // Index 0x5C~0x5F 271 1.2.4.2 rpaulo {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31, 0x3F, 0x2D}, 272 1.2.4.2 rpaulo // Index 0x60~0x63 273 1.2.4.2 rpaulo {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D, 0x3F, 0x3A}, 274 1.2.4.2 rpaulo // Index 0x64~0x67 275 1.2.4.2 rpaulo {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D, 0x31, 0x3F}, 276 1.2.4.2 rpaulo // Index 0x68~0x6B 277 1.2.4.2 rpaulo {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15, 0x00, 0x1C}, 278 1.2.4.2 rpaulo // Index 0x6C~0x6F 279 1.2.4.2 rpaulo {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C, 0x00, 0x07}, 280 1.2.4.2 rpaulo // Index 0x70~0x73 281 1.2.4.2 rpaulo {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C, 0x15, 0x00}, 282 1.2.4.2 rpaulo // Index 0x74~0x77 283 1.2.4.2 rpaulo {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07, 0x1C, 0x00}, 284 1.2.4.2 rpaulo // Index 0x78~0x7B 285 1.2.4.2 rpaulo {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00, 0x1C, 0x15}, 286 1.2.4.2 rpaulo // Index 0x7C~0x7F 287 1.2.4.2 rpaulo {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00, 0x07, 0x1C}, 288 1.2.4.2 rpaulo // Index 0x80~0x83 289 1.2.4.2 rpaulo {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18, 0x0E, 0x1C}, 290 1.2.4.2 rpaulo // Index 0x84~0x87 291 1.2.4.2 rpaulo {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C, 0x0E, 0x11}, 292 1.2.4.2 rpaulo // Index 0x88~0x8B 293 1.2.4.2 rpaulo {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C, 0x18, 0x0E}, 294 1.2.4.2 rpaulo // Index 0x8C~0x8F 295 1.2.4.2 rpaulo {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11, 0x1C, 0x0E}, 296 1.2.4.2 rpaulo // Index 0x90~0x93 297 1.2.4.2 rpaulo {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E, 0x1C, 0x18}, 298 1.2.4.2 rpaulo // Index 0x94~0x97 299 1.2.4.2 rpaulo {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E, 0x11, 0x1C}, 300 1.2.4.2 rpaulo // Index 0x98~0x9B 301 1.2.4.2 rpaulo {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A, 0x14, 0x1C}, 302 1.2.4.2 rpaulo // Index 0x9C~0x9F 303 1.2.4.2 rpaulo {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C, 0x14, 0x16}, 304 1.2.4.2 rpaulo // Index 0xA0~0xA3 305 1.2.4.2 rpaulo {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C, 0x1A, 0x14}, 306 1.2.4.2 rpaulo // Index 0xA4~0xA7 307 1.2.4.2 rpaulo {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16, 0x1C, 0x14}, 308 1.2.4.2 rpaulo // Index 0xA8~0xAB 309 1.2.4.2 rpaulo {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14, 0x1C, 0x1A}, 310 1.2.4.2 rpaulo // Index 0xAC~0xAF 311 1.2.4.2 rpaulo {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14, 0x16, 0x1C}, 312 1.2.4.2 rpaulo // Index 0xB0~0xB3 313 1.2.4.2 rpaulo {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C, 0x00, 0x10}, 314 1.2.4.2 rpaulo // Index 0xB4~0xB7 315 1.2.4.2 rpaulo {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10, 0x00, 0x04}, 316 1.2.4.2 rpaulo // Index 0xB8~0xBB 317 1.2.4.2 rpaulo {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10, 0x0C, 0x00}, 318 1.2.4.2 rpaulo // Index 0xBC~0xBF 319 1.2.4.2 rpaulo {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04, 0x10, 0x00}, 320 1.2.4.2 rpaulo // Index 0xC0~0xC3 321 1.2.4.2 rpaulo {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00, 0x10, 0x0C}, 322 1.2.4.2 rpaulo // Index 0xC4~0xC7 323 1.2.4.2 rpaulo {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00, 0x04, 0x10}, 324 1.2.4.2 rpaulo // Index 0xC8~0xCB 325 1.2.4.2 rpaulo {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E, 0x08, 0x10}, 326 1.2.4.2 rpaulo // Index 0xCC~0xCF 327 1.2.4.2 rpaulo {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10, 0x08, 0x0A}, 328 1.2.4.2 rpaulo // Index 0xD0~0xD3 329 1.2.4.2 rpaulo {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10, 0x0E, 0x08}, 330 1.2.4.2 rpaulo // Index 0xD4~0xD7 331 1.2.4.2 rpaulo {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A, 0x10, 0x08}, 332 1.2.4.2 rpaulo // Index 0xD8~0xDB 333 1.2.4.2 rpaulo {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08, 0x10, 0x0E}, 334 1.2.4.2 rpaulo // Index 0xDC~0xDF 335 1.2.4.2 rpaulo {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08, 0x0A, 0x10}, 336 1.2.4.2 rpaulo // Index 0xE0~0xE3 337 1.2.4.2 rpaulo {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F, 0x0B, 0x10}, 338 1.2.4.2 rpaulo // Index 0xE4~0xE7 339 1.2.4.2 rpaulo {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10, 0x0B, 0x0C}, 340 1.2.4.2 rpaulo // Index 0xE8~0xEB 341 1.2.4.2 rpaulo {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10, 0x0F, 0x0B}, 342 1.2.4.2 rpaulo // Index 0xEC~0xEF 343 1.2.4.2 rpaulo {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C, 0x10, 0x0B}, 344 1.2.4.2 rpaulo // Index 0xF0~0xF3 345 1.2.4.2 rpaulo {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B, 0x10, 0x0F}, 346 1.2.4.2 rpaulo // Index 0xF4~0xF7 347 1.2.4.2 rpaulo {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B, 0x0C, 0x10}, 348 1.2.4.2 rpaulo // Index 0xF8~0xFB 349 1.2.4.2 rpaulo {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, 350 1.2.4.2 rpaulo // Index 0xFC~0xFF 351 1.2.4.2 rpaulo {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00} 352 1.2.4.2 rpaulo }; 353 1.2.4.2 rpaulo 354 1.2.4.2 rpaulo #if notyet 355 1.2.4.2 rpaulo static uint16_t red256[] = { 356 1.2.4.2 rpaulo 0x0 ,0x0 ,0x0 ,0x0 ,0xa800,0xa800,0xa800,0xa800,0x5400,0x5400,0x5400,0x5400,0xfc00,0xfc00,0xfc00,0xfc00, 357 1.2.4.2 rpaulo 0x0 ,0x1400,0x2000,0x2c00,0x3800,0x4400,0x5000,0x6000,0x7000,0x8000,0x9000,0xa000,0xb400,0xc800,0xe000,0xfc00, 358 1.2.4.2 rpaulo 0x0 ,0x4000,0x7c00,0xbc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xbc00,0x7c00,0x4000, 359 1.2.4.2 rpaulo 0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x7c00,0x9c00,0xbc00,0xdc00,0xfc00,0xfc00,0xfc00,0xfc00, 360 1.2.4.2 rpaulo 0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xdc00,0xbc00,0x9c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00, 361 1.2.4.2 rpaulo 0xb400,0xc400,0xd800,0xe800,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xe800,0xd800,0xc400, 362 1.2.4.2 rpaulo 0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0x0 ,0x1c00,0x3800,0x5400,0x7000,0x7000,0x7000,0x7000, 363 1.2.4.2 rpaulo 0x7000,0x7000,0x7000,0x7000,0x7000,0x5400,0x3800,0x1c00,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 , 364 1.2.4.2 rpaulo 0x3800,0x4400,0x5400,0x6000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x6000,0x5400,0x4400, 365 1.2.4.2 rpaulo 0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x5000,0x5800,0x6000,0x6800,0x7000,0x7000,0x7000,0x7000, 366 1.2.4.2 rpaulo 0x7000,0x7000,0x7000,0x7000,0x7000,0x6800,0x6000,0x5800,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000, 367 1.2.4.2 rpaulo 0x0 ,0x1000,0x2000,0x3000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x3000,0x2000,0x1000, 368 1.2.4.2 rpaulo 0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x2000,0x2800,0x3000,0x3800,0x4000,0x4000,0x4000,0x4000, 369 1.2.4.2 rpaulo 0x4000,0x4000,0x4000,0x4000,0x4000,0x3800,0x3000,0x2800,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000, 370 1.2.4.2 rpaulo 0x2c00,0x3000,0x3400,0x3c00,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x3c00,0x3400,0x3000, 371 1.2.4.2 rpaulo 0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 372 1.2.4.2 rpaulo }; 373 1.2.4.2 rpaulo static uint16_t green256[] = { 374 1.2.4.2 rpaulo 0x0 ,0x0 ,0xa800,0xa800,0x0 ,0x0 ,0x5400,0xa800,0x5400,0x5400,0xfc00,0xfc00,0x5400,0x5400,0xfc00,0xfc00, 375 1.2.4.2 rpaulo 0x0 ,0x1400,0x2000,0x2c00,0x3800,0x4400,0x5000,0x6000,0x7000,0x8000,0x9000,0xa000,0xb400,0xc800,0xe000,0xfc00, 376 1.2.4.2 rpaulo 0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x7c00,0xbc00,0xfc00,0xfc00,0xfc00,0xfc00, 377 1.2.4.2 rpaulo 0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xbc00,0x7c00,0x4000,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00, 378 1.2.4.2 rpaulo 0x7c00,0x9c00,0xbc00,0xdc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xdc00,0xbc00,0x9c00, 379 1.2.4.2 rpaulo 0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xc400,0xd800,0xe800,0xfc00,0xfc00,0xfc00,0xfc00, 380 1.2.4.2 rpaulo 0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xe800,0xd800,0xc400,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 , 381 1.2.4.2 rpaulo 0x0 ,0x1c00,0x3800,0x5400,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x5400,0x3800,0x1c00, 382 1.2.4.2 rpaulo 0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x4400,0x5400,0x6000,0x7000,0x7000,0x7000,0x7000, 383 1.2.4.2 rpaulo 0x7000,0x7000,0x7000,0x7000,0x7000,0x6000,0x5400,0x4400,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000, 384 1.2.4.2 rpaulo 0x5000,0x5800,0x6000,0x6800,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x6800,0x6000,0x5800, 385 1.2.4.2 rpaulo 0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x1000,0x2000,0x3000,0x4000,0x4000,0x4000,0x4000, 386 1.2.4.2 rpaulo 0x4000,0x4000,0x4000,0x4000,0x4000,0x3000,0x2000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000, 387 1.2.4.2 rpaulo 0x2000,0x2800,0x3000,0x3800,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x3800,0x3000,0x2800, 388 1.2.4.2 rpaulo 0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x3000,0x3400,0x3c00,0x4000,0x4000,0x4000,0x4000, 389 1.2.4.2 rpaulo 0x4000,0x4000,0x4000,0x4000,0x4000,0x3c00,0x3400,0x3000,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 390 1.2.4.2 rpaulo }; 391 1.2.4.2 rpaulo static uint16_t blue256[] = { 392 1.2.4.2 rpaulo 0x0 ,0xa800,0x0 ,0xa800,0x0 ,0xa800,0x0 ,0xa800,0x5400,0xfc00,0x5400,0xfc00,0x5400,0xfc00,0x5400,0xfc00, 393 1.2.4.2 rpaulo 0x0 ,0x1400,0x2000,0x2c00,0x3800,0x4400,0x5000,0x6000,0x7000,0x8000,0x9000,0xa000,0xb400,0xc800,0xe000,0xfc00, 394 1.2.4.2 rpaulo 0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xbc00,0x7c00,0x4000,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 , 395 1.2.4.2 rpaulo 0x0 ,0x4000,0x7c00,0xbc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xdc00,0xbc00,0x9c00, 396 1.2.4.2 rpaulo 0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x7c00,0x9c00,0xbc00,0xdc00,0xfc00,0xfc00,0xfc00,0xfc00, 397 1.2.4.2 rpaulo 0xfc00,0xfc00,0xfc00,0xfc00,0xfc00,0xe800,0xd800,0xc400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400,0xb400, 398 1.2.4.2 rpaulo 0xb400,0xc400,0xd800,0xe800,0xfc00,0xfc00,0xfc00,0xfc00,0x7000,0x7000,0x7000,0x7000,0x7000,0x5400,0x3800,0x1c00, 399 1.2.4.2 rpaulo 0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x1c00,0x3800,0x5400,0x7000,0x7000,0x7000,0x7000, 400 1.2.4.2 rpaulo 0x7000,0x7000,0x7000,0x7000,0x7000,0x6000,0x5400,0x4400,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800,0x3800, 401 1.2.4.2 rpaulo 0x3800,0x4400,0x5400,0x6000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x7000,0x6800,0x6000,0x5800, 402 1.2.4.2 rpaulo 0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5800,0x6000,0x6800,0x7000,0x7000,0x7000,0x7000, 403 1.2.4.2 rpaulo 0x4000,0x4000,0x4000,0x4000,0x4000,0x3000,0x2000,0x1000,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 , 404 1.2.4.2 rpaulo 0x0 ,0x1000,0x2000,0x3000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x3800,0x3000,0x2800, 405 1.2.4.2 rpaulo 0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2800,0x3000,0x3800,0x4000,0x4000,0x4000,0x4000, 406 1.2.4.2 rpaulo 0x4000,0x4000,0x4000,0x4000,0x4000,0x3c00,0x3400,0x3000,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00,0x2c00, 407 1.2.4.2 rpaulo 0x2c00,0x3000,0x3400,0x3c00,0x4000,0x4000,0x4000,0x4000,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 ,0x0 408 1.2.4.2 rpaulo }; 409 1.2.4.2 rpaulo #endif 410 1.2.4.2 rpaulo 411 1.2.4.2 rpaulo #endif /* _DEV_PCI_UNICHROMECONFIG_H */ 412
Indexes created Sun Oct 12 05:10:08 GMT 2025