unichromefb.c revision 1.10.10.1
1 /* $NetBSD: unichromefb.c,v 1.10.10.1 2008/03/24 07:15:49 keiichi Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Jared D. McNeill. 18 * 4. Neither the name of The NetBSD Foundation nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved. 37 * Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved. 38 * 39 * Permission is hereby granted, free of charge, to any person obtaining a 40 * copy of this software and associated documentation files (the "Software"), 41 * to deal in the Software without restriction, including without limitation 42 * the rights to use, copy, modify, merge, publish, distribute, sub license, 43 * and/or sell copies of the Software, and to permit persons to whom the 44 * Software is furnished to do so, subject to the following conditions: 45 * 46 * The above copyright notice and this permission notice (including the 47 * next paragraph) shall be included in all copies or substantial portions 48 * of the Software. 49 * 50 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 51 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 52 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 53 * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 54 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 55 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 56 * DEALINGS IN THE SOFTWARE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: unichromefb.c,v 1.10.10.1 2008/03/24 07:15:49 keiichi Exp $"); 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/device.h> 65 #include <sys/malloc.h> 66 67 #include <sys/bus.h> 68 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcidevs.h> 72 #include <dev/pci/pciio.h> 73 74 #include <dev/wscons/wsdisplayvar.h> 75 #include <dev/wscons/wsconsio.h> 76 #include <dev/wsfont/wsfont.h> 77 #include <dev/rasops/rasops.h> 78 #include <dev/wscons/wsdisplay_vconsvar.h> 79 80 #include <dev/pci/unichromereg.h> 81 #include <dev/pci/unichromemode.h> 82 #include <dev/pci/unichromehw.h> 83 #include <dev/pci/unichromeconfig.h> 84 #include <dev/pci/unichromeaccel.h> 85 86 #include "vga.h" 87 88 #if NVGA > 0 89 #include <dev/ic/mc6845reg.h> 90 #include <dev/ic/pcdisplayvar.h> 91 #include <dev/ic/vgareg.h> 92 #include <dev/ic/vgavar.h> 93 #endif 94 95 /* XXX */ 96 #define UNICHROMEFB_DEPTH 16 97 #define UNICHROMEFB_MODE VIA_RES_1280X1024 98 #define UNICHROMEFB_WIDTH 1280 99 #define UNICHROMEFB_HEIGHT 1024 100 101 struct unichromefb_softc { 102 struct device sc_dev; 103 struct vcons_data sc_vd; 104 void * sc_fbbase; 105 unsigned int sc_fbaddr; 106 unsigned int sc_fbsize; 107 bus_addr_t sc_mmiobase; 108 bus_size_t sc_mmiosize; 109 110 bus_space_tag_t sc_iot; 111 bus_space_handle_t sc_ioh; 112 113 bus_space_tag_t sc_memt; 114 bus_space_handle_t sc_memh; 115 bus_space_tag_t sc_apmemt; 116 bus_space_handle_t sc_apmemh; 117 118 struct pci_attach_args sc_pa; 119 120 int sc_width; 121 int sc_height; 122 int sc_depth; 123 int sc_stride; 124 125 int sc_wsmode; 126 127 int sc_accel; 128 }; 129 130 static int unichromefb_match(struct device *, struct cfdata *, void *); 131 static void unichromefb_attach(struct device *, struct device *, void *); 132 133 static int unichromefb_drm_print(void *, const char *); 134 static int unichromefb_drm_unmap(struct unichromefb_softc *); 135 static int unichromefb_drm_map(struct unichromefb_softc *); 136 137 struct wsscreen_descr unichromefb_stdscreen = { 138 "fb", 139 0, 0, 140 NULL, 141 8, 16, 142 WSSCREEN_WSCOLORS, NULL, 143 }; 144 145 static int unichromefb_ioctl(void *, void *, u_long, void *, int, 146 struct lwp *); 147 static paddr_t unichromefb_mmap(void *, void *, off_t, int); 148 149 static void unichromefb_init_screen(void *, struct vcons_screen *, 150 int, long *); 151 152 /* hardware access */ 153 static uint8_t uni_rd(struct unichromefb_softc *, int, uint8_t); 154 static void uni_wr(struct unichromefb_softc *, int, uint8_t, uint8_t); 155 static void uni_wr_mask(struct unichromefb_softc *, int, uint8_t, 156 uint8_t, uint8_t); 157 static void uni_wr_x(struct unichromefb_softc *, struct io_reg *, int); 158 static void uni_wr_dac(struct unichromefb_softc *, uint8_t, uint8_t, 159 uint8_t, uint8_t); 160 161 /* helpers */ 162 static struct VideoModeTable * uni_getmode(int); 163 static void uni_setmode(struct unichromefb_softc *, int, int); 164 static void uni_crt_lock(struct unichromefb_softc *); 165 static void uni_crt_unlock(struct unichromefb_softc *); 166 static void uni_crt_enable(struct unichromefb_softc *); 167 static void uni_crt_disable(struct unichromefb_softc *); 168 static void uni_screen_enable(struct unichromefb_softc *); 169 static void uni_screen_disable(struct unichromefb_softc *); 170 static void uni_set_start(struct unichromefb_softc *); 171 static void uni_set_crtc(struct unichromefb_softc *, 172 struct crt_mode_table *, int, int, int); 173 static void uni_load_crtc(struct unichromefb_softc *, struct display_timing, 174 int); 175 static void uni_load_reg(struct unichromefb_softc *, int, int, 176 struct io_register *, int); 177 static void uni_fix_crtc(struct unichromefb_softc *); 178 static void uni_load_offset(struct unichromefb_softc *, int, int, int); 179 static void uni_load_fetchcnt(struct unichromefb_softc *, int, int, int); 180 static void uni_load_fifo(struct unichromefb_softc *, int, int, int); 181 static void uni_set_depth(struct unichromefb_softc *, int, int); 182 static uint32_t uni_get_clkval(struct unichromefb_softc *, int); 183 static void uni_set_vclk(struct unichromefb_softc *, uint32_t, int); 184 static void uni_init_dac(struct unichromefb_softc *, int); 185 static void uni_init_accel(struct unichromefb_softc *); 186 static void uni_set_accel_depth(struct unichromefb_softc *); 187 188 /* graphics ops */ 189 static void uni_wait_idle(struct unichromefb_softc *); 190 static void uni_fillrect(struct unichromefb_softc *, 191 int, int, int, int, int); 192 static void uni_rectinvert(struct unichromefb_softc *, 193 int, int, int, int); 194 static void uni_bitblit(struct unichromefb_softc *, int, int, int, int, 195 int, int); 196 static void uni_setup_mono(struct unichromefb_softc *, int, int, int, 197 int, uint32_t, uint32_t); 198 #if notyet 199 static void uni_cursor_show(struct unichromefb_softc *); 200 static void uni_cursor_hide(struct unichromefb_softc *); 201 #endif 202 203 /* rasops glue */ 204 static void uni_copycols(void *, int, int, int, int); 205 static void uni_copyrows(void *, int, int, int); 206 static void uni_erasecols(void *, int, int, int, long); 207 static void uni_eraserows(void *, int, int, long); 208 static void uni_cursor(void *, int, int, int); 209 static void uni_putchar(void *, int, int, u_int, long); 210 211 struct wsdisplay_accessops unichromefb_accessops = { 212 unichromefb_ioctl, 213 unichromefb_mmap, 214 NULL, 215 NULL, 216 NULL, 217 NULL, 218 NULL, 219 NULL, 220 }; 221 222 static struct vcons_screen unichromefb_console_screen; 223 224 const struct wsscreen_descr *_unichromefb_scrlist[] = { 225 &unichromefb_stdscreen, 226 }; 227 228 struct wsscreen_list unichromefb_screenlist = { 229 sizeof(_unichromefb_scrlist) / sizeof(struct wsscreen_descr *), 230 _unichromefb_scrlist 231 }; 232 233 CFATTACH_DECL(unichromefb, sizeof(struct unichromefb_softc), 234 unichromefb_match, unichromefb_attach, NULL, NULL); 235 236 static int 237 unichromefb_match(struct device *parent, struct cfdata *match, void *opaque) 238 { 239 struct pci_attach_args *pa; 240 241 pa = (struct pci_attach_args *)opaque; 242 243 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 244 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 245 return 0; 246 247 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_VIATECH) 248 return 0; 249 250 switch (PCI_PRODUCT(pa->pa_id)) { 251 case PCI_PRODUCT_VIATECH_VT3314_IG: 252 return 10; /* beat vga(4) */ 253 } 254 255 return 0; 256 } 257 258 static void 259 unichromefb_attach(struct device *parent, struct device *self, void *opaque) 260 { 261 struct unichromefb_softc *sc; 262 struct pci_attach_args *pa; 263 struct rasops_info *ri; 264 struct wsemuldisplaydev_attach_args aa; 265 uint8_t val; 266 long defattr; 267 268 sc = (struct unichromefb_softc *)self; 269 pa = (struct pci_attach_args *)opaque; 270 271 sc->sc_width = UNICHROMEFB_WIDTH; 272 sc->sc_height = UNICHROMEFB_HEIGHT; 273 sc->sc_depth = UNICHROMEFB_DEPTH; 274 sc->sc_stride = sc->sc_width * (sc->sc_depth / 8); 275 276 sc->sc_wsmode = WSDISPLAYIO_MODE_EMUL; 277 278 sc->sc_iot = pa->pa_iot; 279 sc->sc_pa = *pa; 280 281 #if NVGA > 0 282 /* XXX vga_cnattach claims the I/O registers that we need; 283 * we need to nuke it here so we can take over. 284 */ 285 vga_cndetach(); 286 #endif 287 288 if (bus_space_map(sc->sc_iot, VIA_REGBASE, 0x20, 0, &sc->sc_ioh)) { 289 aprint_error(": failed to map I/O registers\n"); 290 return; 291 } 292 293 sc->sc_apmemt = pa->pa_memt; 294 val = uni_rd(sc, VIASR, SR30); 295 sc->sc_fbaddr = val << 24; 296 val = uni_rd(sc, VIASR, SR39); 297 sc->sc_fbsize = val * (4*1024*1024); 298 if (sc->sc_fbsize < 16*1024*1024 || sc->sc_fbsize > 64*1024*1024) 299 sc->sc_fbsize = 16*1024*1024; 300 if (bus_space_map(sc->sc_apmemt, sc->sc_fbaddr, sc->sc_fbsize, 301 BUS_SPACE_MAP_LINEAR, &sc->sc_apmemh)) { 302 aprint_error(": failed to map aperture at 0x%08x/0x%x\n", 303 sc->sc_fbaddr, sc->sc_fbsize); 304 return; 305 } 306 sc->sc_fbbase = (void *)bus_space_vaddr(sc->sc_apmemt, sc->sc_apmemh); 307 308 if (pci_mapreg_map(pa, 0x14, PCI_MAPREG_TYPE_MEM, 0, 309 &sc->sc_memt, &sc->sc_memh, &sc->sc_mmiobase, 310 &sc->sc_mmiosize)) { 311 sc->sc_accel = 0; 312 aprint_error(": failed to map MMIO registers\n"); 313 } else { 314 sc->sc_accel = 1; 315 } 316 317 aprint_naive("\n"); 318 aprint_normal(": VIA UniChrome frame buffer\n"); 319 320 if (sc->sc_accel) 321 aprint_normal("%s: MMIO @0x%08x/0x%x\n", 322 sc->sc_dev.dv_xname, 323 (uint32_t)sc->sc_mmiobase, 324 (uint32_t)sc->sc_mmiosize); 325 326 ri = &unichromefb_console_screen.scr_ri; 327 memset(ri, 0, sizeof(struct rasops_info)); 328 329 vcons_init(&sc->sc_vd, sc, &unichromefb_stdscreen, 330 &unichromefb_accessops); 331 sc->sc_vd.init_screen = unichromefb_init_screen; 332 333 uni_setmode(sc, UNICHROMEFB_MODE, sc->sc_depth); 334 335 uni_init_dac(sc, IGA1); 336 if (sc->sc_accel) { 337 uni_init_accel(sc); 338 uni_fillrect(sc, 0, 0, sc->sc_width, sc->sc_height, 0); 339 } 340 341 aprint_normal("%s: FB @0x%08x (%dx%dx%d)\n", sc->sc_dev.dv_xname, 342 sc->sc_fbaddr, sc->sc_width, sc->sc_height, sc->sc_depth); 343 344 unichromefb_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 345 vcons_init_screen(&sc->sc_vd, &unichromefb_console_screen, 1, &defattr); 346 347 unichromefb_stdscreen.ncols = ri->ri_cols; 348 unichromefb_stdscreen.nrows = ri->ri_rows; 349 unichromefb_stdscreen.textops = &ri->ri_ops; 350 unichromefb_stdscreen.capabilities = ri->ri_caps; 351 unichromefb_stdscreen.modecookie = NULL; 352 353 wsdisplay_cnattach(&unichromefb_stdscreen, ri, 0, 0, defattr); 354 355 aa.console = 1; /* XXX */ 356 aa.scrdata = &unichromefb_screenlist; 357 aa.accessops = &unichromefb_accessops; 358 aa.accesscookie = &sc->sc_vd; 359 360 config_found(self, &aa, wsemuldisplaydevprint); 361 362 config_found_ia(self, "drm", opaque, unichromefb_drm_print); 363 364 return; 365 } 366 367 static int 368 unichromefb_drm_print(void *opaque, const char *pnp) 369 { 370 if (pnp) 371 aprint_normal("direct rendering for %s", pnp); 372 373 return UNSUPP; 374 } 375 376 static int 377 unichromefb_drm_unmap(struct unichromefb_softc *sc) 378 { 379 printf("%s: releasing bus resources\n", sc->sc_dev.dv_xname); 380 381 bus_space_unmap(sc->sc_apmemt, sc->sc_apmemh, sc->sc_fbsize); 382 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mmiosize); 383 bus_space_unmap(sc->sc_iot, sc->sc_ioh, 0x20); 384 385 return 0; 386 } 387 388 static int 389 unichromefb_drm_map(struct unichromefb_softc *sc) 390 { 391 int rv; 392 393 rv = bus_space_map(sc->sc_iot, VIA_REGBASE, 0x20, 0, 394 &sc->sc_ioh); 395 if (rv) { 396 printf("%s: failed to map I/O registers\n", 397 sc->sc_dev.dv_xname); 398 return rv; 399 } 400 rv = bus_space_map(sc->sc_apmemt, sc->sc_fbaddr, sc->sc_fbsize, 401 BUS_SPACE_MAP_LINEAR, &sc->sc_apmemh); 402 if (rv) { 403 printf("%s: failed to map aperture at 0x%08x/0x%x\n", 404 sc->sc_dev.dv_xname, sc->sc_fbaddr, sc->sc_fbsize); 405 return rv; 406 } 407 sc->sc_fbbase = (void *)bus_space_vaddr(sc->sc_apmemt, sc->sc_apmemh); 408 rv = pci_mapreg_map(&sc->sc_pa, 0x14, PCI_MAPREG_TYPE_MEM, 0, 409 &sc->sc_memt, &sc->sc_memh, &sc->sc_mmiobase, 410 &sc->sc_mmiosize); 411 if (rv) { 412 printf("%s: failed to map MMIO registers\n", 413 sc->sc_dev.dv_xname); 414 sc->sc_accel = 0; 415 } 416 417 uni_setmode(sc, UNICHROMEFB_MODE, sc->sc_depth); 418 uni_init_dac(sc, IGA1); 419 if (sc->sc_accel) { 420 uni_init_accel(sc); 421 } 422 423 printf("%s: re-acquired bus resources\n", sc->sc_dev.dv_xname); 424 425 return 0; 426 } 427 428 static int 429 unichromefb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 430 struct lwp *l) 431 { 432 struct vcons_data *vd; 433 struct unichromefb_softc *sc; 434 struct wsdisplay_fbinfo *fb; 435 436 vd = (struct vcons_data *)v; 437 sc = (struct unichromefb_softc *)vd->cookie; 438 439 switch (cmd) { 440 case WSDISPLAYIO_GTYPE: 441 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 442 return 0; 443 case WSDISPLAYIO_GINFO: 444 if (vd->active != NULL) { 445 fb = (struct wsdisplay_fbinfo *)data; 446 fb->width = sc->sc_width; 447 fb->height = sc->sc_height; 448 fb->depth = sc->sc_depth; 449 fb->cmsize = 256; 450 return 0; 451 } else 452 return ENODEV; 453 case WSDISPLAYIO_GVIDEO: 454 return ENODEV; 455 case WSDISPLAYIO_SVIDEO: 456 return ENODEV; 457 case WSDISPLAYIO_GETCMAP: 458 return EINVAL; 459 case WSDISPLAYIO_PUTCMAP: 460 return EINVAL; 461 case WSDISPLAYIO_LINEBYTES: 462 *(u_int *)data = sc->sc_stride; 463 return 0; 464 case WSDISPLAYIO_SMODE: 465 { 466 int new_mode = *(int *)data; 467 if (new_mode != sc->sc_wsmode) { 468 sc->sc_wsmode = new_mode; 469 switch (new_mode) { 470 case WSDISPLAYIO_MODE_EMUL: 471 unichromefb_drm_map(sc); 472 vcons_redraw_screen(vd->active); 473 break; 474 default: 475 unichromefb_drm_unmap(sc); 476 break; 477 } 478 } 479 } 480 return 0; 481 case WSDISPLAYIO_SSPLASH: 482 return ENODEV; 483 case WSDISPLAYIO_SPROGRESS: 484 return ENODEV; 485 486 /* PCI config read/write passthrough. */ 487 case PCI_IOC_CFGREAD: 488 case PCI_IOC_CFGWRITE: 489 return (pci_devioctl(sc->sc_pa.pa_pc, sc->sc_pa.pa_tag, 490 cmd, data, flag, l)); 491 } 492 493 return EPASSTHROUGH; 494 } 495 496 static paddr_t 497 unichromefb_mmap(void *v, void *vs, off_t offset, int prot) 498 { 499 return -1; 500 } 501 502 static void 503 unichromefb_init_screen(void *c, struct vcons_screen *scr, int existing, 504 long *defattr) 505 { 506 struct unichromefb_softc *sc; 507 struct rasops_info *ri; 508 509 sc = (struct unichromefb_softc *)c; 510 ri = &scr->scr_ri; 511 ri->ri_flg = RI_CENTER; 512 ri->ri_depth = sc->sc_depth; 513 ri->ri_width = sc->sc_width; 514 ri->ri_height = sc->sc_height; 515 ri->ri_stride = sc->sc_stride; 516 ri->ri_bits = sc->sc_fbbase; 517 if (existing) 518 ri->ri_flg |= RI_CLEAR; 519 520 switch (ri->ri_depth) { 521 case 32: 522 ri->ri_rnum = ri->ri_gnum = ri->ri_bnum = 8; 523 ri->ri_rpos = 16; 524 ri->ri_gpos = 8; 525 ri->ri_bpos = 0; 526 break; 527 case 16: 528 ri->ri_rnum = 5; 529 ri->ri_gnum = 6; 530 ri->ri_bnum = 5; 531 ri->ri_rpos = 11; 532 ri->ri_gpos = 5; 533 ri->ri_bpos = 0; 534 break; 535 } 536 537 rasops_init(ri, sc->sc_height / 16, sc->sc_width / 8); 538 ri->ri_caps = WSSCREEN_WSCOLORS; 539 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 540 sc->sc_width / ri->ri_font->fontwidth); 541 542 ri->ri_hw = scr; 543 if (sc->sc_accel) { 544 ri->ri_ops.copyrows = uni_copyrows; 545 ri->ri_ops.copycols = uni_copycols; 546 ri->ri_ops.eraserows = uni_eraserows; 547 ri->ri_ops.erasecols = uni_erasecols; 548 ri->ri_ops.cursor = uni_cursor; 549 ri->ri_ops.putchar = uni_putchar; 550 } 551 552 return; 553 } 554 555 /* 556 * hardware access 557 */ 558 static uint8_t 559 uni_rd(struct unichromefb_softc *sc, int off, uint8_t idx) 560 { 561 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx); 562 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, off + 1); 563 } 564 565 static void 566 uni_wr(struct unichromefb_softc *sc, int off, uint8_t idx, uint8_t val) 567 { 568 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx); 569 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off + 1, val); 570 } 571 572 static void 573 uni_wr_mask(struct unichromefb_softc *sc, int off, uint8_t idx, 574 uint8_t val, uint8_t mask) 575 { 576 uint8_t tmp; 577 578 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx); 579 tmp = bus_space_read_1(sc->sc_iot, sc->sc_ioh, off + 1); 580 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off + 1, 581 ((val & mask) | (tmp & ~mask))); 582 } 583 584 static void 585 uni_wr_dac(struct unichromefb_softc *sc, uint8_t idx, 586 uint8_t r, uint8_t g, uint8_t b) 587 { 588 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_INDEX_WRITE, idx); 589 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, r); 590 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, g); 591 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, b); 592 } 593 594 static void 595 uni_wr_x(struct unichromefb_softc *sc, struct io_reg *tbl, int num) 596 { 597 int i; 598 uint8_t tmp; 599 600 for (i = 0; i < num; i++) { 601 bus_space_write_1(sc->sc_iot, sc->sc_ioh, tbl[i].port, 602 tbl[i].index); 603 tmp = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 604 tbl[i].port + 1); 605 tmp = (tmp & (~tbl[i].mask)) | tbl[i].value; 606 bus_space_write_1(sc->sc_iot, sc->sc_ioh, tbl[i].index + 1, 607 tmp); 608 } 609 } 610 611 /* 612 * helpers 613 */ 614 static struct VideoModeTable * 615 uni_getmode(int mode) 616 { 617 int i; 618 619 for (i = 0; i < NUM_TOTAL_MODETABLE; i++) 620 if (CLE266Modes[i].ModeIndex == mode) 621 return &CLE266Modes[i]; 622 623 return NULL; 624 } 625 626 static void 627 uni_setmode(struct unichromefb_softc *sc, int idx, int bpp) 628 { 629 struct VideoModeTable *vtbl; 630 struct crt_mode_table *crt; 631 int i; 632 633 /* XXX */ 634 vtbl = uni_getmode(idx); 635 if (vtbl == NULL) 636 panic("%s: unsupported mode: %d\n", sc->sc_dev.dv_xname, idx); 637 638 crt = vtbl->crtc; 639 640 uni_screen_disable(sc); 641 642 (void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus); 643 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, 0); 644 645 /* XXX assume CN900 for now */ 646 uni_wr_x(sc, CN900_ModeXregs, NUM_TOTAL_CN900_ModeXregs); 647 648 uni_crt_disable(sc); 649 650 /* Fill VPIT params */ 651 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, VPIT.Misc); 652 653 /* Write sequencer */ 654 for (i = 1; i <= StdSR; i++) { 655 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR, i); 656 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR + 1, 657 VPIT.SR[i - 1]); 658 } 659 660 uni_set_start(sc); 661 662 uni_set_crtc(sc, crt, idx, bpp / 8, IGA1); 663 664 for (i = 0; i < StdGR; i++) { 665 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAGR, i); 666 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAGR + 1, 667 VPIT.GR[i]); 668 } 669 670 for (i = 0; i < StdAR; i++) { 671 (void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus); 672 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, i); 673 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, 674 VPIT.AR[i]); 675 } 676 677 (void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus); 678 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, 0x20); 679 680 uni_set_crtc(sc, crt, idx, bpp / 8, IGA1); 681 /* set crt output path */ 682 uni_wr_mask(sc, VIASR, SR16, 0x00, BIT6); 683 684 uni_crt_enable(sc); 685 uni_screen_enable(sc); 686 687 return; 688 } 689 690 static void 691 uni_crt_lock(struct unichromefb_softc *sc) 692 { 693 uni_wr_mask(sc, VIACR, CR11, BIT7, BIT7); 694 } 695 696 static void 697 uni_crt_unlock(struct unichromefb_softc *sc) 698 { 699 uni_wr_mask(sc, VIACR, CR11, 0, BIT7); 700 uni_wr_mask(sc, VIACR, CR47, 0, BIT0); 701 } 702 703 static void 704 uni_crt_enable(struct unichromefb_softc *sc) 705 { 706 uni_wr_mask(sc, VIACR, CR36, 0, BIT5+BIT4); 707 } 708 709 static void 710 uni_crt_disable(struct unichromefb_softc *sc) 711 { 712 uni_wr_mask(sc, VIACR, CR36, BIT5+BIT4, BIT5+BIT4); 713 } 714 715 static void 716 uni_screen_enable(struct unichromefb_softc *sc) 717 { 718 uni_wr_mask(sc, VIASR, SR01, 0, BIT5); 719 } 720 721 static void 722 uni_screen_disable(struct unichromefb_softc *sc) 723 { 724 uni_wr_mask(sc, VIASR, SR01, 0x20, BIT5); 725 } 726 727 static void 728 uni_set_start(struct unichromefb_softc *sc) 729 { 730 uni_crt_unlock(sc); 731 732 uni_wr(sc, VIACR, CR0C, 0x00); 733 uni_wr(sc, VIACR, CR0D, 0x00); 734 uni_wr(sc, VIACR, CR34, 0x00); 735 uni_wr_mask(sc, VIACR, CR48, 0x00, BIT0 + BIT1); 736 737 uni_wr(sc, VIACR, CR62, 0x00); 738 uni_wr(sc, VIACR, CR63, 0x00); 739 uni_wr(sc, VIACR, CR64, 0x00); 740 uni_wr(sc, VIACR, CRA3, 0x00); 741 742 uni_crt_lock(sc); 743 } 744 745 static void 746 uni_set_crtc(struct unichromefb_softc *sc, struct crt_mode_table *ctbl, 747 int mode, int bpp_byte, int iga) 748 { 749 struct VideoModeTable *vtbl; 750 struct display_timing crtreg; 751 int i; 752 int index; 753 int haddr, vaddr; 754 uint8_t val; 755 uint32_t pll_d_n; 756 757 index = 0; 758 759 vtbl = uni_getmode(mode); 760 for (i = 0; i < vtbl->mode_array; i++) { 761 index = i; 762 if (ctbl[i].refresh_rate == 60) 763 break; 764 } 765 766 crtreg = ctbl[index].crtc; 767 768 haddr = crtreg.hor_addr; 769 vaddr = crtreg.ver_addr; 770 771 val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIARMisc); 772 if (ctbl[index].h_sync_polarity == NEGATIVE) { 773 if (ctbl[index].v_sync_polarity == NEGATIVE) 774 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, 775 (val & (~(BIT6+BIT7))) | (BIT6+BIT7)); 776 else 777 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, 778 (val & (~(BIT6+BIT7))) | (BIT6)); 779 } else { 780 if (ctbl[index].v_sync_polarity == NEGATIVE) 781 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, 782 (val & (~(BIT6+BIT7))) | (BIT7)); 783 else 784 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, 785 (val & (~(BIT6+BIT7)))); 786 } 787 788 if (iga == IGA1) { 789 uni_crt_unlock(sc); 790 uni_wr(sc, VIACR, CR09, 0x00); 791 uni_wr_mask(sc, VIACR, CR11, 0x00, BIT4+BIT5+BIT6); 792 uni_wr_mask(sc, VIACR, CR17, 0x00, BIT7); 793 } 794 795 uni_load_crtc(sc, crtreg, iga); 796 uni_fix_crtc(sc); 797 uni_crt_lock(sc); 798 uni_wr_mask(sc, VIACR, CR17, 0x80, BIT7); 799 800 uni_load_offset(sc, haddr, bpp_byte, iga); 801 uni_load_fetchcnt(sc, haddr, bpp_byte, iga); 802 uni_load_fifo(sc, iga, haddr, vaddr); 803 804 uni_set_depth(sc, bpp_byte, iga); 805 pll_d_n = uni_get_clkval(sc, ctbl[index].clk); 806 uni_set_vclk(sc, pll_d_n, iga); 807 } 808 809 static void 810 uni_load_crtc(struct unichromefb_softc *sc, 811 struct display_timing device_timing, int iga) 812 { 813 int regnum, val; 814 struct io_register *reg; 815 int i; 816 817 regnum = val = 0; 818 reg = NULL; 819 820 uni_crt_unlock(sc); 821 822 for (i = 0; i < 12; i++) { 823 switch (iga) { 824 case IGA1: 825 switch (i) { 826 case H_TOTAL_INDEX: 827 val = IGA1_HOR_TOTAL_FORMULA( 828 device_timing.hor_total); 829 regnum = iga1_crtc_reg.hor_total.reg_num; 830 reg = iga1_crtc_reg.hor_total.reg; 831 break; 832 case H_ADDR_INDEX: 833 val = IGA1_HOR_ADDR_FORMULA( 834 device_timing.hor_addr); 835 regnum = iga1_crtc_reg.hor_addr.reg_num; 836 reg = iga1_crtc_reg.hor_addr.reg; 837 break; 838 case H_BLANK_START_INDEX: 839 val = IGA1_HOR_BLANK_START_FORMULA( 840 device_timing.hor_blank_start); 841 regnum = iga1_crtc_reg.hor_blank_start.reg_num; 842 reg = iga1_crtc_reg.hor_blank_start.reg; 843 break; 844 case H_BLANK_END_INDEX: 845 val = IGA1_HOR_BLANK_END_FORMULA( 846 device_timing.hor_blank_start, 847 device_timing.hor_blank_end); 848 regnum = iga1_crtc_reg.hor_blank_end.reg_num; 849 reg = iga1_crtc_reg.hor_blank_end.reg; 850 break; 851 case H_SYNC_START_INDEX: 852 val = IGA1_HOR_SYNC_START_FORMULA( 853 device_timing.hor_sync_start); 854 regnum = iga1_crtc_reg.hor_sync_start.reg_num; 855 reg = iga1_crtc_reg.hor_sync_start.reg; 856 break; 857 case H_SYNC_END_INDEX: 858 val = IGA1_HOR_SYNC_END_FORMULA( 859 device_timing.hor_sync_start, 860 device_timing.hor_sync_end); 861 regnum = iga1_crtc_reg.hor_sync_end.reg_num; 862 reg = iga1_crtc_reg.hor_sync_end.reg; 863 break; 864 case V_TOTAL_INDEX: 865 val = IGA1_VER_TOTAL_FORMULA( 866 device_timing.ver_total); 867 regnum = iga1_crtc_reg.ver_total.reg_num; 868 reg = iga1_crtc_reg.ver_total.reg; 869 break; 870 case V_ADDR_INDEX: 871 val = IGA1_VER_ADDR_FORMULA( 872 device_timing.ver_addr); 873 regnum = iga1_crtc_reg.ver_addr.reg_num; 874 reg = iga1_crtc_reg.ver_addr.reg; 875 break; 876 case V_BLANK_START_INDEX: 877 val = IGA1_VER_BLANK_START_FORMULA( 878 device_timing.ver_blank_start); 879 regnum = iga1_crtc_reg.ver_blank_start.reg_num; 880 reg = iga1_crtc_reg.ver_blank_start.reg; 881 break; 882 case V_BLANK_END_INDEX: 883 val = IGA1_VER_BLANK_END_FORMULA( 884 device_timing.ver_blank_start, 885 device_timing.ver_blank_end); 886 regnum = iga1_crtc_reg.ver_blank_end.reg_num; 887 reg = iga1_crtc_reg.ver_blank_end.reg; 888 break; 889 case V_SYNC_START_INDEX: 890 val = IGA1_VER_SYNC_START_FORMULA( 891 device_timing.ver_sync_start); 892 regnum = iga1_crtc_reg.ver_sync_start.reg_num; 893 reg = iga1_crtc_reg.ver_sync_start.reg; 894 break; 895 case V_SYNC_END_INDEX: 896 val = IGA1_VER_SYNC_END_FORMULA( 897 device_timing.ver_sync_start, 898 device_timing.ver_sync_end); 899 regnum = iga1_crtc_reg.ver_sync_end.reg_num; 900 reg = iga1_crtc_reg.ver_sync_end.reg; 901 break; 902 default: 903 printf("%s: unknown index %d while setting up CRTC\n", 904 sc->sc_dev.dv_xname, i); 905 break; 906 } 907 break; 908 case IGA2: 909 printf("%s: %s: IGA2 not supported\n", 910 sc->sc_dev.dv_xname, __func__); 911 break; 912 } 913 914 uni_load_reg(sc, val, regnum, reg, VIACR); 915 } 916 917 uni_crt_lock(sc); 918 } 919 920 static void 921 uni_load_reg(struct unichromefb_softc *sc, int timing, int regnum, 922 struct io_register *reg, int type) 923 { 924 int regmask, bitnum, data; 925 int i, j; 926 int shift_next_reg; 927 int startidx, endidx, cridx; 928 uint16_t getbit; 929 930 bitnum = 0; 931 932 for (i = 0; i < regnum; i++) { 933 regmask = data = 0; 934 startidx = reg[i].start_bit; 935 endidx = reg[i].end_bit; 936 cridx = reg[i].io_addr; 937 938 shift_next_reg = bitnum; 939 940 for (j = startidx; j <= endidx; j++) { 941 regmask = regmask | (BIT0 << j); 942 getbit = (timing & (BIT0 << bitnum)); 943 data = data | ((getbit >> shift_next_reg) << startidx); 944 ++bitnum; 945 } 946 947 if (type == VIACR) 948 uni_wr_mask(sc, VIACR, cridx, data, regmask); 949 else 950 uni_wr_mask(sc, VIASR, cridx, data, regmask); 951 } 952 953 return; 954 } 955 956 static void 957 uni_fix_crtc(struct unichromefb_softc *sc) 958 { 959 uni_wr_mask(sc, VIACR, CR03, 0x80, BIT7); 960 uni_wr(sc, VIACR, CR18, 0xff); 961 uni_wr_mask(sc, VIACR, CR07, 0x10, BIT4); 962 uni_wr_mask(sc, VIACR, CR09, 0x40, BIT6); 963 uni_wr_mask(sc, VIACR, CR35, 0x10, BIT4); 964 uni_wr_mask(sc, VIACR, CR33, 0x06, BIT0+BIT1+BIT2); 965 uni_wr(sc, VIACR, CR17, 0xe3); 966 uni_wr(sc, VIACR, CR08, 0x00); 967 uni_wr(sc, VIACR, CR14, 0x00); 968 969 return; 970 } 971 972 static void 973 uni_load_offset(struct unichromefb_softc *sc, int haddr, int bpp, int iga) 974 { 975 976 switch (iga) { 977 case IGA1: 978 uni_load_reg(sc, 979 IGA1_OFFSET_FORMULA(haddr, bpp), 980 offset_reg.iga1_offset_reg.reg_num, 981 offset_reg.iga1_offset_reg.reg, 982 VIACR); 983 break; 984 default: 985 printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname, 986 __func__); 987 break; 988 } 989 990 return; 991 } 992 993 static void 994 uni_load_fetchcnt(struct unichromefb_softc *sc, int haddr, int bpp, int iga) 995 { 996 997 switch (iga) { 998 case IGA1: 999 uni_load_reg(sc, 1000 IGA1_FETCH_COUNT_FORMULA(haddr, bpp), 1001 fetch_count_reg.iga1_fetch_count_reg.reg_num, 1002 fetch_count_reg.iga1_fetch_count_reg.reg, 1003 VIASR); 1004 break; 1005 default: 1006 printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname, 1007 __func__); 1008 break; 1009 } 1010 1011 return; 1012 } 1013 1014 static void 1015 uni_load_fifo(struct unichromefb_softc *sc, int iga, int horact, int veract) 1016 { 1017 int val, regnum; 1018 struct io_register *reg; 1019 int iga1_fifo_max_depth, iga1_fifo_threshold; 1020 int iga1_fifo_high_threshold, iga1_display_queue_expire_num; 1021 1022 reg = NULL; 1023 iga1_fifo_max_depth = iga1_fifo_threshold = 0; 1024 iga1_fifo_high_threshold = iga1_display_queue_expire_num = 0; 1025 1026 switch (iga) { 1027 case IGA1: 1028 /* XXX if (type == CN900) { */ 1029 iga1_fifo_max_depth = CN900_IGA1_FIFO_MAX_DEPTH; 1030 iga1_fifo_threshold = CN900_IGA1_FIFO_THRESHOLD; 1031 iga1_fifo_high_threshold = CN900_IGA1_FIFO_HIGH_THRESHOLD; 1032 if (horact > 1280 && veract > 1024) 1033 iga1_display_queue_expire_num = 16; 1034 else 1035 iga1_display_queue_expire_num = 1036 CN900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; 1037 /* XXX } */ 1038 1039 /* set display FIFO depth select */ 1040 val = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth); 1041 regnum = 1042 display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num; 1043 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg; 1044 uni_load_reg(sc, val, regnum, reg, VIASR); 1045 1046 /* set display FIFO threshold select */ 1047 val = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold); 1048 regnum = fifo_threshold_select_reg.iga1_fifo_threshold_select_reg.reg_num; 1049 reg = fifo_threshold_select_reg.iga1_fifo_threshold_select_reg.reg; 1050 uni_load_reg(sc, val, regnum, reg, VIASR); 1051 1052 /* set display FIFO high threshold select */ 1053 val = IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold); 1054 regnum = fifo_high_threshold_select_reg.iga1_fifo_high_threshold_select_reg.reg_num; 1055 reg = fifo_high_threshold_select_reg.iga1_fifo_high_threshold_select_reg.reg; 1056 uni_load_reg(sc, val, regnum, reg, VIASR); 1057 1058 /* set display queue expire num */ 1059 val = IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(iga1_display_queue_expire_num); 1060 regnum = display_queue_expire_num_reg.iga1_display_queue_expire_num_reg.reg_num; 1061 reg = display_queue_expire_num_reg.iga1_display_queue_expire_num_reg.reg; 1062 uni_load_reg(sc, val, regnum, reg, VIASR); 1063 1064 break; 1065 default: 1066 printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname, 1067 __func__); 1068 break; 1069 } 1070 1071 return; 1072 } 1073 1074 static void 1075 uni_set_depth(struct unichromefb_softc *sc, int bpp, int iga) 1076 { 1077 switch (iga) { 1078 case IGA1: 1079 switch (bpp) { 1080 case MODE_32BPP: 1081 uni_wr_mask(sc, VIASR, SR15, 0xae, 0xfe); 1082 break; 1083 case MODE_16BPP: 1084 uni_wr_mask(sc, VIASR, SR15, 0xb6, 0xfe); 1085 break; 1086 case MODE_8BPP: 1087 uni_wr_mask(sc, VIASR, SR15, 0x22, 0xfe); 1088 break; 1089 default: 1090 printf("%s: %s: mode (%d) unsupported\n", 1091 sc->sc_dev.dv_xname, __func__, bpp); 1092 } 1093 break; 1094 default: 1095 printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname, 1096 __func__); 1097 break; 1098 } 1099 } 1100 1101 static uint32_t 1102 uni_get_clkval(struct unichromefb_softc *sc, int clk) 1103 { 1104 int i; 1105 1106 for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) { 1107 if (clk == pll_value[i].clk) { 1108 /* XXX only CN900 supported for now */ 1109 return pll_value[i].k800_pll; 1110 } 1111 } 1112 1113 aprint_error("%s: can't find matching PLL value\n", 1114 sc->sc_dev.dv_xname); 1115 1116 return 0; 1117 } 1118 1119 static void 1120 uni_set_vclk(struct unichromefb_softc *sc, uint32_t clk, int iga) 1121 { 1122 uint8_t val; 1123 1124 /* hardware reset on */ 1125 uni_wr_mask(sc, VIACR, CR17, 0x00, BIT7); 1126 1127 switch (iga) { 1128 case IGA1: 1129 /* XXX only CN900 is supported */ 1130 uni_wr(sc, VIASR, SR44, clk / 0x10000); 1131 uni_wr(sc, VIASR, SR45, (clk & 0xffff) / 0x100); 1132 uni_wr(sc, VIASR, SR46, clk % 0x100); 1133 break; 1134 default: 1135 printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname, 1136 __func__); 1137 break; 1138 } 1139 1140 /* hardware reset off */ 1141 uni_wr_mask(sc, VIACR, CR17, 0x80, BIT7); 1142 1143 /* reset pll */ 1144 switch (iga) { 1145 case IGA1: 1146 uni_wr_mask(sc, VIASR, SR40, 0x02, BIT1); 1147 uni_wr_mask(sc, VIASR, SR40, 0x00, BIT1); 1148 break; 1149 } 1150 1151 /* good to go */ 1152 val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIARMisc); 1153 val |= (BIT2+BIT3); 1154 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, val); 1155 1156 return; 1157 } 1158 1159 static void 1160 uni_init_dac(struct unichromefb_softc *sc, int iga) 1161 { 1162 int i; 1163 1164 /* XXX only IGA1 for now */ 1165 uni_wr_mask(sc, VIASR, SR1A, 0x00, BIT0); 1166 uni_wr_mask(sc, VIASR, SR18, 0x00, BIT7+BIT6); 1167 for (i = 0; i < 256; i++) 1168 uni_wr_dac(sc, i, 1169 palLUT_table[i].red, palLUT_table[i].green, palLUT_table[i].blue); 1170 1171 uni_wr_mask(sc, VIASR, SR18, 0xc0, BIT7+BIT6); 1172 1173 return; 1174 } 1175 1176 static void 1177 uni_init_accel(struct unichromefb_softc *sc) 1178 { 1179 1180 /* init 2D engine regs to reset 2D engine */ 1181 MMIO_OUT32(VIA_REG_GEMODE, 0); 1182 MMIO_OUT32(VIA_REG_SRCPOS, 0); 1183 MMIO_OUT32(VIA_REG_DSTPOS, 0); 1184 MMIO_OUT32(VIA_REG_DIMENSION, 0); 1185 MMIO_OUT32(VIA_REG_PATADDR, 0); 1186 MMIO_OUT32(VIA_REG_FGCOLOR, 0); 1187 MMIO_OUT32(VIA_REG_BGCOLOR, 0); 1188 MMIO_OUT32(VIA_REG_CLIPTL, 0); 1189 MMIO_OUT32(VIA_REG_CLIPBR, 0); 1190 MMIO_OUT32(VIA_REG_OFFSET, 0); 1191 MMIO_OUT32(VIA_REG_KEYCONTROL, 0); 1192 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1193 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1194 MMIO_OUT32(VIA_REG_PITCH, 0); 1195 MMIO_OUT32(VIA_REG_MONOPAT1, 0); 1196 1197 /* init AGP and VQ registers */ 1198 MMIO_OUT32(VIA_REG_TRANSET, 0x00100000); 1199 MMIO_OUT32(VIA_REG_TRANSPACE, 0x00000000); 1200 MMIO_OUT32(VIA_REG_TRANSPACE, 0x00333004); 1201 MMIO_OUT32(VIA_REG_TRANSPACE, 0x60000000); 1202 MMIO_OUT32(VIA_REG_TRANSPACE, 0x61000000); 1203 MMIO_OUT32(VIA_REG_TRANSPACE, 0x62000000); 1204 MMIO_OUT32(VIA_REG_TRANSPACE, 0x63000000); 1205 MMIO_OUT32(VIA_REG_TRANSPACE, 0x64000000); 1206 MMIO_OUT32(VIA_REG_TRANSPACE, 0x7d000000); 1207 1208 MMIO_OUT32(VIA_REG_TRANSET, 0xfe020000); 1209 MMIO_OUT32(VIA_REG_TRANSPACE, 0x00000000); 1210 1211 /* disable VQ */ 1212 MMIO_OUT32(VIA_REG_TRANSET, 0x00fe0000); 1213 MMIO_OUT32(VIA_REG_TRANSPACE, 0x00000004); 1214 MMIO_OUT32(VIA_REG_TRANSPACE, 0x40008c0f); 1215 MMIO_OUT32(VIA_REG_TRANSPACE, 0x44000000); 1216 MMIO_OUT32(VIA_REG_TRANSPACE, 0x45080c04); 1217 MMIO_OUT32(VIA_REG_TRANSPACE, 0x46800408); 1218 1219 uni_set_accel_depth(sc); 1220 1221 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1222 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1223 1224 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1225 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1226 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1227 1228 return; 1229 } 1230 1231 static void 1232 uni_set_accel_depth(struct unichromefb_softc *sc) 1233 { 1234 uint32_t gemode; 1235 1236 gemode = MMIO_IN32(0x04) & 0xfffffcff; 1237 1238 switch (sc->sc_depth) { 1239 case 32: 1240 gemode |= VIA_GEM_32bpp; 1241 break; 1242 case 16: 1243 gemode |= VIA_GEM_16bpp; 1244 break; 1245 default: 1246 gemode |= VIA_GEM_8bpp; 1247 break; 1248 } 1249 1250 /* set colour depth and pitch */ 1251 MMIO_OUT32(VIA_REG_GEMODE, gemode); 1252 1253 return; 1254 } 1255 1256 static void 1257 uni_wait_idle(struct unichromefb_softc *sc) 1258 { 1259 int loop = 0; 1260 1261 while (!(MMIO_IN32(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && 1262 (loop++ < MAXLOOP)) 1263 ; 1264 1265 while ((MMIO_IN32(VIA_REG_STATUS) & 1266 (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) && 1267 (loop++ < MAXLOOP)) 1268 ; 1269 1270 if (loop >= MAXLOOP) 1271 aprint_error("%s: engine stall\n", sc->sc_dev.dv_xname); 1272 1273 return; 1274 } 1275 1276 static void 1277 uni_fillrect(struct unichromefb_softc *sc, int x, int y, int width, 1278 int height, int colour) 1279 { 1280 1281 uni_wait_idle(sc); 1282 1283 MMIO_OUT32(VIA_REG_SRCPOS, 0); 1284 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1285 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1286 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1287 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1288 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1289 MMIO_OUT32(VIA_REG_DSTPOS, ((y << 16) | x)); 1290 MMIO_OUT32(VIA_REG_DIMENSION, 1291 (((height - 1) << 16) | (width - 1))); 1292 MMIO_OUT32(VIA_REG_FGCOLOR, colour); 1293 MMIO_OUT32(VIA_REG_GECMD, (0x01 | 0x2000 | 0xf0 << 24)); 1294 1295 return; 1296 } 1297 1298 static void 1299 uni_rectinvert(struct unichromefb_softc *sc, int x, int y, int width, 1300 int height) 1301 { 1302 1303 uni_wait_idle(sc); 1304 1305 MMIO_OUT32(VIA_REG_SRCPOS, 0); 1306 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1307 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1308 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1309 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1310 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1311 MMIO_OUT32(VIA_REG_DSTPOS, ((y << 16) | x)); 1312 MMIO_OUT32(VIA_REG_DIMENSION, 1313 (((height - 1) << 16) | (width - 1))); 1314 MMIO_OUT32(VIA_REG_GECMD, (0x01 | 0x2000 | 0x55 << 24)); 1315 1316 return; 1317 } 1318 1319 static void 1320 uni_bitblit(struct unichromefb_softc *sc, int xs, int ys, int xd, int yd, int width, int height) 1321 { 1322 uint32_t dir; 1323 1324 dir = 0; 1325 1326 if (ys < yd) { 1327 yd += height - 1; 1328 ys += height - 1; 1329 dir |= 0x4000; 1330 } 1331 1332 if (xs < xd) { 1333 xd += width - 1; 1334 xs += width - 1; 1335 dir |= 0x8000; 1336 } 1337 1338 uni_wait_idle(sc); 1339 1340 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1341 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1342 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1343 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1344 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1345 MMIO_OUT32(VIA_REG_SRCPOS, ys << 16 | xs); 1346 MMIO_OUT32(VIA_REG_DSTPOS, yd << 16 | xd); 1347 MMIO_OUT32(VIA_REG_DIMENSION, ((height - 1) << 16) | (width - 1)); 1348 MMIO_OUT32(VIA_REG_GECMD, (0x01 | dir | (0xcc << 24))); 1349 1350 return; 1351 } 1352 1353 static void 1354 uni_setup_mono(struct unichromefb_softc *sc, int xd, int yd, int width, int height, 1355 uint32_t fg, uint32_t bg) 1356 { 1357 1358 uni_wait_idle(sc); 1359 1360 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1361 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1362 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1363 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1364 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1365 MMIO_OUT32(VIA_REG_SRCPOS, 0); 1366 MMIO_OUT32(VIA_REG_DSTPOS, (yd << 16) | xd); 1367 MMIO_OUT32(VIA_REG_DIMENSION, ((height - 1) << 16) | (width - 1)); 1368 MMIO_OUT32(VIA_REG_FGCOLOR, fg); 1369 MMIO_OUT32(VIA_REG_BGCOLOR, bg); 1370 MMIO_OUT32(VIA_REG_GECMD, 0xcc020142); 1371 1372 return; 1373 } 1374 1375 #if notyet 1376 static void 1377 uni_cursor_show(struct unichromefb_softc *sc) 1378 { 1379 uint32_t val; 1380 1381 val = MMIO_IN32(VIA_REG_CURSOR_MODE); 1382 val |= 1; 1383 MMIO_OUT32(VIA_REG_CURSOR_MODE, val); 1384 1385 return; 1386 } 1387 1388 static void 1389 uni_cursor_hide(struct unichromefb_softc *sc) 1390 { 1391 uint32_t val; 1392 1393 val = MMIO_IN32(VIA_REG_CURSOR_MODE); 1394 val &= 0xfffffffe; 1395 MMIO_OUT32(VIA_REG_CURSOR_MODE, val); 1396 1397 return; 1398 } 1399 #endif 1400 1401 /* 1402 * rasops glue 1403 */ 1404 static void 1405 uni_copycols(void *opaque, int row, int srccol, int dstcol, int ncols) 1406 { 1407 struct rasops_info *ri; 1408 struct vcons_screen *scr; 1409 struct unichromefb_softc *sc; 1410 int xs, xd, y, width, height; 1411 1412 ri = (struct rasops_info *)opaque; 1413 scr = (struct vcons_screen *)ri->ri_hw; 1414 sc = (struct unichromefb_softc *)scr->scr_cookie; 1415 1416 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1417 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1418 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1419 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1420 width = ri->ri_font->fontwidth * ncols; 1421 height = ri->ri_font->fontheight; 1422 uni_bitblit(sc, xs, y, xd, y, width, height); 1423 } 1424 1425 return; 1426 } 1427 1428 static void 1429 uni_copyrows(void *opaque, int srcrow, int dstrow, int nrows) 1430 { 1431 struct rasops_info *ri; 1432 struct vcons_screen *scr; 1433 struct unichromefb_softc *sc; 1434 int x, ys, yd, width, height; 1435 1436 ri = (struct rasops_info *)opaque; 1437 scr = (struct vcons_screen *)ri->ri_hw; 1438 sc = (struct unichromefb_softc *)scr->scr_cookie; 1439 1440 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1441 x = ri->ri_xorigin; 1442 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1443 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1444 width = ri->ri_emuwidth; 1445 height = ri->ri_font->fontheight * nrows; 1446 uni_bitblit(sc, x, ys, x, yd, width, height); 1447 } 1448 1449 return; 1450 } 1451 1452 static void 1453 uni_erasecols(void *opaque, int row, int startcol, int ncols, long fillattr) 1454 { 1455 struct rasops_info *ri; 1456 struct vcons_screen *scr; 1457 struct unichromefb_softc *sc; 1458 int x, y, width, height, fg, bg, ul; 1459 1460 ri = (struct rasops_info *)opaque; 1461 scr = (struct vcons_screen *)ri->ri_hw; 1462 sc = (struct unichromefb_softc *)scr->scr_cookie; 1463 1464 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1465 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1466 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1467 width = ri->ri_font->fontwidth * ncols; 1468 height = ri->ri_font->fontheight; 1469 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1470 uni_fillrect(sc, x, y, width, height, ri->ri_devcmap[bg]); 1471 } 1472 1473 return; 1474 } 1475 1476 static void 1477 uni_eraserows(void *opaque, int row, int nrows, long fillattr) 1478 { 1479 struct rasops_info *ri; 1480 struct vcons_screen *scr; 1481 struct unichromefb_softc *sc; 1482 int x, y, width, height, fg, bg, ul; 1483 1484 ri = (struct rasops_info *)opaque; 1485 scr = (struct vcons_screen *)ri->ri_hw; 1486 sc = (struct unichromefb_softc *)scr->scr_cookie; 1487 1488 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1489 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1490 if ((row == 0) && (nrows == ri->ri_rows)) { 1491 /* clear the whole screen */ 1492 uni_fillrect(sc, 0, 0, ri->ri_width, 1493 ri->ri_height, ri->ri_devcmap[bg]); 1494 } else { 1495 x = ri->ri_xorigin; 1496 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1497 width = ri->ri_emuwidth; 1498 height = ri->ri_font->fontheight * nrows; 1499 uni_fillrect(sc, x, y, width, height, 1500 ri->ri_devcmap[bg]); 1501 } 1502 } 1503 1504 return; 1505 } 1506 1507 static void 1508 uni_cursor(void *opaque, int on, int row, int col) 1509 { 1510 struct rasops_info *ri; 1511 struct vcons_screen *scr; 1512 struct unichromefb_softc *sc; 1513 int x, y, wi, he; 1514 1515 ri = (struct rasops_info *)opaque; 1516 scr = (struct vcons_screen *)ri->ri_hw; 1517 sc = (struct unichromefb_softc *)scr->scr_cookie; 1518 1519 uni_wait_idle(sc); 1520 1521 wi = ri->ri_font->fontwidth; 1522 he = ri->ri_font->fontheight; 1523 1524 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1525 x = ri->ri_ccol * wi + ri->ri_xorigin; 1526 y = ri->ri_crow * he + ri->ri_yorigin; 1527 if (ri->ri_flg & RI_CURSOR) { 1528 uni_rectinvert(sc, x, y, wi, he); 1529 ri->ri_flg &= ~RI_CURSOR; 1530 } 1531 ri->ri_crow = row; 1532 ri->ri_ccol = col; 1533 if (on) { 1534 x = ri->ri_ccol * wi + ri->ri_xorigin; 1535 y = ri->ri_crow * he + ri->ri_yorigin; 1536 uni_rectinvert(sc, x, y, wi, he); 1537 ri->ri_flg |= RI_CURSOR; 1538 } 1539 } else { 1540 ri->ri_flg &= ~RI_CURSOR; 1541 ri->ri_crow = row; 1542 ri->ri_ccol = col; 1543 } 1544 1545 return; 1546 } 1547 1548 static void 1549 uni_putchar(void *opaque, int row, int col, u_int c, long attr) 1550 { 1551 struct rasops_info *ri; 1552 struct vcons_screen *scr; 1553 struct unichromefb_softc *sc; 1554 1555 ri = (struct rasops_info *)opaque; 1556 scr = (struct vcons_screen *)ri->ri_hw; 1557 sc = (struct unichromefb_softc *)scr->scr_cookie; 1558 1559 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1560 uint32_t *data; 1561 int fg, bg, ul, uc, i; 1562 int x, y, wi, he; 1563 1564 wi = ri->ri_font->fontwidth; 1565 he = ri->ri_font->fontheight; 1566 1567 if (!CHAR_IN_FONT(c, ri->ri_font)) 1568 return; 1569 1570 rasops_unpack_attr(attr, &fg, &bg, &ul); 1571 x = ri->ri_xorigin + col * wi; 1572 y = ri->ri_yorigin + row * he; 1573 if (c == 0x20) 1574 uni_fillrect(sc, x, y, wi, he, ri->ri_devcmap[bg]); 1575 else { 1576 uc = c - ri->ri_font->firstchar; 1577 data = (uint32_t *)((uint8_t *)ri->ri_font->data + 1578 uc * ri->ri_fontscale); 1579 uni_setup_mono(sc, x, y, wi, he, 1580 ri->ri_devcmap[fg], ri->ri_devcmap[bg]); 1581 for (i = 0; i < (wi * he) / 4; i++) { 1582 MMIO_OUT32(VIA_MMIO_BLTBASE, *data); 1583 data++; 1584 } 1585 } 1586 } 1587 1588 return; 1589 } 1590
Indexes created Mon Oct 13 05:10:05 GMT 2025