unichromefb.c revision 1.17
1 /* $NetBSD: unichromefb.c,v 1.17 2010/12/16 06:45:50 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2006, 2008 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved. 31 * Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved. 32 * 33 * Permission is hereby granted, free of charge, to any person obtaining a 34 * copy of this software and associated documentation files (the "Software"), 35 * to deal in the Software without restriction, including without limitation 36 * the rights to use, copy, modify, merge, publish, distribute, sub license, 37 * and/or sell copies of the Software, and to permit persons to whom the 38 * Software is furnished to do so, subject to the following conditions: 39 * 40 * The above copyright notice and this permission notice (including the 41 * next paragraph) shall be included in all copies or substantial portions 42 * of the Software. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 45 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 46 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 47 * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 48 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 49 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 50 * DEALINGS IN THE SOFTWARE. 51 */ 52 53 #include <sys/cdefs.h> 54 __KERNEL_RCSID(0, "$NetBSD: unichromefb.c,v 1.17 2010/12/16 06:45:50 cegger Exp $"); 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 #include <sys/malloc.h> 60 61 #include <sys/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 #include <dev/pci/pciio.h> 67 68 #include <dev/wscons/wsdisplayvar.h> 69 #include <dev/wscons/wsconsio.h> 70 #include <dev/wsfont/wsfont.h> 71 #include <dev/rasops/rasops.h> 72 #include <dev/wscons/wsdisplay_vconsvar.h> 73 74 #include <dev/pci/unichromereg.h> 75 #include <dev/pci/unichromemode.h> 76 #include <dev/pci/unichromehw.h> 77 #include <dev/pci/unichromeconfig.h> 78 #include <dev/pci/unichromeaccel.h> 79 80 #include "vga.h" 81 82 #if NVGA > 0 83 #include <dev/ic/mc6845reg.h> 84 #include <dev/ic/pcdisplayvar.h> 85 #include <dev/ic/vgareg.h> 86 #include <dev/ic/vgavar.h> 87 #endif 88 89 /* XXX */ 90 #define UNICHROMEFB_DEPTH 16 91 #define UNICHROMEFB_MODE VIA_RES_1280X1024 92 #define UNICHROMEFB_WIDTH 1280 93 #define UNICHROMEFB_HEIGHT 1024 94 95 struct unichromefb_softc { 96 device_t sc_dev; 97 struct vcons_data sc_vd; 98 void * sc_fbbase; 99 unsigned int sc_fbaddr; 100 unsigned int sc_fbsize; 101 bus_addr_t sc_mmiobase; 102 bus_size_t sc_mmiosize; 103 104 bus_space_tag_t sc_iot; 105 bus_space_handle_t sc_ioh; 106 107 bus_space_tag_t sc_memt; 108 bus_space_handle_t sc_memh; 109 bus_space_tag_t sc_apmemt; 110 bus_space_handle_t sc_apmemh; 111 112 struct pci_attach_args sc_pa; 113 114 int sc_width; 115 int sc_height; 116 int sc_depth; 117 int sc_stride; 118 119 int sc_wsmode; 120 121 int sc_accel; 122 }; 123 124 static int unichromefb_match(device_t, cfdata_t, void *); 125 static void unichromefb_attach(device_t, device_t, void *); 126 127 static int unichromefb_drm_print(void *, const char *); 128 static int unichromefb_drm_unmap(struct unichromefb_softc *); 129 static int unichromefb_drm_map(struct unichromefb_softc *); 130 131 struct wsscreen_descr unichromefb_stdscreen = { 132 "fb", 133 0, 0, 134 NULL, 135 8, 16, 136 WSSCREEN_WSCOLORS, NULL, 137 }; 138 139 static int unichromefb_ioctl(void *, void *, u_long, void *, int, 140 struct lwp *); 141 static paddr_t unichromefb_mmap(void *, void *, off_t, int); 142 143 static void unichromefb_init_screen(void *, struct vcons_screen *, 144 int, long *); 145 146 /* hardware access */ 147 static uint8_t uni_rd(struct unichromefb_softc *, int, uint8_t); 148 static void uni_wr(struct unichromefb_softc *, int, uint8_t, uint8_t); 149 static void uni_wr_mask(struct unichromefb_softc *, int, uint8_t, 150 uint8_t, uint8_t); 151 static void uni_wr_x(struct unichromefb_softc *, struct io_reg *, int); 152 static void uni_wr_dac(struct unichromefb_softc *, uint8_t, uint8_t, 153 uint8_t, uint8_t); 154 155 /* helpers */ 156 static struct VideoModeTable * uni_getmode(int); 157 static void uni_setmode(struct unichromefb_softc *, int, int); 158 static void uni_crt_lock(struct unichromefb_softc *); 159 static void uni_crt_unlock(struct unichromefb_softc *); 160 static void uni_crt_enable(struct unichromefb_softc *); 161 static void uni_crt_disable(struct unichromefb_softc *); 162 static void uni_screen_enable(struct unichromefb_softc *); 163 static void uni_screen_disable(struct unichromefb_softc *); 164 static void uni_set_start(struct unichromefb_softc *); 165 static void uni_set_crtc(struct unichromefb_softc *, 166 struct crt_mode_table *, int, int, int); 167 static void uni_load_crtc(struct unichromefb_softc *, struct display_timing, 168 int); 169 static void uni_load_reg(struct unichromefb_softc *, int, int, 170 struct io_register *, int); 171 static void uni_fix_crtc(struct unichromefb_softc *); 172 static void uni_load_offset(struct unichromefb_softc *, int, int, int); 173 static void uni_load_fetchcnt(struct unichromefb_softc *, int, int, int); 174 static void uni_load_fifo(struct unichromefb_softc *, int, int, int); 175 static void uni_set_depth(struct unichromefb_softc *, int, int); 176 static uint32_t uni_get_clkval(struct unichromefb_softc *, int); 177 static void uni_set_vclk(struct unichromefb_softc *, uint32_t, int); 178 static void uni_init_dac(struct unichromefb_softc *, int); 179 static void uni_init_accel(struct unichromefb_softc *); 180 static void uni_set_accel_depth(struct unichromefb_softc *); 181 182 /* graphics ops */ 183 static void uni_wait_idle(struct unichromefb_softc *); 184 static void uni_fillrect(struct unichromefb_softc *, 185 int, int, int, int, int); 186 static void uni_rectinvert(struct unichromefb_softc *, 187 int, int, int, int); 188 static void uni_bitblit(struct unichromefb_softc *, int, int, int, int, 189 int, int); 190 static void uni_setup_mono(struct unichromefb_softc *, int, int, int, 191 int, uint32_t, uint32_t); 192 #if notyet 193 static void uni_cursor_show(struct unichromefb_softc *); 194 static void uni_cursor_hide(struct unichromefb_softc *); 195 #endif 196 197 /* rasops glue */ 198 static void uni_copycols(void *, int, int, int, int); 199 static void uni_copyrows(void *, int, int, int); 200 static void uni_erasecols(void *, int, int, int, long); 201 static void uni_eraserows(void *, int, int, long); 202 static void uni_cursor(void *, int, int, int); 203 static void uni_putchar(void *, int, int, u_int, long); 204 205 struct wsdisplay_accessops unichromefb_accessops = { 206 unichromefb_ioctl, 207 unichromefb_mmap, 208 NULL, 209 NULL, 210 NULL, 211 NULL, 212 NULL, 213 NULL, 214 }; 215 216 static struct vcons_screen unichromefb_console_screen; 217 218 const struct wsscreen_descr *_unichromefb_scrlist[] = { 219 &unichromefb_stdscreen, 220 }; 221 222 struct wsscreen_list unichromefb_screenlist = { 223 sizeof(_unichromefb_scrlist) / sizeof(struct wsscreen_descr *), 224 _unichromefb_scrlist 225 }; 226 227 CFATTACH_DECL_NEW(unichromefb, sizeof(struct unichromefb_softc), 228 unichromefb_match, unichromefb_attach, NULL, NULL); 229 230 static int 231 unichromefb_match(device_t parent, cfdata_t match, void *opaque) 232 { 233 struct pci_attach_args *pa; 234 235 pa = (struct pci_attach_args *)opaque; 236 237 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 238 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 239 return 0; 240 241 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_VIATECH) 242 return 0; 243 244 switch (PCI_PRODUCT(pa->pa_id)) { 245 case PCI_PRODUCT_VIATECH_VT3314_IG: 246 return 10; /* beat vga(4) */ 247 } 248 249 return 0; 250 } 251 252 static void 253 unichromefb_attach(device_t parent, device_t self, void *opaque) 254 { 255 struct unichromefb_softc *sc = device_private(self); 256 struct pci_attach_args *pa; 257 struct rasops_info *ri; 258 struct wsemuldisplaydev_attach_args aa; 259 uint8_t val; 260 long defattr; 261 262 pa = (struct pci_attach_args *)opaque; 263 264 sc->sc_dev = self; 265 sc->sc_width = UNICHROMEFB_WIDTH; 266 sc->sc_height = UNICHROMEFB_HEIGHT; 267 sc->sc_depth = UNICHROMEFB_DEPTH; 268 sc->sc_stride = sc->sc_width * (sc->sc_depth / 8); 269 270 sc->sc_wsmode = WSDISPLAYIO_MODE_EMUL; 271 272 sc->sc_iot = pa->pa_iot; 273 sc->sc_pa = *pa; 274 275 #if NVGA > 0 276 /* XXX vga_cnattach claims the I/O registers that we need; 277 * we need to nuke it here so we can take over. 278 */ 279 vga_cndetach(); 280 #endif 281 282 if (bus_space_map(sc->sc_iot, VIA_REGBASE, 0x20, 0, &sc->sc_ioh)) { 283 aprint_error(": failed to map I/O registers\n"); 284 return; 285 } 286 287 sc->sc_apmemt = pa->pa_memt; 288 val = uni_rd(sc, VIASR, SR30); 289 sc->sc_fbaddr = val << 24; 290 val = uni_rd(sc, VIASR, SR39); 291 sc->sc_fbsize = val * (4*1024*1024); 292 if (sc->sc_fbsize < 16*1024*1024 || sc->sc_fbsize > 64*1024*1024) 293 sc->sc_fbsize = 16*1024*1024; 294 if (bus_space_map(sc->sc_apmemt, sc->sc_fbaddr, sc->sc_fbsize, 295 BUS_SPACE_MAP_LINEAR, &sc->sc_apmemh)) { 296 aprint_error(": failed to map aperture at 0x%08x/0x%x\n", 297 sc->sc_fbaddr, sc->sc_fbsize); 298 return; 299 } 300 sc->sc_fbbase = (void *)bus_space_vaddr(sc->sc_apmemt, sc->sc_apmemh); 301 302 if (pci_mapreg_map(pa, 0x14, PCI_MAPREG_TYPE_MEM, 0, 303 &sc->sc_memt, &sc->sc_memh, &sc->sc_mmiobase, 304 &sc->sc_mmiosize)) { 305 sc->sc_accel = 0; 306 aprint_error(": failed to map MMIO registers\n"); 307 } else { 308 sc->sc_accel = 1; 309 } 310 311 aprint_naive("\n"); 312 aprint_normal(": VIA UniChrome frame buffer\n"); 313 314 if (sc->sc_accel) 315 aprint_normal_dev(self, "MMIO @0x%08x/0x%x\n", 316 (uint32_t)sc->sc_mmiobase, 317 (uint32_t)sc->sc_mmiosize); 318 319 ri = &unichromefb_console_screen.scr_ri; 320 memset(ri, 0, sizeof(struct rasops_info)); 321 322 vcons_init(&sc->sc_vd, sc, &unichromefb_stdscreen, 323 &unichromefb_accessops); 324 sc->sc_vd.init_screen = unichromefb_init_screen; 325 326 uni_setmode(sc, UNICHROMEFB_MODE, sc->sc_depth); 327 328 uni_init_dac(sc, IGA1); 329 if (sc->sc_accel) { 330 uni_init_accel(sc); 331 uni_fillrect(sc, 0, 0, sc->sc_width, sc->sc_height, 0); 332 } 333 334 aprint_normal_dev(self, "FB @0x%08x (%dx%dx%d)\n", 335 sc->sc_fbaddr, sc->sc_width, sc->sc_height, sc->sc_depth); 336 337 unichromefb_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 338 vcons_init_screen(&sc->sc_vd, &unichromefb_console_screen, 1, &defattr); 339 340 unichromefb_stdscreen.ncols = ri->ri_cols; 341 unichromefb_stdscreen.nrows = ri->ri_rows; 342 unichromefb_stdscreen.textops = &ri->ri_ops; 343 unichromefb_stdscreen.capabilities = ri->ri_caps; 344 unichromefb_stdscreen.modecookie = NULL; 345 346 wsdisplay_cnattach(&unichromefb_stdscreen, ri, 0, 0, defattr); 347 348 aa.console = 1; /* XXX */ 349 aa.scrdata = &unichromefb_screenlist; 350 aa.accessops = &unichromefb_accessops; 351 aa.accesscookie = &sc->sc_vd; 352 353 config_found(self, &aa, wsemuldisplaydevprint); 354 355 config_found_ia(self, "drm", opaque, unichromefb_drm_print); 356 357 return; 358 } 359 360 static int 361 unichromefb_drm_print(void *opaque, const char *pnp) 362 { 363 if (pnp) 364 aprint_normal("drm at %s", pnp); 365 366 return UNCONF; 367 } 368 369 static int 370 unichromefb_drm_unmap(struct unichromefb_softc *sc) 371 { 372 aprint_debug_dev(sc->sc_dev, "releasing bus resources\n"); 373 374 bus_space_unmap(sc->sc_apmemt, sc->sc_apmemh, sc->sc_fbsize); 375 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mmiosize); 376 bus_space_unmap(sc->sc_iot, sc->sc_ioh, 0x20); 377 378 return 0; 379 } 380 381 static int 382 unichromefb_drm_map(struct unichromefb_softc *sc) 383 { 384 int rv; 385 386 rv = bus_space_map(sc->sc_iot, VIA_REGBASE, 0x20, 0, 387 &sc->sc_ioh); 388 if (rv) { 389 aprint_error_dev(sc->sc_dev, "failed to map I/O registers\n"); 390 return rv; 391 } 392 rv = bus_space_map(sc->sc_apmemt, sc->sc_fbaddr, sc->sc_fbsize, 393 BUS_SPACE_MAP_LINEAR, &sc->sc_apmemh); 394 if (rv) { 395 aprint_error_dev(sc->sc_dev, 396 "failed to map aperture at 0x%08x/0x%x\n", 397 sc->sc_fbaddr, sc->sc_fbsize); 398 return rv; 399 } 400 sc->sc_fbbase = (void *)bus_space_vaddr(sc->sc_apmemt, sc->sc_apmemh); 401 rv = pci_mapreg_map(&sc->sc_pa, 0x14, PCI_MAPREG_TYPE_MEM, 0, 402 &sc->sc_memt, &sc->sc_memh, &sc->sc_mmiobase, 403 &sc->sc_mmiosize); 404 if (rv) { 405 aprint_error_dev(sc->sc_dev, "failed to map MMIO registers\n"); 406 sc->sc_accel = 0; 407 } 408 409 uni_setmode(sc, UNICHROMEFB_MODE, sc->sc_depth); 410 uni_init_dac(sc, IGA1); 411 if (sc->sc_accel) 412 uni_init_accel(sc); 413 414 aprint_debug_dev(sc->sc_dev, "re-acquired bus resources\n"); 415 416 return 0; 417 } 418 419 static int 420 unichromefb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 421 struct lwp *l) 422 { 423 struct vcons_data *vd; 424 struct unichromefb_softc *sc; 425 struct wsdisplay_fbinfo *fb; 426 427 vd = (struct vcons_data *)v; 428 sc = (struct unichromefb_softc *)vd->cookie; 429 430 switch (cmd) { 431 case WSDISPLAYIO_GTYPE: 432 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 433 return 0; 434 case WSDISPLAYIO_GINFO: 435 if (vd->active != NULL) { 436 fb = (struct wsdisplay_fbinfo *)data; 437 fb->width = sc->sc_width; 438 fb->height = sc->sc_height; 439 fb->depth = sc->sc_depth; 440 fb->cmsize = 256; 441 return 0; 442 } else 443 return ENODEV; 444 case WSDISPLAYIO_GVIDEO: 445 return ENODEV; 446 case WSDISPLAYIO_SVIDEO: 447 return ENODEV; 448 case WSDISPLAYIO_GETCMAP: 449 return EINVAL; 450 case WSDISPLAYIO_PUTCMAP: 451 return EINVAL; 452 case WSDISPLAYIO_LINEBYTES: 453 *(u_int *)data = sc->sc_stride; 454 return 0; 455 case WSDISPLAYIO_SMODE: { 456 int new_mode = *(int *)data; 457 if (new_mode != sc->sc_wsmode) { 458 sc->sc_wsmode = new_mode; 459 switch (new_mode) { 460 case WSDISPLAYIO_MODE_EMUL: 461 unichromefb_drm_map(sc); 462 vcons_redraw_screen(vd->active); 463 break; 464 default: 465 unichromefb_drm_unmap(sc); 466 break; 467 } 468 } 469 } 470 return 0; 471 case WSDISPLAYIO_SSPLASH: 472 return ENODEV; 473 case WSDISPLAYIO_SPROGRESS: 474 return ENODEV; 475 476 /* PCI config read/write passthrough. */ 477 case PCI_IOC_CFGREAD: 478 case PCI_IOC_CFGWRITE: 479 return (pci_devioctl(sc->sc_pa.pa_pc, sc->sc_pa.pa_tag, 480 cmd, data, flag, l)); 481 } 482 483 return EPASSTHROUGH; 484 } 485 486 static paddr_t 487 unichromefb_mmap(void *v, void *vs, off_t offset, int prot) 488 { 489 return -1; 490 } 491 492 static void 493 unichromefb_init_screen(void *c, struct vcons_screen *scr, int existing, 494 long *defattr) 495 { 496 struct unichromefb_softc *sc; 497 struct rasops_info *ri; 498 499 sc = (struct unichromefb_softc *)c; 500 ri = &scr->scr_ri; 501 ri->ri_flg = RI_CENTER; 502 ri->ri_depth = sc->sc_depth; 503 ri->ri_width = sc->sc_width; 504 ri->ri_height = sc->sc_height; 505 ri->ri_stride = sc->sc_stride; 506 ri->ri_bits = sc->sc_fbbase; 507 if (existing) 508 ri->ri_flg |= RI_CLEAR; 509 510 switch (ri->ri_depth) { 511 case 32: 512 ri->ri_rnum = ri->ri_gnum = ri->ri_bnum = 8; 513 ri->ri_rpos = 16; 514 ri->ri_gpos = 8; 515 ri->ri_bpos = 0; 516 break; 517 case 16: 518 ri->ri_rnum = 5; 519 ri->ri_gnum = 6; 520 ri->ri_bnum = 5; 521 ri->ri_rpos = 11; 522 ri->ri_gpos = 5; 523 ri->ri_bpos = 0; 524 break; 525 } 526 527 rasops_init(ri, sc->sc_height / 16, sc->sc_width / 8); 528 ri->ri_caps = WSSCREEN_WSCOLORS; 529 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 530 sc->sc_width / ri->ri_font->fontwidth); 531 532 ri->ri_hw = scr; 533 if (sc->sc_accel) { 534 ri->ri_ops.copyrows = uni_copyrows; 535 ri->ri_ops.copycols = uni_copycols; 536 ri->ri_ops.eraserows = uni_eraserows; 537 ri->ri_ops.erasecols = uni_erasecols; 538 ri->ri_ops.cursor = uni_cursor; 539 ri->ri_ops.putchar = uni_putchar; 540 } 541 542 return; 543 } 544 545 /* 546 * hardware access 547 */ 548 static uint8_t 549 uni_rd(struct unichromefb_softc *sc, int off, uint8_t idx) 550 { 551 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx); 552 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, off + 1); 553 } 554 555 static void 556 uni_wr(struct unichromefb_softc *sc, int off, uint8_t idx, uint8_t val) 557 { 558 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx); 559 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off + 1, val); 560 } 561 562 static void 563 uni_wr_mask(struct unichromefb_softc *sc, int off, uint8_t idx, 564 uint8_t val, uint8_t mask) 565 { 566 uint8_t tmp; 567 568 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx); 569 tmp = bus_space_read_1(sc->sc_iot, sc->sc_ioh, off + 1); 570 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off + 1, 571 ((val & mask) | (tmp & ~mask))); 572 } 573 574 static void 575 uni_wr_dac(struct unichromefb_softc *sc, uint8_t idx, 576 uint8_t r, uint8_t g, uint8_t b) 577 { 578 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_INDEX_WRITE, idx); 579 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, r); 580 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, g); 581 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, b); 582 } 583 584 static void 585 uni_wr_x(struct unichromefb_softc *sc, struct io_reg *tbl, int num) 586 { 587 int i; 588 uint8_t tmp; 589 590 for (i = 0; i < num; i++) { 591 bus_space_write_1(sc->sc_iot, sc->sc_ioh, tbl[i].port, 592 tbl[i].index); 593 tmp = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 594 tbl[i].port + 1); 595 tmp = (tmp & (~tbl[i].mask)) | tbl[i].value; 596 bus_space_write_1(sc->sc_iot, sc->sc_ioh, tbl[i].index + 1, 597 tmp); 598 } 599 } 600 601 /* 602 * helpers 603 */ 604 static struct VideoModeTable * 605 uni_getmode(int mode) 606 { 607 int i; 608 609 for (i = 0; i < NUM_TOTAL_MODETABLE; i++) 610 if (CLE266Modes[i].ModeIndex == mode) 611 return &CLE266Modes[i]; 612 613 return NULL; 614 } 615 616 static void 617 uni_setmode(struct unichromefb_softc *sc, int idx, int bpp) 618 { 619 struct VideoModeTable *vtbl; 620 struct crt_mode_table *crt; 621 int i; 622 623 /* XXX */ 624 vtbl = uni_getmode(idx); 625 if (vtbl == NULL) 626 panic("%s: unsupported mode: %d\n", 627 device_xname(sc->sc_dev), idx); 628 629 crt = vtbl->crtc; 630 631 uni_screen_disable(sc); 632 633 (void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus); 634 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, 0); 635 636 /* XXX assume CN900 for now */ 637 uni_wr_x(sc, CN900_ModeXregs, NUM_TOTAL_CN900_ModeXregs); 638 639 uni_crt_disable(sc); 640 641 /* Fill VPIT params */ 642 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, VPIT.Misc); 643 644 /* Write sequencer */ 645 for (i = 1; i <= StdSR; i++) { 646 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR, i); 647 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR + 1, 648 VPIT.SR[i - 1]); 649 } 650 651 uni_set_start(sc); 652 653 uni_set_crtc(sc, crt, idx, bpp / 8, IGA1); 654 655 for (i = 0; i < StdGR; i++) { 656 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAGR, i); 657 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAGR + 1, 658 VPIT.GR[i]); 659 } 660 661 for (i = 0; i < StdAR; i++) { 662 (void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus); 663 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, i); 664 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, 665 VPIT.AR[i]); 666 } 667 668 (void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus); 669 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, 0x20); 670 671 uni_set_crtc(sc, crt, idx, bpp / 8, IGA1); 672 /* set crt output path */ 673 uni_wr_mask(sc, VIASR, SR16, 0x00, BIT6); 674 675 uni_crt_enable(sc); 676 uni_screen_enable(sc); 677 678 return; 679 } 680 681 static void 682 uni_crt_lock(struct unichromefb_softc *sc) 683 { 684 uni_wr_mask(sc, VIACR, CR11, BIT7, BIT7); 685 } 686 687 static void 688 uni_crt_unlock(struct unichromefb_softc *sc) 689 { 690 uni_wr_mask(sc, VIACR, CR11, 0, BIT7); 691 uni_wr_mask(sc, VIACR, CR47, 0, BIT0); 692 } 693 694 static void 695 uni_crt_enable(struct unichromefb_softc *sc) 696 { 697 uni_wr_mask(sc, VIACR, CR36, 0, BIT5+BIT4); 698 } 699 700 static void 701 uni_crt_disable(struct unichromefb_softc *sc) 702 { 703 uni_wr_mask(sc, VIACR, CR36, BIT5+BIT4, BIT5+BIT4); 704 } 705 706 static void 707 uni_screen_enable(struct unichromefb_softc *sc) 708 { 709 uni_wr_mask(sc, VIASR, SR01, 0, BIT5); 710 } 711 712 static void 713 uni_screen_disable(struct unichromefb_softc *sc) 714 { 715 uni_wr_mask(sc, VIASR, SR01, 0x20, BIT5); 716 } 717 718 static void 719 uni_set_start(struct unichromefb_softc *sc) 720 { 721 uni_crt_unlock(sc); 722 723 uni_wr(sc, VIACR, CR0C, 0x00); 724 uni_wr(sc, VIACR, CR0D, 0x00); 725 uni_wr(sc, VIACR, CR34, 0x00); 726 uni_wr_mask(sc, VIACR, CR48, 0x00, BIT0 + BIT1); 727 728 uni_wr(sc, VIACR, CR62, 0x00); 729 uni_wr(sc, VIACR, CR63, 0x00); 730 uni_wr(sc, VIACR, CR64, 0x00); 731 uni_wr(sc, VIACR, CRA3, 0x00); 732 733 uni_crt_lock(sc); 734 } 735 736 static void 737 uni_set_crtc(struct unichromefb_softc *sc, struct crt_mode_table *ctbl, 738 int mode, int bpp_byte, int iga) 739 { 740 struct VideoModeTable *vtbl; 741 struct display_timing crtreg; 742 int i; 743 int index; 744 int haddr, vaddr; 745 uint8_t val; 746 uint32_t pll_d_n; 747 748 index = 0; 749 750 vtbl = uni_getmode(mode); 751 for (i = 0; i < vtbl->mode_array; i++) { 752 index = i; 753 if (ctbl[i].refresh_rate == 60) 754 break; 755 } 756 757 crtreg = ctbl[index].crtc; 758 759 haddr = crtreg.hor_addr; 760 vaddr = crtreg.ver_addr; 761 762 val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIARMisc); 763 if (ctbl[index].h_sync_polarity == NEGATIVE) { 764 if (ctbl[index].v_sync_polarity == NEGATIVE) 765 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, 766 (val & (~(BIT6+BIT7))) | (BIT6+BIT7)); 767 else 768 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, 769 (val & (~(BIT6+BIT7))) | (BIT6)); 770 } else { 771 if (ctbl[index].v_sync_polarity == NEGATIVE) 772 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, 773 (val & (~(BIT6+BIT7))) | (BIT7)); 774 else 775 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, 776 (val & (~(BIT6+BIT7)))); 777 } 778 779 if (iga == IGA1) { 780 uni_crt_unlock(sc); 781 uni_wr(sc, VIACR, CR09, 0x00); 782 uni_wr_mask(sc, VIACR, CR11, 0x00, BIT4+BIT5+BIT6); 783 uni_wr_mask(sc, VIACR, CR17, 0x00, BIT7); 784 } 785 786 uni_load_crtc(sc, crtreg, iga); 787 uni_fix_crtc(sc); 788 uni_crt_lock(sc); 789 uni_wr_mask(sc, VIACR, CR17, 0x80, BIT7); 790 791 uni_load_offset(sc, haddr, bpp_byte, iga); 792 uni_load_fetchcnt(sc, haddr, bpp_byte, iga); 793 uni_load_fifo(sc, iga, haddr, vaddr); 794 795 uni_set_depth(sc, bpp_byte, iga); 796 pll_d_n = uni_get_clkval(sc, ctbl[index].clk); 797 uni_set_vclk(sc, pll_d_n, iga); 798 } 799 800 static void 801 uni_load_crtc(struct unichromefb_softc *sc, 802 struct display_timing device_timing, int iga) 803 { 804 int regnum, val; 805 struct io_register *reg; 806 int i; 807 808 regnum = val = 0; 809 reg = NULL; 810 811 uni_crt_unlock(sc); 812 813 for (i = 0; i < 12; i++) { 814 switch (iga) { 815 case IGA1: 816 switch (i) { 817 case H_TOTAL_INDEX: 818 val = IGA1_HOR_TOTAL_FORMULA( 819 device_timing.hor_total); 820 regnum = iga1_crtc_reg.hor_total.reg_num; 821 reg = iga1_crtc_reg.hor_total.reg; 822 break; 823 case H_ADDR_INDEX: 824 val = IGA1_HOR_ADDR_FORMULA( 825 device_timing.hor_addr); 826 regnum = iga1_crtc_reg.hor_addr.reg_num; 827 reg = iga1_crtc_reg.hor_addr.reg; 828 break; 829 case H_BLANK_START_INDEX: 830 val = IGA1_HOR_BLANK_START_FORMULA( 831 device_timing.hor_blank_start); 832 regnum = iga1_crtc_reg.hor_blank_start.reg_num; 833 reg = iga1_crtc_reg.hor_blank_start.reg; 834 break; 835 case H_BLANK_END_INDEX: 836 val = IGA1_HOR_BLANK_END_FORMULA( 837 device_timing.hor_blank_start, 838 device_timing.hor_blank_end); 839 regnum = iga1_crtc_reg.hor_blank_end.reg_num; 840 reg = iga1_crtc_reg.hor_blank_end.reg; 841 break; 842 case H_SYNC_START_INDEX: 843 val = IGA1_HOR_SYNC_START_FORMULA( 844 device_timing.hor_sync_start); 845 regnum = iga1_crtc_reg.hor_sync_start.reg_num; 846 reg = iga1_crtc_reg.hor_sync_start.reg; 847 break; 848 case H_SYNC_END_INDEX: 849 val = IGA1_HOR_SYNC_END_FORMULA( 850 device_timing.hor_sync_start, 851 device_timing.hor_sync_end); 852 regnum = iga1_crtc_reg.hor_sync_end.reg_num; 853 reg = iga1_crtc_reg.hor_sync_end.reg; 854 break; 855 case V_TOTAL_INDEX: 856 val = IGA1_VER_TOTAL_FORMULA( 857 device_timing.ver_total); 858 regnum = iga1_crtc_reg.ver_total.reg_num; 859 reg = iga1_crtc_reg.ver_total.reg; 860 break; 861 case V_ADDR_INDEX: 862 val = IGA1_VER_ADDR_FORMULA( 863 device_timing.ver_addr); 864 regnum = iga1_crtc_reg.ver_addr.reg_num; 865 reg = iga1_crtc_reg.ver_addr.reg; 866 break; 867 case V_BLANK_START_INDEX: 868 val = IGA1_VER_BLANK_START_FORMULA( 869 device_timing.ver_blank_start); 870 regnum = iga1_crtc_reg.ver_blank_start.reg_num; 871 reg = iga1_crtc_reg.ver_blank_start.reg; 872 break; 873 case V_BLANK_END_INDEX: 874 val = IGA1_VER_BLANK_END_FORMULA( 875 device_timing.ver_blank_start, 876 device_timing.ver_blank_end); 877 regnum = iga1_crtc_reg.ver_blank_end.reg_num; 878 reg = iga1_crtc_reg.ver_blank_end.reg; 879 break; 880 case V_SYNC_START_INDEX: 881 val = IGA1_VER_SYNC_START_FORMULA( 882 device_timing.ver_sync_start); 883 regnum = iga1_crtc_reg.ver_sync_start.reg_num; 884 reg = iga1_crtc_reg.ver_sync_start.reg; 885 break; 886 case V_SYNC_END_INDEX: 887 val = IGA1_VER_SYNC_END_FORMULA( 888 device_timing.ver_sync_start, 889 device_timing.ver_sync_end); 890 regnum = iga1_crtc_reg.ver_sync_end.reg_num; 891 reg = iga1_crtc_reg.ver_sync_end.reg; 892 break; 893 default: 894 aprint_error_dev(sc->sc_dev, 895 "unknown index %d while setting up CRTC\n", 896 i); 897 break; 898 } 899 break; 900 case IGA2: 901 aprint_error_dev(sc->sc_dev, "%s: IGA2 not supported\n", 902 __func__); 903 break; 904 } 905 906 uni_load_reg(sc, val, regnum, reg, VIACR); 907 } 908 909 uni_crt_lock(sc); 910 } 911 912 static void 913 uni_load_reg(struct unichromefb_softc *sc, int timing, int regnum, 914 struct io_register *reg, int type) 915 { 916 int regmask, bitnum, data; 917 int i, j; 918 int shift_next_reg; 919 int startidx, endidx, cridx; 920 uint16_t getbit; 921 922 bitnum = 0; 923 924 for (i = 0; i < regnum; i++) { 925 regmask = data = 0; 926 startidx = reg[i].start_bit; 927 endidx = reg[i].end_bit; 928 cridx = reg[i].io_addr; 929 930 shift_next_reg = bitnum; 931 932 for (j = startidx; j <= endidx; j++) { 933 regmask = regmask | (BIT0 << j); 934 getbit = (timing & (BIT0 << bitnum)); 935 data = data | ((getbit >> shift_next_reg) << startidx); 936 ++bitnum; 937 } 938 939 if (type == VIACR) 940 uni_wr_mask(sc, VIACR, cridx, data, regmask); 941 else 942 uni_wr_mask(sc, VIASR, cridx, data, regmask); 943 } 944 945 return; 946 } 947 948 static void 949 uni_fix_crtc(struct unichromefb_softc *sc) 950 { 951 uni_wr_mask(sc, VIACR, CR03, 0x80, BIT7); 952 uni_wr(sc, VIACR, CR18, 0xff); 953 uni_wr_mask(sc, VIACR, CR07, 0x10, BIT4); 954 uni_wr_mask(sc, VIACR, CR09, 0x40, BIT6); 955 uni_wr_mask(sc, VIACR, CR35, 0x10, BIT4); 956 uni_wr_mask(sc, VIACR, CR33, 0x06, BIT0+BIT1+BIT2); 957 uni_wr(sc, VIACR, CR17, 0xe3); 958 uni_wr(sc, VIACR, CR08, 0x00); 959 uni_wr(sc, VIACR, CR14, 0x00); 960 961 return; 962 } 963 964 static void 965 uni_load_offset(struct unichromefb_softc *sc, int haddr, int bpp, int iga) 966 { 967 968 switch (iga) { 969 case IGA1: 970 uni_load_reg(sc, 971 IGA1_OFFSET_FORMULA(haddr, bpp), 972 offset_reg.iga1_offset_reg.reg_num, 973 offset_reg.iga1_offset_reg.reg, 974 VIACR); 975 break; 976 default: 977 aprint_error_dev(sc->sc_dev, "%s: only IGA1 is supported\n", 978 __func__); 979 break; 980 } 981 982 return; 983 } 984 985 static void 986 uni_load_fetchcnt(struct unichromefb_softc *sc, int haddr, int bpp, int iga) 987 { 988 989 switch (iga) { 990 case IGA1: 991 uni_load_reg(sc, 992 IGA1_FETCH_COUNT_FORMULA(haddr, bpp), 993 fetch_count_reg.iga1_fetch_count_reg.reg_num, 994 fetch_count_reg.iga1_fetch_count_reg.reg, 995 VIASR); 996 break; 997 default: 998 aprint_error_dev(sc->sc_dev, "%s: only IGA1 is supported\n", 999 __func__); 1000 break; 1001 } 1002 1003 return; 1004 } 1005 1006 static void 1007 uni_load_fifo(struct unichromefb_softc *sc, int iga, int horact, int veract) 1008 { 1009 int val, regnum; 1010 struct io_register *reg; 1011 int iga1_fifo_max_depth, iga1_fifo_threshold; 1012 int iga1_fifo_high_threshold, iga1_display_queue_expire_num; 1013 1014 reg = NULL; 1015 iga1_fifo_max_depth = iga1_fifo_threshold = 0; 1016 iga1_fifo_high_threshold = iga1_display_queue_expire_num = 0; 1017 1018 switch (iga) { 1019 case IGA1: 1020 /* XXX if (type == CN900) { */ 1021 iga1_fifo_max_depth = CN900_IGA1_FIFO_MAX_DEPTH; 1022 iga1_fifo_threshold = CN900_IGA1_FIFO_THRESHOLD; 1023 iga1_fifo_high_threshold = CN900_IGA1_FIFO_HIGH_THRESHOLD; 1024 if (horact > 1280 && veract > 1024) 1025 iga1_display_queue_expire_num = 16; 1026 else 1027 iga1_display_queue_expire_num = 1028 CN900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; 1029 /* XXX } */ 1030 1031 /* set display FIFO depth select */ 1032 val = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth); 1033 regnum = 1034 display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num; 1035 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg; 1036 uni_load_reg(sc, val, regnum, reg, VIASR); 1037 1038 /* set display FIFO threshold select */ 1039 val = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold); 1040 regnum = fifo_threshold_select_reg.iga1_fifo_threshold_select_reg.reg_num; 1041 reg = fifo_threshold_select_reg.iga1_fifo_threshold_select_reg.reg; 1042 uni_load_reg(sc, val, regnum, reg, VIASR); 1043 1044 /* set display FIFO high threshold select */ 1045 val = IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold); 1046 regnum = fifo_high_threshold_select_reg.iga1_fifo_high_threshold_select_reg.reg_num; 1047 reg = fifo_high_threshold_select_reg.iga1_fifo_high_threshold_select_reg.reg; 1048 uni_load_reg(sc, val, regnum, reg, VIASR); 1049 1050 /* set display queue expire num */ 1051 val = IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(iga1_display_queue_expire_num); 1052 regnum = display_queue_expire_num_reg.iga1_display_queue_expire_num_reg.reg_num; 1053 reg = display_queue_expire_num_reg.iga1_display_queue_expire_num_reg.reg; 1054 uni_load_reg(sc, val, regnum, reg, VIASR); 1055 1056 break; 1057 default: 1058 aprint_error_dev(sc->sc_dev, "%s: only IGA1 is supported\n", 1059 __func__); 1060 break; 1061 } 1062 1063 return; 1064 } 1065 1066 static void 1067 uni_set_depth(struct unichromefb_softc *sc, int bpp, int iga) 1068 { 1069 switch (iga) { 1070 case IGA1: 1071 switch (bpp) { 1072 case MODE_32BPP: 1073 uni_wr_mask(sc, VIASR, SR15, 0xae, 0xfe); 1074 break; 1075 case MODE_16BPP: 1076 uni_wr_mask(sc, VIASR, SR15, 0xb6, 0xfe); 1077 break; 1078 case MODE_8BPP: 1079 uni_wr_mask(sc, VIASR, SR15, 0x22, 0xfe); 1080 break; 1081 default: 1082 aprint_error_dev(sc->sc_dev, 1083 "%s: mode (%d) unsupported\n", __func__, bpp); 1084 } 1085 break; 1086 default: 1087 aprint_error_dev(sc->sc_dev, "%s: only IGA1 is supported\n", 1088 __func__); 1089 break; 1090 } 1091 } 1092 1093 static uint32_t 1094 uni_get_clkval(struct unichromefb_softc *sc, int clk) 1095 { 1096 int i; 1097 1098 for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) { 1099 if (clk == pll_value[i].clk) { 1100 /* XXX only CN900 supported for now */ 1101 return pll_value[i].k800_pll; 1102 } 1103 } 1104 1105 aprint_error_dev(sc->sc_dev, "can't find matching PLL value\n"); 1106 1107 return 0; 1108 } 1109 1110 static void 1111 uni_set_vclk(struct unichromefb_softc *sc, uint32_t clk, int iga) 1112 { 1113 uint8_t val; 1114 1115 /* hardware reset on */ 1116 uni_wr_mask(sc, VIACR, CR17, 0x00, BIT7); 1117 1118 switch (iga) { 1119 case IGA1: 1120 /* XXX only CN900 is supported */ 1121 uni_wr(sc, VIASR, SR44, clk / 0x10000); 1122 uni_wr(sc, VIASR, SR45, (clk & 0xffff) / 0x100); 1123 uni_wr(sc, VIASR, SR46, clk % 0x100); 1124 break; 1125 default: 1126 aprint_error_dev(sc->sc_dev, "%s: only IGA1 is supported\n", 1127 __func__); 1128 break; 1129 } 1130 1131 /* hardware reset off */ 1132 uni_wr_mask(sc, VIACR, CR17, 0x80, BIT7); 1133 1134 /* reset pll */ 1135 switch (iga) { 1136 case IGA1: 1137 uni_wr_mask(sc, VIASR, SR40, 0x02, BIT1); 1138 uni_wr_mask(sc, VIASR, SR40, 0x00, BIT1); 1139 break; 1140 } 1141 1142 /* good to go */ 1143 val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIARMisc); 1144 val |= (BIT2+BIT3); 1145 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, val); 1146 1147 return; 1148 } 1149 1150 static void 1151 uni_init_dac(struct unichromefb_softc *sc, int iga) 1152 { 1153 int i; 1154 1155 /* XXX only IGA1 for now */ 1156 uni_wr_mask(sc, VIASR, SR1A, 0x00, BIT0); 1157 uni_wr_mask(sc, VIASR, SR18, 0x00, BIT7+BIT6); 1158 for (i = 0; i < 256; i++) 1159 uni_wr_dac(sc, i, 1160 palLUT_table[i].red, palLUT_table[i].green, palLUT_table[i].blue); 1161 1162 uni_wr_mask(sc, VIASR, SR18, 0xc0, BIT7+BIT6); 1163 1164 return; 1165 } 1166 1167 static void 1168 uni_init_accel(struct unichromefb_softc *sc) 1169 { 1170 1171 /* init 2D engine regs to reset 2D engine */ 1172 MMIO_OUT32(VIA_REG_GEMODE, 0); 1173 MMIO_OUT32(VIA_REG_SRCPOS, 0); 1174 MMIO_OUT32(VIA_REG_DSTPOS, 0); 1175 MMIO_OUT32(VIA_REG_DIMENSION, 0); 1176 MMIO_OUT32(VIA_REG_PATADDR, 0); 1177 MMIO_OUT32(VIA_REG_FGCOLOR, 0); 1178 MMIO_OUT32(VIA_REG_BGCOLOR, 0); 1179 MMIO_OUT32(VIA_REG_CLIPTL, 0); 1180 MMIO_OUT32(VIA_REG_CLIPBR, 0); 1181 MMIO_OUT32(VIA_REG_OFFSET, 0); 1182 MMIO_OUT32(VIA_REG_KEYCONTROL, 0); 1183 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1184 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1185 MMIO_OUT32(VIA_REG_PITCH, 0); 1186 MMIO_OUT32(VIA_REG_MONOPAT1, 0); 1187 1188 /* init AGP and VQ registers */ 1189 MMIO_OUT32(VIA_REG_TRANSET, 0x00100000); 1190 MMIO_OUT32(VIA_REG_TRANSPACE, 0x00000000); 1191 MMIO_OUT32(VIA_REG_TRANSPACE, 0x00333004); 1192 MMIO_OUT32(VIA_REG_TRANSPACE, 0x60000000); 1193 MMIO_OUT32(VIA_REG_TRANSPACE, 0x61000000); 1194 MMIO_OUT32(VIA_REG_TRANSPACE, 0x62000000); 1195 MMIO_OUT32(VIA_REG_TRANSPACE, 0x63000000); 1196 MMIO_OUT32(VIA_REG_TRANSPACE, 0x64000000); 1197 MMIO_OUT32(VIA_REG_TRANSPACE, 0x7d000000); 1198 1199 MMIO_OUT32(VIA_REG_TRANSET, 0xfe020000); 1200 MMIO_OUT32(VIA_REG_TRANSPACE, 0x00000000); 1201 1202 /* disable VQ */ 1203 MMIO_OUT32(VIA_REG_TRANSET, 0x00fe0000); 1204 MMIO_OUT32(VIA_REG_TRANSPACE, 0x00000004); 1205 MMIO_OUT32(VIA_REG_TRANSPACE, 0x40008c0f); 1206 MMIO_OUT32(VIA_REG_TRANSPACE, 0x44000000); 1207 MMIO_OUT32(VIA_REG_TRANSPACE, 0x45080c04); 1208 MMIO_OUT32(VIA_REG_TRANSPACE, 0x46800408); 1209 1210 uni_set_accel_depth(sc); 1211 1212 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1213 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1214 1215 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1216 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1217 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1218 1219 return; 1220 } 1221 1222 static void 1223 uni_set_accel_depth(struct unichromefb_softc *sc) 1224 { 1225 uint32_t gemode; 1226 1227 gemode = MMIO_IN32(0x04) & 0xfffffcff; 1228 1229 switch (sc->sc_depth) { 1230 case 32: 1231 gemode |= VIA_GEM_32bpp; 1232 break; 1233 case 16: 1234 gemode |= VIA_GEM_16bpp; 1235 break; 1236 default: 1237 gemode |= VIA_GEM_8bpp; 1238 break; 1239 } 1240 1241 /* set colour depth and pitch */ 1242 MMIO_OUT32(VIA_REG_GEMODE, gemode); 1243 1244 return; 1245 } 1246 1247 static void 1248 uni_wait_idle(struct unichromefb_softc *sc) 1249 { 1250 int loop = 0; 1251 1252 while (!(MMIO_IN32(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && 1253 (loop++ < MAXLOOP)) 1254 ; 1255 1256 while ((MMIO_IN32(VIA_REG_STATUS) & 1257 (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) && 1258 (loop++ < MAXLOOP)) 1259 ; 1260 1261 if (loop >= MAXLOOP) 1262 aprint_error_dev(sc->sc_dev, "engine stall\n"); 1263 1264 return; 1265 } 1266 1267 static void 1268 uni_fillrect(struct unichromefb_softc *sc, int x, int y, int width, 1269 int height, int colour) 1270 { 1271 1272 uni_wait_idle(sc); 1273 1274 MMIO_OUT32(VIA_REG_SRCPOS, 0); 1275 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1276 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1277 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1278 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1279 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1280 MMIO_OUT32(VIA_REG_DSTPOS, ((y << 16) | x)); 1281 MMIO_OUT32(VIA_REG_DIMENSION, 1282 (((height - 1) << 16) | (width - 1))); 1283 MMIO_OUT32(VIA_REG_FGCOLOR, colour); 1284 MMIO_OUT32(VIA_REG_GECMD, (0x01 | 0x2000 | 0xf0 << 24)); 1285 1286 return; 1287 } 1288 1289 static void 1290 uni_rectinvert(struct unichromefb_softc *sc, int x, int y, int width, 1291 int height) 1292 { 1293 1294 uni_wait_idle(sc); 1295 1296 MMIO_OUT32(VIA_REG_SRCPOS, 0); 1297 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1298 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1299 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1300 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1301 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1302 MMIO_OUT32(VIA_REG_DSTPOS, ((y << 16) | x)); 1303 MMIO_OUT32(VIA_REG_DIMENSION, 1304 (((height - 1) << 16) | (width - 1))); 1305 MMIO_OUT32(VIA_REG_GECMD, (0x01 | 0x2000 | 0x55 << 24)); 1306 1307 return; 1308 } 1309 1310 static void 1311 uni_bitblit(struct unichromefb_softc *sc, int xs, int ys, int xd, int yd, int width, int height) 1312 { 1313 uint32_t dir; 1314 1315 dir = 0; 1316 1317 if (ys < yd) { 1318 yd += height - 1; 1319 ys += height - 1; 1320 dir |= 0x4000; 1321 } 1322 1323 if (xs < xd) { 1324 xd += width - 1; 1325 xs += width - 1; 1326 dir |= 0x8000; 1327 } 1328 1329 uni_wait_idle(sc); 1330 1331 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1332 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1333 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1334 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1335 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1336 MMIO_OUT32(VIA_REG_SRCPOS, ys << 16 | xs); 1337 MMIO_OUT32(VIA_REG_DSTPOS, yd << 16 | xd); 1338 MMIO_OUT32(VIA_REG_DIMENSION, ((height - 1) << 16) | (width - 1)); 1339 MMIO_OUT32(VIA_REG_GECMD, (0x01 | dir | (0xcc << 24))); 1340 1341 return; 1342 } 1343 1344 static void 1345 uni_setup_mono(struct unichromefb_softc *sc, int xd, int yd, int width, int height, 1346 uint32_t fg, uint32_t bg) 1347 { 1348 1349 uni_wait_idle(sc); 1350 1351 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1352 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1353 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1354 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1355 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1356 MMIO_OUT32(VIA_REG_SRCPOS, 0); 1357 MMIO_OUT32(VIA_REG_DSTPOS, (yd << 16) | xd); 1358 MMIO_OUT32(VIA_REG_DIMENSION, ((height - 1) << 16) | (width - 1)); 1359 MMIO_OUT32(VIA_REG_FGCOLOR, fg); 1360 MMIO_OUT32(VIA_REG_BGCOLOR, bg); 1361 MMIO_OUT32(VIA_REG_GECMD, 0xcc020142); 1362 1363 return; 1364 } 1365 1366 #if notyet 1367 static void 1368 uni_cursor_show(struct unichromefb_softc *sc) 1369 { 1370 uint32_t val; 1371 1372 val = MMIO_IN32(VIA_REG_CURSOR_MODE); 1373 val |= 1; 1374 MMIO_OUT32(VIA_REG_CURSOR_MODE, val); 1375 1376 return; 1377 } 1378 1379 static void 1380 uni_cursor_hide(struct unichromefb_softc *sc) 1381 { 1382 uint32_t val; 1383 1384 val = MMIO_IN32(VIA_REG_CURSOR_MODE); 1385 val &= 0xfffffffe; 1386 MMIO_OUT32(VIA_REG_CURSOR_MODE, val); 1387 1388 return; 1389 } 1390 #endif 1391 1392 /* 1393 * rasops glue 1394 */ 1395 static void 1396 uni_copycols(void *opaque, int row, int srccol, int dstcol, int ncols) 1397 { 1398 struct rasops_info *ri; 1399 struct vcons_screen *scr; 1400 struct unichromefb_softc *sc; 1401 int xs, xd, y, width, height; 1402 1403 ri = (struct rasops_info *)opaque; 1404 scr = (struct vcons_screen *)ri->ri_hw; 1405 sc = (struct unichromefb_softc *)scr->scr_cookie; 1406 1407 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1408 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1409 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1410 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1411 width = ri->ri_font->fontwidth * ncols; 1412 height = ri->ri_font->fontheight; 1413 uni_bitblit(sc, xs, y, xd, y, width, height); 1414 } 1415 1416 return; 1417 } 1418 1419 static void 1420 uni_copyrows(void *opaque, int srcrow, int dstrow, int nrows) 1421 { 1422 struct rasops_info *ri; 1423 struct vcons_screen *scr; 1424 struct unichromefb_softc *sc; 1425 int x, ys, yd, width, height; 1426 1427 ri = (struct rasops_info *)opaque; 1428 scr = (struct vcons_screen *)ri->ri_hw; 1429 sc = (struct unichromefb_softc *)scr->scr_cookie; 1430 1431 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1432 x = ri->ri_xorigin; 1433 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1434 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1435 width = ri->ri_emuwidth; 1436 height = ri->ri_font->fontheight * nrows; 1437 uni_bitblit(sc, x, ys, x, yd, width, height); 1438 } 1439 1440 return; 1441 } 1442 1443 static void 1444 uni_erasecols(void *opaque, int row, int startcol, int ncols, long fillattr) 1445 { 1446 struct rasops_info *ri; 1447 struct vcons_screen *scr; 1448 struct unichromefb_softc *sc; 1449 int x, y, width, height, fg, bg, ul; 1450 1451 ri = (struct rasops_info *)opaque; 1452 scr = (struct vcons_screen *)ri->ri_hw; 1453 sc = (struct unichromefb_softc *)scr->scr_cookie; 1454 1455 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1456 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1457 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1458 width = ri->ri_font->fontwidth * ncols; 1459 height = ri->ri_font->fontheight; 1460 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1461 uni_fillrect(sc, x, y, width, height, ri->ri_devcmap[bg]); 1462 } 1463 1464 return; 1465 } 1466 1467 static void 1468 uni_eraserows(void *opaque, int row, int nrows, long fillattr) 1469 { 1470 struct rasops_info *ri; 1471 struct vcons_screen *scr; 1472 struct unichromefb_softc *sc; 1473 int x, y, width, height, fg, bg, ul; 1474 1475 ri = (struct rasops_info *)opaque; 1476 scr = (struct vcons_screen *)ri->ri_hw; 1477 sc = (struct unichromefb_softc *)scr->scr_cookie; 1478 1479 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1480 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1481 if ((row == 0) && (nrows == ri->ri_rows)) { 1482 /* clear the whole screen */ 1483 uni_fillrect(sc, 0, 0, ri->ri_width, 1484 ri->ri_height, ri->ri_devcmap[bg]); 1485 } else { 1486 x = ri->ri_xorigin; 1487 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1488 width = ri->ri_emuwidth; 1489 height = ri->ri_font->fontheight * nrows; 1490 uni_fillrect(sc, x, y, width, height, 1491 ri->ri_devcmap[bg]); 1492 } 1493 } 1494 1495 return; 1496 } 1497 1498 static void 1499 uni_cursor(void *opaque, int on, int row, int col) 1500 { 1501 struct rasops_info *ri; 1502 struct vcons_screen *scr; 1503 struct unichromefb_softc *sc; 1504 int x, y, wi, he; 1505 1506 ri = (struct rasops_info *)opaque; 1507 scr = (struct vcons_screen *)ri->ri_hw; 1508 sc = (struct unichromefb_softc *)scr->scr_cookie; 1509 1510 uni_wait_idle(sc); 1511 1512 wi = ri->ri_font->fontwidth; 1513 he = ri->ri_font->fontheight; 1514 1515 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1516 x = ri->ri_ccol * wi + ri->ri_xorigin; 1517 y = ri->ri_crow * he + ri->ri_yorigin; 1518 if (ri->ri_flg & RI_CURSOR) { 1519 uni_rectinvert(sc, x, y, wi, he); 1520 ri->ri_flg &= ~RI_CURSOR; 1521 } 1522 ri->ri_crow = row; 1523 ri->ri_ccol = col; 1524 if (on) { 1525 x = ri->ri_ccol * wi + ri->ri_xorigin; 1526 y = ri->ri_crow * he + ri->ri_yorigin; 1527 uni_rectinvert(sc, x, y, wi, he); 1528 ri->ri_flg |= RI_CURSOR; 1529 } 1530 } else { 1531 ri->ri_flg &= ~RI_CURSOR; 1532 ri->ri_crow = row; 1533 ri->ri_ccol = col; 1534 } 1535 1536 return; 1537 } 1538 1539 static void 1540 uni_putchar(void *opaque, int row, int col, u_int c, long attr) 1541 { 1542 struct rasops_info *ri; 1543 struct vcons_screen *scr; 1544 struct unichromefb_softc *sc; 1545 1546 ri = (struct rasops_info *)opaque; 1547 scr = (struct vcons_screen *)ri->ri_hw; 1548 sc = (struct unichromefb_softc *)scr->scr_cookie; 1549 1550 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1551 uint32_t *data; 1552 int fg, bg, ul, uc, i; 1553 int x, y, wi, he; 1554 1555 wi = ri->ri_font->fontwidth; 1556 he = ri->ri_font->fontheight; 1557 1558 if (!CHAR_IN_FONT(c, ri->ri_font)) 1559 return; 1560 1561 rasops_unpack_attr(attr, &fg, &bg, &ul); 1562 x = ri->ri_xorigin + col * wi; 1563 y = ri->ri_yorigin + row * he; 1564 if (c == 0x20) 1565 uni_fillrect(sc, x, y, wi, he, ri->ri_devcmap[bg]); 1566 else { 1567 uc = c - ri->ri_font->firstchar; 1568 data = (uint32_t *)((uint8_t *)ri->ri_font->data + 1569 uc * ri->ri_fontscale); 1570 uni_setup_mono(sc, x, y, wi, he, 1571 ri->ri_devcmap[fg], ri->ri_devcmap[bg]); 1572 for (i = 0; i < (wi * he) / 4; i++) { 1573 MMIO_OUT32(VIA_MMIO_BLTBASE, *data); 1574 data++; 1575 } 1576 } 1577 } 1578 1579 return; 1580 } 1581
Indexes created Tue Sep 30 17:09:57 GMT 2025