unichromefb.c revision 1.5
1 /* $NetBSD: unichromefb.c,v 1.5 2007/01/12 04:20:33 ober Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Jared D. McNeill. 18 * 4. Neither the name of The NetBSD Foundation nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved. 37 * Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved. 38 * 39 * Permission is hereby granted, free of charge, to any person obtaining a 40 * copy of this software and associated documentation files (the "Software"), 41 * to deal in the Software without restriction, including without limitation 42 * the rights to use, copy, modify, merge, publish, distribute, sub license, 43 * and/or sell copies of the Software, and to permit persons to whom the 44 * Software is furnished to do so, subject to the following conditions: 45 * 46 * The above copyright notice and this permission notice (including the 47 * next paragraph) shall be included in all copies or substantial portions 48 * of the Software. 49 * 50 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 51 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 52 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 53 * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 54 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 55 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 56 * DEALINGS IN THE SOFTWARE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: unichromefb.c,v 1.5 2007/01/12 04:20:33 ober Exp $"); 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/device.h> 65 #include <sys/malloc.h> 66 67 #include <machine/bus.h> 68 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/wscons/wsdisplayvar.h> 74 #include <dev/wscons/wsconsio.h> 75 #include <dev/wsfont/wsfont.h> 76 #include <dev/rasops/rasops.h> 77 #include <dev/wscons/wsdisplay_vconsvar.h> 78 79 #include <dev/pci/unichromereg.h> 80 #include <dev/pci/unichromemode.h> 81 #include <dev/pci/unichromehw.h> 82 #include <dev/pci/unichromeconfig.h> 83 #include <dev/pci/unichromeaccel.h> 84 85 #include "vga.h" 86 87 #if NVGA > 0 88 #include <dev/ic/mc6845reg.h> 89 #include <dev/ic/pcdisplayvar.h> 90 #include <dev/ic/vgareg.h> 91 #include <dev/ic/vgavar.h> 92 #endif 93 94 /* XXX */ 95 #define UNICHROMEFB_DEPTH 16 96 #define UNICHROMEFB_MODE VIA_RES_1280X1024 97 #define UNICHROMEFB_WIDTH 1280 98 #define UNICHROMEFB_HEIGHT 1024 99 100 struct unichromefb_softc { 101 struct device sc_dev; 102 struct vcons_data sc_vd; 103 void * sc_fbbase; 104 unsigned int sc_fbaddr; 105 unsigned int sc_fbsize; 106 107 bus_space_tag_t sc_iot; 108 bus_space_handle_t sc_ioh; 109 110 bus_space_tag_t sc_memt; 111 bus_space_handle_t sc_memh; 112 113 int sc_width; 114 int sc_height; 115 int sc_depth; 116 int sc_stride; 117 118 int sc_wsmode; 119 120 int sc_accel; 121 }; 122 123 static int unichromefb_match(struct device *, struct cfdata *, void *); 124 static void unichromefb_attach(struct device *, struct device *, void *); 125 126 struct wsscreen_descr unichromefb_stdscreen = { 127 "fb", 128 0, 0, 129 NULL, 130 8, 16, 131 WSSCREEN_WSCOLORS, NULL, 132 }; 133 134 static int unichromefb_ioctl(void *, void *, u_long, caddr_t, int, 135 struct lwp *); 136 static paddr_t unichromefb_mmap(void *, void *, off_t, int); 137 138 static void unichromefb_init_screen(void *, struct vcons_screen *, 139 int, long *); 140 141 /* hardware access */ 142 static uint8_t uni_rd(struct unichromefb_softc *, int, uint8_t); 143 static void uni_wr(struct unichromefb_softc *, int, uint8_t, uint8_t); 144 static void uni_wr_mask(struct unichromefb_softc *, int, uint8_t, 145 uint8_t, uint8_t); 146 static void uni_wr_x(struct unichromefb_softc *, struct io_reg *, int); 147 static void uni_wr_dac(struct unichromefb_softc *, uint8_t, uint8_t, 148 uint8_t, uint8_t); 149 150 /* helpers */ 151 static struct VideoModeTable * uni_getmode(int); 152 static void uni_setmode(struct unichromefb_softc *, int, int); 153 static void uni_crt_lock(struct unichromefb_softc *); 154 static void uni_crt_unlock(struct unichromefb_softc *); 155 static void uni_crt_enable(struct unichromefb_softc *); 156 static void uni_crt_disable(struct unichromefb_softc *); 157 static void uni_screen_enable(struct unichromefb_softc *); 158 static void uni_screen_disable(struct unichromefb_softc *); 159 static void uni_set_start(struct unichromefb_softc *); 160 static void uni_set_crtc(struct unichromefb_softc *, 161 struct crt_mode_table *, int, int, int); 162 static void uni_load_crtc(struct unichromefb_softc *, struct display_timing, 163 int); 164 static void uni_load_reg(struct unichromefb_softc *, int, int, 165 struct io_register *, int); 166 static void uni_fix_crtc(struct unichromefb_softc *); 167 static void uni_load_offset(struct unichromefb_softc *, int, int, int); 168 static void uni_load_fetchcnt(struct unichromefb_softc *, int, int, int); 169 static void uni_load_fifo(struct unichromefb_softc *, int, int, int); 170 static void uni_set_depth(struct unichromefb_softc *, int, int); 171 static uint32_t uni_get_clkval(struct unichromefb_softc *, int); 172 static void uni_set_vclk(struct unichromefb_softc *, uint32_t, int); 173 static void uni_init_dac(struct unichromefb_softc *, int); 174 static void uni_init_accel(struct unichromefb_softc *); 175 static void uni_set_accel_depth(struct unichromefb_softc *); 176 177 /* graphics ops */ 178 static void uni_wait_idle(struct unichromefb_softc *); 179 static void uni_fillrect(struct unichromefb_softc *, 180 int, int, int, int, int); 181 static void uni_rectinvert(struct unichromefb_softc *, 182 int, int, int, int); 183 static void uni_bitblit(struct unichromefb_softc *, int, int, int, int, 184 int, int); 185 static void uni_setup_mono(struct unichromefb_softc *, int, int, int, 186 int, uint32_t, uint32_t); 187 #if notyet 188 static void uni_cursor_show(struct unichromefb_softc *); 189 static void uni_cursor_hide(struct unichromefb_softc *); 190 #endif 191 192 /* rasops glue */ 193 static void uni_copycols(void *, int, int, int, int); 194 static void uni_copyrows(void *, int, int, int); 195 static void uni_erasecols(void *, int, int, int, long); 196 static void uni_eraserows(void *, int, int, long); 197 static void uni_cursor(void *, int, int, int); 198 static void uni_putchar(void *, int, int, u_int, long); 199 200 struct wsdisplay_accessops unichromefb_accessops = { 201 unichromefb_ioctl, 202 unichromefb_mmap, 203 NULL, 204 NULL, 205 NULL, 206 NULL, 207 NULL, 208 NULL, 209 }; 210 211 static struct vcons_screen unichromefb_console_screen; 212 213 const struct wsscreen_descr *_unichromefb_scrlist[] = { 214 &unichromefb_stdscreen, 215 }; 216 217 struct wsscreen_list unichromefb_screenlist = { 218 sizeof(_unichromefb_scrlist) / sizeof(struct wsscreen_descr *), 219 _unichromefb_scrlist 220 }; 221 222 CFATTACH_DECL(unichromefb, sizeof(struct unichromefb_softc), 223 unichromefb_match, unichromefb_attach, NULL, NULL); 224 225 static int 226 unichromefb_match(struct device *parent, struct cfdata *match, void *opaque) 227 { 228 struct pci_attach_args *pa; 229 230 pa = (struct pci_attach_args *)opaque; 231 232 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 233 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 234 return 0; 235 236 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_VIATECH) 237 return 0; 238 239 switch (PCI_PRODUCT(pa->pa_id)) { 240 case PCI_PRODUCT_VIATECH_VT3314_IG: 241 return 10; /* beat vga(4) */ 242 } 243 244 return 0; 245 } 246 247 static void 248 unichromefb_attach(struct device *parent, struct device *self, void *opaque) 249 { 250 struct unichromefb_softc *sc; 251 struct pci_attach_args *pa; 252 struct rasops_info *ri; 253 struct wsemuldisplaydev_attach_args aa; 254 bus_space_handle_t ap_memh; 255 uint8_t val; 256 bus_addr_t mmiobase; 257 bus_size_t mmiosize; 258 long defattr; 259 260 sc = (struct unichromefb_softc *)self; 261 pa = (struct pci_attach_args *)opaque; 262 263 sc->sc_width = UNICHROMEFB_WIDTH; 264 sc->sc_height = UNICHROMEFB_HEIGHT; 265 sc->sc_depth = UNICHROMEFB_DEPTH; 266 sc->sc_stride = sc->sc_width * (sc->sc_depth / 8); 267 268 sc->sc_wsmode = WSDISPLAYIO_MODE_EMUL; 269 270 sc->sc_iot = pa->pa_iot; 271 272 #if NVGA > 0 273 /* XXX vga_cnattach claims the I/O registers that we need; 274 * we need to nuke it here so we can take over. 275 */ 276 vga_cndetach(); 277 #endif 278 279 if (bus_space_map(sc->sc_iot, VIA_REGBASE, 0x20, 0, &sc->sc_ioh)) { 280 aprint_error(": failed to map I/O registers\n"); 281 return; 282 } 283 284 sc->sc_memt = pa->pa_memt; 285 val = uni_rd(sc, VIASR, SR30); 286 sc->sc_fbaddr = val << 24; 287 val = uni_rd(sc, VIASR, SR39); 288 sc->sc_fbsize = val * (4*1024*1024); 289 if (sc->sc_fbsize < 16*1024*1024 || sc->sc_fbsize > 64*1024*1024) 290 sc->sc_fbsize = 16*1024*1024; 291 if (bus_space_map(sc->sc_memt, sc->sc_fbaddr, sc->sc_fbsize, 292 BUS_SPACE_MAP_LINEAR, &ap_memh)) { 293 aprint_error(": failed to map aperture at 0x%08x/0x%x\n", 294 sc->sc_fbaddr, sc->sc_fbsize); 295 return; 296 } 297 sc->sc_fbbase = (caddr_t)bus_space_vaddr(sc->sc_memt, ap_memh); 298 299 if (pci_mapreg_map(pa, 0x14, PCI_MAPREG_TYPE_MEM, 0, 300 &sc->sc_memt, &sc->sc_memh, &mmiobase, &mmiosize)) { 301 sc->sc_accel = 0; 302 aprint_error(": failed to map MMIO registers\n"); 303 } else { 304 sc->sc_accel = 1; 305 } 306 307 aprint_naive("\n"); 308 aprint_normal(": VIA UniChrome frame buffer\n"); 309 310 if (sc->sc_accel) 311 aprint_normal("%s: MMIO @0x%08x/0x%x\n", 312 sc->sc_dev.dv_xname, (uint32_t)mmiobase, 313 (uint32_t)mmiosize); 314 315 ri = &unichromefb_console_screen.scr_ri; 316 memset(ri, 0, sizeof(struct rasops_info)); 317 318 vcons_init(&sc->sc_vd, sc, &unichromefb_stdscreen, 319 &unichromefb_accessops); 320 sc->sc_vd.init_screen = unichromefb_init_screen; 321 322 uni_setmode(sc, UNICHROMEFB_MODE, sc->sc_depth); 323 324 uni_init_dac(sc, IGA1); 325 if (sc->sc_accel) { 326 uni_init_accel(sc); 327 uni_fillrect(sc, 0, 0, sc->sc_width, sc->sc_height, 0); 328 } 329 330 aprint_normal("%s: FB @0x%08x (%dx%dx%d)\n", sc->sc_dev.dv_xname, 331 sc->sc_fbaddr, sc->sc_width, sc->sc_height, sc->sc_depth); 332 333 unichromefb_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 334 vcons_init_screen(&sc->sc_vd, &unichromefb_console_screen, 1, &defattr); 335 336 unichromefb_stdscreen.ncols = ri->ri_cols; 337 unichromefb_stdscreen.nrows = ri->ri_rows; 338 unichromefb_stdscreen.textops = &ri->ri_ops; 339 unichromefb_stdscreen.capabilities = ri->ri_caps; 340 unichromefb_stdscreen.modecookie = NULL; 341 342 wsdisplay_cnattach(&unichromefb_stdscreen, ri, 0, 0, defattr); 343 344 aa.console = 1; /* XXX */ 345 aa.scrdata = &unichromefb_screenlist; 346 aa.accessops = &unichromefb_accessops; 347 aa.accesscookie = &sc->sc_vd; 348 349 config_found(self, &aa, wsemuldisplaydevprint); 350 351 return; 352 } 353 354 static int 355 unichromefb_ioctl(void *v, void *vs, u_long cmd, caddr_t data, int flag, 356 struct lwp *l) 357 { 358 struct vcons_data *vd; 359 struct unichromefb_softc *sc; 360 struct wsdisplay_fbinfo *fb; 361 362 vd = (struct vcons_data *)v; 363 sc = (struct unichromefb_softc *)vd->cookie; 364 365 switch (cmd) { 366 case WSDISPLAYIO_GTYPE: 367 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 368 return 0; 369 case WSDISPLAYIO_GINFO: 370 if (vd->active != NULL) { 371 fb = (struct wsdisplay_fbinfo *)data; 372 fb->width = sc->sc_width; 373 fb->height = sc->sc_height; 374 fb->depth = sc->sc_depth; 375 fb->cmsize = 256; 376 return 0; 377 } else 378 return ENODEV; 379 case WSDISPLAYIO_GVIDEO: 380 return ENODEV; 381 case WSDISPLAYIO_SVIDEO: 382 return ENODEV; 383 case WSDISPLAYIO_GETCMAP: 384 return EINVAL; 385 case WSDISPLAYIO_PUTCMAP: 386 return EINVAL; 387 case WSDISPLAYIO_LINEBYTES: 388 *(u_int *)data = sc->sc_stride; 389 return 0; 390 case WSDISPLAYIO_SMODE: 391 { 392 int new_mode = *(int *)data; 393 if (new_mode != sc->sc_wsmode) { 394 sc->sc_wsmode = new_mode; 395 if (new_mode == WSDISPLAYIO_MODE_EMUL) 396 vcons_redraw_screen(vd->active); 397 } 398 } 399 return 0; 400 case WSDISPLAYIO_SSPLASH: 401 return ENODEV; 402 case WSDISPLAYIO_SPROGRESS: 403 return ENODEV; 404 } 405 406 return EPASSTHROUGH; 407 } 408 409 static paddr_t 410 unichromefb_mmap(void *v, void *vs, off_t offset, int prot) 411 { 412 return -1; 413 } 414 415 static void 416 unichromefb_init_screen(void *c, struct vcons_screen *scr, int existing, 417 long *defattr) 418 { 419 struct unichromefb_softc *sc; 420 struct rasops_info *ri; 421 422 sc = (struct unichromefb_softc *)c; 423 ri = &scr->scr_ri; 424 ri->ri_flg = RI_CENTER; 425 ri->ri_depth = sc->sc_depth; 426 ri->ri_width = sc->sc_width; 427 ri->ri_height = sc->sc_height; 428 ri->ri_stride = sc->sc_stride; 429 ri->ri_bits = sc->sc_fbbase; 430 if (existing) 431 ri->ri_flg |= RI_CLEAR; 432 433 switch (ri->ri_depth) { 434 case 32: 435 ri->ri_rnum = ri->ri_gnum = ri->ri_bnum = 8; 436 ri->ri_rpos = 16; 437 ri->ri_gpos = 8; 438 ri->ri_bpos = 0; 439 break; 440 case 16: 441 ri->ri_rnum = 5; 442 ri->ri_gnum = 6; 443 ri->ri_bnum = 5; 444 ri->ri_rpos = 11; 445 ri->ri_gpos = 5; 446 ri->ri_bpos = 0; 447 break; 448 } 449 450 rasops_init(ri, sc->sc_height / 16, sc->sc_width / 8); 451 ri->ri_caps = WSSCREEN_WSCOLORS; 452 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 453 sc->sc_width / ri->ri_font->fontwidth); 454 455 ri->ri_hw = scr; 456 if (sc->sc_accel) { 457 ri->ri_ops.copyrows = uni_copyrows; 458 ri->ri_ops.copycols = uni_copycols; 459 ri->ri_ops.eraserows = uni_eraserows; 460 ri->ri_ops.erasecols = uni_erasecols; 461 ri->ri_ops.cursor = uni_cursor; 462 ri->ri_ops.putchar = uni_putchar; 463 } 464 465 return; 466 } 467 468 /* 469 * hardware access 470 */ 471 static uint8_t 472 uni_rd(struct unichromefb_softc *sc, int off, uint8_t idx) 473 { 474 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx); 475 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, off + 1); 476 } 477 478 static void 479 uni_wr(struct unichromefb_softc *sc, int off, uint8_t idx, uint8_t val) 480 { 481 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx); 482 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off + 1, val); 483 } 484 485 static void 486 uni_wr_mask(struct unichromefb_softc *sc, int off, uint8_t idx, 487 uint8_t val, uint8_t mask) 488 { 489 uint8_t tmp; 490 491 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx); 492 tmp = bus_space_read_1(sc->sc_iot, sc->sc_ioh, off + 1); 493 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off + 1, 494 ((val & mask) | (tmp & ~mask))); 495 } 496 497 static void 498 uni_wr_dac(struct unichromefb_softc *sc, uint8_t idx, 499 uint8_t r, uint8_t g, uint8_t b) 500 { 501 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_INDEX_WRITE, idx); 502 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, r); 503 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, g); 504 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, b); 505 } 506 507 static void 508 uni_wr_x(struct unichromefb_softc *sc, struct io_reg *tbl, int num) 509 { 510 int i; 511 uint8_t tmp; 512 513 for (i = 0; i < num; i++) { 514 bus_space_write_1(sc->sc_iot, sc->sc_ioh, tbl[i].port, 515 tbl[i].index); 516 tmp = bus_space_read_1(sc->sc_iot, sc->sc_iot, 517 tbl[i].port + 1); 518 tmp = (tmp & (~tbl[i].mask)) | tbl[i].value; 519 bus_space_write_1(sc->sc_iot, sc->sc_ioh, tbl[i].index + 1, 520 tmp); 521 } 522 } 523 524 /* 525 * helpers 526 */ 527 static struct VideoModeTable * 528 uni_getmode(int mode) 529 { 530 int i; 531 532 for (i = 0; i < NUM_TOTAL_MODETABLE; i++) 533 if (CLE266Modes[i].ModeIndex == mode) 534 return &CLE266Modes[i]; 535 536 return NULL; 537 } 538 539 static void 540 uni_setmode(struct unichromefb_softc *sc, int idx, int bpp) 541 { 542 struct VideoModeTable *vtbl; 543 struct crt_mode_table *crt; 544 int i; 545 546 /* XXX */ 547 vtbl = uni_getmode(idx); 548 if (vtbl == NULL) 549 panic("%s: unsupported mode: %d\n", sc->sc_dev.dv_xname, idx); 550 551 crt = vtbl->crtc; 552 553 uni_screen_disable(sc); 554 555 (void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus); 556 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, 0); 557 558 /* XXX assume CN900 for now */ 559 uni_wr_x(sc, CN900_ModeXregs, NUM_TOTAL_CN900_ModeXregs); 560 561 uni_crt_disable(sc); 562 563 /* Fill VPIT params */ 564 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, VPIT.Misc); 565 566 /* Write sequencer */ 567 for (i = 1; i <= StdSR; i++) { 568 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR, i); 569 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR + 1, 570 VPIT.SR[i - 1]); 571 } 572 573 uni_set_start(sc); 574 575 uni_set_crtc(sc, crt, idx, bpp / 8, IGA1); 576 577 for (i = 0; i < StdGR; i++) { 578 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAGR, i); 579 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAGR + 1, 580 VPIT.GR[i]); 581 } 582 583 for (i = 0; i < StdAR; i++) { 584 (void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus); 585 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, i); 586 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, 587 VPIT.AR[i]); 588 } 589 590 (void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus); 591 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, 0x20); 592 593 uni_set_crtc(sc, crt, idx, bpp / 8, IGA1); 594 /* set crt output path */ 595 uni_wr_mask(sc, VIASR, SR16, 0x00, BIT6); 596 597 uni_crt_enable(sc); 598 uni_screen_enable(sc); 599 600 return; 601 } 602 603 static void 604 uni_crt_lock(struct unichromefb_softc *sc) 605 { 606 uni_wr_mask(sc, VIACR, CR11, BIT7, BIT7); 607 } 608 609 static void 610 uni_crt_unlock(struct unichromefb_softc *sc) 611 { 612 uni_wr_mask(sc, VIACR, CR11, 0, BIT7); 613 uni_wr_mask(sc, VIACR, CR47, 0, BIT0); 614 } 615 616 static void 617 uni_crt_enable(struct unichromefb_softc *sc) 618 { 619 uni_wr_mask(sc, VIACR, CR36, 0, BIT5+BIT4); 620 } 621 622 static void 623 uni_crt_disable(struct unichromefb_softc *sc) 624 { 625 uni_wr_mask(sc, VIACR, CR36, BIT5+BIT4, BIT5+BIT4); 626 } 627 628 static void 629 uni_screen_enable(struct unichromefb_softc *sc) 630 { 631 uni_wr_mask(sc, VIASR, SR01, 0, BIT5); 632 } 633 634 static void 635 uni_screen_disable(struct unichromefb_softc *sc) 636 { 637 uni_wr_mask(sc, VIASR, SR01, 0x20, BIT5); 638 } 639 640 static void 641 uni_set_start(struct unichromefb_softc *sc) 642 { 643 uni_crt_unlock(sc); 644 645 uni_wr(sc, VIACR, CR0C, 0x00); 646 uni_wr(sc, VIACR, CR0D, 0x00); 647 uni_wr(sc, VIACR, CR34, 0x00); 648 uni_wr_mask(sc, VIACR, CR48, 0x00, BIT0 + BIT1); 649 650 uni_wr(sc, VIACR, CR62, 0x00); 651 uni_wr(sc, VIACR, CR63, 0x00); 652 uni_wr(sc, VIACR, CR64, 0x00); 653 uni_wr(sc, VIACR, CRA3, 0x00); 654 655 uni_crt_lock(sc); 656 } 657 658 static void 659 uni_set_crtc(struct unichromefb_softc *sc, struct crt_mode_table *ctbl, 660 int mode, int bpp_byte, int iga) 661 { 662 struct VideoModeTable *vtbl; 663 struct display_timing crtreg; 664 int i; 665 int index; 666 int haddr, vaddr; 667 uint8_t val; 668 uint32_t pll_d_n; 669 670 index = 0; 671 672 vtbl = uni_getmode(mode); 673 for (i = 0; i < vtbl->mode_array; i++) { 674 index = i; 675 if (ctbl[i].refresh_rate == 60) 676 break; 677 } 678 679 crtreg = ctbl[index].crtc; 680 681 haddr = crtreg.hor_addr; 682 vaddr = crtreg.ver_addr; 683 684 val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIARMisc); 685 if (ctbl[index].h_sync_polarity == NEGATIVE) { 686 if (ctbl[index].v_sync_polarity == NEGATIVE) 687 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, 688 (val & (~(BIT6+BIT7))) | (BIT6+BIT7)); 689 else 690 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, 691 (val & (~(BIT6+BIT7))) | (BIT6)); 692 } else { 693 if (ctbl[index].v_sync_polarity == NEGATIVE) 694 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, 695 (val & (~(BIT6+BIT7))) | (BIT7)); 696 else 697 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, 698 (val & (~(BIT6+BIT7)))); 699 } 700 701 if (iga == IGA1) { 702 uni_crt_unlock(sc); 703 uni_wr(sc, VIACR, CR09, 0x00); 704 uni_wr_mask(sc, VIACR, CR11, 0x00, BIT4+BIT5+BIT6); 705 uni_wr_mask(sc, VIACR, CR17, 0x00, BIT7); 706 } 707 708 uni_load_crtc(sc, crtreg, iga); 709 uni_fix_crtc(sc); 710 uni_crt_lock(sc); 711 uni_wr_mask(sc, VIACR, CR17, 0x80, BIT7); 712 713 uni_load_offset(sc, haddr, bpp_byte, iga); 714 uni_load_fetchcnt(sc, haddr, bpp_byte, iga); 715 uni_load_fifo(sc, iga, haddr, vaddr); 716 717 uni_set_depth(sc, bpp_byte, iga); 718 pll_d_n = uni_get_clkval(sc, ctbl[index].clk); 719 uni_set_vclk(sc, pll_d_n, iga); 720 } 721 722 static void 723 uni_load_crtc(struct unichromefb_softc *sc, 724 struct display_timing device_timing, int iga) 725 { 726 int regnum, val; 727 struct io_register *reg; 728 int i; 729 730 regnum = val = 0; 731 reg = NULL; 732 733 uni_crt_unlock(sc); 734 735 for (i = 0; i < 12; i++) { 736 switch (iga) { 737 case IGA1: 738 switch (i) { 739 case H_TOTAL_INDEX: 740 val = IGA1_HOR_TOTAL_FORMULA( 741 device_timing.hor_total); 742 regnum = iga1_crtc_reg.hor_total.reg_num; 743 reg = iga1_crtc_reg.hor_total.reg; 744 break; 745 case H_ADDR_INDEX: 746 val = IGA1_HOR_ADDR_FORMULA( 747 device_timing.hor_addr); 748 regnum = iga1_crtc_reg.hor_addr.reg_num; 749 reg = iga1_crtc_reg.hor_addr.reg; 750 break; 751 case H_BLANK_START_INDEX: 752 val = IGA1_HOR_BLANK_START_FORMULA( 753 device_timing.hor_blank_start); 754 regnum = iga1_crtc_reg.hor_blank_start.reg_num; 755 reg = iga1_crtc_reg.hor_blank_start.reg; 756 break; 757 case H_BLANK_END_INDEX: 758 val = IGA1_HOR_BLANK_END_FORMULA( 759 device_timing.hor_blank_start, 760 device_timing.hor_blank_end); 761 regnum = iga1_crtc_reg.hor_blank_end.reg_num; 762 reg = iga1_crtc_reg.hor_blank_end.reg; 763 break; 764 case H_SYNC_START_INDEX: 765 val = IGA1_HOR_SYNC_START_FORMULA( 766 device_timing.hor_sync_start); 767 regnum = iga1_crtc_reg.hor_sync_start.reg_num; 768 reg = iga1_crtc_reg.hor_sync_start.reg; 769 break; 770 case H_SYNC_END_INDEX: 771 val = IGA1_HOR_SYNC_END_FORMULA( 772 device_timing.hor_sync_start, 773 device_timing.hor_sync_end); 774 regnum = iga1_crtc_reg.hor_sync_end.reg_num; 775 reg = iga1_crtc_reg.hor_sync_end.reg; 776 break; 777 case V_TOTAL_INDEX: 778 val = IGA1_VER_TOTAL_FORMULA( 779 device_timing.ver_total); 780 regnum = iga1_crtc_reg.ver_total.reg_num; 781 reg = iga1_crtc_reg.ver_total.reg; 782 break; 783 case V_ADDR_INDEX: 784 val = IGA1_VER_ADDR_FORMULA( 785 device_timing.ver_addr); 786 regnum = iga1_crtc_reg.ver_addr.reg_num; 787 reg = iga1_crtc_reg.ver_addr.reg; 788 break; 789 case V_BLANK_START_INDEX: 790 val = IGA1_VER_BLANK_START_FORMULA( 791 device_timing.ver_blank_start); 792 regnum = iga1_crtc_reg.ver_blank_start.reg_num; 793 reg = iga1_crtc_reg.ver_blank_start.reg; 794 break; 795 case V_BLANK_END_INDEX: 796 val = IGA1_VER_BLANK_END_FORMULA( 797 device_timing.ver_blank_start, 798 device_timing.ver_blank_end); 799 regnum = iga1_crtc_reg.ver_blank_end.reg_num; 800 reg = iga1_crtc_reg.ver_blank_end.reg; 801 break; 802 case V_SYNC_START_INDEX: 803 val = IGA1_VER_SYNC_START_FORMULA( 804 device_timing.ver_sync_start); 805 regnum = iga1_crtc_reg.ver_sync_start.reg_num; 806 reg = iga1_crtc_reg.ver_sync_start.reg; 807 break; 808 case V_SYNC_END_INDEX: 809 val = IGA1_VER_SYNC_END_FORMULA( 810 device_timing.ver_sync_start, 811 device_timing.ver_sync_end); 812 regnum = iga1_crtc_reg.ver_sync_end.reg_num; 813 reg = iga1_crtc_reg.ver_sync_end.reg; 814 break; 815 default: 816 printf("%s: unknown index %d while setting up CRTC\n", 817 sc->sc_dev.dv_xname, i); 818 break; 819 } 820 break; 821 case IGA2: 822 printf("%s: %s: IGA2 not supported\n", 823 sc->sc_dev.dv_xname, __func__); 824 break; 825 } 826 827 uni_load_reg(sc, val, regnum, reg, VIACR); 828 } 829 830 uni_crt_lock(sc); 831 } 832 833 static void 834 uni_load_reg(struct unichromefb_softc *sc, int timing, int regnum, 835 struct io_register *reg, int type) 836 { 837 int regmask, bitnum, data; 838 int i, j; 839 int shift_next_reg; 840 int startidx, endidx, cridx; 841 uint16_t getbit; 842 843 bitnum = 0; 844 845 for (i = 0; i < regnum; i++) { 846 regmask = data = 0; 847 startidx = reg[i].start_bit; 848 endidx = reg[i].end_bit; 849 cridx = reg[i].io_addr; 850 851 shift_next_reg = bitnum; 852 853 for (j = startidx; j <= endidx; j++) { 854 regmask = regmask | (BIT0 << j); 855 getbit = (timing & (BIT0 << bitnum)); 856 data = data | ((getbit >> shift_next_reg) << startidx); 857 ++bitnum; 858 } 859 860 if (type == VIACR) 861 uni_wr_mask(sc, VIACR, cridx, data, regmask); 862 else 863 uni_wr_mask(sc, VIASR, cridx, data, regmask); 864 } 865 866 return; 867 } 868 869 static void 870 uni_fix_crtc(struct unichromefb_softc *sc) 871 { 872 uni_wr_mask(sc, VIACR, CR03, 0x80, BIT7); 873 uni_wr(sc, VIACR, CR18, 0xff); 874 uni_wr_mask(sc, VIACR, CR07, 0x10, BIT4); 875 uni_wr_mask(sc, VIACR, CR09, 0x40, BIT6); 876 uni_wr_mask(sc, VIACR, CR35, 0x10, BIT4); 877 uni_wr_mask(sc, VIACR, CR33, 0x06, BIT0+BIT1+BIT2); 878 uni_wr(sc, VIACR, CR17, 0xe3); 879 uni_wr(sc, VIACR, CR08, 0x00); 880 uni_wr(sc, VIACR, CR14, 0x00); 881 882 return; 883 } 884 885 static void 886 uni_load_offset(struct unichromefb_softc *sc, int haddr, int bpp, int iga) 887 { 888 889 switch (iga) { 890 case IGA1: 891 uni_load_reg(sc, 892 IGA1_OFFSET_FORMULA(haddr, bpp), 893 offset_reg.iga1_offset_reg.reg_num, 894 offset_reg.iga1_offset_reg.reg, 895 VIACR); 896 break; 897 default: 898 printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname, 899 __func__); 900 break; 901 } 902 903 return; 904 } 905 906 static void 907 uni_load_fetchcnt(struct unichromefb_softc *sc, int haddr, int bpp, int iga) 908 { 909 910 switch (iga) { 911 case IGA1: 912 uni_load_reg(sc, 913 IGA1_FETCH_COUNT_FORMULA(haddr, bpp), 914 fetch_count_reg.iga1_fetch_count_reg.reg_num, 915 fetch_count_reg.iga1_fetch_count_reg.reg, 916 VIASR); 917 break; 918 default: 919 printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname, 920 __func__); 921 break; 922 } 923 924 return; 925 } 926 927 static void 928 uni_load_fifo(struct unichromefb_softc *sc, int iga, int horact, int veract) 929 { 930 int val, regnum; 931 struct io_register *reg; 932 int iga1_fifo_max_depth, iga1_fifo_threshold; 933 int iga1_fifo_high_threshold, iga1_display_queue_expire_num; 934 935 reg = NULL; 936 iga1_fifo_max_depth = iga1_fifo_threshold = 0; 937 iga1_fifo_high_threshold = iga1_display_queue_expire_num = 0; 938 939 switch (iga) { 940 case IGA1: 941 /* XXX if (type == CN900) { */ 942 iga1_fifo_max_depth = CN900_IGA1_FIFO_MAX_DEPTH; 943 iga1_fifo_threshold = CN900_IGA1_FIFO_THRESHOLD; 944 iga1_fifo_high_threshold = CN900_IGA1_FIFO_HIGH_THRESHOLD; 945 if (horact > 1280 && veract > 1024) 946 iga1_display_queue_expire_num = 16; 947 else 948 iga1_display_queue_expire_num = 949 CN900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; 950 /* XXX } */ 951 952 /* set display FIFO depth select */ 953 val = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth); 954 regnum = 955 display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num; 956 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg; 957 uni_load_reg(sc, val, regnum, reg, VIASR); 958 959 /* set display FIFO threshold select */ 960 val = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold); 961 regnum = fifo_threshold_select_reg.iga1_fifo_threshold_select_reg.reg_num; 962 reg = fifo_threshold_select_reg.iga1_fifo_threshold_select_reg.reg; 963 uni_load_reg(sc, val, regnum, reg, VIASR); 964 965 /* set display FIFO high threshold select */ 966 val = IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold); 967 regnum = fifo_high_threshold_select_reg.iga1_fifo_high_threshold_select_reg.reg_num; 968 reg = fifo_high_threshold_select_reg.iga1_fifo_high_threshold_select_reg.reg; 969 uni_load_reg(sc, val, regnum, reg, VIASR); 970 971 /* set display queue expire num */ 972 val = IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(iga1_display_queue_expire_num); 973 regnum = display_queue_expire_num_reg.iga1_display_queue_expire_num_reg.reg_num; 974 reg = display_queue_expire_num_reg.iga1_display_queue_expire_num_reg.reg; 975 uni_load_reg(sc, val, regnum, reg, VIASR); 976 977 break; 978 default: 979 printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname, 980 __func__); 981 break; 982 } 983 984 return; 985 } 986 987 static void 988 uni_set_depth(struct unichromefb_softc *sc, int bpp, int iga) 989 { 990 switch (iga) { 991 case IGA1: 992 switch (bpp) { 993 case MODE_32BPP: 994 uni_wr_mask(sc, VIASR, SR15, 0xae, 0xfe); 995 break; 996 case MODE_16BPP: 997 uni_wr_mask(sc, VIASR, SR15, 0xb6, 0xfe); 998 break; 999 case MODE_8BPP: 1000 uni_wr_mask(sc, VIASR, SR15, 0x22, 0xfe); 1001 break; 1002 default: 1003 printf("%s: %s: mode (%d) unsupported\n", 1004 sc->sc_dev.dv_xname, __func__, bpp); 1005 } 1006 break; 1007 default: 1008 printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname, 1009 __func__); 1010 break; 1011 } 1012 } 1013 1014 static uint32_t 1015 uni_get_clkval(struct unichromefb_softc *sc, int clk) 1016 { 1017 int i; 1018 1019 for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) { 1020 if (clk == pll_value[i].clk) { 1021 /* XXX only CN900 supported for now */ 1022 return pll_value[i].k800_pll; 1023 } 1024 } 1025 1026 aprint_error("%s: can't find matching PLL value\n", 1027 sc->sc_dev.dv_xname); 1028 1029 return 0; 1030 } 1031 1032 static void 1033 uni_set_vclk(struct unichromefb_softc *sc, uint32_t clk, int iga) 1034 { 1035 uint8_t val; 1036 1037 /* hardware reset on */ 1038 uni_wr_mask(sc, VIACR, CR17, 0x00, BIT7); 1039 1040 switch (iga) { 1041 case IGA1: 1042 /* XXX only CN900 is supported */ 1043 uni_wr(sc, VIASR, SR44, clk / 0x10000); 1044 uni_wr(sc, VIASR, SR45, (clk & 0xffff) / 0x100); 1045 uni_wr(sc, VIASR, SR46, clk % 0x100); 1046 break; 1047 default: 1048 printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname, 1049 __func__); 1050 break; 1051 } 1052 1053 /* hardware reset off */ 1054 uni_wr_mask(sc, VIACR, CR17, 0x80, BIT7); 1055 1056 /* reset pll */ 1057 switch (iga) { 1058 case IGA1: 1059 uni_wr_mask(sc, VIASR, SR40, 0x02, BIT1); 1060 uni_wr_mask(sc, VIASR, SR40, 0x00, BIT1); 1061 break; 1062 } 1063 1064 /* good to go */ 1065 val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIARMisc); 1066 val |= (BIT2+BIT3); 1067 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, val); 1068 1069 return; 1070 } 1071 1072 static void 1073 uni_init_dac(struct unichromefb_softc *sc, int iga) 1074 { 1075 int i; 1076 1077 /* XXX only IGA1 for now */ 1078 uni_wr_mask(sc, VIASR, SR1A, 0x00, BIT0); 1079 uni_wr_mask(sc, VIASR, SR18, 0x00, BIT7+BIT6); 1080 for (i = 0; i < 256; i++) 1081 uni_wr_dac(sc, i, 1082 palLUT_table[i].red, palLUT_table[i].green, palLUT_table[i].blue); 1083 1084 uni_wr_mask(sc, VIASR, SR18, 0xc0, BIT7+BIT6); 1085 1086 return; 1087 } 1088 1089 static void 1090 uni_init_accel(struct unichromefb_softc *sc) 1091 { 1092 1093 /* init 2D engine regs to reset 2D engine */ 1094 MMIO_OUT32(VIA_REG_GEMODE, 0); 1095 MMIO_OUT32(VIA_REG_SRCPOS, 0); 1096 MMIO_OUT32(VIA_REG_DSTPOS, 0); 1097 MMIO_OUT32(VIA_REG_DIMENSION, 0); 1098 MMIO_OUT32(VIA_REG_PATADDR, 0); 1099 MMIO_OUT32(VIA_REG_FGCOLOR, 0); 1100 MMIO_OUT32(VIA_REG_BGCOLOR, 0); 1101 MMIO_OUT32(VIA_REG_CLIPTL, 0); 1102 MMIO_OUT32(VIA_REG_CLIPBR, 0); 1103 MMIO_OUT32(VIA_REG_OFFSET, 0); 1104 MMIO_OUT32(VIA_REG_KEYCONTROL, 0); 1105 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1106 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1107 MMIO_OUT32(VIA_REG_PITCH, 0); 1108 MMIO_OUT32(VIA_REG_MONOPAT1, 0); 1109 1110 /* init AGP and VQ registers */ 1111 MMIO_OUT32(VIA_REG_TRANSET, 0x00100000); 1112 MMIO_OUT32(VIA_REG_TRANSPACE, 0x00000000); 1113 MMIO_OUT32(VIA_REG_TRANSPACE, 0x00333004); 1114 MMIO_OUT32(VIA_REG_TRANSPACE, 0x60000000); 1115 MMIO_OUT32(VIA_REG_TRANSPACE, 0x61000000); 1116 MMIO_OUT32(VIA_REG_TRANSPACE, 0x62000000); 1117 MMIO_OUT32(VIA_REG_TRANSPACE, 0x63000000); 1118 MMIO_OUT32(VIA_REG_TRANSPACE, 0x64000000); 1119 MMIO_OUT32(VIA_REG_TRANSPACE, 0x7d000000); 1120 1121 MMIO_OUT32(VIA_REG_TRANSET, 0xfe020000); 1122 MMIO_OUT32(VIA_REG_TRANSPACE, 0x00000000); 1123 1124 /* disable VQ */ 1125 MMIO_OUT32(VIA_REG_TRANSET, 0x00fe0000); 1126 MMIO_OUT32(VIA_REG_TRANSPACE, 0x00000004); 1127 MMIO_OUT32(VIA_REG_TRANSPACE, 0x40008c0f); 1128 MMIO_OUT32(VIA_REG_TRANSPACE, 0x44000000); 1129 MMIO_OUT32(VIA_REG_TRANSPACE, 0x45080c04); 1130 MMIO_OUT32(VIA_REG_TRANSPACE, 0x46800408); 1131 1132 uni_set_accel_depth(sc); 1133 1134 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1135 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1136 1137 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1138 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1139 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1140 1141 return; 1142 } 1143 1144 static void 1145 uni_set_accel_depth(struct unichromefb_softc *sc) 1146 { 1147 uint32_t gemode; 1148 1149 gemode = MMIO_IN32(0x04) & 0xfffffcff; 1150 1151 switch (sc->sc_depth) { 1152 case 32: 1153 gemode |= VIA_GEM_32bpp; 1154 break; 1155 case 16: 1156 gemode |= VIA_GEM_16bpp; 1157 break; 1158 default: 1159 gemode |= VIA_GEM_8bpp; 1160 break; 1161 } 1162 1163 /* set colour depth and pitch */ 1164 MMIO_OUT32(VIA_REG_GEMODE, gemode); 1165 1166 return; 1167 } 1168 1169 static void 1170 uni_wait_idle(struct unichromefb_softc *sc) 1171 { 1172 int loop = 0; 1173 1174 while (!(MMIO_IN32(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && 1175 (loop++ < MAXLOOP)) 1176 ; 1177 1178 while ((MMIO_IN32(VIA_REG_STATUS) & 1179 (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) && 1180 (loop++ < MAXLOOP)) 1181 ; 1182 1183 if (loop >= MAXLOOP) 1184 aprint_error("%s: engine stall\n", sc->sc_dev.dv_xname); 1185 1186 return; 1187 } 1188 1189 static void 1190 uni_fillrect(struct unichromefb_softc *sc, int x, int y, int width, 1191 int height, int colour) 1192 { 1193 1194 uni_wait_idle(sc); 1195 1196 MMIO_OUT32(VIA_REG_SRCPOS, 0); 1197 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1198 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1199 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1200 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1201 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1202 MMIO_OUT32(VIA_REG_DSTPOS, ((y << 16) | x)); 1203 MMIO_OUT32(VIA_REG_DIMENSION, 1204 (((height - 1) << 16) | (width - 1))); 1205 MMIO_OUT32(VIA_REG_FGCOLOR, colour); 1206 MMIO_OUT32(VIA_REG_GECMD, (0x01 | 0x2000 | 0xf0 << 24)); 1207 1208 return; 1209 } 1210 1211 static void 1212 uni_rectinvert(struct unichromefb_softc *sc, int x, int y, int width, 1213 int height) 1214 { 1215 1216 uni_wait_idle(sc); 1217 1218 MMIO_OUT32(VIA_REG_SRCPOS, 0); 1219 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1220 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1221 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1222 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1223 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1224 MMIO_OUT32(VIA_REG_DSTPOS, ((y << 16) | x)); 1225 MMIO_OUT32(VIA_REG_DIMENSION, 1226 (((height - 1) << 16) | (width - 1))); 1227 MMIO_OUT32(VIA_REG_GECMD, (0x01 | 0x2000 | 0x55 << 24)); 1228 1229 return; 1230 } 1231 1232 static void 1233 uni_bitblit(struct unichromefb_softc *sc, int xs, int ys, int xd, int yd, int width, int height) 1234 { 1235 uint32_t dir; 1236 1237 dir = 0; 1238 1239 if (ys < yd) { 1240 yd += height - 1; 1241 ys += height - 1; 1242 dir |= 0x4000; 1243 } 1244 1245 if (xs < xd) { 1246 xd += width - 1; 1247 xs += width - 1; 1248 dir |= 0x8000; 1249 } 1250 1251 uni_wait_idle(sc); 1252 1253 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1254 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1255 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1256 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1257 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1258 MMIO_OUT32(VIA_REG_SRCPOS, ys << 16 | xs); 1259 MMIO_OUT32(VIA_REG_DSTPOS, yd << 16 | xd); 1260 MMIO_OUT32(VIA_REG_DIMENSION, ((height - 1) << 16) | (width - 1)); 1261 MMIO_OUT32(VIA_REG_GECMD, (0x01 | dir | (0xcc << 24))); 1262 1263 return; 1264 } 1265 1266 static void 1267 uni_setup_mono(struct unichromefb_softc *sc, int xd, int yd, int width, int height, 1268 uint32_t fg, uint32_t bg) 1269 { 1270 1271 uni_wait_idle(sc); 1272 1273 MMIO_OUT32(VIA_REG_SRCBASE, 0); 1274 MMIO_OUT32(VIA_REG_DSTBASE, 0); 1275 MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE | 1276 (((sc->sc_width * sc->sc_depth >> 3) >> 3) | 1277 (((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16))); 1278 MMIO_OUT32(VIA_REG_SRCPOS, 0); 1279 MMIO_OUT32(VIA_REG_DSTPOS, (yd << 16) | xd); 1280 MMIO_OUT32(VIA_REG_DIMENSION, ((height - 1) << 16) | (width - 1)); 1281 MMIO_OUT32(VIA_REG_FGCOLOR, fg); 1282 MMIO_OUT32(VIA_REG_BGCOLOR, bg); 1283 MMIO_OUT32(VIA_REG_GECMD, 0xcc020142); 1284 1285 return; 1286 } 1287 1288 #if notyet 1289 static void 1290 uni_cursor_show(struct unichromefb_softc *sc) 1291 { 1292 uint32_t val; 1293 1294 val = MMIO_IN32(VIA_REG_CURSOR_MODE); 1295 val |= 1; 1296 MMIO_OUT32(VIA_REG_CURSOR_MODE, val); 1297 1298 return; 1299 } 1300 1301 static void 1302 uni_cursor_hide(struct unichromefb_softc *sc) 1303 { 1304 uint32_t val; 1305 1306 val = MMIO_IN32(VIA_REG_CURSOR_MODE); 1307 val &= 0xfffffffe; 1308 MMIO_OUT32(VIA_REG_CURSOR_MODE, val); 1309 1310 return; 1311 } 1312 #endif 1313 1314 /* 1315 * rasops glue 1316 */ 1317 static void 1318 uni_copycols(void *opaque, int row, int srccol, int dstcol, int ncols) 1319 { 1320 struct rasops_info *ri; 1321 struct vcons_screen *scr; 1322 struct unichromefb_softc *sc; 1323 int xs, xd, y, width, height; 1324 1325 ri = (struct rasops_info *)opaque; 1326 scr = (struct vcons_screen *)ri->ri_hw; 1327 sc = (struct unichromefb_softc *)scr->scr_cookie; 1328 1329 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1330 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1331 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1332 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1333 width = ri->ri_font->fontwidth * ncols; 1334 height = ri->ri_font->fontheight; 1335 uni_bitblit(sc, xs, y, xd, y, width, height); 1336 } 1337 1338 return; 1339 } 1340 1341 static void 1342 uni_copyrows(void *opaque, int srcrow, int dstrow, int nrows) 1343 { 1344 struct rasops_info *ri; 1345 struct vcons_screen *scr; 1346 struct unichromefb_softc *sc; 1347 int x, ys, yd, width, height; 1348 1349 ri = (struct rasops_info *)opaque; 1350 scr = (struct vcons_screen *)ri->ri_hw; 1351 sc = (struct unichromefb_softc *)scr->scr_cookie; 1352 1353 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1354 x = ri->ri_xorigin; 1355 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1356 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1357 width = ri->ri_emuwidth; 1358 height = ri->ri_font->fontheight * nrows; 1359 uni_bitblit(sc, x, ys, x, yd, width, height); 1360 } 1361 1362 return; 1363 } 1364 1365 static void 1366 uni_erasecols(void *opaque, int row, int startcol, int ncols, long fillattr) 1367 { 1368 struct rasops_info *ri; 1369 struct vcons_screen *scr; 1370 struct unichromefb_softc *sc; 1371 int x, y, width, height, fg, bg, ul; 1372 1373 ri = (struct rasops_info *)opaque; 1374 scr = (struct vcons_screen *)ri->ri_hw; 1375 sc = (struct unichromefb_softc *)scr->scr_cookie; 1376 1377 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1378 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1379 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1380 width = ri->ri_font->fontwidth * ncols; 1381 height = ri->ri_font->fontheight; 1382 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1383 uni_fillrect(sc, x, y, width, height, ri->ri_devcmap[bg]); 1384 } 1385 1386 return; 1387 } 1388 1389 static void 1390 uni_eraserows(void *opaque, int row, int nrows, long fillattr) 1391 { 1392 struct rasops_info *ri; 1393 struct vcons_screen *scr; 1394 struct unichromefb_softc *sc; 1395 int x, y, width, height, fg, bg, ul; 1396 1397 ri = (struct rasops_info *)opaque; 1398 scr = (struct vcons_screen *)ri->ri_hw; 1399 sc = (struct unichromefb_softc *)scr->scr_cookie; 1400 1401 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1402 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1403 if ((row == 0) && (nrows == ri->ri_rows)) { 1404 /* clear the whole screen */ 1405 uni_fillrect(sc, 0, 0, ri->ri_width, 1406 ri->ri_height, ri->ri_devcmap[bg]); 1407 } else { 1408 x = ri->ri_xorigin; 1409 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1410 width = ri->ri_emuwidth; 1411 height = ri->ri_font->fontheight * nrows; 1412 uni_fillrect(sc, x, y, width, height, 1413 ri->ri_devcmap[bg]); 1414 } 1415 } 1416 1417 return; 1418 } 1419 1420 static void 1421 uni_cursor(void *opaque, int on, int row, int col) 1422 { 1423 struct rasops_info *ri; 1424 struct vcons_screen *scr; 1425 struct unichromefb_softc *sc; 1426 int x, y, wi, he; 1427 1428 ri = (struct rasops_info *)opaque; 1429 scr = (struct vcons_screen *)ri->ri_hw; 1430 sc = (struct unichromefb_softc *)scr->scr_cookie; 1431 1432 uni_wait_idle(sc); 1433 1434 wi = ri->ri_font->fontwidth; 1435 he = ri->ri_font->fontheight; 1436 1437 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1438 x = ri->ri_ccol * wi + ri->ri_xorigin; 1439 y = ri->ri_crow * he + ri->ri_yorigin; 1440 if (ri->ri_flg & RI_CURSOR) { 1441 uni_rectinvert(sc, x, y, wi, he); 1442 ri->ri_flg &= ~RI_CURSOR; 1443 } 1444 ri->ri_crow = row; 1445 ri->ri_ccol = col; 1446 if (on) { 1447 x = ri->ri_ccol * wi + ri->ri_xorigin; 1448 y = ri->ri_crow * he + ri->ri_yorigin; 1449 uni_rectinvert(sc, x, y, wi, he); 1450 ri->ri_flg |= RI_CURSOR; 1451 } 1452 } else { 1453 ri->ri_flg &= ~RI_CURSOR; 1454 ri->ri_crow = row; 1455 ri->ri_ccol = col; 1456 } 1457 1458 return; 1459 } 1460 1461 static void 1462 uni_putchar(void *opaque, int row, int col, u_int c, long attr) 1463 { 1464 struct rasops_info *ri; 1465 struct vcons_screen *scr; 1466 struct unichromefb_softc *sc; 1467 1468 ri = (struct rasops_info *)opaque; 1469 scr = (struct vcons_screen *)ri->ri_hw; 1470 sc = (struct unichromefb_softc *)scr->scr_cookie; 1471 1472 if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) { 1473 uint32_t *data; 1474 int fg, bg, ul, uc, i; 1475 int x, y, wi, he; 1476 1477 wi = ri->ri_font->fontwidth; 1478 he = ri->ri_font->fontheight; 1479 1480 if (!CHAR_IN_FONT(c, ri->ri_font)) 1481 return; 1482 1483 rasops_unpack_attr(attr, &fg, &bg, &ul); 1484 x = ri->ri_xorigin + col * wi; 1485 y = ri->ri_yorigin + row * he; 1486 if (c == 0x20) 1487 uni_fillrect(sc, x, y, wi, he, ri->ri_devcmap[bg]); 1488 else { 1489 uc = c - ri->ri_font->firstchar; 1490 data = (uint32_t *)((uint8_t *)ri->ri_font->data + 1491 uc * ri->ri_fontscale); 1492 uni_setup_mono(sc, x, y, wi, he, 1493 ri->ri_devcmap[fg], ri->ri_devcmap[bg]); 1494 for (i = 0; i < (wi * he) / 4; i++) { 1495 MMIO_OUT32(VIA_MMIO_BLTBASE, *data); 1496 data++; 1497 } 1498 } 1499 } 1500 1501 return; 1502 } 1503
Indexes created Tue Sep 30 20:09:53 GMT 2025