universe_pci.c revision 1.2
1 /* $NetBSD: universe_pci.c,v 1.2 2000/03/12 11:21:02 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1999 5 * Matthias Drochner. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Common functions for PCI-VME-interfaces using the 31 * Newbridge/Tundra Universe II chip (CA91C142). 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 /*#include <dev/pci/pcidevs.h>*/ 41 42 #include <machine/bus.h> 43 44 #include <dev/vme/vmereg.h> 45 #include <dev/vme/vmevar.h> 46 47 #include <dev/ic/universereg.h> 48 #include <dev/pci/universe_pci_var.h> 49 50 int univ_pci_intr __P((void *)); 51 52 #define read_csr_4(d, reg) \ 53 bus_space_read_4(d->csrt, d->csrh, offsetof(struct universereg, reg)) 54 #define write_csr_4(d, reg, val) \ 55 bus_space_write_4(d->csrt, d->csrh, offsetof(struct universereg, reg), val) 56 57 #define _pso(i) offsetof(struct universereg, __CONCAT(pcislv, i)) 58 static int pcislvoffsets[8] = { 59 _pso(0), _pso(1), _pso(2), _pso(3), 60 _pso(4), _pso(5), _pso(6), _pso(7) 61 }; 62 #undef _pso 63 64 #define read_pcislv(d, idx, reg) \ 65 bus_space_read_4(d->csrt, d->csrh, \ 66 pcislvoffsets[idx] + offsetof(struct universe_pcislvimg, reg)) 67 #define write_pcislv(d, idx, reg, val) \ 68 bus_space_write_4(d->csrt, d->csrh, \ 69 pcislvoffsets[idx] + offsetof(struct universe_pcislvimg, reg), val) 70 71 72 #define _vso(i) offsetof(struct universereg, __CONCAT(vmeslv, i)) 73 static int vmeslvoffsets[8] = { 74 _vso(0), _vso(1), _vso(2), _vso(3), 75 _vso(4), _vso(5), _vso(6), _vso(7) 76 }; 77 #undef _vso 78 79 #define read_vmeslv(d, idx, reg) \ 80 bus_space_read_4(d->csrt, d->csrh, \ 81 vmeslvoffsets[idx] + offsetof(struct universe_vmeslvimg, reg)) 82 #define write_vmeslv(d, idx, reg, val) \ 83 bus_space_write_4(d->csrt, d->csrh, \ 84 vmeslvoffsets[idx] + offsetof(struct universe_vmeslvimg, reg), val) 85 86 int 87 univ_pci_attach(d, pa, name, inthdl, intcookie) 88 struct univ_pci_data *d; 89 struct pci_attach_args *pa; 90 const char *name; 91 void (*inthdl) __P((void *, int, int)); 92 void *intcookie; 93 { 94 pci_chipset_tag_t pc = pa->pa_pc; 95 pci_intr_handle_t ih; 96 const char *intrstr = NULL; 97 u_int32_t reg; 98 int i; 99 100 d->pc = pc; 101 strncpy(d->devname, name, sizeof(d->devname)); 102 d->devname[sizeof(d->devname) - 1] = '\0'; 103 104 if (pci_mapreg_map(pa, 0x10, 105 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 106 0, &d->csrt, &d->csrh, NULL, NULL) && 107 pci_mapreg_map(pa, 0x14, 108 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 109 0, &d->csrt, &d->csrh, NULL, NULL) && 110 pci_mapreg_map(pa, 0x10, 111 PCI_MAPREG_TYPE_IO, 112 0, &d->csrt, &d->csrh, NULL, NULL) && 113 pci_mapreg_map(pa, 0x14, 114 PCI_MAPREG_TYPE_IO, 115 0, &d->csrt, &d->csrh, NULL, NULL)) 116 return (-1); 117 118 /* name sure the chip is in a sane state */ 119 write_csr_4(d, lint_en, 0); /* mask all PCI interrupts */ 120 write_csr_4(d, vint_en, 0); /* mask all VME interrupts */ 121 write_csr_4(d, dgcs, 0x40000000); /* stop DMA activity */ 122 for (i = 0; i < 8; i++) { 123 univ_pci_unmapvme(d, i); 124 univ_pci_unmappci(d, i); 125 } 126 write_csr_4(d, slsi, 0); /* disable "special PCI slave image" */ 127 128 /* enable DMA */ 129 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 130 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 131 PCI_COMMAND_MASTER_ENABLE); 132 133 reg = read_csr_4(d, misc_ctl); 134 printf("%s: ", name); 135 if (reg & 0x00020000) /* SYSCON */ 136 printf("VME bus controller, "); 137 reg = read_csr_4(d, mast_ctl); 138 printf("requesting at VME bus level %d\n", (reg >> 22) & 3); 139 140 /* Map and establish the PCI interrupt. */ 141 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 142 pa->pa_intrline, &ih)) { 143 printf("%s: couldn't map interrupt\n", name); 144 return (-1); 145 } 146 intrstr = pci_intr_string(pc, ih); 147 /* 148 * Use a low interrupt level (the lowest?). 149 * We will raise before calling a subdevice's handler. 150 */ 151 d->ih = pci_intr_establish(pc, ih, IPL_BIO, univ_pci_intr, d); 152 if (d->ih == NULL) { 153 printf("%s: couldn't establish interrupt", name); 154 if (intrstr != NULL) 155 printf(" at %s", intrstr); 156 printf("\n"); 157 return (-1); 158 } 159 printf("%s: interrupting at %s\n", name, intrstr); 160 161 /* handle all VME interrupts (XXX should be configurable) */ 162 d->vmeinthandler = inthdl; 163 d->vmeintcookie = intcookie; 164 write_csr_4(d, lint_stat, 0x00ff37ff); /* ack all pending IRQs */ 165 write_csr_4(d, lint_en, 0x000000fe); /* enable VME IRQ 1..7 */ 166 167 return (0); 168 } 169 170 int 171 univ_pci_mapvme(d, wnd, vmebase, len, am, datawidth, pcibase) 172 struct univ_pci_data *d; 173 int wnd; 174 vme_addr_t vmebase; 175 u_int32_t len; 176 vme_am_t am; 177 vme_datasize_t datawidth; 178 u_int32_t pcibase; 179 { 180 u_int32_t ctl = 0x80000000; 181 182 switch (am & VME_AM_ADRSIZEMASK) { 183 case VME_AM_A32: 184 ctl |= 0x00020000; 185 break; 186 case VME_AM_A24: 187 ctl |= 0x00010000; 188 break; 189 case VME_AM_A16: 190 break; 191 default: 192 return (EINVAL); 193 } 194 if (am & VME_AM_SUPER) 195 ctl |= 0x00001000; 196 if ((am & VME_AM_MODEMASK) == VME_AM_PRG) 197 ctl |= 0x00004000; 198 if (datawidth & VME_D32) 199 ctl |= 0x00800000; 200 else if (datawidth & VME_D16) 201 ctl |= 0x00400000; 202 else if (!(datawidth & VME_D8)) 203 return (EINVAL); 204 205 #ifdef UNIV_DEBUG 206 printf("%s: wnd %d, map VME %x-%x to %x, ctl=%x\n", 207 d->devname, wnd, vmebase, vmebase + len, pcibase, ctl); 208 #endif 209 210 write_pcislv(d, wnd, lsi_bs, pcibase); 211 write_pcislv(d, wnd, lsi_bd, pcibase + len); 212 write_pcislv(d, wnd, lsi_to, vmebase - pcibase); 213 write_pcislv(d, wnd, lsi_ctl, ctl); 214 return (0); 215 } 216 217 void 218 univ_pci_unmapvme(d, wnd) 219 struct univ_pci_data *d; 220 int wnd; 221 { 222 #ifdef UNIV_DEBUG 223 printf("%s: unmap VME wnd %d\n", d->devname, wnd); 224 #endif 225 write_pcislv(d, wnd, lsi_ctl, 0); 226 } 227 228 229 int 230 univ_pci_mappci(d, wnd, pcibase, len, vmebase, am) 231 struct univ_pci_data *d; 232 int wnd; 233 u_int32_t pcibase; 234 u_int32_t len; 235 vme_addr_t vmebase; 236 vme_am_t am; 237 { 238 u_int32_t ctl = 0x80000000; 239 240 switch (am & VME_AM_ADRSIZEMASK) { 241 case VME_AM_A32: 242 ctl |= 0x00020000; 243 break; 244 case VME_AM_A24: 245 ctl |= 0x00010000; 246 break; 247 case VME_AM_A16: 248 break; 249 default: 250 return (EINVAL); 251 } 252 if (am & VME_AM_SUPER) 253 ctl |= 0x00200000; 254 else 255 ctl |= 0x00300000; /* both */ 256 if ((am & VME_AM_MODEMASK) == VME_AM_PRG) 257 ctl |= 0x00800000; 258 else 259 ctl |= 0x00c00000; /* both */ 260 261 #ifdef UNIV_DEBUG 262 printf("%s: wnd %d, map PCI %x-%x to %x, ctl=%x\n", 263 d->devname, wnd, pcibase, pcibase + len, vmebase, ctl); 264 #endif 265 266 write_vmeslv(d, wnd, vsi_bs, vmebase); 267 write_vmeslv(d, wnd, vsi_bd, vmebase + len); 268 write_vmeslv(d, wnd, vsi_to, pcibase - vmebase); 269 write_vmeslv(d, wnd, vsi_ctl, ctl); 270 return (0); 271 } 272 273 void 274 univ_pci_unmappci(d, wnd) 275 struct univ_pci_data *d; 276 int wnd; 277 { 278 #ifdef UNIV_DEBUG 279 printf("%s: unmap PCI wnd %d\n", d->devname, wnd); 280 #endif 281 write_vmeslv(d, wnd, vsi_ctl, 0); 282 } 283 284 int 285 univ_pci_vmebuserr(d, clear) 286 struct univ_pci_data *d; 287 int clear; 288 { 289 u_int32_t pcicsr; 290 291 pcicsr = read_csr_4(d, pci_csr); 292 if ((pcicsr & 0xf8000000) && clear) 293 write_csr_4(d, pci_csr, pcicsr | 0xf8000000); 294 return (pcicsr & 0x08000000); /* target abort */ 295 } 296 297 int 298 univ_pci_intr(v) 299 void *v; 300 { 301 struct univ_pci_data *d = v; 302 u_int32_t intcsr; 303 int i, vec; 304 305 intcsr = read_csr_4(d, lint_stat) & 0xffffff; 306 if (!intcsr) 307 return (0); 308 309 /* ack everything */ 310 write_csr_4(d, lint_stat, intcsr); 311 #ifdef UNIV_DEBUG 312 printf("%s: intr, lint_stat=%x\n", d->devname, intcsr); 313 #endif 314 if (intcsr & 0x000000fe) { /* VME interrupt */ 315 for (i = 7; i >= 1; i--) { 316 if (!(intcsr & (1 << i))) 317 continue; 318 vec = read_csr_4(d, v_statid[i - 1]); 319 if (vec & 0x100) { 320 printf("%s: err irq %d\n", d->devname, i); 321 continue; 322 } 323 if (d->vmeinthandler) 324 (*d->vmeinthandler)(d->vmeintcookie, i, vec); 325 } 326 } 327 328 return (1); 329 } 330
Indexes created Wed Sep 24 05:09:52 GMT 2025