vga_pci.c revision 1.32.8.2
1 /* $NetBSD: vga_pci.c,v 1.32.8.2 2007/09/03 16:48:24 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: vga_pci.c,v 1.32.8.2 2007/09/03 16:48:24 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/malloc.h> 38 39 #include <dev/pci/pcireg.h> 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcidevs.h> 42 #include <dev/pci/pciio.h> 43 44 #include <dev/ic/mc6845reg.h> 45 #include <dev/ic/pcdisplayvar.h> 46 #include <dev/ic/vgareg.h> 47 #include <dev/ic/vgavar.h> 48 #include <dev/pci/vga_pcivar.h> 49 50 #include <dev/isa/isareg.h> /* For legacy VGA address ranges */ 51 52 #include <dev/wscons/wsconsio.h> 53 #include <dev/wscons/wsdisplayvar.h> 54 55 #define NBARS 6 /* number of PCI BARs */ 56 57 struct vga_bar { 58 bus_addr_t vb_base; 59 bus_size_t vb_size; 60 pcireg_t vb_type; 61 int vb_flags; 62 }; 63 64 struct vga_pci_softc { 65 struct vga_softc sc_vga; 66 67 pci_chipset_tag_t sc_pc; 68 pcitag_t sc_pcitag; 69 70 struct vga_bar sc_bars[NBARS]; 71 struct vga_bar sc_rom; 72 73 struct pci_conf_state sc_pciconf; 74 }; 75 76 static int vga_pci_match(struct device *, struct cfdata *, void *); 77 static void vga_pci_attach(struct device *, struct device *, void *); 78 static pnp_status_t vga_pci_power(device_t, pnp_request_t, void *); 79 static int vga_pci_lookup_quirks(struct pci_attach_args *); 80 81 CFATTACH_DECL(vga_pci, sizeof(struct vga_pci_softc), 82 vga_pci_match, vga_pci_attach, NULL, NULL); 83 84 static int vga_pci_ioctl(void *, u_long, void *, int, struct lwp *); 85 static paddr_t vga_pci_mmap(void *, off_t, int); 86 87 static const struct vga_funcs vga_pci_funcs = { 88 vga_pci_ioctl, 89 vga_pci_mmap, 90 }; 91 92 static const struct { 93 int id; 94 int quirks; 95 } vga_pci_quirks[] = { 96 {PCI_ID_CODE(PCI_VENDOR_SILMOTION, PCI_PRODUCT_SILMOTION_SM712), 97 VGA_QUIRK_NOFASTSCROLL}, 98 }; 99 100 static const struct { 101 int vid; 102 int quirks; 103 } vga_pci_vquirks[] = { 104 {PCI_VENDOR_ATI, VGA_QUIRK_ONEFONT}, 105 }; 106 107 static int 108 vga_pci_lookup_quirks(struct pci_attach_args *pa) 109 { 110 int i; 111 112 for (i = 0; i < sizeof(vga_pci_quirks) / sizeof (vga_pci_quirks[0]); 113 i++) { 114 if (vga_pci_quirks[i].id == pa->pa_id) 115 return (vga_pci_quirks[i].quirks); 116 } 117 for (i = 0; i < sizeof(vga_pci_vquirks) / sizeof (vga_pci_vquirks[0]); 118 i++) { 119 if (vga_pci_vquirks[i].vid == PCI_VENDOR(pa->pa_id)) 120 return (vga_pci_vquirks[i].quirks); 121 } 122 return (0); 123 } 124 125 static int 126 vga_pci_match(struct device *parent, struct cfdata *match, 127 void *aux) 128 { 129 struct pci_attach_args *pa = aux; 130 int potential; 131 132 potential = 0; 133 134 /* 135 * If it's prehistoric/vga or display/vga, we might match. 136 * For the console device, this is just a sanity check. 137 */ 138 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_PREHISTORIC && 139 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_PREHISTORIC_VGA) 140 potential = 1; 141 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY && 142 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA) 143 potential = 1; 144 145 if (!potential) 146 return (0); 147 148 /* check whether it is disabled by firmware */ 149 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) 150 & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 151 != (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 152 return (0); 153 154 /* If it's the console, we have a winner! */ 155 if (vga_is_console(pa->pa_iot, WSDISPLAY_TYPE_PCIVGA)) 156 return (1); 157 158 /* 159 * If we might match, make sure that the card actually looks OK. 160 */ 161 if (!vga_common_probe(pa->pa_iot, pa->pa_memt)) 162 return (0); 163 164 return (1); 165 } 166 167 static void 168 vga_pci_attach(struct device *parent, struct device *self, void *aux) 169 { 170 struct vga_pci_softc *psc = (void *) self; 171 struct vga_softc *sc = &psc->sc_vga; 172 struct pci_attach_args *pa = aux; 173 pnp_status_t status; 174 char devinfo[256]; 175 int bar, reg; 176 177 psc->sc_pc = pa->pa_pc; 178 psc->sc_pcitag = pa->pa_tag; 179 180 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 181 printf(": %s (rev. 0x%02x)\n", devinfo, 182 PCI_REVISION(pa->pa_class)); 183 184 /* 185 * Gather info about all the BARs. These are used to allow 186 * the X server to map the VGA device. 187 */ 188 for (bar = 0; bar < NBARS; bar++) { 189 reg = PCI_MAPREG_START + (bar * 4); 190 if (!pci_mapreg_probe(psc->sc_pc, psc->sc_pcitag, reg, 191 &psc->sc_bars[bar].vb_type)) { 192 /* there is no valid mapping register */ 193 continue; 194 } 195 if (PCI_MAPREG_TYPE(psc->sc_bars[bar].vb_type) == 196 PCI_MAPREG_TYPE_IO) { 197 /* Don't bother fetching I/O BARs. */ 198 continue; 199 } 200 #ifndef __LP64__ 201 if (PCI_MAPREG_MEM_TYPE(psc->sc_bars[bar].vb_type) == 202 PCI_MAPREG_MEM_TYPE_64BIT) { 203 /* XXX */ 204 printf("%s: WARNING: ignoring 64-bit BAR @ 0x%02x\n", 205 sc->sc_dev.dv_xname, reg); 206 bar++; 207 continue; 208 } 209 #endif 210 if (pci_mapreg_info(psc->sc_pc, psc->sc_pcitag, reg, 211 psc->sc_bars[bar].vb_type, 212 &psc->sc_bars[bar].vb_base, 213 &psc->sc_bars[bar].vb_size, 214 &psc->sc_bars[bar].vb_flags)) 215 printf("%s: WARNING: strange BAR @ 0x%02x\n", 216 sc->sc_dev.dv_xname, reg); 217 } 218 219 /* XXX Expansion ROM? */ 220 221 vga_common_attach(sc, pa->pa_iot, pa->pa_memt, WSDISPLAY_TYPE_PCIVGA, 222 vga_pci_lookup_quirks(pa), &vga_pci_funcs); 223 224 status = pnp_register(self, vga_pci_power); 225 if (status != PNP_STATUS_SUCCESS) 226 aprint_error("%s: couldn't establish power handler\n", 227 device_xname(self)); 228 config_found_ia(self, "drm", aux, vga_drm_print); 229 } 230 231 static pnp_status_t 232 vga_pci_power(device_t dv, pnp_request_t req, void *opaque) 233 { 234 struct vga_pci_softc *sc; 235 pnp_capabilities_t *pcaps; 236 pnp_state_t *pstate; 237 pci_chipset_tag_t pc; 238 pcitag_t tag; 239 240 sc = (struct vga_pci_softc *)dv; 241 pc = sc->sc_pc; 242 tag = sc->sc_pcitag; 243 244 switch (req) { 245 case PNP_REQUEST_GET_CAPABILITIES: 246 pcaps = opaque; 247 pcaps->state = PNP_STATE_D0 | PNP_STATE_D3; 248 break; 249 case PNP_REQUEST_GET_STATE: 250 pstate = opaque; 251 *pstate = PNP_STATE_D0; /* XXX */ 252 break; 253 case PNP_REQUEST_SET_STATE: 254 pstate = opaque; 255 switch (*pstate) { 256 case PNP_STATE_D0: 257 pci_conf_restore(pc, tag, &sc->sc_pciconf); 258 return vga_power(dv, req, opaque); 259 break; 260 case PNP_STATE_D3: 261 pci_conf_capture(pc, tag, &sc->sc_pciconf); 262 break; 263 default: 264 return PNP_STATUS_UNSUPPORTED; 265 } 266 break; 267 default: 268 return PNP_STATUS_UNSUPPORTED; 269 } 270 271 return PNP_STATUS_SUCCESS; 272 } 273 274 int 275 vga_pci_cnattach(bus_space_tag_t iot, bus_space_tag_t memt, 276 pci_chipset_tag_t pc, int bus, int device, 277 int function) 278 { 279 280 return (vga_cnattach(iot, memt, WSDISPLAY_TYPE_PCIVGA, 0)); 281 } 282 283 int 284 vga_drm_print(void *aux, const char *pnp) 285 { 286 if (pnp) 287 aprint_normal("direct rendering for %s", pnp); 288 return (UNSUPP); 289 } 290 291 292 static int 293 vga_pci_ioctl(void *v, u_long cmd, void *data, int flag, struct lwp *l) 294 { 295 struct vga_config *vc = v; 296 struct vga_pci_softc *psc = (void *) vc->softc; 297 298 switch (cmd) { 299 /* PCI config read/write passthrough. */ 300 case PCI_IOC_CFGREAD: 301 case PCI_IOC_CFGWRITE: 302 return (pci_devioctl(psc->sc_pc, psc->sc_pcitag, 303 cmd, data, flag, l)); 304 305 default: 306 return (EPASSTHROUGH); 307 } 308 } 309 310 static paddr_t 311 vga_pci_mmap(void *v, off_t offset, int prot) 312 { 313 struct vga_config *vc = v; 314 struct vga_pci_softc *psc = (void *) vc->softc; 315 struct vga_bar *vb; 316 int bar; 317 318 for (bar = 0; bar < NBARS; bar++) { 319 vb = &psc->sc_bars[bar]; 320 if (vb->vb_size == 0) 321 continue; 322 if (offset >= vb->vb_base && 323 offset < (vb->vb_base + vb->vb_size)) { 324 /* XXX This the right thing to do with flags? */ 325 return (bus_space_mmap(vc->hdl.vh_memt, vb->vb_base, 326 (offset - vb->vb_base), prot, vb->vb_flags)); 327 } 328 } 329 330 /* XXX Expansion ROM? */ 331 332 /* 333 * Allow mmap access to the legacy ISA hole. This is where 334 * the legacy video BIOS will be located, and also where 335 * the legacy VGA display buffer is located. 336 * 337 * XXX Security implications, here? 338 */ 339 if (offset >= IOM_BEGIN && offset < IOM_END) 340 return (bus_space_mmap(vc->hdl.vh_memt, IOM_BEGIN, 341 (offset - IOM_BEGIN), prot, 0)); 342 343 /* Range not found. */ 344 return (-1); 345 } 346
Indexes created Fri Oct 03 02:09:57 GMT 2025