vga_pci.c revision 1.39
1 /* $NetBSD: vga_pci.c,v 1.39 2008/02/29 06:13:39 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: vga_pci.c,v 1.39 2008/02/29 06:13:39 dyoung Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/malloc.h> 38 39 #include <dev/pci/pcireg.h> 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcidevs.h> 42 #include <dev/pci/pciio.h> 43 44 #include <dev/ic/mc6845reg.h> 45 #include <dev/ic/pcdisplayvar.h> 46 #include <dev/ic/vgareg.h> 47 #include <dev/ic/vgavar.h> 48 #include <dev/pci/vga_pcivar.h> 49 50 #include <dev/isa/isareg.h> /* For legacy VGA address ranges */ 51 52 #include <dev/wscons/wsconsio.h> 53 #include <dev/wscons/wsdisplayvar.h> 54 55 #include "opt_vga.h" 56 57 #ifdef VGA_POST 58 #include <x86/vga_post.h> 59 #endif 60 61 #define NBARS 6 /* number of PCI BARs */ 62 63 struct vga_bar { 64 bus_addr_t vb_base; 65 bus_size_t vb_size; 66 pcireg_t vb_type; 67 int vb_flags; 68 }; 69 70 struct vga_pci_softc { 71 struct vga_softc sc_vga; 72 73 pci_chipset_tag_t sc_pc; 74 pcitag_t sc_pcitag; 75 76 struct vga_bar sc_bars[NBARS]; 77 struct vga_bar sc_rom; 78 79 #ifdef VGA_POST 80 struct vga_post *sc_posth; 81 #endif 82 }; 83 84 static int vga_pci_match(struct device *, struct cfdata *, void *); 85 static void vga_pci_attach(struct device *, struct device *, void *); 86 static int vga_pci_lookup_quirks(struct pci_attach_args *); 87 static bool vga_pci_resume(device_t dv PMF_FN_PROTO); 88 89 CFATTACH_DECL(vga_pci, sizeof(struct vga_pci_softc), 90 vga_pci_match, vga_pci_attach, NULL, NULL); 91 92 static int vga_pci_ioctl(void *, u_long, void *, int, struct lwp *); 93 static paddr_t vga_pci_mmap(void *, off_t, int); 94 95 static const struct vga_funcs vga_pci_funcs = { 96 vga_pci_ioctl, 97 vga_pci_mmap, 98 }; 99 100 static const struct { 101 int id; 102 int quirks; 103 } vga_pci_quirks[] = { 104 {PCI_ID_CODE(PCI_VENDOR_SILMOTION, PCI_PRODUCT_SILMOTION_SM712), 105 VGA_QUIRK_NOFASTSCROLL}, 106 }; 107 108 static const struct { 109 int vid; 110 int quirks; 111 } vga_pci_vquirks[] = { 112 {PCI_VENDOR_ATI, VGA_QUIRK_ONEFONT}, 113 }; 114 115 static int 116 vga_pci_lookup_quirks(struct pci_attach_args *pa) 117 { 118 int i; 119 120 for (i = 0; i < sizeof(vga_pci_quirks) / sizeof (vga_pci_quirks[0]); 121 i++) { 122 if (vga_pci_quirks[i].id == pa->pa_id) 123 return (vga_pci_quirks[i].quirks); 124 } 125 for (i = 0; i < sizeof(vga_pci_vquirks) / sizeof (vga_pci_vquirks[0]); 126 i++) { 127 if (vga_pci_vquirks[i].vid == PCI_VENDOR(pa->pa_id)) 128 return (vga_pci_vquirks[i].quirks); 129 } 130 return (0); 131 } 132 133 static int 134 vga_pci_match(struct device *parent, struct cfdata *match, 135 void *aux) 136 { 137 struct pci_attach_args *pa = aux; 138 int potential; 139 140 potential = 0; 141 142 /* 143 * If it's prehistoric/vga or display/vga, we might match. 144 * For the console device, this is just a sanity check. 145 */ 146 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_PREHISTORIC && 147 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_PREHISTORIC_VGA) 148 potential = 1; 149 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY && 150 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA) 151 potential = 1; 152 153 if (!potential) 154 return (0); 155 156 /* check whether it is disabled by firmware */ 157 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) 158 & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 159 != (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 160 return (0); 161 162 /* If it's the console, we have a winner! */ 163 if (vga_is_console(pa->pa_iot, WSDISPLAY_TYPE_PCIVGA)) 164 return (1); 165 166 /* 167 * If we might match, make sure that the card actually looks OK. 168 */ 169 if (!vga_common_probe(pa->pa_iot, pa->pa_memt)) 170 return (0); 171 172 return (1); 173 } 174 175 static void 176 vga_pci_attach(struct device *parent, struct device *self, void *aux) 177 { 178 struct vga_pci_softc *psc = (void *) self; 179 struct vga_softc *sc = &psc->sc_vga; 180 struct pci_attach_args *pa = aux; 181 char devinfo[256]; 182 int bar, reg; 183 184 psc->sc_pc = pa->pa_pc; 185 psc->sc_pcitag = pa->pa_tag; 186 187 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 188 aprint_naive("\n"); 189 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 190 PCI_REVISION(pa->pa_class)); 191 192 /* 193 * Gather info about all the BARs. These are used to allow 194 * the X server to map the VGA device. 195 */ 196 for (bar = 0; bar < NBARS; bar++) { 197 reg = PCI_MAPREG_START + (bar * 4); 198 if (!pci_mapreg_probe(psc->sc_pc, psc->sc_pcitag, reg, 199 &psc->sc_bars[bar].vb_type)) { 200 /* there is no valid mapping register */ 201 continue; 202 } 203 if (PCI_MAPREG_TYPE(psc->sc_bars[bar].vb_type) == 204 PCI_MAPREG_TYPE_IO) { 205 /* Don't bother fetching I/O BARs. */ 206 continue; 207 } 208 #ifndef __LP64__ 209 if (PCI_MAPREG_MEM_TYPE(psc->sc_bars[bar].vb_type) == 210 PCI_MAPREG_MEM_TYPE_64BIT) { 211 /* XXX */ 212 aprint_error("%s: WARNING: ignoring 64-bit BAR @ 0x%02x\n", 213 sc->sc_dev.dv_xname, reg); 214 bar++; 215 continue; 216 } 217 #endif 218 if (pci_mapreg_info(psc->sc_pc, psc->sc_pcitag, reg, 219 psc->sc_bars[bar].vb_type, 220 &psc->sc_bars[bar].vb_base, 221 &psc->sc_bars[bar].vb_size, 222 &psc->sc_bars[bar].vb_flags)) 223 aprint_error("%s: WARNING: strange BAR @ 0x%02x\n", 224 sc->sc_dev.dv_xname, reg); 225 } 226 227 /* XXX Expansion ROM? */ 228 229 vga_common_attach(sc, pa->pa_iot, pa->pa_memt, WSDISPLAY_TYPE_PCIVGA, 230 vga_pci_lookup_quirks(pa), &vga_pci_funcs); 231 232 #ifdef VGA_POST 233 psc->sc_posth = vga_post_init(pa->pa_bus, pa->pa_device, pa->pa_function); 234 if (psc->sc_posth == NULL) 235 aprint_error_dev(self, "WARNING: could not prepare POST handler\n"); 236 #endif 237 238 /* 239 * XXX Do not use the generic PCI framework for now as 240 * XXX it would power down the device when the console 241 * XXX is still using it. 242 */ 243 if (!pmf_device_register(self, NULL, vga_pci_resume)) 244 aprint_error_dev(self, "couldn't establish power handler\n"); 245 config_found_ia(self, "drm", aux, vga_drm_print); 246 } 247 248 static bool 249 vga_pci_resume(device_t dv PMF_FN_ARGS) 250 { 251 struct vga_pci_softc *sc = device_private(dv); 252 253 vga_resume(&sc->sc_vga); 254 255 #ifdef VGA_POST 256 if (sc->sc_posth != NULL) 257 vga_post_call(sc->sc_posth); 258 #endif 259 260 return true; 261 } 262 263 int 264 vga_pci_cnattach(bus_space_tag_t iot, bus_space_tag_t memt, 265 pci_chipset_tag_t pc, int bus, int device, 266 int function) 267 { 268 269 return (vga_cnattach(iot, memt, WSDISPLAY_TYPE_PCIVGA, 0)); 270 } 271 272 int 273 vga_drm_print(void *aux, const char *pnp) 274 { 275 if (pnp) 276 aprint_normal("direct rendering for %s", pnp); 277 return (UNSUPP); 278 } 279 280 281 static int 282 vga_pci_ioctl(void *v, u_long cmd, void *data, int flag, struct lwp *l) 283 { 284 struct vga_config *vc = v; 285 struct vga_pci_softc *psc = (void *) vc->softc; 286 287 switch (cmd) { 288 /* PCI config read/write passthrough. */ 289 case PCI_IOC_CFGREAD: 290 case PCI_IOC_CFGWRITE: 291 return (pci_devioctl(psc->sc_pc, psc->sc_pcitag, 292 cmd, data, flag, l)); 293 294 default: 295 return (EPASSTHROUGH); 296 } 297 } 298 299 static paddr_t 300 vga_pci_mmap(void *v, off_t offset, int prot) 301 { 302 struct vga_config *vc = v; 303 struct vga_pci_softc *psc = (void *) vc->softc; 304 struct vga_bar *vb; 305 int bar; 306 307 for (bar = 0; bar < NBARS; bar++) { 308 vb = &psc->sc_bars[bar]; 309 if (vb->vb_size == 0) 310 continue; 311 if (offset >= vb->vb_base && 312 offset < (vb->vb_base + vb->vb_size)) { 313 /* XXX This the right thing to do with flags? */ 314 return (bus_space_mmap(vc->hdl.vh_memt, vb->vb_base, 315 (offset - vb->vb_base), prot, vb->vb_flags)); 316 } 317 } 318 319 /* XXX Expansion ROM? */ 320 321 /* 322 * Allow mmap access to the legacy ISA hole. This is where 323 * the legacy video BIOS will be located, and also where 324 * the legacy VGA display buffer is located. 325 * 326 * XXX Security implications, here? 327 */ 328 if (offset >= IOM_BEGIN && offset < IOM_END) 329 return (bus_space_mmap(vc->hdl.vh_memt, IOM_BEGIN, 330 (offset - IOM_BEGIN), prot, 0)); 331 332 /* Range not found. */ 333 return (-1); 334 } 335
Indexes created Tue Sep 23 21:09:50 GMT 2025