vga_pci.c revision 1.45
1 /* $NetBSD: vga_pci.c,v 1.45 2009/05/06 09:25:17 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: vga_pci.c,v 1.45 2009/05/06 09:25:17 cegger Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/malloc.h> 38 39 #include <dev/pci/pcireg.h> 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcidevs.h> 42 #include <dev/pci/pciio.h> 43 44 #include <dev/ic/mc6845reg.h> 45 #include <dev/ic/pcdisplayvar.h> 46 #include <dev/ic/vgareg.h> 47 #include <dev/ic/vgavar.h> 48 #include <dev/pci/vga_pcivar.h> 49 50 #include <dev/isa/isareg.h> /* For legacy VGA address ranges */ 51 52 #include <dev/wscons/wsconsio.h> 53 #include <dev/wscons/wsdisplayvar.h> 54 55 #include "opt_vga.h" 56 57 #ifdef VGA_POST 58 # if defined(__i386__) || defined(__amd64__) 59 # include "acpi.h" 60 # endif 61 #include <x86/vga_post.h> 62 #endif 63 64 #define NBARS 6 /* number of PCI BARs */ 65 66 struct vga_bar { 67 bus_addr_t vb_base; 68 bus_size_t vb_size; 69 pcireg_t vb_type; 70 int vb_flags; 71 }; 72 73 struct vga_pci_softc { 74 struct vga_softc sc_vga; 75 76 pci_chipset_tag_t sc_pc; 77 pcitag_t sc_pcitag; 78 79 struct vga_bar sc_bars[NBARS]; 80 struct vga_bar sc_rom; 81 82 #ifdef VGA_POST 83 struct vga_post *sc_posth; 84 #endif 85 86 struct pci_attach_args sc_paa; 87 }; 88 89 static int vga_pci_match(struct device *, cfdata_t, void *); 90 static void vga_pci_attach(struct device *, struct device *, void *); 91 static int vga_pci_rescan(struct device *, const char *, const int *); 92 static int vga_pci_lookup_quirks(struct pci_attach_args *); 93 static bool vga_pci_resume(device_t dv PMF_FN_PROTO); 94 95 CFATTACH_DECL2_NEW(vga_pci, sizeof(struct vga_pci_softc), 96 vga_pci_match, vga_pci_attach, NULL, NULL, vga_pci_rescan, NULL); 97 98 static int vga_pci_ioctl(void *, u_long, void *, int, struct lwp *); 99 static paddr_t vga_pci_mmap(void *, off_t, int); 100 101 static const struct vga_funcs vga_pci_funcs = { 102 vga_pci_ioctl, 103 vga_pci_mmap, 104 }; 105 106 static const struct { 107 int id; 108 int quirks; 109 } vga_pci_quirks[] = { 110 {PCI_ID_CODE(PCI_VENDOR_SILMOTION, PCI_PRODUCT_SILMOTION_SM712), 111 VGA_QUIRK_NOFASTSCROLL}, 112 }; 113 114 static const struct { 115 int vid; 116 int quirks; 117 } vga_pci_vquirks[] = { 118 {PCI_VENDOR_ATI, VGA_QUIRK_ONEFONT}, 119 }; 120 121 static int 122 vga_pci_lookup_quirks(struct pci_attach_args *pa) 123 { 124 int i; 125 126 for (i = 0; i < sizeof(vga_pci_quirks) / sizeof (vga_pci_quirks[0]); 127 i++) { 128 if (vga_pci_quirks[i].id == pa->pa_id) 129 return (vga_pci_quirks[i].quirks); 130 } 131 for (i = 0; i < sizeof(vga_pci_vquirks) / sizeof (vga_pci_vquirks[0]); 132 i++) { 133 if (vga_pci_vquirks[i].vid == PCI_VENDOR(pa->pa_id)) 134 return (vga_pci_vquirks[i].quirks); 135 } 136 return (0); 137 } 138 139 static int 140 vga_pci_match(struct device *parent, cfdata_t match, 141 void *aux) 142 { 143 struct pci_attach_args *pa = aux; 144 int potential; 145 146 potential = 0; 147 148 /* 149 * If it's prehistoric/vga or display/vga, we might match. 150 * For the console device, this is just a sanity check. 151 */ 152 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_PREHISTORIC && 153 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_PREHISTORIC_VGA) 154 potential = 1; 155 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY && 156 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA) 157 potential = 1; 158 159 if (!potential) 160 return (0); 161 162 /* check whether it is disabled by firmware */ 163 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) 164 & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 165 != (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 166 return (0); 167 168 /* If it's the console, we have a winner! */ 169 if (vga_is_console(pa->pa_iot, WSDISPLAY_TYPE_PCIVGA)) 170 return (1); 171 172 /* 173 * If we might match, make sure that the card actually looks OK. 174 */ 175 if (!vga_common_probe(pa->pa_iot, pa->pa_memt)) 176 return (0); 177 178 return (1); 179 } 180 181 static void 182 vga_pci_attach(struct device *parent, struct device *self, void *aux) 183 { 184 struct vga_pci_softc *psc = device_private(self); 185 struct vga_softc *sc = &psc->sc_vga; 186 struct pci_attach_args *pa = aux; 187 char devinfo[256]; 188 int bar, reg; 189 190 sc->sc_dev = self; 191 psc->sc_pc = pa->pa_pc; 192 psc->sc_pcitag = pa->pa_tag; 193 psc->sc_paa = *pa; 194 195 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 196 aprint_naive("\n"); 197 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 198 PCI_REVISION(pa->pa_class)); 199 200 /* 201 * Gather info about all the BARs. These are used to allow 202 * the X server to map the VGA device. 203 */ 204 for (bar = 0; bar < NBARS; bar++) { 205 reg = PCI_MAPREG_START + (bar * 4); 206 if (!pci_mapreg_probe(psc->sc_pc, psc->sc_pcitag, reg, 207 &psc->sc_bars[bar].vb_type)) { 208 /* there is no valid mapping register */ 209 continue; 210 } 211 if (PCI_MAPREG_TYPE(psc->sc_bars[bar].vb_type) == 212 PCI_MAPREG_TYPE_IO) { 213 /* Don't bother fetching I/O BARs. */ 214 continue; 215 } 216 #ifndef __LP64__ 217 if (PCI_MAPREG_MEM_TYPE(psc->sc_bars[bar].vb_type) == 218 PCI_MAPREG_MEM_TYPE_64BIT) { 219 /* XXX */ 220 aprint_error_dev(self, 221 "WARNING: ignoring 64-bit BAR @ 0x%02x\n", reg); 222 bar++; 223 continue; 224 } 225 #endif 226 if (pci_mapreg_info(psc->sc_pc, psc->sc_pcitag, reg, 227 psc->sc_bars[bar].vb_type, 228 &psc->sc_bars[bar].vb_base, 229 &psc->sc_bars[bar].vb_size, 230 &psc->sc_bars[bar].vb_flags)) 231 aprint_error_dev(self, 232 "WARNING: strange BAR @ 0x%02x\n", reg); 233 } 234 235 /* XXX Expansion ROM? */ 236 237 vga_common_attach(sc, pa->pa_iot, pa->pa_memt, WSDISPLAY_TYPE_PCIVGA, 238 vga_pci_lookup_quirks(pa), &vga_pci_funcs); 239 240 #ifdef VGA_POST 241 psc->sc_posth = vga_post_init(pa->pa_bus, pa->pa_device, pa->pa_function); 242 if (psc->sc_posth == NULL) 243 aprint_error_dev(self, "WARNING: could not prepare POST handler\n"); 244 #endif 245 246 /* 247 * XXX Do not use the generic PCI framework for now as 248 * XXX it would power down the device when the console 249 * XXX is still using it. 250 */ 251 if (!pmf_device_register(self, NULL, vga_pci_resume)) 252 aprint_error_dev(self, "couldn't establish power handler\n"); 253 config_found_ia(self, "drm", aux, vga_drm_print); 254 } 255 256 static int 257 vga_pci_rescan(struct device *self, const char *ifattr, const int *locators) 258 { 259 struct vga_pci_softc *psc = device_private(self); 260 261 config_found_ia(self, "drm", &psc->sc_paa, vga_drm_print); 262 263 return 0; 264 } 265 266 static bool 267 vga_pci_resume(device_t dv PMF_FN_ARGS) 268 { 269 #if defined(VGA_POST) && NACPI > 0 270 extern int acpi_md_vbios_reset; 271 #endif 272 struct vga_pci_softc *sc = device_private(dv); 273 274 vga_resume(&sc->sc_vga); 275 276 #if defined(VGA_POST) && NACPI > 0 277 if (sc->sc_posth != NULL && acpi_md_vbios_reset == 2) 278 vga_post_call(sc->sc_posth); 279 #endif 280 281 return true; 282 } 283 284 int 285 vga_pci_cnattach(bus_space_tag_t iot, bus_space_tag_t memt, 286 pci_chipset_tag_t pc, int bus, int device, 287 int function) 288 { 289 290 return (vga_cnattach(iot, memt, WSDISPLAY_TYPE_PCIVGA, 0)); 291 } 292 293 int 294 vga_drm_print(void *aux, const char *pnp) 295 { 296 if (pnp) 297 aprint_normal("drm at %s", pnp); 298 return (UNCONF); 299 } 300 301 302 static int 303 vga_pci_ioctl(void *v, u_long cmd, void *data, int flag, struct lwp *l) 304 { 305 struct vga_config *vc = v; 306 struct vga_pci_softc *psc = (void *) vc->softc; 307 308 switch (cmd) { 309 /* PCI config read/write passthrough. */ 310 case PCI_IOC_CFGREAD: 311 case PCI_IOC_CFGWRITE: 312 return (pci_devioctl(psc->sc_pc, psc->sc_pcitag, 313 cmd, data, flag, l)); 314 315 default: 316 return (EPASSTHROUGH); 317 } 318 } 319 320 static paddr_t 321 vga_pci_mmap(void *v, off_t offset, int prot) 322 { 323 struct vga_config *vc = v; 324 struct vga_pci_softc *psc = (void *) vc->softc; 325 struct vga_bar *vb; 326 int bar; 327 328 for (bar = 0; bar < NBARS; bar++) { 329 vb = &psc->sc_bars[bar]; 330 if (vb->vb_size == 0) 331 continue; 332 if (offset >= vb->vb_base && 333 offset < (vb->vb_base + vb->vb_size)) { 334 /* XXX This the right thing to do with flags? */ 335 return (bus_space_mmap(vc->hdl.vh_memt, vb->vb_base, 336 (offset - vb->vb_base), prot, vb->vb_flags)); 337 } 338 } 339 340 /* XXX Expansion ROM? */ 341 342 /* 343 * Allow mmap access to the legacy ISA hole. This is where 344 * the legacy video BIOS will be located, and also where 345 * the legacy VGA display buffer is located. 346 * 347 * XXX Security implications, here? 348 */ 349 if (offset >= IOM_BEGIN && offset < IOM_END) 350 return (bus_space_mmap(vc->hdl.vh_memt, IOM_BEGIN, 351 (offset - IOM_BEGIN), prot, 0)); 352 353 /* Range not found. */ 354 return (-1); 355 } 356
Indexes created Fri Oct 03 02:09:57 GMT 2025