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viogpu.h revision 1.1.4.2 
      1 /* $NetBSD: viogpu.h,v 1.1.4.2 2025/08/02 05:57:00 perseant Exp $ */
      2 /*
      3  * Virtio GPU Device
      4  *
      5  * Copyright Red Hat, Inc. 2013-2014
      6  *
      7  * Authors:
      8  *     Dave Airlie <airlied (at) redhat.com>
      9  *     Gerd Hoffmann <kraxel (at) redhat.com>
     10  *
     11  * This header is BSD licensed so anyone can use the definitions
     12  * to implement compatible drivers/servers:
     13  *
     14  * Redistribution and use in source and binary forms, with or without
     15  * modification, are permitted provided that the following conditions
     16  * are met:
     17  * 1. Redistributions of source code must retain the above copyright
     18  *    notice, this list of conditions and the following disclaimer.
     19  * 2. Redistributions in binary form must reproduce the above copyright
     20  *    notice, this list of conditions and the following disclaimer in the
     21  *    documentation and/or other materials provided with the distribution.
     22  * 3. Neither the name of IBM nor the names of its contributors
     23  *    may be used to endorse or promote products derived from this software
     24  *    without specific prior written permission.
     25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     26  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
     28  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR
     29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
     32  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     33  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     34  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
     35  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     36  * SUCH DAMAGE.
     37  */
     38 
     39 #ifndef VIRTIO_GPU_HW_H
     40 #define VIRTIO_GPU_HW_H
     41 
     42 #include <sys/types.h>
     43 
     44 #define __u8 uint8_t
     45 #define __u32 uint32_t
     46 #define __le16 uint16_t
     47 #define __le32 uint32_t
     48 #define __le64 uint64_t
     49 
     50 /*
     51  * VIRTIO_GPU_CMD_CTX_*
     52  * VIRTIO_GPU_CMD_*_3D
     53  */
     54 #define VIRTIO_GPU_F_VIRGL               (1ULL << 0)
     55 
     56 /*
     57  * VIRTIO_GPU_CMD_GET_EDID
     58  */
     59 #define VIRTIO_GPU_F_EDID                (1ULL << 1)
     60 /*
     61  * VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID
     62  */
     63 #define VIRTIO_GPU_F_RESOURCE_UUID       (1ULL << 2)
     64 
     65 /*
     66  * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB
     67  */
     68 #define VIRTIO_GPU_F_RESOURCE_BLOB       (1ULL << 3)
     69 
     70 enum virtio_gpu_ctrl_type {
     71 	VIRTIO_GPU_UNDEFINED = 0,
     72 
     73 	/* 2d commands */
     74 	VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
     75 	VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
     76 	VIRTIO_GPU_CMD_RESOURCE_UNREF,
     77 	VIRTIO_GPU_CMD_SET_SCANOUT,
     78 	VIRTIO_GPU_CMD_RESOURCE_FLUSH,
     79 	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
     80 	VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
     81 	VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
     82 	VIRTIO_GPU_CMD_GET_CAPSET_INFO,
     83 	VIRTIO_GPU_CMD_GET_CAPSET,
     84 	VIRTIO_GPU_CMD_GET_EDID,
     85 	VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,
     86 	VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB,
     87 	VIRTIO_GPU_CMD_SET_SCANOUT_BLOB,
     88 
     89 	/* 3d commands */
     90 	VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
     91 	VIRTIO_GPU_CMD_CTX_DESTROY,
     92 	VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
     93 	VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
     94 	VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
     95 	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
     96 	VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
     97 	VIRTIO_GPU_CMD_SUBMIT_3D,
     98 	VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB,
     99 	VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB,
    100 
    101 	/* cursor commands */
    102 	VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
    103 	VIRTIO_GPU_CMD_MOVE_CURSOR,
    104 
    105 	/* success responses */
    106 	VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
    107 	VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
    108 	VIRTIO_GPU_RESP_OK_CAPSET_INFO,
    109 	VIRTIO_GPU_RESP_OK_CAPSET,
    110 	VIRTIO_GPU_RESP_OK_EDID,
    111 	VIRTIO_GPU_RESP_OK_RESOURCE_UUID,
    112 	VIRTIO_GPU_RESP_OK_MAP_INFO,
    113 
    114 	/* error responses */
    115 	VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
    116 	VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
    117 	VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
    118 	VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
    119 	VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
    120 	VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
    121 };
    122 
    123 enum virtio_gpu_shm_id {
    124 	VIRTIO_GPU_SHM_ID_UNDEFINED = 0,
    125 	/*
    126 	 * VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB
    127 	 * VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB
    128 	 */
    129 	VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1
    130 };
    131 
    132 #define VIRTIO_GPU_FLAG_FENCE (1 << 0)
    133 
    134 struct virtio_gpu_ctrl_hdr {
    135 	__le32 type;
    136 	__le32 flags;
    137 	__le64 fence_id;
    138 	__le32 ctx_id;
    139 	__le32 padding;
    140 } __packed;
    141 
    142 /* data passed in the cursor vq */
    143 
    144 struct virtio_gpu_cursor_pos {
    145 	__le32 scanout_id;
    146 	__le32 x;
    147 	__le32 y;
    148 	__le32 padding;
    149 } __packed;
    150 
    151 /* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
    152 struct virtio_gpu_update_cursor {
    153 	struct virtio_gpu_ctrl_hdr hdr;
    154 	struct virtio_gpu_cursor_pos pos;  /* update & move */
    155 	__le32 resource_id;           /* update only */
    156 	__le32 hot_x;                 /* update only */
    157 	__le32 hot_y;                 /* update only */
    158 	__le32 padding;
    159 } __packed;
    160 
    161 /* data passed in the control vq, 2d related */
    162 
    163 struct virtio_gpu_rect {
    164 	__le32 x;
    165 	__le32 y;
    166 	__le32 width;
    167 	__le32 height;
    168 } __packed;
    169 
    170 /* VIRTIO_GPU_CMD_RESOURCE_UNREF */
    171 struct virtio_gpu_resource_unref {
    172 	struct virtio_gpu_ctrl_hdr hdr;
    173 	__le32 resource_id;
    174 	__le32 padding;
    175 } __packed;
    176 
    177 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
    178 struct virtio_gpu_resource_create_2d {
    179 	struct virtio_gpu_ctrl_hdr hdr;
    180 	__le32 resource_id;
    181 	__le32 format;
    182 	__le32 width;
    183 	__le32 height;
    184 } __packed;
    185 
    186 /* VIRTIO_GPU_CMD_SET_SCANOUT */
    187 struct virtio_gpu_set_scanout {
    188 	struct virtio_gpu_ctrl_hdr hdr;
    189 	struct virtio_gpu_rect r;
    190 	__le32 scanout_id;
    191 	__le32 resource_id;
    192 } __packed;
    193 
    194 /* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
    195 struct virtio_gpu_resource_flush {
    196 	struct virtio_gpu_ctrl_hdr hdr;
    197 	struct virtio_gpu_rect r;
    198 	__le32 resource_id;
    199 	__le32 padding;
    200 } __packed;
    201 
    202 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
    203 struct virtio_gpu_transfer_to_host_2d {
    204 	struct virtio_gpu_ctrl_hdr hdr;
    205 	struct virtio_gpu_rect r;
    206 	__le64 offset;
    207 	__le32 resource_id;
    208 	__le32 padding;
    209 } __packed;
    210 
    211 struct virtio_gpu_mem_entry {
    212 	__le64 addr;
    213 	__le32 length;
    214 	__le32 padding;
    215 } __packed;
    216 
    217 /* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
    218 struct virtio_gpu_resource_attach_backing {
    219 	struct virtio_gpu_ctrl_hdr hdr;
    220 	__le32 resource_id;
    221 	__le32 nr_entries;
    222 } __packed;
    223 
    224 /* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
    225 struct virtio_gpu_resource_detach_backing {
    226 	struct virtio_gpu_ctrl_hdr hdr;
    227 	__le32 resource_id;
    228 	__le32 padding;
    229 } __packed;
    230 
    231 /* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
    232 #define VIRTIO_GPU_MAX_SCANOUTS 16
    233 struct virtio_gpu_resp_display_info {
    234 	struct virtio_gpu_ctrl_hdr hdr;
    235 	struct virtio_gpu_display_one {
    236 		struct virtio_gpu_rect r;
    237 		__le32 enabled;
    238 		__le32 flags;
    239 	} pmodes[VIRTIO_GPU_MAX_SCANOUTS];
    240 } __packed;
    241 
    242 /* data passed in the control vq, 3d related */
    243 
    244 struct virtio_gpu_box {
    245 	__le32 x, y, z;
    246 	__le32 w, h, d;
    247 } __packed;
    248 
    249 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
    250 struct virtio_gpu_transfer_host_3d {
    251 	struct virtio_gpu_ctrl_hdr hdr;
    252 	struct virtio_gpu_box box;
    253 	__le64 offset;
    254 	__le32 resource_id;
    255 	__le32 level;
    256 	__le32 stride;
    257 	__le32 layer_stride;
    258 } __packed;
    259 
    260 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
    261 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
    262 struct virtio_gpu_resource_create_3d {
    263 	struct virtio_gpu_ctrl_hdr hdr;
    264 	__le32 resource_id;
    265 	__le32 target;
    266 	__le32 format;
    267 	__le32 bind;
    268 	__le32 width;
    269 	__le32 height;
    270 	__le32 depth;
    271 	__le32 array_size;
    272 	__le32 last_level;
    273 	__le32 nr_samples;
    274 	__le32 flags;
    275 	__le32 padding;
    276 } __packed;
    277 
    278 /* VIRTIO_GPU_CMD_CTX_CREATE */
    279 struct virtio_gpu_ctx_create {
    280 	struct virtio_gpu_ctrl_hdr hdr;
    281 	__le32 nlen;
    282 	__le32 padding;
    283 	char debug_name[64];
    284 } __packed;
    285 
    286 /* VIRTIO_GPU_CMD_CTX_DESTROY */
    287 struct virtio_gpu_ctx_destroy {
    288 	struct virtio_gpu_ctrl_hdr hdr;
    289 } __packed;
    290 
    291 /* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
    292 struct virtio_gpu_ctx_resource {
    293 	struct virtio_gpu_ctrl_hdr hdr;
    294 	__le32 resource_id;
    295 	__le32 padding;
    296 } __packed;
    297 
    298 /* VIRTIO_GPU_CMD_SUBMIT_3D */
    299 struct virtio_gpu_cmd_submit {
    300 	struct virtio_gpu_ctrl_hdr hdr;
    301 	__le32 size;
    302 	__le32 padding;
    303 } __packed;
    304 
    305 #define VIRTIO_GPU_CAPSET_VIRGL 1
    306 #define VIRTIO_GPU_CAPSET_VIRGL2 2
    307 
    308 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
    309 struct virtio_gpu_get_capset_info {
    310 	struct virtio_gpu_ctrl_hdr hdr;
    311 	__le32 capset_index;
    312 	__le32 padding;
    313 } __packed;
    314 
    315 /* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
    316 struct virtio_gpu_resp_capset_info {
    317 	struct virtio_gpu_ctrl_hdr hdr;
    318 	__le32 capset_id;
    319 	__le32 capset_max_version;
    320 	__le32 capset_max_size;
    321 	__le32 padding;
    322 } __packed;
    323 
    324 /* VIRTIO_GPU_CMD_GET_CAPSET */
    325 struct virtio_gpu_get_capset {
    326 	struct virtio_gpu_ctrl_hdr hdr;
    327 	__le32 capset_id;
    328 	__le32 capset_version;
    329 } __packed;
    330 
    331 /* VIRTIO_GPU_RESP_OK_CAPSET */
    332 struct virtio_gpu_resp_capset {
    333 	struct virtio_gpu_ctrl_hdr hdr;
    334 	__u8 capset_data[];
    335 } __packed;
    336 
    337 /* VIRTIO_GPU_CMD_GET_EDID */
    338 struct virtio_gpu_cmd_get_edid {
    339 	struct virtio_gpu_ctrl_hdr hdr;
    340 	__le32 scanout;
    341 	__le32 padding;
    342 } __packed;
    343 
    344 /* VIRTIO_GPU_RESP_OK_EDID */
    345 struct virtio_gpu_resp_edid {
    346 	struct virtio_gpu_ctrl_hdr hdr;
    347 	__le32 size;
    348 	__le32 padding;
    349 	__u8 edid[1024];
    350 } __packed;
    351 
    352 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
    353 
    354 struct virtio_gpu_config {
    355 	__le32 events_read;
    356 	__le32 events_clear;
    357 	__le32 num_scanouts;
    358 	__le32 num_capsets;
    359 } __packed;
    360 
    361 /* simple formats for fbcon/X use */
    362 enum virtio_gpu_formats {
    363 	VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM  = 1,
    364 	VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM  = 2,
    365 	VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM  = 3,
    366 	VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM  = 4,
    367 
    368 	VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM  = 67,
    369 	VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM  = 68,
    370 
    371 	VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM  = 121,
    372 	VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM  = 134,
    373 };
    374 
    375 /* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */
    376 struct virtio_gpu_resource_assign_uuid {
    377 	struct virtio_gpu_ctrl_hdr hdr;
    378 	__le32 resource_id;
    379 	__le32 padding;
    380 } __packed;
    381 
    382 /* VIRTIO_GPU_RESP_OK_RESOURCE_UUID */
    383 struct virtio_gpu_resp_resource_uuid {
    384 	struct virtio_gpu_ctrl_hdr hdr;
    385 	__u8 uuid[16];
    386 } __packed;
    387 
    388 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */
    389 struct virtio_gpu_resource_create_blob {
    390 	struct virtio_gpu_ctrl_hdr hdr;
    391 	__le32 resource_id;
    392 #define VIRTIO_GPU_BLOB_MEM_GUEST             0x0001
    393 #define VIRTIO_GPU_BLOB_MEM_HOST3D            0x0002
    394 #define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST      0x0003
    395 
    396 #define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE     0x0001
    397 #define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE    0x0002
    398 #define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
    399 	/* zero is invalid blob mem */
    400 	__le32 blob_mem;
    401 	__le32 blob_flags;
    402 	__le32 nr_entries;
    403 	__le64 blob_id;
    404 	__le64 size;
    405 	/*
    406 	 * sizeof(nr_entries * virtio_gpu_mem_entry) bytes follow
    407 	 */
    408 } __packed;
    409 
    410 /* VIRTIO_GPU_CMD_SET_SCANOUT_BLOB */
    411 struct virtio_gpu_set_scanout_blob {
    412 	struct virtio_gpu_ctrl_hdr hdr;
    413 	struct virtio_gpu_rect r;
    414 	__le32 scanout_id;
    415 	__le32 resource_id;
    416 	__le32 width;
    417 	__le32 height;
    418 	__le32 format;
    419 	__le32 padding;
    420 	__le32 strides[4];
    421 	__le32 offsets[4];
    422 } __packed;
    423 
    424 /* VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB */
    425 struct virtio_gpu_resource_map_blob {
    426 	struct virtio_gpu_ctrl_hdr hdr;
    427 	__le32 resource_id;
    428 	__le32 padding;
    429 	__le64 offset;
    430 } __packed;
    431 
    432 /* VIRTIO_GPU_RESP_OK_MAP_INFO */
    433 #define VIRTIO_GPU_MAP_CACHE_MASK     0x0f
    434 #define VIRTIO_GPU_MAP_CACHE_NONE     0x00
    435 #define VIRTIO_GPU_MAP_CACHE_CACHED   0x01
    436 #define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02
    437 #define VIRTIO_GPU_MAP_CACHE_WC       0x03
    438 struct virtio_gpu_resp_map_info {
    439 	struct virtio_gpu_ctrl_hdr hdr;
    440 	__u32 map_info;
    441 	__u32 padding;
    442 } __packed;
    443 
    444 /* VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB */
    445 struct virtio_gpu_resource_unmap_blob {
    446 	struct virtio_gpu_ctrl_hdr hdr;
    447 	__le32 resource_id;
    448 	__le32 padding;
    449 } __packed;
    450 
    451 #endif
    452