virtio_pci.c revision 1.35
1 /* $NetBSD: virtio_pci.c,v 1.35 2022/03/17 22:53:13 uwe Exp $ */ 2 3 /* 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * Copyright (c) 2012 Stefan Fritsch. 6 * Copyright (c) 2010 Minoura Makoto. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: virtio_pci.c,v 1.35 2022/03/17 22:53:13 uwe Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kmem.h> 36 #include <sys/module.h> 37 #include <sys/endian.h> 38 #include <sys/interrupt.h> 39 #include <sys/syslog.h> 40 41 #include <sys/device.h> 42 43 #include <dev/pci/pcidevs.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 47 #include <dev/pci/virtioreg.h> /* XXX: move to non-pci */ 48 #include <dev/pci/virtio_pcireg.h> 49 50 #define VIRTIO_PRIVATE 51 #include <dev/pci/virtiovar.h> /* XXX: move to non-pci */ 52 53 54 #define VIRTIO_PCI_LOG(_sc, _use_log, _fmt, _args...) \ 55 do { \ 56 if ((_use_log)) { \ 57 log(LOG_DEBUG, "%s: " _fmt, \ 58 device_xname((_sc)->sc_dev), \ 59 ##_args); \ 60 } else { \ 61 aprint_error_dev((_sc)->sc_dev, \ 62 _fmt, ##_args); \ 63 } \ 64 } while(0) 65 66 static int virtio_pci_match(device_t, cfdata_t, void *); 67 static void virtio_pci_attach(device_t, device_t, void *); 68 static int virtio_pci_rescan(device_t, const char *, const int *); 69 static int virtio_pci_detach(device_t, int); 70 71 72 #define NMAPREG ((PCI_MAPREG_END - PCI_MAPREG_START) / \ 73 sizeof(pcireg_t)) 74 struct virtio_pci_softc { 75 struct virtio_softc sc_sc; 76 77 /* IO space */ 78 bus_space_tag_t sc_iot; 79 bus_space_handle_t sc_ioh; 80 bus_size_t sc_iosize; 81 bus_size_t sc_mapped_iosize; 82 83 /* BARs */ 84 bus_space_tag_t sc_bars_iot[NMAPREG]; 85 bus_space_handle_t sc_bars_ioh[NMAPREG]; 86 bus_size_t sc_bars_iosize[NMAPREG]; 87 88 /* notify space */ 89 bus_space_tag_t sc_notify_iot; 90 bus_space_handle_t sc_notify_ioh; 91 bus_size_t sc_notify_iosize; 92 uint32_t sc_notify_off_multiplier; 93 94 /* isr space */ 95 bus_space_tag_t sc_isr_iot; 96 bus_space_handle_t sc_isr_ioh; 97 bus_size_t sc_isr_iosize; 98 99 /* generic */ 100 struct pci_attach_args sc_pa; 101 pci_intr_handle_t *sc_ihp; 102 void **sc_ihs; 103 int sc_ihs_num; 104 int sc_devcfg_offset; /* for 0.9 */ 105 }; 106 107 static int virtio_pci_attach_09(device_t, void *); 108 static void virtio_pci_kick_09(struct virtio_softc *, uint16_t); 109 static uint16_t virtio_pci_read_queue_size_09(struct virtio_softc *, uint16_t); 110 static void virtio_pci_setup_queue_09(struct virtio_softc *, uint16_t, uint64_t); 111 static void virtio_pci_set_status_09(struct virtio_softc *, int); 112 static void virtio_pci_negotiate_features_09(struct virtio_softc *, uint64_t); 113 114 static int virtio_pci_attach_10(device_t, void *); 115 static void virtio_pci_kick_10(struct virtio_softc *, uint16_t); 116 static uint16_t virtio_pci_read_queue_size_10(struct virtio_softc *, uint16_t); 117 static void virtio_pci_setup_queue_10(struct virtio_softc *, uint16_t, uint64_t); 118 static void virtio_pci_set_status_10(struct virtio_softc *, int); 119 static void virtio_pci_negotiate_features_10(struct virtio_softc *, uint64_t); 120 static int virtio_pci_find_cap(struct virtio_pci_softc *psc, int cfg_type, void *buf, int buflen); 121 122 static int virtio_pci_alloc_interrupts(struct virtio_softc *); 123 static void virtio_pci_free_interrupts(struct virtio_softc *); 124 static int virtio_pci_adjust_config_region(struct virtio_pci_softc *psc); 125 static int virtio_pci_intr(void *arg); 126 static int virtio_pci_msix_queue_intr(void *); 127 static int virtio_pci_msix_config_intr(void *); 128 static int virtio_pci_setup_interrupts_09(struct virtio_softc *, int); 129 static int virtio_pci_setup_interrupts_10(struct virtio_softc *, int); 130 static int virtio_pci_establish_msix_interrupts(struct virtio_softc *, 131 struct pci_attach_args *); 132 static int virtio_pci_establish_intx_interrupt(struct virtio_softc *, 133 struct pci_attach_args *); 134 static bool virtio_pci_msix_enabled(struct virtio_pci_softc *); 135 136 #define VIRTIO_MSIX_CONFIG_VECTOR_INDEX 0 137 #define VIRTIO_MSIX_QUEUE_VECTOR_INDEX 1 138 139 /* 140 * When using PCI attached virtio on aarch64-eb under Qemu, the IO space 141 * suddenly read BIG_ENDIAN where it should stay LITTLE_ENDIAN. The data read 142 * 1 byte at a time seem OK but reading bigger lengths result in swapped 143 * endian. This is most notable on reading 8 byters since we can't use 144 * bus_space_{read,write}_8(). 145 */ 146 147 #if defined(__aarch64__) && BYTE_ORDER == BIG_ENDIAN 148 # define READ_ENDIAN_09 BIG_ENDIAN /* should be LITTLE_ENDIAN */ 149 # define READ_ENDIAN_10 BIG_ENDIAN 150 # define STRUCT_ENDIAN_09 BIG_ENDIAN 151 # define STRUCT_ENDIAN_10 LITTLE_ENDIAN 152 #elif BYTE_ORDER == BIG_ENDIAN 153 # define READ_ENDIAN_09 LITTLE_ENDIAN 154 # define READ_ENDIAN_10 BIG_ENDIAN 155 # define STRUCT_ENDIAN_09 BIG_ENDIAN 156 # define STRUCT_ENDIAN_10 LITTLE_ENDIAN 157 #else /* little endian */ 158 # define READ_ENDIAN_09 LITTLE_ENDIAN 159 # define READ_ENDIAN_10 LITTLE_ENDIAN 160 # define STRUCT_ENDIAN_09 LITTLE_ENDIAN 161 # define STRUCT_ENDIAN_10 LITTLE_ENDIAN 162 #endif 163 164 165 CFATTACH_DECL3_NEW(virtio_pci, sizeof(struct virtio_pci_softc), 166 virtio_pci_match, virtio_pci_attach, virtio_pci_detach, NULL, 167 virtio_pci_rescan, NULL, DVF_DETACH_SHUTDOWN); 168 169 static const struct virtio_ops virtio_pci_ops_09 = { 170 .kick = virtio_pci_kick_09, 171 .read_queue_size = virtio_pci_read_queue_size_09, 172 .setup_queue = virtio_pci_setup_queue_09, 173 .set_status = virtio_pci_set_status_09, 174 .neg_features = virtio_pci_negotiate_features_09, 175 .alloc_interrupts = virtio_pci_alloc_interrupts, 176 .free_interrupts = virtio_pci_free_interrupts, 177 .setup_interrupts = virtio_pci_setup_interrupts_09, 178 }; 179 180 static const struct virtio_ops virtio_pci_ops_10 = { 181 .kick = virtio_pci_kick_10, 182 .read_queue_size = virtio_pci_read_queue_size_10, 183 .setup_queue = virtio_pci_setup_queue_10, 184 .set_status = virtio_pci_set_status_10, 185 .neg_features = virtio_pci_negotiate_features_10, 186 .alloc_interrupts = virtio_pci_alloc_interrupts, 187 .free_interrupts = virtio_pci_free_interrupts, 188 .setup_interrupts = virtio_pci_setup_interrupts_10, 189 }; 190 191 static int 192 virtio_pci_match(device_t parent, cfdata_t match, void *aux) 193 { 194 struct pci_attach_args *pa; 195 196 pa = (struct pci_attach_args *)aux; 197 switch (PCI_VENDOR(pa->pa_id)) { 198 case PCI_VENDOR_QUMRANET: 199 /* Transitional devices MUST have a PCI Revision ID of 0. */ 200 if (((PCI_PRODUCT_QUMRANET_VIRTIO_1000 <= 201 PCI_PRODUCT(pa->pa_id)) && 202 (PCI_PRODUCT(pa->pa_id) <= 203 PCI_PRODUCT_QUMRANET_VIRTIO_103F)) && 204 PCI_REVISION(pa->pa_class) == 0) 205 return 1; 206 /* 207 * Non-transitional devices SHOULD have a PCI Revision 208 * ID of 1 or higher. Drivers MUST match any PCI 209 * Revision ID value. 210 */ 211 if (((PCI_PRODUCT_QUMRANET_VIRTIO_1040 <= 212 PCI_PRODUCT(pa->pa_id)) && 213 (PCI_PRODUCT(pa->pa_id) <= 214 PCI_PRODUCT_QUMRANET_VIRTIO_107F)) && 215 /* XXX: TODO */ 216 PCI_REVISION(pa->pa_class) == 1) 217 return 1; 218 break; 219 } 220 221 return 0; 222 } 223 224 static void 225 virtio_pci_attach(device_t parent, device_t self, void *aux) 226 { 227 struct virtio_pci_softc * const psc = device_private(self); 228 struct virtio_softc * const sc = &psc->sc_sc; 229 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 230 pci_chipset_tag_t pc = pa->pa_pc; 231 pcitag_t tag = pa->pa_tag; 232 int revision; 233 int ret; 234 pcireg_t id; 235 pcireg_t csr; 236 237 revision = PCI_REVISION(pa->pa_class); 238 switch (revision) { 239 case 0: 240 /* subsystem ID shows what I am */ 241 id = PCI_SUBSYS_ID(pci_conf_read(pc, tag, PCI_SUBSYS_ID_REG)); 242 break; 243 case 1: 244 /* pci product number shows what I am */ 245 id = PCI_PRODUCT(pa->pa_id) - PCI_PRODUCT_QUMRANET_VIRTIO_1040; 246 break; 247 default: 248 aprint_normal(": unknown revision 0x%02x; giving up\n", 249 revision); 250 return; 251 } 252 253 aprint_normal("\n"); 254 aprint_naive("\n"); 255 virtio_print_device_type(self, id, revision); 256 257 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 258 csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE; 259 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 260 261 sc->sc_dev = self; 262 psc->sc_pa = *pa; 263 psc->sc_iot = pa->pa_iot; 264 265 sc->sc_dmat = pa->pa_dmat; 266 if (pci_dma64_available(pa)) 267 sc->sc_dmat = pa->pa_dmat64; 268 269 /* attach is dependent on revision */ 270 ret = 0; 271 if (revision == 1) { 272 /* try to attach 1.0 */ 273 ret = virtio_pci_attach_10(self, aux); 274 } 275 if (ret == 0 && revision == 0) { 276 /* revision 0 means 0.9 only or both 0.9 and 1.0 */ 277 ret = virtio_pci_attach_09(self, aux); 278 } 279 if (ret) { 280 aprint_error_dev(self, "cannot attach (%d)\n", ret); 281 return; 282 } 283 KASSERT(sc->sc_ops); 284 285 /* preset config region */ 286 psc->sc_devcfg_offset = VIRTIO_CONFIG_DEVICE_CONFIG_NOMSI; 287 if (virtio_pci_adjust_config_region(psc)) 288 return; 289 290 /* generic */ 291 virtio_device_reset(sc); 292 virtio_set_status(sc, VIRTIO_CONFIG_DEVICE_STATUS_ACK); 293 virtio_set_status(sc, VIRTIO_CONFIG_DEVICE_STATUS_DRIVER); 294 295 sc->sc_childdevid = id; 296 sc->sc_child = NULL; 297 virtio_pci_rescan(self, NULL, NULL); 298 return; 299 } 300 301 /* ARGSUSED */ 302 static int 303 virtio_pci_rescan(device_t self, const char *ifattr, const int *locs) 304 { 305 struct virtio_pci_softc * const psc = device_private(self); 306 struct virtio_softc * const sc = &psc->sc_sc; 307 struct virtio_attach_args va; 308 309 if (sc->sc_child) /* Child already attached? */ 310 return 0; 311 312 memset(&va, 0, sizeof(va)); 313 va.sc_childdevid = sc->sc_childdevid; 314 315 config_found(self, &va, NULL, CFARGS_NONE); 316 317 if (virtio_attach_failed(sc)) 318 return 0; 319 320 return 0; 321 } 322 323 324 static int 325 virtio_pci_detach(device_t self, int flags) 326 { 327 struct virtio_pci_softc * const psc = device_private(self); 328 struct virtio_softc * const sc = &psc->sc_sc; 329 int r; 330 331 if (sc->sc_child != NULL) { 332 r = config_detach(sc->sc_child, flags); 333 if (r) 334 return r; 335 } 336 337 /* Check that child detached properly */ 338 KASSERT(sc->sc_child == NULL); 339 KASSERT(sc->sc_vqs == NULL); 340 KASSERT(psc->sc_ihs_num == 0); 341 342 if (psc->sc_iosize) 343 bus_space_unmap(psc->sc_iot, psc->sc_ioh, 344 psc->sc_mapped_iosize); 345 psc->sc_iosize = 0; 346 347 return 0; 348 } 349 350 351 static int 352 virtio_pci_attach_09(device_t self, void *aux) 353 //struct virtio_pci_softc *psc, struct pci_attach_args *pa) 354 { 355 struct virtio_pci_softc * const psc = device_private(self); 356 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 357 struct virtio_softc * const sc = &psc->sc_sc; 358 // pci_chipset_tag_t pc = pa->pa_pc; 359 // pcitag_t tag = pa->pa_tag; 360 361 /* complete IO region */ 362 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 363 &psc->sc_iot, &psc->sc_ioh, NULL, &psc->sc_iosize)) { 364 aprint_error_dev(self, "can't map i/o space\n"); 365 return EIO; 366 } 367 psc->sc_mapped_iosize = psc->sc_iosize; 368 369 /* queue space */ 370 if (bus_space_subregion(psc->sc_iot, psc->sc_ioh, 371 VIRTIO_CONFIG_QUEUE_NOTIFY, 2, &psc->sc_notify_ioh)) { 372 aprint_error_dev(self, "can't map notify i/o space\n"); 373 return EIO; 374 } 375 psc->sc_notify_iosize = 2; 376 psc->sc_notify_iot = psc->sc_iot; 377 378 /* ISR space */ 379 if (bus_space_subregion(psc->sc_iot, psc->sc_ioh, 380 VIRTIO_CONFIG_ISR_STATUS, 1, &psc->sc_isr_ioh)) { 381 aprint_error_dev(self, "can't map isr i/o space\n"); 382 return EIO; 383 } 384 psc->sc_isr_iosize = 1; 385 psc->sc_isr_iot = psc->sc_iot; 386 387 /* set our version 0.9 ops */ 388 sc->sc_ops = &virtio_pci_ops_09; 389 sc->sc_bus_endian = READ_ENDIAN_09; 390 sc->sc_struct_endian = STRUCT_ENDIAN_09; 391 return 0; 392 } 393 394 395 static int 396 virtio_pci_attach_10(device_t self, void *aux) 397 { 398 struct virtio_pci_softc * const psc = device_private(self); 399 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 400 struct virtio_softc * const sc = &psc->sc_sc; 401 pci_chipset_tag_t pc = pa->pa_pc; 402 pcitag_t tag = pa->pa_tag; 403 404 struct virtio_pci_cap common, isr, device; 405 struct virtio_pci_notify_cap notify; 406 int have_device_cfg = 0; 407 bus_size_t bars[NMAPREG] = { 0 }; 408 int bars_idx[NMAPREG] = { 0 }; 409 struct virtio_pci_cap *caps[] = { &common, &isr, &device, ¬ify.cap }; 410 int i, j, ret = 0; 411 412 if (virtio_pci_find_cap(psc, VIRTIO_PCI_CAP_COMMON_CFG, 413 &common, sizeof(common))) 414 return ENODEV; 415 if (virtio_pci_find_cap(psc, VIRTIO_PCI_CAP_NOTIFY_CFG, 416 ¬ify, sizeof(notify))) 417 return ENODEV; 418 if (virtio_pci_find_cap(psc, VIRTIO_PCI_CAP_ISR_CFG, 419 &isr, sizeof(isr))) 420 return ENODEV; 421 if (virtio_pci_find_cap(psc, VIRTIO_PCI_CAP_DEVICE_CFG, 422 &device, sizeof(device))) 423 memset(&device, 0, sizeof(device)); 424 else 425 have_device_cfg = 1; 426 427 /* Figure out which bars we need to map */ 428 for (i = 0; i < __arraycount(caps); i++) { 429 int bar = caps[i]->bar; 430 bus_size_t len = caps[i]->offset + caps[i]->length; 431 if (caps[i]->length == 0) 432 continue; 433 if (bars[bar] < len) 434 bars[bar] = len; 435 } 436 437 for (i = j = 0; i < __arraycount(bars); i++) { 438 int reg; 439 pcireg_t type; 440 if (bars[i] == 0) 441 continue; 442 reg = PCI_BAR(i); 443 type = pci_mapreg_type(pc, tag, reg); 444 if (pci_mapreg_map(pa, reg, type, 0, 445 &psc->sc_bars_iot[j], &psc->sc_bars_ioh[j], 446 NULL, &psc->sc_bars_iosize[j])) { 447 aprint_error_dev(self, "can't map bar %u \n", i); 448 ret = EIO; 449 goto err; 450 } 451 aprint_debug_dev(self, 452 "bar[%d]: iot %p, size 0x%" PRIxBUSSIZE "\n", 453 j, psc->sc_bars_iot[j], psc->sc_bars_iosize[j]); 454 bars_idx[i] = j; 455 j++; 456 } 457 458 i = bars_idx[notify.cap.bar]; 459 if (bus_space_subregion(psc->sc_bars_iot[i], psc->sc_bars_ioh[i], 460 notify.cap.offset, notify.cap.length, 461 &psc->sc_notify_ioh)) { 462 aprint_error_dev(self, "can't map notify i/o space\n"); 463 ret = EIO; 464 goto err; 465 } 466 psc->sc_notify_iosize = notify.cap.length; 467 psc->sc_notify_iot = psc->sc_bars_iot[i]; 468 psc->sc_notify_off_multiplier = le32toh(notify.notify_off_multiplier); 469 470 if (have_device_cfg) { 471 i = bars_idx[device.bar]; 472 if (bus_space_subregion(psc->sc_bars_iot[i], psc->sc_bars_ioh[i], 473 device.offset, device.length, 474 &sc->sc_devcfg_ioh)) { 475 aprint_error_dev(self, "can't map devcfg i/o space\n"); 476 ret = EIO; 477 goto err; 478 } 479 aprint_debug_dev(self, 480 "device.offset = 0x%x, device.length = 0x%x\n", 481 device.offset, device.length); 482 sc->sc_devcfg_iosize = device.length; 483 sc->sc_devcfg_iot = psc->sc_bars_iot[i]; 484 } 485 486 i = bars_idx[isr.bar]; 487 if (bus_space_subregion(psc->sc_bars_iot[i], psc->sc_bars_ioh[i], 488 isr.offset, isr.length, &psc->sc_isr_ioh)) { 489 aprint_error_dev(self, "can't map isr i/o space\n"); 490 ret = EIO; 491 goto err; 492 } 493 psc->sc_isr_iosize = isr.length; 494 psc->sc_isr_iot = psc->sc_bars_iot[i]; 495 496 i = bars_idx[common.bar]; 497 if (bus_space_subregion(psc->sc_bars_iot[i], psc->sc_bars_ioh[i], 498 common.offset, common.length, &psc->sc_ioh)) { 499 aprint_error_dev(self, "can't map common i/o space\n"); 500 ret = EIO; 501 goto err; 502 } 503 psc->sc_iosize = common.length; 504 psc->sc_iot = psc->sc_bars_iot[i]; 505 psc->sc_mapped_iosize = psc->sc_bars_iosize[i]; 506 507 psc->sc_sc.sc_version_1 = 1; 508 509 /* set our version 1.0 ops */ 510 sc->sc_ops = &virtio_pci_ops_10; 511 sc->sc_bus_endian = READ_ENDIAN_10; 512 sc->sc_struct_endian = STRUCT_ENDIAN_10; 513 return 0; 514 515 err: 516 /* undo our pci_mapreg_map()s */ 517 for (i = 0; i < __arraycount(bars); i++) { 518 if (psc->sc_bars_iosize[i] == 0) 519 continue; 520 bus_space_unmap(psc->sc_bars_iot[i], psc->sc_bars_ioh[i], 521 psc->sc_bars_iosize[i]); 522 } 523 return ret; 524 } 525 526 /* v1.0 attach helper */ 527 static int 528 virtio_pci_find_cap(struct virtio_pci_softc *psc, int cfg_type, void *buf, int buflen) 529 { 530 device_t self = psc->sc_sc.sc_dev; 531 pci_chipset_tag_t pc = psc->sc_pa.pa_pc; 532 pcitag_t tag = psc->sc_pa.pa_tag; 533 unsigned int offset, i, len; 534 union { 535 pcireg_t reg[8]; 536 struct virtio_pci_cap vcap; 537 } *v = buf; 538 539 if (buflen < sizeof(struct virtio_pci_cap)) 540 return ERANGE; 541 542 if (!pci_get_capability(pc, tag, PCI_CAP_VENDSPEC, &offset, &v->reg[0])) 543 return ENOENT; 544 545 do { 546 for (i = 0; i < 4; i++) 547 v->reg[i] = 548 le32toh(pci_conf_read(pc, tag, offset + i * 4)); 549 if (v->vcap.cfg_type == cfg_type) 550 break; 551 offset = v->vcap.cap_next; 552 } while (offset != 0); 553 554 if (offset == 0) 555 return ENOENT; 556 557 if (v->vcap.cap_len > sizeof(struct virtio_pci_cap)) { 558 len = roundup(v->vcap.cap_len, sizeof(pcireg_t)); 559 if (len > buflen) { 560 aprint_error_dev(self, "%s cap too large\n", __func__); 561 return ERANGE; 562 } 563 for (i = 4; i < len / sizeof(pcireg_t); i++) 564 v->reg[i] = 565 le32toh(pci_conf_read(pc, tag, offset + i * 4)); 566 } 567 568 /* endian fixup */ 569 v->vcap.offset = le32toh(v->vcap.offset); 570 v->vcap.length = le32toh(v->vcap.length); 571 return 0; 572 } 573 574 575 /* ------------------------------------- 576 * Version 0.9 support 577 * -------------------------------------*/ 578 579 static void 580 virtio_pci_kick_09(struct virtio_softc *sc, uint16_t idx) 581 { 582 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 583 584 bus_space_write_2(psc->sc_notify_iot, psc->sc_notify_ioh, 0, idx); 585 } 586 587 /* only applicable for v 0.9 but also called for 1.0 */ 588 static int 589 virtio_pci_adjust_config_region(struct virtio_pci_softc *psc) 590 { 591 struct virtio_softc * const sc = (struct virtio_softc *) psc; 592 device_t self = psc->sc_sc.sc_dev; 593 594 if (psc->sc_sc.sc_version_1) 595 return 0; 596 597 sc->sc_devcfg_iosize = psc->sc_iosize - psc->sc_devcfg_offset; 598 sc->sc_devcfg_iot = psc->sc_iot; 599 if (bus_space_subregion(psc->sc_iot, psc->sc_ioh, 600 psc->sc_devcfg_offset, sc->sc_devcfg_iosize, 601 &sc->sc_devcfg_ioh)) { 602 aprint_error_dev(self, "can't map config i/o space\n"); 603 return EIO; 604 } 605 606 return 0; 607 } 608 609 static uint16_t 610 virtio_pci_read_queue_size_09(struct virtio_softc *sc, uint16_t idx) 611 { 612 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 613 614 bus_space_write_2(psc->sc_iot, psc->sc_ioh, 615 VIRTIO_CONFIG_QUEUE_SELECT, idx); 616 return bus_space_read_2(psc->sc_iot, psc->sc_ioh, 617 VIRTIO_CONFIG_QUEUE_SIZE); 618 } 619 620 static void 621 virtio_pci_setup_queue_09(struct virtio_softc *sc, uint16_t idx, uint64_t addr) 622 { 623 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 624 625 bus_space_write_2(psc->sc_iot, psc->sc_ioh, 626 VIRTIO_CONFIG_QUEUE_SELECT, idx); 627 bus_space_write_4(psc->sc_iot, psc->sc_ioh, 628 VIRTIO_CONFIG_QUEUE_ADDRESS, addr / VIRTIO_PAGE_SIZE); 629 630 if (psc->sc_ihs_num > 1) { 631 int vec = VIRTIO_MSIX_QUEUE_VECTOR_INDEX; 632 if (sc->sc_child_mq) 633 vec += idx; 634 bus_space_write_2(psc->sc_iot, psc->sc_ioh, 635 VIRTIO_CONFIG_MSI_QUEUE_VECTOR, vec); 636 } 637 } 638 639 static void 640 virtio_pci_set_status_09(struct virtio_softc *sc, int status) 641 { 642 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 643 int old = 0; 644 645 if (status != 0) { 646 old = bus_space_read_1(psc->sc_iot, psc->sc_ioh, 647 VIRTIO_CONFIG_DEVICE_STATUS); 648 } 649 bus_space_write_1(psc->sc_iot, psc->sc_ioh, 650 VIRTIO_CONFIG_DEVICE_STATUS, status|old); 651 } 652 653 static void 654 virtio_pci_negotiate_features_09(struct virtio_softc *sc, uint64_t guest_features) 655 { 656 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 657 uint32_t r; 658 659 r = bus_space_read_4(psc->sc_iot, psc->sc_ioh, 660 VIRTIO_CONFIG_DEVICE_FEATURES); 661 662 r &= guest_features; 663 664 bus_space_write_4(psc->sc_iot, psc->sc_ioh, 665 VIRTIO_CONFIG_GUEST_FEATURES, r); 666 667 sc->sc_active_features = r; 668 } 669 670 /* ------------------------------------- 671 * Version 1.0 support 672 * -------------------------------------*/ 673 674 static void 675 virtio_pci_kick_10(struct virtio_softc *sc, uint16_t idx) 676 { 677 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 678 unsigned offset = sc->sc_vqs[idx].vq_notify_off * 679 psc->sc_notify_off_multiplier; 680 681 bus_space_write_2(psc->sc_notify_iot, psc->sc_notify_ioh, offset, idx); 682 } 683 684 685 static uint16_t 686 virtio_pci_read_queue_size_10(struct virtio_softc *sc, uint16_t idx) 687 { 688 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 689 bus_space_tag_t iot = psc->sc_iot; 690 bus_space_handle_t ioh = psc->sc_ioh; 691 692 bus_space_write_2(iot, ioh, VIRTIO_CONFIG1_QUEUE_SELECT, idx); 693 return bus_space_read_2(iot, ioh, VIRTIO_CONFIG1_QUEUE_SIZE); 694 } 695 696 /* 697 * By definition little endian only in v1.0 and 8 byters are allowed to be 698 * written as two 4 byters 699 * 700 * This is not a general purpose function that can be used in any 701 * driver. Virtio specifically allows the 8 byte bus transaction 702 * to be split into two 4 byte transactions. Do not copy/use it 703 * in other device drivers unless you know that the device accepts it. 704 */ 705 static __inline void 706 virtio_pci_bus_space_write_8(bus_space_tag_t iot, bus_space_handle_t ioh, 707 bus_size_t offset, uint64_t value) 708 { 709 #if defined(__HAVE_BUS_SPACE_8) 710 bus_space_write_8(iot, ioh, offset, value); 711 #elif _QUAD_HIGHWORD 712 bus_space_write_4(iot, ioh, offset, BUS_ADDR_LO32(value)); 713 bus_space_write_4(iot, ioh, offset + 4, BUS_ADDR_HI32(value)); 714 #else 715 bus_space_write_4(iot, ioh, offset, BUS_ADDR_HI32(value)); 716 bus_space_write_4(iot, ioh, offset + 4, BUS_ADDR_LO32(value)); 717 #endif 718 } 719 720 static void 721 virtio_pci_setup_queue_10(struct virtio_softc *sc, uint16_t idx, uint64_t addr) 722 { 723 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 724 struct virtqueue *vq = &sc->sc_vqs[idx]; 725 bus_space_tag_t iot = psc->sc_iot; 726 bus_space_handle_t ioh = psc->sc_ioh; 727 KASSERT(vq->vq_index == idx); 728 729 bus_space_write_2(iot, ioh, VIRTIO_CONFIG1_QUEUE_SELECT, vq->vq_index); 730 if (addr == 0) { 731 bus_space_write_2(iot, ioh, VIRTIO_CONFIG1_QUEUE_ENABLE, 0); 732 virtio_pci_bus_space_write_8(iot, ioh, 733 VIRTIO_CONFIG1_QUEUE_DESC, 0); 734 virtio_pci_bus_space_write_8(iot, ioh, 735 VIRTIO_CONFIG1_QUEUE_AVAIL, 0); 736 virtio_pci_bus_space_write_8(iot, ioh, 737 VIRTIO_CONFIG1_QUEUE_USED, 0); 738 } else { 739 virtio_pci_bus_space_write_8(iot, ioh, 740 VIRTIO_CONFIG1_QUEUE_DESC, addr); 741 virtio_pci_bus_space_write_8(iot, ioh, 742 VIRTIO_CONFIG1_QUEUE_AVAIL, addr + vq->vq_availoffset); 743 virtio_pci_bus_space_write_8(iot, ioh, 744 VIRTIO_CONFIG1_QUEUE_USED, addr + vq->vq_usedoffset); 745 bus_space_write_2(iot, ioh, 746 VIRTIO_CONFIG1_QUEUE_ENABLE, 1); 747 vq->vq_notify_off = bus_space_read_2(iot, ioh, 748 VIRTIO_CONFIG1_QUEUE_NOTIFY_OFF); 749 } 750 751 if (psc->sc_ihs_num > 1) { 752 int vec = VIRTIO_MSIX_QUEUE_VECTOR_INDEX; 753 if (sc->sc_child_mq) 754 vec += idx; 755 bus_space_write_2(iot, ioh, 756 VIRTIO_CONFIG1_QUEUE_MSIX_VECTOR, vec); 757 } 758 } 759 760 static void 761 virtio_pci_set_status_10(struct virtio_softc *sc, int status) 762 { 763 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 764 bus_space_tag_t iot = psc->sc_iot; 765 bus_space_handle_t ioh = psc->sc_ioh; 766 int old = 0; 767 768 if (status) 769 old = bus_space_read_1(iot, ioh, VIRTIO_CONFIG1_DEVICE_STATUS); 770 bus_space_write_1(iot, ioh, VIRTIO_CONFIG1_DEVICE_STATUS, status | old); 771 } 772 773 void 774 virtio_pci_negotiate_features_10(struct virtio_softc *sc, uint64_t guest_features) 775 { 776 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 777 device_t self = sc->sc_dev; 778 bus_space_tag_t iot = psc->sc_iot; 779 bus_space_handle_t ioh = psc->sc_ioh; 780 uint64_t host, negotiated, device_status; 781 782 guest_features |= VIRTIO_F_VERSION_1; 783 /* notify on empty is 0.9 only */ 784 guest_features &= ~VIRTIO_F_NOTIFY_ON_EMPTY; 785 sc->sc_active_features = 0; 786 787 bus_space_write_4(iot, ioh, VIRTIO_CONFIG1_DEVICE_FEATURE_SELECT, 0); 788 host = bus_space_read_4(iot, ioh, VIRTIO_CONFIG1_DEVICE_FEATURE); 789 bus_space_write_4(iot, ioh, VIRTIO_CONFIG1_DEVICE_FEATURE_SELECT, 1); 790 host |= (uint64_t) 791 bus_space_read_4(iot, ioh, VIRTIO_CONFIG1_DEVICE_FEATURE) << 32; 792 793 negotiated = host & guest_features; 794 795 bus_space_write_4(iot, ioh, VIRTIO_CONFIG1_DRIVER_FEATURE_SELECT, 0); 796 bus_space_write_4(iot, ioh, VIRTIO_CONFIG1_DRIVER_FEATURE, 797 negotiated & 0xffffffff); 798 bus_space_write_4(iot, ioh, VIRTIO_CONFIG1_DRIVER_FEATURE_SELECT, 1); 799 bus_space_write_4(iot, ioh, VIRTIO_CONFIG1_DRIVER_FEATURE, 800 negotiated >> 32); 801 virtio_pci_set_status_10(sc, VIRTIO_CONFIG_DEVICE_STATUS_FEATURES_OK); 802 803 device_status = bus_space_read_1(iot, ioh, VIRTIO_CONFIG1_DEVICE_STATUS); 804 if ((device_status & VIRTIO_CONFIG_DEVICE_STATUS_FEATURES_OK) == 0) { 805 aprint_error_dev(self, "feature negotiation failed\n"); 806 bus_space_write_1(iot, ioh, VIRTIO_CONFIG1_DEVICE_STATUS, 807 VIRTIO_CONFIG_DEVICE_STATUS_FAILED); 808 return; 809 } 810 811 if ((negotiated & VIRTIO_F_VERSION_1) == 0) { 812 aprint_error_dev(self, "host rejected version 1\n"); 813 bus_space_write_1(iot, ioh, VIRTIO_CONFIG1_DEVICE_STATUS, 814 VIRTIO_CONFIG_DEVICE_STATUS_FAILED); 815 return; 816 } 817 818 sc->sc_active_features = negotiated; 819 return; 820 } 821 822 823 /* ------------------------------------- 824 * Generic PCI interrupt code 825 * -------------------------------------*/ 826 827 static int 828 virtio_pci_setup_interrupts_10(struct virtio_softc *sc, int reinit) 829 { 830 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 831 bus_space_tag_t iot = psc->sc_iot; 832 bus_space_handle_t ioh = psc->sc_ioh; 833 int vector, ret, qid; 834 835 if (!virtio_pci_msix_enabled(psc)) 836 return 0; 837 838 vector = VIRTIO_MSIX_CONFIG_VECTOR_INDEX; 839 bus_space_write_2(iot, ioh, 840 VIRTIO_CONFIG1_CONFIG_MSIX_VECTOR, vector); 841 ret = bus_space_read_2(iot, ioh, VIRTIO_CONFIG1_CONFIG_MSIX_VECTOR); 842 if (ret != vector) { 843 VIRTIO_PCI_LOG(sc, reinit, 844 "can't set config msix vector\n"); 845 return -1; 846 } 847 848 for (qid = 0; qid < sc->sc_nvqs; qid++) { 849 vector = VIRTIO_MSIX_QUEUE_VECTOR_INDEX; 850 851 if (sc->sc_child_mq) 852 vector += qid; 853 bus_space_write_2(iot, ioh, VIRTIO_CONFIG1_QUEUE_SELECT, qid); 854 bus_space_write_2(iot, ioh, VIRTIO_CONFIG1_QUEUE_MSIX_VECTOR, 855 vector); 856 ret = bus_space_read_2(iot, ioh, 857 VIRTIO_CONFIG1_QUEUE_MSIX_VECTOR); 858 if (ret != vector) { 859 VIRTIO_PCI_LOG(sc, reinit, "can't set queue %d " 860 "msix vector\n", qid); 861 return -1; 862 } 863 } 864 865 return 0; 866 } 867 868 static int 869 virtio_pci_setup_interrupts_09(struct virtio_softc *sc, int reinit) 870 { 871 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 872 int offset, vector, ret, qid; 873 874 if (!virtio_pci_msix_enabled(psc)) 875 return 0; 876 877 offset = VIRTIO_CONFIG_MSI_CONFIG_VECTOR; 878 vector = VIRTIO_MSIX_CONFIG_VECTOR_INDEX; 879 880 bus_space_write_2(psc->sc_iot, psc->sc_ioh, offset, vector); 881 ret = bus_space_read_2(psc->sc_iot, psc->sc_ioh, offset); 882 aprint_debug_dev(sc->sc_dev, "expected=%d, actual=%d\n", 883 vector, ret); 884 if (ret != vector) { 885 VIRTIO_PCI_LOG(sc, reinit, 886 "can't set config msix vector\n"); 887 return -1; 888 } 889 890 for (qid = 0; qid < sc->sc_nvqs; qid++) { 891 offset = VIRTIO_CONFIG_QUEUE_SELECT; 892 bus_space_write_2(psc->sc_iot, psc->sc_ioh, offset, qid); 893 894 offset = VIRTIO_CONFIG_MSI_QUEUE_VECTOR; 895 vector = VIRTIO_MSIX_QUEUE_VECTOR_INDEX; 896 897 if (sc->sc_child_mq) 898 vector += qid; 899 900 bus_space_write_2(psc->sc_iot, psc->sc_ioh, offset, vector); 901 ret = bus_space_read_2(psc->sc_iot, psc->sc_ioh, offset); 902 aprint_debug_dev(sc->sc_dev, "expected=%d, actual=%d\n", 903 vector, ret); 904 if (ret != vector) { 905 VIRTIO_PCI_LOG(sc, reinit, "can't set queue %d " 906 "msix vector\n", qid); 907 return -1; 908 } 909 } 910 911 return 0; 912 } 913 914 static int 915 virtio_pci_establish_msix_interrupts(struct virtio_softc *sc, 916 struct pci_attach_args *pa) 917 { 918 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 919 device_t self = sc->sc_dev; 920 pci_chipset_tag_t pc = pa->pa_pc; 921 struct virtqueue *vq; 922 char intrbuf[PCI_INTRSTR_LEN]; 923 char intr_xname[INTRDEVNAMEBUF]; 924 char const *intrstr; 925 int idx, qid, n; 926 927 idx = VIRTIO_MSIX_CONFIG_VECTOR_INDEX; 928 if (sc->sc_flags & VIRTIO_F_INTR_MPSAFE) 929 pci_intr_setattr(pc, &psc->sc_ihp[idx], PCI_INTR_MPSAFE, true); 930 931 snprintf(intr_xname, sizeof(intr_xname), "%s config", 932 device_xname(sc->sc_dev)); 933 934 psc->sc_ihs[idx] = pci_intr_establish_xname(pc, psc->sc_ihp[idx], 935 sc->sc_ipl, virtio_pci_msix_config_intr, sc, intr_xname); 936 if (psc->sc_ihs[idx] == NULL) { 937 aprint_error_dev(self, "couldn't establish MSI-X for config\n"); 938 goto error; 939 } 940 941 idx = VIRTIO_MSIX_QUEUE_VECTOR_INDEX; 942 if (sc->sc_child_mq) { 943 for (qid = 0; qid < sc->sc_nvqs; qid++) { 944 n = idx + qid; 945 vq = &sc->sc_vqs[qid]; 946 947 snprintf(intr_xname, sizeof(intr_xname), "%s vq#%d", 948 device_xname(sc->sc_dev), qid); 949 950 if (sc->sc_flags & VIRTIO_F_INTR_MPSAFE) { 951 pci_intr_setattr(pc, &psc->sc_ihp[n], 952 PCI_INTR_MPSAFE, true); 953 } 954 955 psc->sc_ihs[n] = pci_intr_establish_xname(pc, psc->sc_ihp[n], 956 sc->sc_ipl, vq->vq_intrhand, vq->vq_intrhand_arg, intr_xname); 957 if (psc->sc_ihs[n] == NULL) { 958 aprint_error_dev(self, "couldn't establish MSI-X for a vq\n"); 959 goto error; 960 } 961 } 962 } else { 963 if (sc->sc_flags & VIRTIO_F_INTR_MPSAFE) 964 pci_intr_setattr(pc, &psc->sc_ihp[idx], PCI_INTR_MPSAFE, true); 965 966 snprintf(intr_xname, sizeof(intr_xname), "%s queues", 967 device_xname(sc->sc_dev)); 968 psc->sc_ihs[idx] = pci_intr_establish_xname(pc, psc->sc_ihp[idx], 969 sc->sc_ipl, virtio_pci_msix_queue_intr, sc, intr_xname); 970 if (psc->sc_ihs[idx] == NULL) { 971 aprint_error_dev(self, "couldn't establish MSI-X for queues\n"); 972 goto error; 973 } 974 } 975 976 idx = VIRTIO_MSIX_CONFIG_VECTOR_INDEX; 977 intrstr = pci_intr_string(pc, psc->sc_ihp[idx], intrbuf, sizeof(intrbuf)); 978 aprint_normal_dev(self, "config interrupting at %s\n", intrstr); 979 idx = VIRTIO_MSIX_QUEUE_VECTOR_INDEX; 980 if (sc->sc_child_mq) { 981 kcpuset_t *affinity; 982 int affinity_to, r; 983 984 kcpuset_create(&affinity, false); 985 986 for (qid = 0; qid < sc->sc_nvqs; qid++) { 987 n = idx + qid; 988 affinity_to = (qid / 2) % ncpu; 989 990 intrstr = pci_intr_string(pc, psc->sc_ihp[n], 991 intrbuf, sizeof(intrbuf)); 992 993 kcpuset_zero(affinity); 994 kcpuset_set(affinity, affinity_to); 995 r = interrupt_distribute(psc->sc_ihs[n], affinity, NULL); 996 if (r == 0) { 997 aprint_normal_dev(self, 998 "for vq #%d interrupting at %s affinity to %u\n", 999 qid, intrstr, affinity_to); 1000 } else { 1001 aprint_normal_dev(self, 1002 "for vq #%d interrupting at %s\n", 1003 qid, intrstr); 1004 } 1005 } 1006 1007 kcpuset_destroy(affinity); 1008 } else { 1009 intrstr = pci_intr_string(pc, psc->sc_ihp[idx], intrbuf, sizeof(intrbuf)); 1010 aprint_normal_dev(self, "queues interrupting at %s\n", intrstr); 1011 } 1012 1013 return 0; 1014 1015 error: 1016 idx = VIRTIO_MSIX_CONFIG_VECTOR_INDEX; 1017 if (psc->sc_ihs[idx] != NULL) 1018 pci_intr_disestablish(psc->sc_pa.pa_pc, psc->sc_ihs[idx]); 1019 idx = VIRTIO_MSIX_QUEUE_VECTOR_INDEX; 1020 if (sc->sc_child_mq) { 1021 for (qid = 0; qid < sc->sc_nvqs; qid++) { 1022 n = idx + qid; 1023 if (psc->sc_ihs[n] == NULL) 1024 continue; 1025 pci_intr_disestablish(psc->sc_pa.pa_pc, psc->sc_ihs[n]); 1026 } 1027 1028 } else { 1029 if (psc->sc_ihs[idx] != NULL) 1030 pci_intr_disestablish(psc->sc_pa.pa_pc, psc->sc_ihs[idx]); 1031 } 1032 1033 return -1; 1034 } 1035 1036 static int 1037 virtio_pci_establish_intx_interrupt(struct virtio_softc *sc, 1038 struct pci_attach_args *pa) 1039 { 1040 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 1041 device_t self = sc->sc_dev; 1042 pci_chipset_tag_t pc = pa->pa_pc; 1043 char intrbuf[PCI_INTRSTR_LEN]; 1044 char const *intrstr; 1045 1046 if (sc->sc_flags & VIRTIO_F_INTR_MPSAFE) 1047 pci_intr_setattr(pc, &psc->sc_ihp[0], PCI_INTR_MPSAFE, true); 1048 1049 psc->sc_ihs[0] = pci_intr_establish_xname(pc, psc->sc_ihp[0], 1050 sc->sc_ipl, virtio_pci_intr, sc, device_xname(sc->sc_dev)); 1051 if (psc->sc_ihs[0] == NULL) { 1052 aprint_error_dev(self, "couldn't establish INTx\n"); 1053 return -1; 1054 } 1055 1056 intrstr = pci_intr_string(pc, psc->sc_ihp[0], intrbuf, sizeof(intrbuf)); 1057 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1058 1059 return 0; 1060 } 1061 1062 static int 1063 virtio_pci_alloc_interrupts(struct virtio_softc *sc) 1064 { 1065 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 1066 device_t self = sc->sc_dev; 1067 pci_chipset_tag_t pc = psc->sc_pa.pa_pc; 1068 pcitag_t tag = psc->sc_pa.pa_tag; 1069 int error; 1070 int nmsix; 1071 int off; 1072 int counts[PCI_INTR_TYPE_SIZE]; 1073 pci_intr_type_t max_type; 1074 pcireg_t ctl; 1075 1076 nmsix = pci_msix_count(psc->sc_pa.pa_pc, psc->sc_pa.pa_tag); 1077 aprint_debug_dev(self, "pci_msix_count=%d\n", nmsix); 1078 1079 /* We need at least two: one for config and the other for queues */ 1080 if ((sc->sc_flags & VIRTIO_F_INTR_MSIX) == 0 || nmsix < 2) { 1081 /* Try INTx only */ 1082 max_type = PCI_INTR_TYPE_INTX; 1083 counts[PCI_INTR_TYPE_INTX] = 1; 1084 } else { 1085 /* Try MSI-X first and INTx second */ 1086 if (sc->sc_nvqs + VIRTIO_MSIX_QUEUE_VECTOR_INDEX <= nmsix) { 1087 nmsix = sc->sc_nvqs + VIRTIO_MSIX_QUEUE_VECTOR_INDEX; 1088 } else { 1089 sc->sc_child_mq = false; 1090 } 1091 1092 if (sc->sc_child_mq == false) { 1093 nmsix = 2; 1094 } 1095 1096 max_type = PCI_INTR_TYPE_MSIX; 1097 counts[PCI_INTR_TYPE_MSIX] = nmsix; 1098 counts[PCI_INTR_TYPE_MSI] = 0; 1099 counts[PCI_INTR_TYPE_INTX] = 1; 1100 } 1101 1102 retry: 1103 error = pci_intr_alloc(&psc->sc_pa, &psc->sc_ihp, counts, max_type); 1104 if (error != 0) { 1105 aprint_error_dev(self, "couldn't map interrupt\n"); 1106 return -1; 1107 } 1108 1109 if (pci_intr_type(pc, psc->sc_ihp[0]) == PCI_INTR_TYPE_MSIX) { 1110 psc->sc_ihs = kmem_zalloc(sizeof(*psc->sc_ihs) * nmsix, 1111 KM_SLEEP); 1112 1113 error = virtio_pci_establish_msix_interrupts(sc, &psc->sc_pa); 1114 if (error != 0) { 1115 kmem_free(psc->sc_ihs, sizeof(*psc->sc_ihs) * nmsix); 1116 pci_intr_release(pc, psc->sc_ihp, nmsix); 1117 1118 /* Retry INTx */ 1119 max_type = PCI_INTR_TYPE_INTX; 1120 counts[PCI_INTR_TYPE_INTX] = 1; 1121 goto retry; 1122 } 1123 1124 psc->sc_ihs_num = nmsix; 1125 psc->sc_devcfg_offset = VIRTIO_CONFIG_DEVICE_CONFIG_MSI; 1126 virtio_pci_adjust_config_region(psc); 1127 } else if (pci_intr_type(pc, psc->sc_ihp[0]) == PCI_INTR_TYPE_INTX) { 1128 psc->sc_ihs = kmem_zalloc(sizeof(*psc->sc_ihs) * 1, 1129 KM_SLEEP); 1130 1131 error = virtio_pci_establish_intx_interrupt(sc, &psc->sc_pa); 1132 if (error != 0) { 1133 kmem_free(psc->sc_ihs, sizeof(*psc->sc_ihs) * 1); 1134 pci_intr_release(pc, psc->sc_ihp, 1); 1135 return -1; 1136 } 1137 1138 psc->sc_ihs_num = 1; 1139 psc->sc_devcfg_offset = VIRTIO_CONFIG_DEVICE_CONFIG_NOMSI; 1140 virtio_pci_adjust_config_region(psc); 1141 1142 error = pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL); 1143 if (error != 0) { 1144 ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 1145 ctl &= ~PCI_MSIX_CTL_ENABLE; 1146 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 1147 } 1148 } 1149 1150 return 0; 1151 } 1152 1153 static void 1154 virtio_pci_free_interrupts(struct virtio_softc *sc) 1155 { 1156 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 1157 1158 for (int i = 0; i < psc->sc_ihs_num; i++) { 1159 if (psc->sc_ihs[i] == NULL) 1160 continue; 1161 pci_intr_disestablish(psc->sc_pa.pa_pc, psc->sc_ihs[i]); 1162 psc->sc_ihs[i] = NULL; 1163 } 1164 1165 if (psc->sc_ihs_num > 0) 1166 pci_intr_release(psc->sc_pa.pa_pc, psc->sc_ihp, psc->sc_ihs_num); 1167 1168 if (psc->sc_ihs != NULL) { 1169 kmem_free(psc->sc_ihs, sizeof(*psc->sc_ihs) * psc->sc_ihs_num); 1170 psc->sc_ihs = NULL; 1171 } 1172 psc->sc_ihs_num = 0; 1173 } 1174 1175 static bool 1176 virtio_pci_msix_enabled(struct virtio_pci_softc *psc) 1177 { 1178 pci_chipset_tag_t pc = psc->sc_pa.pa_pc; 1179 1180 if (pci_intr_type(pc, psc->sc_ihp[0]) == PCI_INTR_TYPE_MSIX) 1181 return true; 1182 1183 return false; 1184 } 1185 1186 /* 1187 * Interrupt handler. 1188 */ 1189 static int 1190 virtio_pci_intr(void *arg) 1191 { 1192 struct virtio_softc *sc = arg; 1193 struct virtio_pci_softc * const psc = (struct virtio_pci_softc *)sc; 1194 int isr, r = 0; 1195 1196 /* check and ack the interrupt */ 1197 isr = bus_space_read_1(psc->sc_isr_iot, psc->sc_isr_ioh, 0); 1198 if (isr == 0) 1199 return 0; 1200 if ((isr & VIRTIO_CONFIG_ISR_CONFIG_CHANGE) && 1201 (sc->sc_config_change != NULL)) 1202 r = (sc->sc_config_change)(sc); 1203 if (sc->sc_intrhand != NULL) { 1204 if (sc->sc_soft_ih != NULL) 1205 softint_schedule(sc->sc_soft_ih); 1206 else 1207 r |= (sc->sc_intrhand)(sc); 1208 } 1209 1210 return r; 1211 } 1212 1213 static int 1214 virtio_pci_msix_queue_intr(void *arg) 1215 { 1216 struct virtio_softc *sc = arg; 1217 int r = 0; 1218 1219 if (sc->sc_intrhand != NULL) { 1220 if (sc->sc_soft_ih != NULL) 1221 softint_schedule(sc->sc_soft_ih); 1222 else 1223 r |= (sc->sc_intrhand)(sc); 1224 } 1225 1226 return r; 1227 } 1228 1229 static int 1230 virtio_pci_msix_config_intr(void *arg) 1231 { 1232 struct virtio_softc *sc = arg; 1233 int r = 0; 1234 1235 if (sc->sc_config_change != NULL) 1236 r = (sc->sc_config_change)(sc); 1237 return r; 1238 } 1239 1240 MODULE(MODULE_CLASS_DRIVER, virtio_pci, "pci,virtio"); 1241 1242 #ifdef _MODULE 1243 #include "ioconf.c" 1244 #endif 1245 1246 static int 1247 virtio_pci_modcmd(modcmd_t cmd, void *opaque) 1248 { 1249 int error = 0; 1250 1251 #ifdef _MODULE 1252 switch (cmd) { 1253 case MODULE_CMD_INIT: 1254 error = config_init_component(cfdriver_ioconf_virtio_pci, 1255 cfattach_ioconf_virtio_pci, cfdata_ioconf_virtio_pci); 1256 break; 1257 case MODULE_CMD_FINI: 1258 error = config_fini_component(cfdriver_ioconf_virtio_pci, 1259 cfattach_ioconf_virtio_pci, cfdata_ioconf_virtio_pci); 1260 break; 1261 default: 1262 error = ENOTTY; 1263 break; 1264 } 1265 #endif 1266 1267 return error; 1268 } 1269
Indexes created Mon Sep 22 13:09:51 GMT 2025