pwmclock.c revision 1.5.2.4
1 1.5.2.4 yamt /* $NetBSD: pwmclock.c,v 1.5.2.4 2014/05/22 11:40:34 yamt Exp $ */ 2 1.5.2.2 yamt 3 1.5.2.2 yamt /* 4 1.5.2.2 yamt * Copyright (c) 2011 Michael Lorenz 5 1.5.2.2 yamt * All rights reserved. 6 1.5.2.2 yamt * 7 1.5.2.2 yamt * Redistribution and use in source and binary forms, with or without 8 1.5.2.2 yamt * modification, are permitted provided that the following conditions 9 1.5.2.2 yamt * are met: 10 1.5.2.2 yamt * 1. Redistributions of source code must retain the above copyright 11 1.5.2.2 yamt * notice, this list of conditions and the following disclaimer. 12 1.5.2.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 13 1.5.2.2 yamt * notice, this list of conditions and the following disclaimer in the 14 1.5.2.2 yamt * documentation and/or other materials provided with the distribution. 15 1.5.2.2 yamt * 16 1.5.2.2 yamt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.5.2.2 yamt * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.5.2.2 yamt * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.5.2.2 yamt * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.5.2.2 yamt * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 1.5.2.2 yamt * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 1.5.2.2 yamt * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 1.5.2.2 yamt * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 1.5.2.2 yamt * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 1.5.2.2 yamt * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 1.5.2.2 yamt */ 27 1.5.2.2 yamt 28 1.5.2.2 yamt #include <sys/cdefs.h> 29 1.5.2.4 yamt __KERNEL_RCSID(0, "$NetBSD: pwmclock.c,v 1.5.2.4 2014/05/22 11:40:34 yamt Exp $"); 30 1.5.2.2 yamt 31 1.5.2.2 yamt #include <sys/param.h> 32 1.5.2.2 yamt #include <sys/systm.h> 33 1.5.2.2 yamt #include <sys/kernel.h> 34 1.5.2.2 yamt #include <sys/device.h> 35 1.5.2.2 yamt #include <sys/cpu.h> 36 1.5.2.2 yamt #include <sys/timetc.h> 37 1.5.2.2 yamt #include <sys/sysctl.h> 38 1.5.2.2 yamt 39 1.5.2.2 yamt #include <dev/pci/voyagervar.h> 40 1.5.2.2 yamt #include <dev/ic/sm502reg.h> 41 1.5.2.2 yamt 42 1.5.2.2 yamt #include <mips/mips3_clock.h> 43 1.5.2.2 yamt #include <mips/locore.h> 44 1.5.2.2 yamt #include <mips/bonito/bonitoreg.h> 45 1.5.2.2 yamt #include <mips/bonito/bonitovar.h> 46 1.5.2.2 yamt 47 1.5.2.2 yamt #include "opt_pwmclock.h" 48 1.5.2.2 yamt 49 1.5.2.2 yamt #ifdef PWMCLOCK_DEBUG 50 1.5.2.2 yamt #define DPRINTF aprint_error 51 1.5.2.2 yamt #else 52 1.5.2.2 yamt #define DPRINTF while (0) printf 53 1.5.2.2 yamt #endif 54 1.5.2.2 yamt 55 1.5.2.2 yamt int pwmclock_intr(void *); 56 1.5.2.2 yamt 57 1.5.2.2 yamt struct pwmclock_softc { 58 1.5.2.2 yamt device_t sc_dev; 59 1.5.2.2 yamt bus_space_tag_t sc_memt; 60 1.5.2.2 yamt bus_space_handle_t sc_regh; 61 1.5.2.2 yamt uint32_t sc_reg, sc_last; 62 1.5.2.2 yamt uint32_t sc_scale[8]; 63 1.5.2.2 yamt uint32_t sc_count; /* should probably be 64 bit */ 64 1.5.2.2 yamt int sc_step; 65 1.5.2.2 yamt int sc_step_wanted; 66 1.5.2.2 yamt void *sc_shutdown_cookie; 67 1.5.2.2 yamt }; 68 1.5.2.2 yamt 69 1.5.2.2 yamt static int pwmclock_match(device_t, cfdata_t, void *); 70 1.5.2.2 yamt static void pwmclock_attach(device_t, device_t, void *); 71 1.5.2.2 yamt 72 1.5.2.2 yamt CFATTACH_DECL_NEW(pwmclock, sizeof(struct pwmclock_softc), 73 1.5.2.2 yamt pwmclock_match, pwmclock_attach, NULL, NULL); 74 1.5.2.2 yamt 75 1.5.2.2 yamt static void pwmclock_start(void); 76 1.5.2.2 yamt static u_int get_pwmclock_timecount(struct timecounter *); 77 1.5.2.2 yamt 78 1.5.2.2 yamt struct pwmclock_softc *pwmclock; 79 1.5.2.2 yamt extern void (*initclocks_ptr)(void); 80 1.5.2.2 yamt extern struct clockframe cf; 81 1.5.2.2 yamt 82 1.5.2.2 yamt /* 0, 1/4, 3/8, 1/2, 5/8, 3/4, 7/8, 1 */ 83 1.5.2.2 yamt static int scale_m[] = {1, 1, 3, 1, 5, 3, 7, 1}; 84 1.5.2.2 yamt static int scale_d[] = {0, 4, 8, 2, 8, 4, 8, 1}; 85 1.5.2.2 yamt 86 1.5.2.2 yamt #define scale(x, f) (x * scale_d[f] / scale_m[f]) 87 1.5.2.2 yamt 88 1.5.2.2 yamt void pwmclock_set_speed(struct pwmclock_softc *, int); 89 1.5.2.2 yamt static int pwmclock_cpuspeed_temp(SYSCTLFN_ARGS); 90 1.5.2.2 yamt static int pwmclock_cpuspeed_cur(SYSCTLFN_ARGS); 91 1.5.2.2 yamt static int pwmclock_cpuspeed_available(SYSCTLFN_ARGS); 92 1.5.2.2 yamt 93 1.5.2.2 yamt static void pwmclock_shutdown(void *); 94 1.5.2.2 yamt 95 1.5.2.2 yamt static struct timecounter pwmclock_timecounter = { 96 1.5.2.2 yamt get_pwmclock_timecount, /* get_timecount */ 97 1.5.2.2 yamt 0, /* no poll_pps */ 98 1.5.2.2 yamt 0xffffffff, /* counter_mask */ 99 1.5.2.2 yamt 0, /* frequency */ 100 1.5.2.2 yamt "pwm", /* name */ 101 1.5.2.2 yamt 100, /* quality */ 102 1.5.2.2 yamt NULL, /* tc_priv */ 103 1.5.2.2 yamt NULL /* tc_next */ 104 1.5.2.2 yamt }; 105 1.5.2.2 yamt 106 1.5.2.2 yamt static int 107 1.5.2.2 yamt pwmclock_match(device_t parent, cfdata_t match, void *aux) 108 1.5.2.2 yamt { 109 1.5.2.2 yamt struct voyager_attach_args *vaa = (struct voyager_attach_args *)aux; 110 1.5.2.2 yamt 111 1.5.2.2 yamt if (strcmp(vaa->vaa_name, "pwmclock") == 0) return 100; 112 1.5.2.2 yamt return 0; 113 1.5.2.2 yamt } 114 1.5.2.2 yamt 115 1.5.2.2 yamt static uint32_t 116 1.5.2.2 yamt pwmclock_wait_edge(struct pwmclock_softc *sc) 117 1.5.2.2 yamt { 118 1.5.2.2 yamt /* clear interrupt */ 119 1.5.2.2 yamt bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, sc->sc_reg); 120 1.5.2.2 yamt while ((bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_PWM1) & 121 1.5.2.2 yamt SM502_PWM_INTR_PENDING) == 0); 122 1.5.2.2 yamt return mips3_cp0_count_read(); 123 1.5.2.2 yamt } 124 1.5.2.2 yamt 125 1.5.2.2 yamt static void 126 1.5.2.2 yamt pwmclock_attach(device_t parent, device_t self, void *aux) 127 1.5.2.2 yamt { 128 1.5.2.2 yamt struct pwmclock_softc *sc = device_private(self); 129 1.5.2.2 yamt struct voyager_attach_args *vaa = aux; 130 1.5.2.2 yamt const struct sysctlnode *sysctl_node, *me, *freq; 131 1.5.2.2 yamt uint32_t reg, last, curr, diff, acc; 132 1.5.2.2 yamt int i, clk; 133 1.5.2.2 yamt 134 1.5.2.2 yamt sc->sc_dev = self; 135 1.5.2.2 yamt sc->sc_memt = vaa->vaa_tag; 136 1.5.2.2 yamt sc->sc_regh = vaa->vaa_regh; 137 1.5.2.2 yamt 138 1.5.2.2 yamt aprint_normal("\n"); 139 1.5.2.2 yamt 140 1.5.2.2 yamt voyager_establish_intr(parent, 22, pwmclock_intr, sc); 141 1.5.2.2 yamt reg = voyager_set_pwm(100, 100); /* 100Hz, 10% duty cycle */ 142 1.5.2.2 yamt reg |= SM502_PWM_ENABLE | SM502_PWM_ENABLE_INTR | 143 1.5.2.2 yamt SM502_PWM_INTR_PENDING; 144 1.5.2.2 yamt sc->sc_reg = reg; 145 1.5.2.2 yamt pwmclock = sc; 146 1.5.2.2 yamt initclocks_ptr = pwmclock_start; 147 1.5.2.2 yamt 148 1.5.2.2 yamt /* 149 1.5.2.2 yamt * Establish a hook so on shutdown we can set the CPU clock back to 150 1.5.2.2 yamt * full speed. This is necessary because PMON doesn't change the 151 1.5.2.2 yamt * clock scale register on a warm boot, the MIPS clock code gets 152 1.5.2.2 yamt * confused if we're too slow and the loongson-specific bits run 153 1.5.2.2 yamt * too late in the boot process 154 1.5.2.2 yamt */ 155 1.5.2.2 yamt sc->sc_shutdown_cookie = shutdownhook_establish(pwmclock_shutdown, sc); 156 1.5.2.2 yamt 157 1.5.2.2 yamt /* ok, let's see how far the cycle counter gets between interrupts */ 158 1.5.2.2 yamt DPRINTF("calibrating CPU timer...\n"); 159 1.5.2.2 yamt for (clk = 1; clk < 8; clk++) { 160 1.5.2.4 yamt 161 1.5.2.2 yamt REGVAL(LS2F_CHIPCFG0) = 162 1.5.2.2 yamt (REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | clk; 163 1.5.2.2 yamt bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, 164 1.5.2.2 yamt sc->sc_reg); 165 1.5.2.2 yamt acc = 0; 166 1.5.2.2 yamt last = pwmclock_wait_edge(sc); 167 1.5.2.2 yamt for (i = 0; i < 16; i++) { 168 1.5.2.2 yamt curr = pwmclock_wait_edge(sc); 169 1.5.2.2 yamt diff = curr - last; 170 1.5.2.2 yamt acc += diff; 171 1.5.2.2 yamt last = curr; 172 1.5.2.2 yamt } 173 1.5.2.2 yamt sc->sc_scale[clk] = (acc >> 4) / 5000; 174 1.5.2.2 yamt } 175 1.5.2.2 yamt #ifdef PWMCLOCK_DEBUG 176 1.5.2.2 yamt for (clk = 1; clk < 8; clk++) { 177 1.5.2.2 yamt aprint_normal_dev(sc->sc_dev, "%d/8: %d\n", clk + 1, 178 1.5.2.2 yamt sc->sc_scale[clk]); 179 1.5.2.2 yamt } 180 1.5.2.2 yamt #endif 181 1.5.2.2 yamt sc->sc_step = 7; 182 1.5.2.2 yamt sc->sc_step_wanted = 7; 183 1.5.2.2 yamt 184 1.5.2.2 yamt /* now setup sysctl */ 185 1.5.2.2 yamt if (sysctl_createv(NULL, 0, NULL, 186 1.5.2.2 yamt &me, 187 1.5.2.2 yamt CTLFLAG_READWRITE, CTLTYPE_NODE, "loongson", NULL, NULL, 188 1.5.2.2 yamt 0, NULL, 0, CTL_MACHDEP, CTL_CREATE, CTL_EOL) != 0) 189 1.5.2.2 yamt aprint_error_dev(sc->sc_dev, 190 1.5.2.2 yamt "couldn't create 'loongson' node\n"); 191 1.5.2.2 yamt 192 1.5.2.2 yamt if (sysctl_createv(NULL, 0, NULL, 193 1.5.2.2 yamt &freq, 194 1.5.2.2 yamt CTLFLAG_READWRITE, CTLTYPE_NODE, "frequency", NULL, NULL, 0, NULL, 195 1.5.2.2 yamt 0, CTL_MACHDEP, me->sysctl_num, CTL_CREATE, CTL_EOL) != 0) 196 1.5.2.2 yamt aprint_error_dev(sc->sc_dev, 197 1.5.2.2 yamt "couldn't create 'frequency' node\n"); 198 1.5.2.2 yamt 199 1.5.2.2 yamt if (sysctl_createv(NULL, 0, NULL, 200 1.5.2.2 yamt &sysctl_node, 201 1.5.2.2 yamt CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 202 1.5.2.2 yamt CTLTYPE_INT, "target", "CPU speed", pwmclock_cpuspeed_temp, 203 1.5.2.3 yamt 0, (void *)sc, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num, 204 1.5.2.2 yamt CTL_CREATE, CTL_EOL) == 0) { 205 1.5.2.2 yamt } else 206 1.5.2.2 yamt aprint_error_dev(sc->sc_dev, 207 1.5.2.2 yamt "couldn't create 'target' node\n"); 208 1.5.2.2 yamt 209 1.5.2.2 yamt if (sysctl_createv(NULL, 0, NULL, 210 1.5.2.2 yamt &sysctl_node, 211 1.5.2.2 yamt CTLFLAG_READWRITE, 212 1.5.2.2 yamt CTLTYPE_INT, "current", NULL, pwmclock_cpuspeed_cur, 213 1.5.2.3 yamt 1, (void *)sc, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num, 214 1.5.2.2 yamt CTL_CREATE, CTL_EOL) == 0) { 215 1.5.2.2 yamt } else 216 1.5.2.2 yamt aprint_error_dev(sc->sc_dev, 217 1.5.2.2 yamt "couldn't create 'current' node\n"); 218 1.5.2.2 yamt 219 1.5.2.2 yamt if (sysctl_createv(NULL, 0, NULL, 220 1.5.2.2 yamt &sysctl_node, 221 1.5.2.2 yamt CTLFLAG_READWRITE, 222 1.5.2.2 yamt CTLTYPE_STRING, "available", NULL, pwmclock_cpuspeed_available, 223 1.5.2.3 yamt 2, (void *)sc, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num, 224 1.5.2.2 yamt CTL_CREATE, CTL_EOL) == 0) { 225 1.5.2.2 yamt } else 226 1.5.2.2 yamt aprint_error_dev(sc->sc_dev, 227 1.5.2.2 yamt "couldn't create 'available' node\n"); 228 1.5.2.2 yamt } 229 1.5.2.2 yamt 230 1.5.2.2 yamt static void 231 1.5.2.2 yamt pwmclock_shutdown(void *cookie) 232 1.5.2.2 yamt { 233 1.5.2.2 yamt struct pwmclock_softc *sc = cookie; 234 1.5.2.2 yamt 235 1.5.2.2 yamt /* just in case the interrupt handler runs again after this */ 236 1.5.2.2 yamt sc->sc_step_wanted = 7; 237 1.5.2.2 yamt /* set the clock to full speed */ 238 1.5.2.2 yamt REGVAL(LS2F_CHIPCFG0) = 239 1.5.2.2 yamt (REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | 7; 240 1.5.2.2 yamt } 241 1.5.2.2 yamt 242 1.5.2.2 yamt void 243 1.5.2.2 yamt pwmclock_set_speed(struct pwmclock_softc *sc, int speed) 244 1.5.2.2 yamt { 245 1.5.2.2 yamt 246 1.5.2.2 yamt if ((speed < 1) || (speed > 7)) 247 1.5.2.2 yamt return; 248 1.5.2.2 yamt sc->sc_step_wanted = speed; 249 1.5.2.2 yamt DPRINTF("%s: %d\n", __func__, speed); 250 1.5.2.2 yamt } 251 1.5.2.2 yamt 252 1.5.2.2 yamt /* 253 1.5.2.2 yamt * the PWM interrupt handler 254 1.5.2.2 yamt * we don't have a CPU clock independent, high resolution counter so we're 255 1.5.2.2 yamt * stuck with a PWM that can't count and a CP0 counter that slows down or 256 1.5.2.2 yamt * speeds up with the actual CPU speed. In order to still get halfway 257 1.5.2.2 yamt * accurate time we do the following: 258 1.5.2.2 yamt * - only change CPU speed in the timer interrupt 259 1.5.2.2 yamt * - each timer interrupt we measure how many CP0 cycles passed since last 260 1.5.2.2 yamt * time, adjust for CPU speed since we can be sure it didn't change, use 261 1.5.2.2 yamt * that to update a separate counter 262 1.5.2.2 yamt * - when reading the time counter we take the number of CP0 ticks since 263 1.5.2.2 yamt * the last timer interrupt, scale it to CPU clock, return that plus the 264 1.5.2.2 yamt * interrupt updated counter mentioned above to get something close to 265 1.5.2.2 yamt * CP0 running at full speed 266 1.5.2.2 yamt * - when changing CPU speed do it as close to taking the time from CP0 as 267 1.5.2.2 yamt * possible to keep the period of time we spend with CP0 running at the 268 1.5.2.2 yamt * wrong frequency as short as possible - hopefully short enough to stay 269 1.5.2.2 yamt * insignificant compared to other noise since switching speeds isn't 270 1.5.2.2 yamt * going to happen all that often 271 1.5.2.2 yamt */ 272 1.5.2.2 yamt 273 1.5.2.2 yamt int 274 1.5.2.2 yamt pwmclock_intr(void *cookie) 275 1.5.2.2 yamt { 276 1.5.2.2 yamt struct pwmclock_softc *sc = cookie; 277 1.5.2.2 yamt uint32_t reg, now, diff; 278 1.5.2.2 yamt 279 1.5.2.2 yamt /* is it us? */ 280 1.5.2.2 yamt reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_PWM1); 281 1.5.2.2 yamt if ((reg & SM502_PWM_INTR_PENDING) == 0) 282 1.5.2.2 yamt return 0; 283 1.5.2.2 yamt 284 1.5.2.2 yamt /* yes, it's us, so clear the interrupt */ 285 1.5.2.2 yamt bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, sc->sc_reg); 286 1.5.2.2 yamt 287 1.5.2.2 yamt /* 288 1.5.2.2 yamt * this looks kinda funny but what we want here is this: 289 1.5.2.2 yamt * - reading the counter and changing the CPU clock should be as 290 1.5.2.2 yamt * close together as possible in order to remain halfway accurate 291 1.5.2.2 yamt * - we need to use the previous sc_step in order to scale the 292 1.5.2.2 yamt * interval passed since the last clock interrupt correctly, so 293 1.5.2.2 yamt * we only change sc_step after doing that 294 1.5.2.2 yamt */ 295 1.5.2.2 yamt if (sc->sc_step_wanted != sc->sc_step) { 296 1.5.2.4 yamt 297 1.5.2.2 yamt REGVAL(LS2F_CHIPCFG0) = 298 1.5.2.2 yamt (REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | 299 1.5.2.2 yamt sc->sc_step_wanted; 300 1.5.2.2 yamt } 301 1.5.2.2 yamt 302 1.5.2.2 yamt now = mips3_cp0_count_read(); 303 1.5.2.2 yamt diff = now - sc->sc_last; 304 1.5.2.2 yamt sc->sc_count += scale(diff, sc->sc_step); 305 1.5.2.2 yamt sc->sc_last = now; 306 1.5.2.2 yamt if (sc->sc_step_wanted != sc->sc_step) { 307 1.5.2.2 yamt sc->sc_step = sc->sc_step_wanted; 308 1.5.2.2 yamt } 309 1.5.2.4 yamt 310 1.5.2.2 yamt hardclock(&cf); 311 1.5.2.2 yamt 312 1.5.2.2 yamt return 1; 313 1.5.2.2 yamt } 314 1.5.2.2 yamt 315 1.5.2.2 yamt static void 316 1.5.2.2 yamt pwmclock_start(void) 317 1.5.2.2 yamt { 318 1.5.2.2 yamt struct pwmclock_softc *sc = pwmclock; 319 1.5.2.2 yamt sc->sc_count = 0; 320 1.5.2.2 yamt sc->sc_last = mips3_cp0_count_read(); 321 1.5.2.2 yamt pwmclock_timecounter.tc_frequency = curcpu()->ci_cpu_freq / 2; 322 1.5.2.2 yamt tc_init(&pwmclock_timecounter); 323 1.5.2.2 yamt bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, sc->sc_reg); 324 1.5.2.2 yamt } 325 1.5.2.2 yamt 326 1.5.2.2 yamt static u_int 327 1.5.2.2 yamt get_pwmclock_timecount(struct timecounter *tc) 328 1.5.2.2 yamt { 329 1.5.2.2 yamt struct pwmclock_softc *sc = pwmclock; 330 1.5.2.2 yamt uint32_t now, diff; 331 1.5.2.2 yamt 332 1.5.2.2 yamt now = mips3_cp0_count_read(); 333 1.5.2.2 yamt diff = now - sc->sc_last; 334 1.5.2.2 yamt return sc->sc_count + scale(diff, sc->sc_step); 335 1.5.2.2 yamt } 336 1.5.2.2 yamt 337 1.5.2.2 yamt static int 338 1.5.2.2 yamt pwmclock_cpuspeed_temp(SYSCTLFN_ARGS) 339 1.5.2.2 yamt { 340 1.5.2.2 yamt struct sysctlnode node = *rnode; 341 1.5.2.2 yamt struct pwmclock_softc *sc = node.sysctl_data; 342 1.5.2.2 yamt int mhz, i; 343 1.5.2.2 yamt 344 1.5.2.2 yamt mhz = sc->sc_scale[sc->sc_step_wanted]; 345 1.5.2.2 yamt 346 1.5.2.2 yamt node.sysctl_data = &mhz; 347 1.5.2.2 yamt if (sysctl_lookup(SYSCTLFN_CALL(&node)) == 0) { 348 1.5.2.2 yamt int new_reg; 349 1.5.2.2 yamt 350 1.5.2.2 yamt new_reg = *(int *)node.sysctl_data; 351 1.5.2.2 yamt i = 1; 352 1.5.2.2 yamt while ((i < 8) && (sc->sc_scale[i] != new_reg)) 353 1.5.2.2 yamt i++; 354 1.5.2.2 yamt if (i > 7) 355 1.5.2.2 yamt return EINVAL; 356 1.5.2.2 yamt pwmclock_set_speed(sc, i); 357 1.5.2.2 yamt return 0; 358 1.5.2.2 yamt } 359 1.5.2.2 yamt return EINVAL; 360 1.5.2.2 yamt } 361 1.5.2.2 yamt 362 1.5.2.2 yamt static int 363 1.5.2.2 yamt pwmclock_cpuspeed_cur(SYSCTLFN_ARGS) 364 1.5.2.2 yamt { 365 1.5.2.2 yamt struct sysctlnode node = *rnode; 366 1.5.2.2 yamt struct pwmclock_softc *sc = node.sysctl_data; 367 1.5.2.2 yamt int mhz; 368 1.5.2.2 yamt 369 1.5.2.2 yamt mhz = sc->sc_scale[sc->sc_step]; 370 1.5.2.2 yamt node.sysctl_data = &mhz; 371 1.5.2.2 yamt return sysctl_lookup(SYSCTLFN_CALL(&node)); 372 1.5.2.2 yamt } 373 1.5.2.2 yamt 374 1.5.2.2 yamt static int 375 1.5.2.2 yamt pwmclock_cpuspeed_available(SYSCTLFN_ARGS) 376 1.5.2.2 yamt { 377 1.5.2.2 yamt struct sysctlnode node = *rnode; 378 1.5.2.2 yamt struct pwmclock_softc *sc = node.sysctl_data; 379 1.5.2.2 yamt char buf[128]; 380 1.5.2.2 yamt 381 1.5.2.2 yamt snprintf(buf, 128, "%d %d %d %d %d %d %d", sc->sc_scale[1], 382 1.5.2.2 yamt sc->sc_scale[2], sc->sc_scale[3], sc->sc_scale[4], 383 1.5.2.2 yamt sc->sc_scale[5], sc->sc_scale[6], sc->sc_scale[7]); 384 1.5.2.2 yamt node.sysctl_data = buf; 385 1.5.2.2 yamt return(sysctl_lookup(SYSCTLFN_CALL(&node))); 386 1.5.2.2 yamt } 387 1.5.2.2 yamt 388 1.5.2.2 yamt SYSCTL_SETUP(sysctl_ams_setup, "sysctl obio subtree setup") 389 1.5.2.2 yamt { 390 1.5.2.2 yamt 391 1.5.2.2 yamt sysctl_createv(NULL, 0, NULL, NULL, 392 1.5.2.2 yamt CTLFLAG_PERMANENT, 393 1.5.2.2 yamt CTLTYPE_NODE, "machdep", NULL, 394 1.5.2.2 yamt NULL, 0, NULL, 0, 395 1.5.2.2 yamt CTL_MACHDEP, CTL_EOL); 396 1.5.2.2 yamt } 397
Indexes created Wed Oct 01 18:09:54 GMT 2025