pwmclock.c revision 1.3.4.2
1 /* $NetBSD: pwmclock.c,v 1.3.4.2 2012/02/18 07:34:55 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2011 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pwmclock.c,v 1.3.4.2 2012/02/18 07:34:55 mrg Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/cpu.h> 36 #include <sys/timetc.h> 37 #include <sys/sysctl.h> 38 39 #include <dev/pci/voyagervar.h> 40 #include <dev/ic/sm502reg.h> 41 42 #include <mips/mips3_clock.h> 43 #include <mips/locore.h> 44 #include <mips/bonito/bonitoreg.h> 45 #include <mips/bonito/bonitovar.h> 46 47 #include "opt_pwmclock.h" 48 49 #ifdef PWMCLOCK_DEBUG 50 #define DPRINTF aprint_error 51 #else 52 #define DPRINTF while (0) printf 53 #endif 54 55 int pwmclock_intr(void *); 56 57 struct pwmclock_softc { 58 device_t sc_dev; 59 bus_space_tag_t sc_memt; 60 bus_space_handle_t sc_regh; 61 uint32_t sc_reg, sc_last; 62 uint32_t sc_scale[8]; 63 uint32_t sc_count; /* should probably be 64 bit */ 64 int sc_step; 65 int sc_step_wanted; 66 }; 67 68 static int pwmclock_match(device_t, cfdata_t, void *); 69 static void pwmclock_attach(device_t, device_t, void *); 70 71 CFATTACH_DECL_NEW(pwmclock, sizeof(struct pwmclock_softc), 72 pwmclock_match, pwmclock_attach, NULL, NULL); 73 74 static void pwmclock_start(void); 75 static u_int get_pwmclock_timecount(struct timecounter *); 76 77 struct pwmclock_softc *pwmclock; 78 extern void (*initclocks_ptr)(void); 79 extern struct clockframe cf; 80 81 /* 0, 1/4, 3/8, 1/2, 5/8, 3/4, 7/8, 1 */ 82 static int scale_m[] = {1, 1, 3, 1, 5, 3, 7, 1}; 83 static int scale_d[] = {0, 4, 8, 2, 8, 4, 8, 1}; 84 85 #define scale(x, f) (x * scale_d[f] / scale_m[f]) 86 87 void pwmclock_set_speed(struct pwmclock_softc *, int); 88 static int pwmclock_cpuspeed_temp(SYSCTLFN_ARGS); 89 static int pwmclock_cpuspeed_cur(SYSCTLFN_ARGS); 90 static int pwmclock_cpuspeed_available(SYSCTLFN_ARGS); 91 92 static struct timecounter pwmclock_timecounter = { 93 get_pwmclock_timecount, /* get_timecount */ 94 0, /* no poll_pps */ 95 0xffffffff, /* counter_mask */ 96 0, /* frequency */ 97 "pwm", /* name */ 98 100, /* quality */ 99 NULL, /* tc_priv */ 100 NULL /* tc_next */ 101 }; 102 103 static int 104 pwmclock_match(device_t parent, cfdata_t match, void *aux) 105 { 106 struct voyager_attach_args *vaa = (struct voyager_attach_args *)aux; 107 108 if (strcmp(vaa->vaa_name, "pwmclock") == 0) return 100; 109 return 0; 110 } 111 112 static uint32_t 113 pwmclock_wait_edge(struct pwmclock_softc *sc) 114 { 115 /* clear interrupt */ 116 bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, sc->sc_reg); 117 while ((bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_PWM1) & SM502_PWM_INTR_PENDING) == 0); 118 return mips3_cp0_count_read(); 119 } 120 121 static void 122 pwmclock_attach(device_t parent, device_t self, void *aux) 123 { 124 struct pwmclock_softc *sc = device_private(self); 125 struct voyager_attach_args *vaa = aux; 126 const struct sysctlnode *sysctl_node, *me, *freq; 127 uint32_t reg, last, curr, diff, acc; 128 int i, clk; 129 130 sc->sc_dev = self; 131 sc->sc_memt = vaa->vaa_tag; 132 sc->sc_regh = vaa->vaa_regh; 133 134 aprint_normal("\n"); 135 136 voyager_establish_intr(parent, 22, pwmclock_intr, sc); 137 reg = voyager_set_pwm(100, 100); /* 100Hz, 10% duty cycle */ 138 reg |= SM502_PWM_ENABLE | SM502_PWM_ENABLE_INTR | SM502_PWM_INTR_PENDING; 139 sc->sc_reg = reg; 140 pwmclock = sc; 141 initclocks_ptr = pwmclock_start; 142 143 /* ok, let's see how far the cycle counter gets between interrupts */ 144 DPRINTF("calibrating CPU timer...\n"); 145 for (clk = 1; clk < 8; clk++) { 146 REGVAL(LS2F_CHIPCFG0) = (REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | clk; 147 bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, sc->sc_reg); 148 acc = 0; 149 last = pwmclock_wait_edge(sc); 150 for (i = 0; i < 16; i++) { 151 curr = pwmclock_wait_edge(sc); 152 diff = curr - last; 153 acc += diff; 154 last = curr; 155 } 156 sc->sc_scale[clk] = (acc >> 4) / 5000; 157 } 158 #ifdef PWMCLOCK_DEBUG 159 for (clk = 1; clk < 8; clk++) { 160 aprint_normal_dev(sc->sc_dev, "%d/8: %d\n", clk + 1, sc->sc_scale[clk]); 161 } 162 #endif 163 sc->sc_step = 7; 164 sc->sc_step_wanted = 7; 165 166 /* now setup sysctl */ 167 if (sysctl_createv(NULL, 0, NULL, 168 &me, 169 CTLFLAG_READWRITE, CTLTYPE_NODE, "loongson", NULL, NULL, 170 0, NULL, 0, CTL_MACHDEP, CTL_CREATE, CTL_EOL) != 0) 171 aprint_error_dev(sc->sc_dev, "couldn't create 'loongson' node\n"); 172 173 if (sysctl_createv(NULL, 0, NULL, 174 &freq, 175 CTLFLAG_READWRITE, CTLTYPE_NODE, "frequency", NULL, NULL, 176 0, NULL, 0, CTL_MACHDEP, me->sysctl_num, CTL_CREATE, CTL_EOL) != 0) 177 aprint_error_dev(sc->sc_dev, "couldn't create 'frequency' node\n"); 178 179 if (sysctl_createv(NULL, 0, NULL, 180 &sysctl_node, 181 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 182 CTLTYPE_INT, "target", "CPU speed", pwmclock_cpuspeed_temp, 183 0, sc, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num, 184 CTL_CREATE, CTL_EOL) == 0) { 185 } else 186 aprint_error_dev(sc->sc_dev, "couldn't create 'target' node\n"); 187 188 if (sysctl_createv(NULL, 0, NULL, 189 &sysctl_node, 190 CTLFLAG_READWRITE, 191 CTLTYPE_INT, "current", NULL, pwmclock_cpuspeed_cur, 192 1, sc, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num, 193 CTL_CREATE, CTL_EOL) == 0) { 194 } else 195 aprint_error_dev(sc->sc_dev, "couldn't create 'current' node\n"); 196 197 if (sysctl_createv(NULL, 0, NULL, 198 &sysctl_node, 199 CTLFLAG_READWRITE, 200 CTLTYPE_STRING, "available", NULL, pwmclock_cpuspeed_available, 201 2, sc, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num, 202 CTL_CREATE, CTL_EOL) == 0) { 203 } else 204 aprint_error_dev(sc->sc_dev, "couldn't create 'available' node\n"); 205 } 206 207 void 208 pwmclock_set_speed(struct pwmclock_softc *sc, int speed) 209 { 210 211 if ((speed < 1) || (speed > 7)) 212 return; 213 sc->sc_step_wanted = speed; 214 DPRINTF("%s: %d\n", __func__, speed); 215 } 216 217 /* 218 * the PWM interrupt handler 219 * we don't have a CPU clock independent, high resolution counter so we're 220 * stuck with a PWM that can't count and a CP0 counter that slows down or 221 * speeds up with the actual CPU speed. In order to still get halfway 222 * accurate time we do the following: 223 * - only change CPU speed in the timer interrupt 224 * - each timer interrupt we measure how many CP0 cycles passed since last 225 * time, adjust for CPU speed since we can be sure it didn't change, use 226 * that to update a separate counter 227 * - when reading the time counter we take the number of CP0 ticks since 228 * the last timer interrupt, scale it to CPU clock, return that plus the 229 * interrupt updated counter mentioned above to get something close to 230 * CP0 running at full speed 231 * - when changing CPU speed do it as close to taking the time from CP0 as 232 * possible to keep the period of time we spend with CP0 running at the 233 * wrong frequency as short as possible - hopefully short enough to stay 234 * insignificant compared to other noise since switching speeds isn't 235 * going to happen all that often 236 */ 237 238 int 239 pwmclock_intr(void *cookie) 240 { 241 struct pwmclock_softc *sc = cookie; 242 uint32_t reg, now, diff; 243 244 /* is it us? */ 245 reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_PWM1); 246 if ((reg & SM502_PWM_INTR_PENDING) == 0) 247 return 0; 248 249 /* yes, it's us, so clear the interrupt */ 250 bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, sc->sc_reg); 251 252 /* 253 * this looks kinda funny but what we want here is this: 254 * - reading the counter and changing the CPU clock should be as 255 * close together as possible in order to remain halfway accurate 256 * - we need to use the previous sc_step in order to scale the 257 * interval passed since the last clock interrupt correctly, so 258 * we only change sc_step after doing that 259 */ 260 if (sc->sc_step_wanted != sc->sc_step) { 261 REGVAL(LS2F_CHIPCFG0) = 262 (REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | 263 sc->sc_step_wanted; 264 } 265 266 now = mips3_cp0_count_read(); 267 diff = now - sc->sc_last; 268 sc->sc_count += scale(diff, sc->sc_step); 269 sc->sc_last = now; 270 if (sc->sc_step_wanted != sc->sc_step) { 271 sc->sc_step = sc->sc_step_wanted; 272 } 273 hardclock(&cf); 274 275 return 1; 276 } 277 278 static void 279 pwmclock_start(void) 280 { 281 struct pwmclock_softc *sc = pwmclock; 282 sc->sc_count = 0; 283 sc->sc_last = mips3_cp0_count_read(); 284 pwmclock_timecounter.tc_frequency = curcpu()->ci_cpu_freq / 2; 285 tc_init(&pwmclock_timecounter); 286 bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, sc->sc_reg); 287 } 288 289 static u_int 290 get_pwmclock_timecount(struct timecounter *tc) 291 { 292 struct pwmclock_softc *sc = pwmclock; 293 uint32_t now, diff; 294 295 now = mips3_cp0_count_read(); 296 diff = now - sc->sc_last; 297 return sc->sc_count + scale(diff, sc->sc_step); 298 } 299 300 static int 301 pwmclock_cpuspeed_temp(SYSCTLFN_ARGS) 302 { 303 struct sysctlnode node = *rnode; 304 struct pwmclock_softc *sc = node.sysctl_data; 305 int mhz, i; 306 307 mhz = sc->sc_scale[sc->sc_step_wanted]; 308 309 node.sysctl_data = &mhz; 310 if (sysctl_lookup(SYSCTLFN_CALL(&node)) == 0) { 311 int new_reg; 312 313 new_reg = *(int *)node.sysctl_data; 314 i = 1; 315 while ((i < 8) && (sc->sc_scale[i] != new_reg)) 316 i++; 317 if (i > 7) 318 return EINVAL; 319 pwmclock_set_speed(sc, i); 320 return 0; 321 } 322 return EINVAL; 323 } 324 325 static int 326 pwmclock_cpuspeed_cur(SYSCTLFN_ARGS) 327 { 328 struct sysctlnode node = *rnode; 329 struct pwmclock_softc *sc = node.sysctl_data; 330 int mhz; 331 332 mhz = sc->sc_scale[sc->sc_step]; 333 node.sysctl_data = &mhz; 334 return sysctl_lookup(SYSCTLFN_CALL(&node)); 335 } 336 337 static int 338 pwmclock_cpuspeed_available(SYSCTLFN_ARGS) 339 { 340 struct sysctlnode node = *rnode; 341 struct pwmclock_softc *sc = node.sysctl_data; 342 char buf[128]; 343 344 snprintf(buf, 128, "%d %d %d %d %d %d %d", sc->sc_scale[1], 345 sc->sc_scale[2], sc->sc_scale[3], sc->sc_scale[4], 346 sc->sc_scale[5], sc->sc_scale[6], sc->sc_scale[7]); 347 node.sysctl_data = buf; 348 return(sysctl_lookup(SYSCTLFN_CALL(&node))); 349 } 350 351 SYSCTL_SETUP(sysctl_ams_setup, "sysctl obio subtree setup") 352 { 353 354 sysctl_createv(NULL, 0, NULL, NULL, 355 CTLFLAG_PERMANENT, 356 CTLTYPE_NODE, "machdep", NULL, 357 NULL, 0, NULL, 0, 358 CTL_MACHDEP, CTL_EOL); 359 } 360
Indexes created Wed Oct 01 07:09:59 GMT 2025