pwmclock.c revision 1.9
1 /* $NetBSD: pwmclock.c,v 1.9 2013/05/13 16:01:31 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2011 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pwmclock.c,v 1.9 2013/05/13 16:01:31 christos Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/cpu.h> 36 #include <sys/timetc.h> 37 #include <sys/sysctl.h> 38 39 #include <dev/pci/voyagervar.h> 40 #include <dev/ic/sm502reg.h> 41 42 #include <mips/mips3_clock.h> 43 #include <mips/locore.h> 44 #include <mips/bonito/bonitoreg.h> 45 #include <mips/bonito/bonitovar.h> 46 47 #include "opt_pwmclock.h" 48 49 #ifdef PWMCLOCK_DEBUG 50 #define DPRINTF aprint_error 51 #else 52 #define DPRINTF while (0) printf 53 #endif 54 55 int pwmclock_intr(void *); 56 57 struct pwmclock_softc { 58 device_t sc_dev; 59 bus_space_tag_t sc_memt; 60 bus_space_handle_t sc_regh; 61 uint32_t sc_reg, sc_last; 62 uint32_t sc_scale[8]; 63 uint32_t sc_count; /* should probably be 64 bit */ 64 int sc_step; 65 int sc_step_wanted; 66 void *sc_shutdown_cookie; 67 }; 68 69 static int pwmclock_match(device_t, cfdata_t, void *); 70 static void pwmclock_attach(device_t, device_t, void *); 71 72 CFATTACH_DECL_NEW(pwmclock, sizeof(struct pwmclock_softc), 73 pwmclock_match, pwmclock_attach, NULL, NULL); 74 75 static void pwmclock_start(void); 76 static u_int get_pwmclock_timecount(struct timecounter *); 77 78 struct pwmclock_softc *pwmclock; 79 extern void (*initclocks_ptr)(void); 80 81 /* 0, 1/4, 3/8, 1/2, 5/8, 3/4, 7/8, 1 */ 82 static int scale_m[] = {1, 1, 3, 1, 5, 3, 7, 1}; 83 static int scale_d[] = {0, 4, 8, 2, 8, 4, 8, 1}; 84 85 #define scale(x, f) (x * scale_d[f] / scale_m[f]) 86 87 void pwmclock_set_speed(struct pwmclock_softc *, int); 88 static int pwmclock_cpuspeed_temp(SYSCTLFN_ARGS); 89 static int pwmclock_cpuspeed_cur(SYSCTLFN_ARGS); 90 static int pwmclock_cpuspeed_available(SYSCTLFN_ARGS); 91 92 static void pwmclock_shutdown(void *); 93 94 static struct timecounter pwmclock_timecounter = { 95 get_pwmclock_timecount, /* get_timecount */ 96 0, /* no poll_pps */ 97 0xffffffff, /* counter_mask */ 98 0, /* frequency */ 99 "pwm", /* name */ 100 100, /* quality */ 101 NULL, /* tc_priv */ 102 NULL /* tc_next */ 103 }; 104 105 static int 106 pwmclock_match(device_t parent, cfdata_t match, void *aux) 107 { 108 struct voyager_attach_args *vaa = (struct voyager_attach_args *)aux; 109 110 if (strcmp(vaa->vaa_name, "pwmclock") == 0) return 100; 111 return 0; 112 } 113 114 static uint32_t 115 pwmclock_wait_edge(struct pwmclock_softc *sc) 116 { 117 /* clear interrupt */ 118 bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, sc->sc_reg); 119 while ((bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_PWM1) & 120 SM502_PWM_INTR_PENDING) == 0); 121 return mips3_cp0_count_read(); 122 } 123 124 static void 125 pwmclock_attach(device_t parent, device_t self, void *aux) 126 { 127 struct pwmclock_softc *sc = device_private(self); 128 struct voyager_attach_args *vaa = aux; 129 const struct sysctlnode *sysctl_node, *me, *freq; 130 uint32_t reg, last, curr, diff, acc; 131 int i, clk; 132 133 sc->sc_dev = self; 134 sc->sc_memt = vaa->vaa_tag; 135 sc->sc_regh = vaa->vaa_regh; 136 137 aprint_normal("\n"); 138 139 voyager_establish_intr(parent, 22, pwmclock_intr, sc); 140 reg = voyager_set_pwm(100, 100); /* 100Hz, 10% duty cycle */ 141 reg |= SM502_PWM_ENABLE | SM502_PWM_ENABLE_INTR | 142 SM502_PWM_INTR_PENDING; 143 sc->sc_reg = reg; 144 pwmclock = sc; 145 initclocks_ptr = pwmclock_start; 146 147 /* 148 * Establish a hook so on shutdown we can set the CPU clock back to 149 * full speed. This is necessary because PMON doesn't change the 150 * clock scale register on a warm boot, the MIPS clock code gets 151 * confused if we're too slow and the loongson-specific bits run 152 * too late in the boot process 153 */ 154 sc->sc_shutdown_cookie = shutdownhook_establish(pwmclock_shutdown, sc); 155 156 /* ok, let's see how far the cycle counter gets between interrupts */ 157 DPRINTF("calibrating CPU timer...\n"); 158 for (clk = 1; clk < 8; clk++) { 159 160 REGVAL(LS2F_CHIPCFG0) = 161 (REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | clk; 162 bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, 163 sc->sc_reg); 164 acc = 0; 165 last = pwmclock_wait_edge(sc); 166 for (i = 0; i < 16; i++) { 167 curr = pwmclock_wait_edge(sc); 168 diff = curr - last; 169 acc += diff; 170 last = curr; 171 } 172 sc->sc_scale[clk] = (acc >> 4) / 5000; 173 } 174 #ifdef PWMCLOCK_DEBUG 175 for (clk = 1; clk < 8; clk++) { 176 aprint_normal_dev(sc->sc_dev, "%d/8: %d\n", clk + 1, 177 sc->sc_scale[clk]); 178 } 179 #endif 180 sc->sc_step = 7; 181 sc->sc_step_wanted = 7; 182 183 /* now setup sysctl */ 184 if (sysctl_createv(NULL, 0, NULL, 185 &me, 186 CTLFLAG_READWRITE, CTLTYPE_NODE, "loongson", NULL, NULL, 187 0, NULL, 0, CTL_MACHDEP, CTL_CREATE, CTL_EOL) != 0) 188 aprint_error_dev(sc->sc_dev, 189 "couldn't create 'loongson' node\n"); 190 191 if (sysctl_createv(NULL, 0, NULL, 192 &freq, 193 CTLFLAG_READWRITE, CTLTYPE_NODE, "frequency", NULL, NULL, 0, NULL, 194 0, CTL_MACHDEP, me->sysctl_num, CTL_CREATE, CTL_EOL) != 0) 195 aprint_error_dev(sc->sc_dev, 196 "couldn't create 'frequency' node\n"); 197 198 if (sysctl_createv(NULL, 0, NULL, 199 &sysctl_node, 200 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 201 CTLTYPE_INT, "target", "CPU speed", pwmclock_cpuspeed_temp, 202 0, (void *)sc, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num, 203 CTL_CREATE, CTL_EOL) == 0) { 204 } else 205 aprint_error_dev(sc->sc_dev, 206 "couldn't create 'target' node\n"); 207 208 if (sysctl_createv(NULL, 0, NULL, 209 &sysctl_node, 210 CTLFLAG_READWRITE, 211 CTLTYPE_INT, "current", NULL, pwmclock_cpuspeed_cur, 212 1, (void *)sc, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num, 213 CTL_CREATE, CTL_EOL) == 0) { 214 } else 215 aprint_error_dev(sc->sc_dev, 216 "couldn't create 'current' node\n"); 217 218 if (sysctl_createv(NULL, 0, NULL, 219 &sysctl_node, 220 CTLFLAG_READWRITE, 221 CTLTYPE_STRING, "available", NULL, pwmclock_cpuspeed_available, 222 2, (void *)sc, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num, 223 CTL_CREATE, CTL_EOL) == 0) { 224 } else 225 aprint_error_dev(sc->sc_dev, 226 "couldn't create 'available' node\n"); 227 } 228 229 static void 230 pwmclock_shutdown(void *cookie) 231 { 232 struct pwmclock_softc *sc = cookie; 233 234 /* just in case the interrupt handler runs again after this */ 235 sc->sc_step_wanted = 7; 236 /* set the clock to full speed */ 237 REGVAL(LS2F_CHIPCFG0) = 238 (REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | 7; 239 } 240 241 void 242 pwmclock_set_speed(struct pwmclock_softc *sc, int speed) 243 { 244 245 if ((speed < 1) || (speed > 7)) 246 return; 247 sc->sc_step_wanted = speed; 248 DPRINTF("%s: %d\n", __func__, speed); 249 } 250 251 /* 252 * the PWM interrupt handler 253 * we don't have a CPU clock independent, high resolution counter so we're 254 * stuck with a PWM that can't count and a CP0 counter that slows down or 255 * speeds up with the actual CPU speed. In order to still get halfway 256 * accurate time we do the following: 257 * - only change CPU speed in the timer interrupt 258 * - each timer interrupt we measure how many CP0 cycles passed since last 259 * time, adjust for CPU speed since we can be sure it didn't change, use 260 * that to update a separate counter 261 * - when reading the time counter we take the number of CP0 ticks since 262 * the last timer interrupt, scale it to CPU clock, return that plus the 263 * interrupt updated counter mentioned above to get something close to 264 * CP0 running at full speed 265 * - when changing CPU speed do it as close to taking the time from CP0 as 266 * possible to keep the period of time we spend with CP0 running at the 267 * wrong frequency as short as possible - hopefully short enough to stay 268 * insignificant compared to other noise since switching speeds isn't 269 * going to happen all that often 270 */ 271 272 int 273 pwmclock_intr(void *cookie) 274 { 275 struct pwmclock_softc *sc = cookie; 276 uint32_t reg, now, diff; 277 278 /* is it us? */ 279 reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_PWM1); 280 if ((reg & SM502_PWM_INTR_PENDING) == 0) 281 return 0; 282 283 /* yes, it's us, so clear the interrupt */ 284 bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, sc->sc_reg); 285 286 /* 287 * this looks kinda funny but what we want here is this: 288 * - reading the counter and changing the CPU clock should be as 289 * close together as possible in order to remain halfway accurate 290 * - we need to use the previous sc_step in order to scale the 291 * interval passed since the last clock interrupt correctly, so 292 * we only change sc_step after doing that 293 */ 294 if (sc->sc_step_wanted != sc->sc_step) { 295 296 REGVAL(LS2F_CHIPCFG0) = 297 (REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | 298 sc->sc_step_wanted; 299 } 300 301 now = mips3_cp0_count_read(); 302 diff = now - sc->sc_last; 303 sc->sc_count += scale(diff, sc->sc_step); 304 sc->sc_last = now; 305 if (sc->sc_step_wanted != sc->sc_step) { 306 sc->sc_step = sc->sc_step_wanted; 307 } 308 #ifdef notyet 309 struct clockframe cf; 310 311 cf.pc = pc; 312 cf.sr = status; 313 cf.intr = (curcpu()->ci_idepth > 1); 314 hardclock(&cf); 315 #endif 316 317 return 1; 318 } 319 320 static void 321 pwmclock_start(void) 322 { 323 struct pwmclock_softc *sc = pwmclock; 324 sc->sc_count = 0; 325 sc->sc_last = mips3_cp0_count_read(); 326 pwmclock_timecounter.tc_frequency = curcpu()->ci_cpu_freq / 2; 327 tc_init(&pwmclock_timecounter); 328 bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, sc->sc_reg); 329 } 330 331 static u_int 332 get_pwmclock_timecount(struct timecounter *tc) 333 { 334 struct pwmclock_softc *sc = pwmclock; 335 uint32_t now, diff; 336 337 now = mips3_cp0_count_read(); 338 diff = now - sc->sc_last; 339 return sc->sc_count + scale(diff, sc->sc_step); 340 } 341 342 static int 343 pwmclock_cpuspeed_temp(SYSCTLFN_ARGS) 344 { 345 struct sysctlnode node = *rnode; 346 struct pwmclock_softc *sc = node.sysctl_data; 347 int mhz, i; 348 349 mhz = sc->sc_scale[sc->sc_step_wanted]; 350 351 node.sysctl_data = &mhz; 352 if (sysctl_lookup(SYSCTLFN_CALL(&node)) == 0) { 353 int new_reg; 354 355 new_reg = *(int *)node.sysctl_data; 356 i = 1; 357 while ((i < 8) && (sc->sc_scale[i] != new_reg)) 358 i++; 359 if (i > 7) 360 return EINVAL; 361 pwmclock_set_speed(sc, i); 362 return 0; 363 } 364 return EINVAL; 365 } 366 367 static int 368 pwmclock_cpuspeed_cur(SYSCTLFN_ARGS) 369 { 370 struct sysctlnode node = *rnode; 371 struct pwmclock_softc *sc = node.sysctl_data; 372 int mhz; 373 374 mhz = sc->sc_scale[sc->sc_step]; 375 node.sysctl_data = &mhz; 376 return sysctl_lookup(SYSCTLFN_CALL(&node)); 377 } 378 379 static int 380 pwmclock_cpuspeed_available(SYSCTLFN_ARGS) 381 { 382 struct sysctlnode node = *rnode; 383 struct pwmclock_softc *sc = node.sysctl_data; 384 char buf[128]; 385 386 snprintf(buf, 128, "%d %d %d %d %d %d %d", sc->sc_scale[1], 387 sc->sc_scale[2], sc->sc_scale[3], sc->sc_scale[4], 388 sc->sc_scale[5], sc->sc_scale[6], sc->sc_scale[7]); 389 node.sysctl_data = buf; 390 return(sysctl_lookup(SYSCTLFN_CALL(&node))); 391 } 392 393 SYSCTL_SETUP(sysctl_ams_setup, "sysctl obio subtree setup") 394 { 395 396 sysctl_createv(NULL, 0, NULL, NULL, 397 CTLFLAG_PERMANENT, 398 CTLTYPE_NODE, "machdep", NULL, 399 NULL, 0, NULL, 0, 400 CTL_MACHDEP, CTL_EOL); 401 } 402
Indexes created Tue Sep 30 20:09:53 GMT 2025