xhci_pci.c revision 1.20
1 /* $NetBSD: xhci_pci.c,v 1.20 2019/01/18 07:03:02 skrll Exp $ */ 2 /* OpenBSD: xhci_pci.c,v 1.4 2014/07/12 17:38:51 yuo Exp */ 3 4 /* 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: xhci_pci.c,v 1.20 2019/01/18 07:03:02 skrll Exp $"); 36 37 #ifdef _KERNEL_OPT 38 #include "opt_xhci_pci.h" 39 #endif 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/proc.h> 46 #include <sys/queue.h> 47 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcidevs.h> 52 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usbdi.h> 55 #include <dev/usb/usbdivar.h> 56 #include <dev/usb/usb_mem.h> 57 58 #include <dev/usb/xhcireg.h> 59 #include <dev/usb/xhcivar.h> 60 61 struct xhci_pci_softc { 62 struct xhci_softc sc_xhci; 63 pci_chipset_tag_t sc_pc; 64 pcitag_t sc_tag; 65 void *sc_ih; 66 pci_intr_handle_t *sc_pihp; 67 }; 68 69 static int 70 xhci_pci_match(device_t parent, cfdata_t match, void *aux) 71 { 72 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 73 74 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 75 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 76 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_XHCI) 77 return 1; 78 79 return 0; 80 } 81 82 static int 83 xhci_pci_port_route(struct xhci_pci_softc *psc) 84 { 85 struct xhci_softc * const sc = &psc->sc_xhci; 86 87 pcireg_t val; 88 89 /* 90 * Check USB3 Port Routing Mask register that indicates the ports 91 * can be changed from OS, and turn on by USB3 Port SS Enable register. 92 */ 93 val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3PRM); 94 aprint_debug_dev(sc->sc_dev, 95 "USB3PRM / USB3.0 configurable ports: 0x%08x\n", val); 96 97 pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3_PSSEN, val); 98 val = pci_conf_read(psc->sc_pc, psc->sc_tag,PCI_XHCI_INTEL_USB3_PSSEN); 99 aprint_debug_dev(sc->sc_dev, 100 "USB3_PSSEN / Enabled USB3.0 ports under xHCI: 0x%08x\n", val); 101 102 /* 103 * Check USB2 Port Routing Mask register that indicates the USB2.0 104 * ports to be controlled by xHCI HC, and switch them to xHCI HC. 105 */ 106 val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB2PRM); 107 aprint_debug_dev(sc->sc_dev, 108 "XUSB2PRM / USB2.0 ports can switch from EHCI to xHCI:" 109 "0x%08x\n", val); 110 pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PR, val); 111 val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PR); 112 aprint_debug_dev(sc->sc_dev, 113 "XUSB2PR / USB2.0 ports under xHCI: 0x%08x\n", val); 114 115 return 0; 116 } 117 118 static void 119 xhci_pci_attach(device_t parent, device_t self, void *aux) 120 { 121 struct xhci_pci_softc * const psc = device_private(self); 122 struct xhci_softc * const sc = &psc->sc_xhci; 123 struct pci_attach_args *const pa = (struct pci_attach_args *)aux; 124 const pci_chipset_tag_t pc = pa->pa_pc; 125 const pcitag_t tag = pa->pa_tag; 126 char const *intrstr; 127 pcireg_t csr, memtype, usbrev; 128 uint32_t hccparams; 129 char intrbuf[PCI_INTRSTR_LEN]; 130 bus_addr_t memaddr; 131 int flags, msixoff; 132 int err; 133 134 sc->sc_dev = self; 135 136 pci_aprint_devinfo(pa, "USB Controller"); 137 138 /* Check for quirks */ 139 sc->sc_quirks = 0; 140 141 /* check if memory space access is enabled */ 142 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 143 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 144 sc->sc_ios = 0; 145 aprint_error_dev(self, "memory access is disabled\n"); 146 return; 147 } 148 149 /* map MMIO registers */ 150 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_CBMEM); 151 if (PCI_MAPREG_TYPE(memtype) != PCI_MAPREG_TYPE_MEM) { 152 sc->sc_ios = 0; 153 aprint_error_dev(self, "BAR not 64 or 32-bit MMIO\n"); 154 return; 155 } 156 157 sc->sc_iot = pa->pa_memt; 158 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, PCI_CBMEM, memtype, 159 &memaddr, &sc->sc_ios, &flags) != 0) { 160 sc->sc_ios = 0; 161 aprint_error_dev(self, "can't get map info\n"); 162 return; 163 } 164 165 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &msixoff, 166 NULL)) { 167 pcireg_t msixtbl; 168 uint32_t table_offset; 169 int bir; 170 171 msixtbl = pci_conf_read(pa->pa_pc, pa->pa_tag, 172 msixoff + PCI_MSIX_TBLOFFSET); 173 table_offset = msixtbl & PCI_MSIX_TBLOFFSET_MASK; 174 bir = msixtbl & PCI_MSIX_PBABIR_MASK; 175 /* Shrink map area for MSI-X table */ 176 if (bir == PCI_MAPREG_NUM(PCI_CBMEM)) 177 sc->sc_ios = table_offset; 178 } 179 if (bus_space_map(sc->sc_iot, memaddr, sc->sc_ios, flags, 180 &sc->sc_ioh)) { 181 sc->sc_ios = 0; 182 aprint_error_dev(self, "can't map mem space\n"); 183 return; 184 } 185 186 psc->sc_pc = pc; 187 psc->sc_tag = tag; 188 189 hccparams = bus_space_read_4(sc->sc_iot, sc->sc_ioh, XHCI_HCCPARAMS); 190 191 if (pci_dma64_available(pa) && (XHCI_HCC_AC64(hccparams) != 0)) 192 sc->sc_bus.ub_dmatag = pa->pa_dmat64; 193 else 194 sc->sc_bus.ub_dmatag = pa->pa_dmat; 195 196 /* Enable the device. */ 197 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 198 csr | PCI_COMMAND_MASTER_ENABLE); 199 200 /* Allocate and establish the interrupt. */ 201 if (pci_intr_alloc(pa, &psc->sc_pihp, NULL, 0)) { 202 aprint_error_dev(self, "can't allocate handler\n"); 203 goto fail; 204 } 205 intrstr = pci_intr_string(pc, psc->sc_pihp[0], intrbuf, 206 sizeof(intrbuf)); 207 psc->sc_ih = pci_intr_establish_xname(pc, psc->sc_pihp[0], IPL_USB, 208 xhci_intr, sc, device_xname(sc->sc_dev)); 209 if (psc->sc_ih == NULL) { 210 pci_intr_release(pc, psc->sc_pihp, 1); 211 psc->sc_ih = NULL; 212 aprint_error_dev(self, "couldn't establish interrupt"); 213 if (intrstr != NULL) 214 aprint_error(" at %s", intrstr); 215 aprint_error("\n"); 216 goto fail; 217 } 218 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 219 220 usbrev = pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK; 221 switch (usbrev) { 222 case PCI_USBREV_3_0: 223 sc->sc_bus.ub_revision = USBREV_3_0; 224 break; 225 case PCI_USBREV_3_1: 226 sc->sc_bus.ub_revision = USBREV_3_1; 227 break; 228 default: 229 if (usbrev < PCI_USBREV_3_0) { 230 aprint_error_dev(self, "Unknown revision (%02x). Set to 3.0.\n", 231 usbrev); 232 sc->sc_bus.ub_revision = USBREV_3_0; 233 } else { 234 /* Default to the latest revision */ 235 aprint_normal_dev(self, 236 "Unknown revision (%02x). Set to 3.1.\n", usbrev); 237 sc->sc_bus.ub_revision = USBREV_3_1; 238 } 239 break; 240 } 241 242 /* Intel chipset requires SuperSpeed enable and USB2 port routing */ 243 switch (PCI_VENDOR(pa->pa_id)) { 244 case PCI_VENDOR_INTEL: 245 sc->sc_quirks |= XHCI_QUIRK_INTEL; 246 break; 247 default: 248 break; 249 } 250 251 err = xhci_init(sc); 252 if (err) { 253 aprint_error_dev(self, "init failed, error=%d\n", err); 254 goto fail; 255 } 256 257 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 258 xhci_pci_port_route(psc); 259 260 if (!pmf_device_register1(self, xhci_suspend, xhci_resume, 261 xhci_shutdown)) 262 aprint_error_dev(self, "couldn't establish power handler\n"); 263 264 /* Attach usb buses. */ 265 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 266 267 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 268 269 return; 270 271 fail: 272 if (psc->sc_ih != NULL) { 273 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 274 psc->sc_ih = NULL; 275 } 276 if (psc->sc_pihp != NULL) { 277 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1); 278 psc->sc_pihp = NULL; 279 } 280 if (sc->sc_ios) { 281 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 282 sc->sc_ios = 0; 283 } 284 return; 285 } 286 287 static int 288 xhci_pci_detach(device_t self, int flags) 289 { 290 struct xhci_pci_softc * const psc = device_private(self); 291 struct xhci_softc * const sc = &psc->sc_xhci; 292 int rv; 293 294 if (sc->sc_ios != 0) { 295 rv = xhci_detach(sc, flags); 296 if (rv) 297 return rv; 298 299 pmf_device_deregister(self); 300 301 xhci_shutdown(self, flags); 302 303 #if 0 304 /* Disable interrupts, so we don't get any spurious ones. */ 305 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 306 OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 307 #endif 308 } 309 310 if (psc->sc_ih != NULL) { 311 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 312 psc->sc_ih = NULL; 313 } 314 if (psc->sc_pihp != NULL) { 315 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1); 316 psc->sc_pihp = NULL; 317 } 318 if (sc->sc_ios) { 319 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 320 sc->sc_ios = 0; 321 } 322 323 return 0; 324 } 325 326 CFATTACH_DECL3_NEW(xhci_pci, sizeof(struct xhci_pci_softc), 327 xhci_pci_match, xhci_pci_attach, xhci_pci_detach, xhci_activate, NULL, 328 xhci_childdet, DVF_DETACH_SHUTDOWN); 329
Indexes created Tue Sep 30 20:09:53 GMT 2025