xhci_pci.c revision 1.3
1 /* $NetBSD: xhci_pci.c,v 1.3 2014/03/29 19:28:25 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: xhci_pci.c,v 1.3 2014/03/29 19:28:25 christos Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/proc.h> 41 #include <sys/queue.h> 42 43 #include <sys/bus.h> 44 45 #include <dev/pci/pcivar.h> 46 47 #include <dev/usb/usb.h> 48 #include <dev/usb/usbdi.h> 49 #include <dev/usb/usbdivar.h> 50 #include <dev/usb/usb_mem.h> 51 52 #include <dev/usb/xhcireg.h> 53 #include <dev/usb/xhcivar.h> 54 55 struct xhci_pci_softc { 56 struct xhci_softc sc_xhci; 57 pci_chipset_tag_t sc_pc; 58 pcitag_t sc_tag; 59 }; 60 61 static int 62 xhci_pci_match(device_t parent, cfdata_t match, void *aux) 63 { 64 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 65 66 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 67 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 68 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_XHCI) 69 return 1; 70 71 return 0; 72 } 73 74 static void 75 xhci_pci_attach(device_t parent, device_t self, void *aux) 76 { 77 struct xhci_pci_softc * const psc = device_private(self); 78 struct xhci_softc * const sc = &psc->sc_xhci; 79 struct pci_attach_args *const pa = (struct pci_attach_args *)aux; 80 const pci_chipset_tag_t pc = pa->pa_pc; 81 const pcitag_t tag = pa->pa_tag; 82 char const *intrstr; 83 pci_intr_handle_t ih; 84 pcireg_t csr, memtype; 85 int err; 86 //const char *vendor; 87 uint32_t hccparams; 88 char intrbuf[PCI_INTRSTR_LEN]; 89 90 sc->sc_dev = self; 91 sc->sc_bus.hci_private = sc; 92 93 pci_aprint_devinfo(pa, "USB Controller"); 94 95 /* check if memory space access is enabled */ 96 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 97 #ifdef DEBUG 98 printf("csr: %08x\n", csr); 99 #endif 100 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 101 aprint_error_dev(self, "memory access is disabled\n"); 102 return; 103 } 104 105 /* map MMIO registers */ 106 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_CBMEM); 107 switch (memtype) { 108 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 109 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 110 if (pci_mapreg_map(pa, PCI_CBMEM, memtype, 0, 111 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_ios)) { 112 sc->sc_ios = 0; 113 aprint_error_dev(self, "can't map mem space\n"); 114 return; 115 } 116 break; 117 default: 118 aprint_error_dev(self, "BAR not 64 or 32-bit MMIO\n"); 119 return; 120 break; 121 } 122 123 psc->sc_pc = pc; 124 psc->sc_tag = tag; 125 126 hccparams = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 0x10); 127 128 if (pci_dma64_available(pa) && ((hccparams&1)==1)) 129 sc->sc_bus.dmatag = pa->pa_dmat64; 130 else 131 sc->sc_bus.dmatag = pa->pa_dmat; 132 133 /* Enable the device. */ 134 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 135 csr | PCI_COMMAND_MASTER_ENABLE); 136 137 /* Map and establish the interrupt. */ 138 if (pci_intr_map(pa, &ih)) { 139 aprint_error_dev(self, "couldn't map interrupt\n"); 140 goto fail; 141 } 142 143 /* 144 * Allocate IRQ 145 */ 146 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 147 sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, xhci_intr, sc); 148 if (sc->sc_ih == NULL) { 149 aprint_error_dev(self, "couldn't establish interrupt"); 150 if (intrstr != NULL) 151 aprint_error(" at %s", intrstr); 152 aprint_error("\n"); 153 goto fail; 154 } 155 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 156 157 #if 0 158 /* Figure out vendor for root hub descriptor. */ 159 vendor = pci_findvendor(pa->pa_id); 160 sc->sc_id_vendor = PCI_VENDOR(pa->pa_id); 161 if (vendor) 162 strlcpy(sc->sc_vendor, vendor, sizeof(sc->sc_vendor)); 163 else 164 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 165 "vendor 0x%04x", PCI_VENDOR(pa->pa_id)); 166 #endif 167 168 err = xhci_init(sc); 169 if (err) { 170 aprint_error_dev(self, "init failed, error=%d\n", err); 171 goto fail; 172 } 173 174 if (!pmf_device_register1(self, xhci_suspend, xhci_resume, 175 xhci_shutdown)) 176 aprint_error_dev(self, "couldn't establish power handler\n"); 177 178 /* Attach usb device. */ 179 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 180 return; 181 182 fail: 183 if (sc->sc_ih) { 184 pci_intr_disestablish(psc->sc_pc, sc->sc_ih); 185 sc->sc_ih = NULL; 186 } 187 if (sc->sc_ios) { 188 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 189 sc->sc_ios = 0; 190 } 191 return; 192 } 193 194 static int 195 xhci_pci_detach(device_t self, int flags) 196 { 197 struct xhci_pci_softc * const psc = device_private(self); 198 struct xhci_softc * const sc = &psc->sc_xhci; 199 int rv; 200 201 rv = xhci_detach(sc, flags); 202 if (rv) 203 return rv; 204 205 pmf_device_deregister(self); 206 207 xhci_shutdown(self, flags); 208 209 if (sc->sc_ios) { 210 #if 0 211 /* Disable interrupts, so we don't get any spurious ones. */ 212 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 213 OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 214 #endif 215 } 216 217 if (sc->sc_ih != NULL) { 218 pci_intr_disestablish(psc->sc_pc, sc->sc_ih); 219 sc->sc_ih = NULL; 220 } 221 if (sc->sc_ios) { 222 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 223 sc->sc_ios = 0; 224 } 225 226 return 0; 227 } 228 229 CFATTACH_DECL3_NEW(xhci_pci, sizeof(struct xhci_pci_softc), 230 xhci_pci_match, xhci_pci_attach, xhci_pci_detach, xhci_activate, NULL, 231 xhci_childdet, DVF_DETACH_SHUTDOWN); 232
Indexes created Wed Oct 01 13:09:50 GMT 2025