xhci_pci.c revision 1.5
1 /* $NetBSD: xhci_pci.c,v 1.5 2016/04/23 10:15:31 skrll Exp $ */ 2 /* OpenBSD: xhci_pci.c,v 1.4 2014/07/12 17:38:51 yuo Exp */ 3 4 /* 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: xhci_pci.c,v 1.5 2016/04/23 10:15:31 skrll Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/proc.h> 42 #include <sys/queue.h> 43 44 #include <sys/bus.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 49 #include <dev/usb/usb.h> 50 #include <dev/usb/usbdi.h> 51 #include <dev/usb/usbdivar.h> 52 #include <dev/usb/usb_mem.h> 53 54 #include <dev/usb/xhcireg.h> 55 #include <dev/usb/xhcivar.h> 56 57 struct xhci_pci_quirk { 58 pci_vendor_id_t vendor; 59 pci_product_id_t product; 60 int quirks; 61 }; 62 63 static const struct xhci_pci_quirk xhci_pci_quirks[] = { 64 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_XHCI, 65 XHCI_QUIRK_FORCE_INTR }, 66 }; 67 68 struct xhci_pci_softc { 69 struct xhci_softc sc_xhci; 70 pci_chipset_tag_t sc_pc; 71 pcitag_t sc_tag; 72 void *sc_ih; 73 pci_intr_handle_t *sc_pihp; 74 }; 75 76 static int 77 xhci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product) 78 { 79 int i; 80 81 for (i = 0; i < __arraycount(xhci_pci_quirks); i++) 82 if (vendor == xhci_pci_quirks[i].vendor && 83 product == xhci_pci_quirks[i].product) 84 return xhci_pci_quirks[i].quirks; 85 return 0; 86 } 87 88 static int 89 xhci_pci_match(device_t parent, cfdata_t match, void *aux) 90 { 91 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 92 93 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 94 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 95 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_XHCI) 96 return 1; 97 98 return 0; 99 } 100 101 static int 102 xhci_pci_port_route(struct xhci_pci_softc *psc) 103 { 104 struct xhci_softc * const sc = &psc->sc_xhci; 105 106 pcireg_t val; 107 108 /* 109 * Check USB3 Port Routing Mask register that indicates the ports 110 * can be changed from OS, and turn on by USB3 Port SS Enable register. 111 */ 112 val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3PRM); 113 aprint_debug_dev(sc->sc_dev, 114 "USB3PRM / USB3.0 configurable ports: 0x%08x\n", val); 115 116 pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3_PSSEN, val); 117 val = pci_conf_read(psc->sc_pc, psc->sc_tag,PCI_XHCI_INTEL_USB3_PSSEN); 118 aprint_debug_dev(sc->sc_dev, 119 "USB3_PSSEN / Enabled USB3.0 ports under xHCI: 0x%08x\n", val); 120 121 /* 122 * Check USB2 Port Routing Mask register that indicates the USB2.0 123 * ports to be controlled by xHCI HC, and switch them to xHCI HC. 124 */ 125 val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB2PRM); 126 aprint_debug_dev(sc->sc_dev, 127 "XUSB2PRM / USB2.0 ports can switch from EHCI to xHCI:" 128 "0x%08x\n", val); 129 pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PR, val); 130 val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PR); 131 aprint_debug_dev(sc->sc_dev, 132 "XUSB2PR / USB2.0 ports under xHCI: 0x%08x\n", val); 133 134 return 0; 135 } 136 137 static void 138 xhci_pci_attach(device_t parent, device_t self, void *aux) 139 { 140 struct xhci_pci_softc * const psc = device_private(self); 141 struct xhci_softc * const sc = &psc->sc_xhci; 142 struct pci_attach_args *const pa = (struct pci_attach_args *)aux; 143 const pci_chipset_tag_t pc = pa->pa_pc; 144 const pcitag_t tag = pa->pa_tag; 145 char const *intrstr; 146 pcireg_t csr, memtype; 147 int err; 148 uint32_t hccparams; 149 char intrbuf[PCI_INTRSTR_LEN]; 150 151 sc->sc_dev = self; 152 sc->sc_bus.ub_hcpriv = sc; 153 154 pci_aprint_devinfo(pa, "USB Controller"); 155 156 /* Check for quirks */ 157 sc->sc_quirks = xhci_pci_has_quirk(PCI_VENDOR(pa->pa_id), 158 PCI_PRODUCT(pa->pa_id)); 159 160 /* check if memory space access is enabled */ 161 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 162 #ifdef DEBUG 163 printf("%s: csr: %08x\n", __func__, csr); 164 #endif 165 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 166 aprint_error_dev(self, "memory access is disabled\n"); 167 return; 168 } 169 170 /* map MMIO registers */ 171 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_CBMEM); 172 switch (memtype) { 173 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 174 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 175 if (pci_mapreg_map(pa, PCI_CBMEM, memtype, 0, 176 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_ios)) { 177 sc->sc_ios = 0; 178 aprint_error_dev(self, "can't map mem space\n"); 179 return; 180 } 181 break; 182 default: 183 aprint_error_dev(self, "BAR not 64 or 32-bit MMIO\n"); 184 return; 185 } 186 187 psc->sc_pc = pc; 188 psc->sc_tag = tag; 189 190 hccparams = bus_space_read_4(sc->sc_iot, sc->sc_ioh, XHCI_HCCPARAMS); 191 192 if (pci_dma64_available(pa) && (XHCI_HCC_AC64(hccparams) != 0)) 193 sc->sc_bus.ub_dmatag = pa->pa_dmat64; 194 else 195 sc->sc_bus.ub_dmatag = pa->pa_dmat; 196 197 /* Enable the device. */ 198 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 199 csr | PCI_COMMAND_MASTER_ENABLE); 200 201 /* Allocate and establish the interrupt. */ 202 if (pci_intr_alloc(pa, &psc->sc_pihp, NULL, 0)) { 203 aprint_error_dev(self, "can't allocate handler\n"); 204 goto fail; 205 } 206 intrstr = pci_intr_string(pc, psc->sc_pihp[0], intrbuf, 207 sizeof(intrbuf)); 208 psc->sc_ih = pci_intr_establish(pc, psc->sc_pihp[0], IPL_USB, 209 xhci_intr, sc); 210 if (psc->sc_ih == NULL) { 211 aprint_error_dev(self, "couldn't establish interrupt"); 212 if (intrstr != NULL) 213 aprint_error(" at %s", intrstr); 214 aprint_error("\n"); 215 goto fail; 216 } 217 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 218 219 /* Figure out vendor for root hub descriptor. */ 220 sc->sc_id_vendor = PCI_VENDOR(pa->pa_id); 221 pci_findvendor(sc->sc_vendor, sizeof(sc->sc_vendor), 222 sc->sc_id_vendor); 223 224 /* Intel chipset requires SuperSpeed enable and USB2 port routing */ 225 switch (PCI_VENDOR(pa->pa_id)) { 226 case PCI_VENDOR_INTEL: 227 sc->sc_quirks |= XHCI_QUIRK_INTEL; 228 break; 229 default: 230 break; 231 } 232 233 err = xhci_init(sc); 234 if (err) { 235 aprint_error_dev(self, "init failed, error=%d\n", err); 236 goto fail; 237 } 238 239 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 240 xhci_pci_port_route(psc); 241 242 if (!pmf_device_register1(self, xhci_suspend, xhci_resume, 243 xhci_shutdown)) 244 aprint_error_dev(self, "couldn't establish power handler\n"); 245 246 /* Attach usb device. */ 247 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 248 return; 249 250 fail: 251 if (psc->sc_ih) { 252 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1); 253 psc->sc_ih = NULL; 254 } 255 if (sc->sc_ios) { 256 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 257 sc->sc_ios = 0; 258 } 259 return; 260 } 261 262 static int 263 xhci_pci_detach(device_t self, int flags) 264 { 265 struct xhci_pci_softc * const psc = device_private(self); 266 struct xhci_softc * const sc = &psc->sc_xhci; 267 int rv; 268 269 rv = xhci_detach(sc, flags); 270 if (rv) 271 return rv; 272 273 pmf_device_deregister(self); 274 275 xhci_shutdown(self, flags); 276 277 if (sc->sc_ios) { 278 #if 0 279 /* Disable interrupts, so we don't get any spurious ones. */ 280 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 281 OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 282 #endif 283 } 284 285 if (psc->sc_ih != NULL) { 286 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1); 287 psc->sc_ih = NULL; 288 } 289 if (sc->sc_ios) { 290 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 291 sc->sc_ios = 0; 292 } 293 294 return 0; 295 } 296 297 CFATTACH_DECL3_NEW(xhci_pci, sizeof(struct xhci_pci_softc), 298 xhci_pci_match, xhci_pci_attach, xhci_pci_detach, xhci_activate, NULL, 299 xhci_childdet, DVF_DETACH_SHUTDOWN); 300
Indexes created Wed Oct 01 07:09:59 GMT 2025