xhci_pci.c revision 1.8
1 /* $NetBSD: xhci_pci.c,v 1.8 2017/01/19 16:05:00 skrll Exp $ */ 2 /* OpenBSD: xhci_pci.c,v 1.4 2014/07/12 17:38:51 yuo Exp */ 3 4 /* 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: xhci_pci.c,v 1.8 2017/01/19 16:05:00 skrll Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/proc.h> 42 #include <sys/queue.h> 43 44 #include <sys/bus.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 49 #include <dev/usb/usb.h> 50 #include <dev/usb/usbdi.h> 51 #include <dev/usb/usbdivar.h> 52 #include <dev/usb/usb_mem.h> 53 54 #include <dev/usb/xhcireg.h> 55 #include <dev/usb/xhcivar.h> 56 57 struct xhci_pci_softc { 58 struct xhci_softc sc_xhci; 59 pci_chipset_tag_t sc_pc; 60 pcitag_t sc_tag; 61 void *sc_ih; 62 pci_intr_handle_t *sc_pihp; 63 }; 64 65 static int 66 xhci_pci_match(device_t parent, cfdata_t match, void *aux) 67 { 68 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 69 70 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 71 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 72 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_XHCI) 73 return 1; 74 75 return 0; 76 } 77 78 static int 79 xhci_pci_port_route(struct xhci_pci_softc *psc) 80 { 81 struct xhci_softc * const sc = &psc->sc_xhci; 82 83 pcireg_t val; 84 85 /* 86 * Check USB3 Port Routing Mask register that indicates the ports 87 * can be changed from OS, and turn on by USB3 Port SS Enable register. 88 */ 89 val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3PRM); 90 aprint_debug_dev(sc->sc_dev, 91 "USB3PRM / USB3.0 configurable ports: 0x%08x\n", val); 92 93 pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3_PSSEN, val); 94 val = pci_conf_read(psc->sc_pc, psc->sc_tag,PCI_XHCI_INTEL_USB3_PSSEN); 95 aprint_debug_dev(sc->sc_dev, 96 "USB3_PSSEN / Enabled USB3.0 ports under xHCI: 0x%08x\n", val); 97 98 /* 99 * Check USB2 Port Routing Mask register that indicates the USB2.0 100 * ports to be controlled by xHCI HC, and switch them to xHCI HC. 101 */ 102 val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB2PRM); 103 aprint_debug_dev(sc->sc_dev, 104 "XUSB2PRM / USB2.0 ports can switch from EHCI to xHCI:" 105 "0x%08x\n", val); 106 pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PR, val); 107 val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PR); 108 aprint_debug_dev(sc->sc_dev, 109 "XUSB2PR / USB2.0 ports under xHCI: 0x%08x\n", val); 110 111 return 0; 112 } 113 114 static void 115 xhci_pci_attach(device_t parent, device_t self, void *aux) 116 { 117 struct xhci_pci_softc * const psc = device_private(self); 118 struct xhci_softc * const sc = &psc->sc_xhci; 119 struct pci_attach_args *const pa = (struct pci_attach_args *)aux; 120 const pci_chipset_tag_t pc = pa->pa_pc; 121 const pcitag_t tag = pa->pa_tag; 122 char const *intrstr; 123 pcireg_t csr, memtype; 124 int err; 125 uint32_t hccparams; 126 char intrbuf[PCI_INTRSTR_LEN]; 127 128 sc->sc_dev = self; 129 130 pci_aprint_devinfo(pa, "USB Controller"); 131 132 /* Check for quirks */ 133 sc->sc_quirks = 0; 134 135 /* check if memory space access is enabled */ 136 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 137 #ifdef DEBUG 138 printf("%s: csr: %08x\n", __func__, csr); 139 #endif 140 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 141 aprint_error_dev(self, "memory access is disabled\n"); 142 return; 143 } 144 145 /* map MMIO registers */ 146 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_CBMEM); 147 switch (memtype) { 148 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 149 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 150 if (pci_mapreg_map(pa, PCI_CBMEM, memtype, 0, 151 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_ios)) { 152 sc->sc_ios = 0; 153 aprint_error_dev(self, "can't map mem space\n"); 154 return; 155 } 156 break; 157 default: 158 aprint_error_dev(self, "BAR not 64 or 32-bit MMIO\n"); 159 return; 160 } 161 162 psc->sc_pc = pc; 163 psc->sc_tag = tag; 164 165 hccparams = bus_space_read_4(sc->sc_iot, sc->sc_ioh, XHCI_HCCPARAMS); 166 167 if (pci_dma64_available(pa) && (XHCI_HCC_AC64(hccparams) != 0)) 168 sc->sc_bus.ub_dmatag = pa->pa_dmat64; 169 else 170 sc->sc_bus.ub_dmatag = pa->pa_dmat; 171 172 /* Enable the device. */ 173 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 174 csr | PCI_COMMAND_MASTER_ENABLE); 175 176 /* Allocate and establish the interrupt. */ 177 if (pci_intr_alloc(pa, &psc->sc_pihp, NULL, 0)) { 178 aprint_error_dev(self, "can't allocate handler\n"); 179 goto fail; 180 } 181 intrstr = pci_intr_string(pc, psc->sc_pihp[0], intrbuf, 182 sizeof(intrbuf)); 183 psc->sc_ih = pci_intr_establish_xname(pc, psc->sc_pihp[0], IPL_USB, 184 xhci_intr, sc, device_xname(sc->sc_dev)); 185 if (psc->sc_ih == NULL) { 186 aprint_error_dev(self, "couldn't establish interrupt"); 187 if (intrstr != NULL) 188 aprint_error(" at %s", intrstr); 189 aprint_error("\n"); 190 goto fail; 191 } 192 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 193 194 /* Figure out vendor for root hub descriptor. */ 195 sc->sc_id_vendor = PCI_VENDOR(pa->pa_id); 196 pci_findvendor(sc->sc_vendor, sizeof(sc->sc_vendor), 197 sc->sc_id_vendor); 198 199 /* Intel chipset requires SuperSpeed enable and USB2 port routing */ 200 switch (PCI_VENDOR(pa->pa_id)) { 201 case PCI_VENDOR_INTEL: 202 sc->sc_quirks |= XHCI_QUIRK_INTEL; 203 break; 204 default: 205 break; 206 } 207 208 err = xhci_init(sc); 209 if (err) { 210 aprint_error_dev(self, "init failed, error=%d\n", err); 211 goto fail; 212 } 213 214 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 215 xhci_pci_port_route(psc); 216 217 if (!pmf_device_register1(self, xhci_suspend, xhci_resume, 218 xhci_shutdown)) 219 aprint_error_dev(self, "couldn't establish power handler\n"); 220 221 /* Attach usb buses. */ 222 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 223 224 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 225 226 return; 227 228 fail: 229 if (psc->sc_ih) { 230 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1); 231 psc->sc_ih = NULL; 232 } 233 if (sc->sc_ios) { 234 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 235 sc->sc_ios = 0; 236 } 237 return; 238 } 239 240 static int 241 xhci_pci_detach(device_t self, int flags) 242 { 243 struct xhci_pci_softc * const psc = device_private(self); 244 struct xhci_softc * const sc = &psc->sc_xhci; 245 int rv; 246 247 rv = xhci_detach(sc, flags); 248 if (rv) 249 return rv; 250 251 pmf_device_deregister(self); 252 253 xhci_shutdown(self, flags); 254 255 if (sc->sc_ios) { 256 #if 0 257 /* Disable interrupts, so we don't get any spurious ones. */ 258 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 259 OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 260 #endif 261 } 262 263 if (psc->sc_ih != NULL) { 264 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1); 265 psc->sc_ih = NULL; 266 } 267 if (sc->sc_ios) { 268 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 269 sc->sc_ios = 0; 270 } 271 272 return 0; 273 } 274 275 CFATTACH_DECL3_NEW(xhci_pci, sizeof(struct xhci_pci_softc), 276 xhci_pci_match, xhci_pci_attach, xhci_pci_detach, xhci_activate, NULL, 277 xhci_childdet, DVF_DETACH_SHUTDOWN); 278
Indexes created Wed Oct 01 13:09:50 GMT 2025