ydsvar.h revision 1.1.2.2
1 1.1.2.2 nathanw /* $NetBSD: ydsvar.h,v 1.1.2.2 2001/04/09 01:57:15 nathanw Exp $ */ 2 1.1.2.2 nathanw 3 1.1.2.2 nathanw /* 4 1.1.2.2 nathanw * Copyright (c) 2000, 2001 Kazuki Sakamoto and Minoura Makoto. 5 1.1.2.2 nathanw * All rights reserved. 6 1.1.2.2 nathanw * 7 1.1.2.2 nathanw * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 nathanw * modification, are permitted provided that the following conditions 9 1.1.2.2 nathanw * are met: 10 1.1.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 nathanw * documentation and/or other materials provided with the distribution. 15 1.1.2.2 nathanw * 16 1.1.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1.2.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1.2.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1.2.2 nathanw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1.2.2 nathanw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 1.1.2.2 nathanw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 1.1.2.2 nathanw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 1.1.2.2 nathanw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 1.1.2.2 nathanw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 1.1.2.2 nathanw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 1.1.2.2 nathanw */ 27 1.1.2.2 nathanw 28 1.1.2.2 nathanw #ifndef _DEV_PCI_YDSVAR_H_ 29 1.1.2.2 nathanw #define _DEV_PCI_YDSVAR_H_ 30 1.1.2.2 nathanw 31 1.1.2.2 nathanw #define N_PLAY_SLOTS 2 /* We use only 2 (R and L) */ 32 1.1.2.2 nathanw #define N_PLAY_SLOT_CTRL 2 33 1.1.2.2 nathanw #define WORK_SIZE 0x0400 34 1.1.2.2 nathanw 35 1.1.2.2 nathanw /* 36 1.1.2.2 nathanw * softc 37 1.1.2.2 nathanw */ 38 1.1.2.2 nathanw struct yds_dma { 39 1.1.2.2 nathanw bus_dmamap_t map; 40 1.1.2.2 nathanw caddr_t addr; /* VA */ 41 1.1.2.2 nathanw bus_dma_segment_t segs[1]; 42 1.1.2.2 nathanw int nsegs; 43 1.1.2.2 nathanw size_t size; 44 1.1.2.2 nathanw struct yds_dma *next; 45 1.1.2.2 nathanw }; 46 1.1.2.2 nathanw 47 1.1.2.2 nathanw struct yds_codec_softc { 48 1.1.2.2 nathanw struct device sc_dev; /* base device */ 49 1.1.2.2 nathanw struct yds_softc *sc; 50 1.1.2.2 nathanw int id; 51 1.1.2.2 nathanw int status_data; 52 1.1.2.2 nathanw int status_addr; 53 1.1.2.2 nathanw struct ac97_host_if host_if; 54 1.1.2.2 nathanw struct ac97_codec_if *codec_if; 55 1.1.2.2 nathanw }; 56 1.1.2.2 nathanw 57 1.1.2.2 nathanw struct yds_softc { 58 1.1.2.2 nathanw struct device sc_dev; /* base device */ 59 1.1.2.2 nathanw pci_chipset_tag_t sc_pc; 60 1.1.2.2 nathanw pcitag_t sc_pcitag; 61 1.1.2.2 nathanw pcireg_t sc_id; 62 1.1.2.2 nathanw void *sc_ih; /* interrupt vectoring */ 63 1.1.2.2 nathanw bus_space_tag_t memt; 64 1.1.2.2 nathanw bus_space_handle_t memh; 65 1.1.2.2 nathanw bus_dma_tag_t sc_dmatag; /* DMA tag */ 66 1.1.2.2 nathanw u_int sc_flags; 67 1.1.2.2 nathanw 68 1.1.2.2 nathanw struct yds_codec_softc sc_codec[2]; /* Primary/Secondary AC97 */ 69 1.1.2.2 nathanw 70 1.1.2.2 nathanw struct yds_dma *sc_dmas; /* List of DMA handles */ 71 1.1.2.2 nathanw 72 1.1.2.2 nathanw /* 73 1.1.2.2 nathanw * Play/record status 74 1.1.2.2 nathanw */ 75 1.1.2.2 nathanw struct { 76 1.1.2.2 nathanw void (*intr)(void *); /* rint/pint */ 77 1.1.2.2 nathanw void *intr_arg; /* arg for intr */ 78 1.1.2.2 nathanw u_int offset; /* filled up to here */ 79 1.1.2.2 nathanw u_int blksize; 80 1.1.2.2 nathanw u_int factor; /* byte per sample */ 81 1.1.2.2 nathanw u_int length; /* ring buffer length */ 82 1.1.2.2 nathanw struct yds_dma *dma; /* DMA handle for ring buf */ 83 1.1.2.2 nathanw } sc_play, sc_rec; 84 1.1.2.2 nathanw 85 1.1.2.2 nathanw /* 86 1.1.2.2 nathanw * DSP control data 87 1.1.2.2 nathanw * 88 1.1.2.2 nathanw * Work space, play control data table, play slot control data, 89 1.1.2.2 nathanw * rec slot control data and effect slot control data are 90 1.1.2.2 nathanw * stored in a single memory segment in this order. 91 1.1.2.2 nathanw */ 92 1.1.2.2 nathanw struct yds_dma sc_ctrldata; 93 1.1.2.2 nathanw /* KVA and offset in buffer of play ctrl data tbl */ 94 1.1.2.2 nathanw u_int32_t *ptbl; 95 1.1.2.2 nathanw off_t ptbloff; 96 1.1.2.2 nathanw /* KVA and offset in buffer of rec slot ctrl data */ 97 1.1.2.2 nathanw struct rec_slot_ctrl_bank *rbank; 98 1.1.2.2 nathanw off_t rbankoff; 99 1.1.2.2 nathanw /* Array of KVA pointers and offset of play slot control data */ 100 1.1.2.2 nathanw struct play_slot_ctrl_bank *pbankp[N_PLAY_SLOT_CTRL_BANK 101 1.1.2.2 nathanw *N_PLAY_SLOTS]; 102 1.1.2.2 nathanw off_t pbankoff; 103 1.1.2.2 nathanw 104 1.1.2.2 nathanw /* 105 1.1.2.2 nathanw * Legacy support 106 1.1.2.2 nathanw */ 107 1.1.2.2 nathanw bus_space_tag_t sc_legacy_iot; 108 1.1.2.2 nathanw bus_space_handle_t sc_opl_ioh; 109 1.1.2.2 nathanw struct device *sc_mpu; 110 1.1.2.2 nathanw bus_space_handle_t sc_mpu_ioh; 111 1.1.2.2 nathanw }; 112 1.1.2.2 nathanw #define sc_opl_iot sc_legacy_iot 113 1.1.2.2 nathanw #define sc_mpu_iot sc_legacy_iot 114 1.1.2.2 nathanw 115 1.1.2.2 nathanw #endif /* _DEV_PCI_YDSVAR_H_ */ 116
Indexes created Wed Oct 22 13:09:56 GMT 2025