esp_pcmcia.c revision 1.6
1 /* $NetBSD: esp_pcmcia.c,v 1.6 2000/06/05 15:08:01 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/buf.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsipi_all.h> 49 #include <dev/scsipi/scsiconf.h> 50 51 #include <dev/pcmcia/pcmciareg.h> 52 #include <dev/pcmcia/pcmciavar.h> 53 #include <dev/pcmcia/pcmciadevs.h> 54 55 #include <dev/ic/ncr53c9xreg.h> 56 #include <dev/ic/ncr53c9xvar.h> 57 58 struct esp_pcmcia_softc { 59 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 60 61 int sc_active; /* Pseudo-DMA state vars */ 62 int sc_tc; 63 int sc_datain; 64 size_t sc_dmasize; 65 size_t sc_dmatrans; 66 char **sc_dmaaddr; 67 size_t *sc_pdmalen; 68 69 /* PCMCIA-specific goo. */ 70 struct pcmcia_io_handle sc_pcioh; /* PCMCIA i/o space info */ 71 int sc_io_window; /* our i/o window */ 72 struct pcmcia_function *sc_pf; /* our PCMCIA function */ 73 void *sc_ih; /* interrupt handler */ 74 #ifdef ESP_PCMCIA_POLL 75 struct callout sc_poll_ch; 76 #endif 77 int sc_flags; 78 #define ESP_PCMCIA_ATTACHED 1 /* attach completed */ 79 #define ESP_PCMCIA_ATTACHING 2 /* attach in progress */ 80 }; 81 82 int esp_pcmcia_match __P((struct device *, struct cfdata *, void *)); 83 void esp_pcmcia_attach __P((struct device *, struct device *, void *)); 84 void esp_pcmcia_init __P((struct esp_pcmcia_softc *)); 85 int esp_pcmcia_detach __P((struct device *, int)); 86 int esp_pcmcia_enable __P((void *, int)); 87 88 static struct scsipi_adapter esp_pci_adapter = { 89 0, /* adapter refcnt */ 90 ncr53c9x_scsi_cmd, /* cmd */ 91 minphys, /* minphys */ 92 NULL, /* ioctl */ 93 esp_pcmcia_enable, /* enable */ 94 }; 95 96 struct cfattach esp_pcmcia_ca = { 97 sizeof(struct esp_pcmcia_softc), esp_pcmcia_match, esp_pcmcia_attach, 98 esp_pcmcia_detach 99 }; 100 101 /* 102 * Functions and the switch for the MI code. 103 */ 104 #ifdef ESP_PCMCIA_POLL 105 void esp_pcmcia_poll __P((void *)); 106 #endif 107 u_char esp_pcmcia_read_reg __P((struct ncr53c9x_softc *, int)); 108 void esp_pcmcia_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 109 int esp_pcmcia_dma_isintr __P((struct ncr53c9x_softc *)); 110 void esp_pcmcia_dma_reset __P((struct ncr53c9x_softc *)); 111 int esp_pcmcia_dma_intr __P((struct ncr53c9x_softc *)); 112 int esp_pcmcia_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 113 size_t *, int, size_t *)); 114 void esp_pcmcia_dma_go __P((struct ncr53c9x_softc *)); 115 void esp_pcmcia_dma_stop __P((struct ncr53c9x_softc *)); 116 int esp_pcmcia_dma_isactive __P((struct ncr53c9x_softc *)); 117 118 struct ncr53c9x_glue esp_pcmcia_glue = { 119 esp_pcmcia_read_reg, 120 esp_pcmcia_write_reg, 121 esp_pcmcia_dma_isintr, 122 esp_pcmcia_dma_reset, 123 esp_pcmcia_dma_intr, 124 esp_pcmcia_dma_setup, 125 esp_pcmcia_dma_go, 126 esp_pcmcia_dma_stop, 127 esp_pcmcia_dma_isactive, 128 NULL, /* gl_clear_latched_intr */ 129 }; 130 131 const struct pcmcia_product esp_pcmcia_products[] = { 132 { PCMCIA_STR_PANASONIC_KXLC002, PCMCIA_VENDOR_PANASONIC, 133 PCMCIA_PRODUCT_PANASONIC_KXLC002, 0 }, 134 135 { NULL } 136 }; 137 138 int 139 esp_pcmcia_match(parent, match, aux) 140 struct device *parent; 141 struct cfdata *match; 142 void *aux; 143 { 144 struct pcmcia_attach_args *pa = aux; 145 146 if (pcmcia_product_lookup(pa, esp_pcmcia_products, 147 sizeof esp_pcmcia_products[0], NULL) != NULL) 148 return (1); 149 return (0); 150 } 151 152 void 153 esp_pcmcia_attach(parent, self, aux) 154 struct device *parent, *self; 155 void *aux; 156 { 157 struct esp_pcmcia_softc *esc = (void *)self; 158 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 159 struct pcmcia_attach_args *pa = aux; 160 struct pcmcia_config_entry *cfe; 161 struct pcmcia_function *pf = pa->pf; 162 const struct pcmcia_product *pp; 163 164 esc->sc_pf = pf; 165 166 for (cfe = SIMPLEQ_FIRST(&pf->cfe_head); cfe != NULL; 167 cfe = SIMPLEQ_NEXT(cfe, cfe_list)) { 168 if (cfe->num_memspace != 0 || 169 cfe->num_iospace != 1) 170 continue; 171 172 if (pcmcia_io_alloc(pa->pf, cfe->iospace[0].start, 173 cfe->iospace[0].length, 0, &esc->sc_pcioh) == 0) 174 break; 175 } 176 177 if (cfe == 0) { 178 printf(": can't alloc i/o space\n"); 179 goto no_config_entry; 180 } 181 182 /* Enable the card. */ 183 pcmcia_function_init(pf, cfe); 184 if (pcmcia_function_enable(pf)) { 185 printf(": function enable failed\n"); 186 goto enable_failed; 187 } 188 189 /* Map in the I/O space */ 190 if (pcmcia_io_map(pa->pf, PCMCIA_WIDTH_AUTO, 0, esc->sc_pcioh.size, 191 &esc->sc_pcioh, &esc->sc_io_window)) { 192 printf(": can't map i/o space\n"); 193 goto iomap_failed; 194 } 195 196 pp = pcmcia_product_lookup(pa, esp_pcmcia_products, 197 sizeof esp_pcmcia_products[0], NULL); 198 if (pp == NULL) { 199 printf("\n"); 200 panic("esp_pcmcia_attach: impossible"); 201 } 202 203 printf(": %s\n", pp->pp_name); 204 205 esp_pcmcia_init(esc); 206 207 /* 208 * Initialize nca board itself. 209 */ 210 esc->sc_flags |= ESP_PCMCIA_ATTACHING; 211 ncr53c9x_attach(sc, &esp_pci_adapter, NULL); 212 esc->sc_flags &= ~ESP_PCMCIA_ATTACHING; 213 esc->sc_flags |= ESP_PCMCIA_ATTACHED; 214 return; 215 216 iomap_failed: 217 /* Disable the device. */ 218 pcmcia_function_disable(esc->sc_pf); 219 220 enable_failed: 221 /* Unmap our I/O space. */ 222 pcmcia_io_free(esc->sc_pf, &esc->sc_pcioh); 223 224 no_config_entry: 225 return; 226 } 227 228 void 229 esp_pcmcia_init(esc) 230 struct esp_pcmcia_softc *esc; 231 { 232 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 233 bus_space_tag_t iot = esc->sc_pcioh.iot; 234 bus_space_handle_t ioh = esc->sc_pcioh.ioh; 235 236 /* id 7, clock 40M, parity ON, sync OFF, fast ON, slow ON */ 237 238 sc->sc_glue = &esp_pcmcia_glue; 239 240 #ifdef ESP_PCMCIA_POLL 241 callout_init(&esc->sc_poll_ch); 242 #endif 243 244 sc->sc_rev = NCR_VARIANT_ESP406; 245 sc->sc_id = 7; 246 sc->sc_freq = 40; 247 /* try -PARENB -SLOW */ 248 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB | NCRCFG1_SLOW; 249 /* try +FE */ 250 sc->sc_cfg2 = NCRCFG2_SCSI2; 251 /* try -IDM -FSCSI -FCLK */ 252 sc->sc_cfg3 = NCRESPCFG3_CDB | NCRESPCFG3_FCLK | NCRESPCFG3_IDM | 253 NCRESPCFG3_FSCSI; 254 sc->sc_cfg4 = NCRCFG4_ACTNEG; 255 /* try +INTP */ 256 sc->sc_cfg5 = NCRCFG5_CRS1 | NCRCFG5_AADDR | NCRCFG5_PTRINC; 257 sc->sc_minsync = 0; 258 sc->sc_maxxfer = 64 * 1024; 259 260 bus_space_write_1(iot, ioh, NCR_CFG5, sc->sc_cfg5); 261 262 bus_space_write_1(iot, ioh, NCR_PIOI, 0); 263 bus_space_write_1(iot, ioh, NCR_PSTAT, 0); 264 bus_space_write_1(iot, ioh, 0x09, 0x24); 265 266 bus_space_write_1(iot, ioh, NCR_CFG4, sc->sc_cfg4); 267 } 268 269 int 270 esp_pcmcia_detach(self, flags) 271 struct device *self; 272 int flags; 273 { 274 struct esp_pcmcia_softc *esc = (void *)self; 275 int error; 276 277 if ((esc->sc_flags & ESP_PCMCIA_ATTACHED) == 0) { 278 /* Nothing to detach. */ 279 return (0); 280 } 281 282 error = ncr53c9x_detach(&esc->sc_ncr53c9x, flags); 283 if (error) 284 return (error); 285 286 /* Unmap our i/o window and i/o space. */ 287 pcmcia_io_unmap(esc->sc_pf, esc->sc_io_window); 288 pcmcia_io_free(esc->sc_pf, &esc->sc_pcioh); 289 290 return (0); 291 } 292 293 int 294 esp_pcmcia_enable(arg, onoff) 295 void *arg; 296 int onoff; 297 { 298 struct esp_pcmcia_softc *esc = arg; 299 300 if (onoff) { 301 #ifdef ESP_PCMCIA_POLL 302 callout_reset(&esc->sc_poll_ch, 1, esp_pcmcia_poll, esc); 303 #else 304 /* Establish the interrupt handler. */ 305 esc->sc_ih = pcmcia_intr_establish(esc->sc_pf, IPL_BIO, 306 ncr53c9x_intr, &esc->sc_ncr53c9x); 307 if (esc->sc_ih == NULL) { 308 printf("%s: couldn't establish interrupt handler\n", 309 esc->sc_ncr53c9x.sc_dev.dv_xname); 310 return (EIO); 311 } 312 #endif 313 314 /* 315 * If attach is in progress, we know that card power is 316 * enabled and chip will be initialized later. 317 * Otherwise, enable and reset now. 318 */ 319 if ((esc->sc_flags & ESP_PCMCIA_ATTACHING) == 0) { 320 if (pcmcia_function_enable(esc->sc_pf)) { 321 printf("%s: couldn't enable PCMCIA function\n", 322 esc->sc_ncr53c9x.sc_dev.dv_xname); 323 pcmcia_intr_disestablish(esc->sc_pf, 324 esc->sc_ih); 325 return (EIO); 326 } 327 328 /* Initialize only chip. */ 329 ncr53c9x_init(&esc->sc_ncr53c9x, 0); 330 } 331 } else { 332 pcmcia_function_disable(esc->sc_pf); 333 #ifdef ESP_PCMCIA_POLL 334 callout_stop(&esc->sc_poll_ch); 335 #else 336 pcmcia_intr_disestablish(esc->sc_pf, esc->sc_ih); 337 #endif 338 } 339 340 return (0); 341 } 342 343 #ifdef ESP_PCMCIA_POLL 344 void 345 esp_pcmcia_poll(arg) 346 void *arg; 347 { 348 struct esp_pcmcia_softc *esc = arg; 349 350 (void) ncr53c9x_intr(&esc->sc_ncr53c9x); 351 callout_reset(&esc->sc_poll_ch, 1, esp_pcmcia_poll, esc); 352 } 353 #endif 354 355 /* 356 * Glue functions. 357 */ 358 u_char 359 esp_pcmcia_read_reg(sc, reg) 360 struct ncr53c9x_softc *sc; 361 int reg; 362 { 363 struct esp_pcmcia_softc *esc = (struct esp_pcmcia_softc *)sc; 364 u_char v; 365 366 v = bus_space_read_1(esc->sc_pcioh.iot, esc->sc_pcioh.ioh, reg); 367 return v; 368 } 369 370 void 371 esp_pcmcia_write_reg(sc, reg, val) 372 struct ncr53c9x_softc *sc; 373 int reg; 374 u_char val; 375 { 376 struct esp_pcmcia_softc *esc = (struct esp_pcmcia_softc *)sc; 377 u_char v = val; 378 379 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) 380 v = NCRCMD_TRANS; 381 bus_space_write_1(esc->sc_pcioh.iot, esc->sc_pcioh.ioh, reg, v); 382 } 383 384 int 385 esp_pcmcia_dma_isintr(sc) 386 struct ncr53c9x_softc *sc; 387 { 388 389 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 390 } 391 392 void 393 esp_pcmcia_dma_reset(sc) 394 struct ncr53c9x_softc *sc; 395 { 396 struct esp_pcmcia_softc *esc = (struct esp_pcmcia_softc *)sc; 397 398 esc->sc_active = 0; 399 esc->sc_tc = 0; 400 } 401 402 int 403 esp_pcmcia_dma_intr(sc) 404 struct ncr53c9x_softc *sc; 405 { 406 struct esp_pcmcia_softc *esc = (struct esp_pcmcia_softc *)sc; 407 u_char *p; 408 u_int espphase, espstat, espintr; 409 int cnt; 410 411 if (esc->sc_active == 0) { 412 printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname); 413 return -1; 414 } 415 416 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 417 esc->sc_active = 0; 418 return 0; 419 } 420 421 cnt = *esc->sc_pdmalen; 422 if (*esc->sc_pdmalen == 0) { 423 printf("%s: data interrupt, but no count left\n", 424 sc->sc_dev.dv_xname); 425 } 426 427 p = *esc->sc_dmaaddr; 428 espphase = sc->sc_phase; 429 espstat = (u_int) sc->sc_espstat; 430 espintr = (u_int) sc->sc_espintr; 431 do { 432 if (esc->sc_datain) { 433 *p++ = NCR_READ_REG(sc, NCR_FIFO); 434 cnt--; 435 if (espphase == DATA_IN_PHASE) 436 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 437 else 438 esc->sc_active = 0; 439 } else { 440 if (espphase == DATA_OUT_PHASE || 441 espphase == MESSAGE_OUT_PHASE) { 442 NCR_WRITE_REG(sc, NCR_FIFO, *p++); 443 cnt--; 444 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 445 } else 446 esc->sc_active = 0; 447 } 448 449 if (esc->sc_active) { 450 while (!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT)); 451 espstat = NCR_READ_REG(sc, NCR_STAT); 452 espintr = NCR_READ_REG(sc, NCR_INTR); 453 espphase = (espintr & NCRINTR_DIS) 454 ? /* Disconnected */ BUSFREE_PHASE 455 : espstat & PHASE_MASK; 456 } 457 } while (esc->sc_active && espintr); 458 sc->sc_phase = espphase; 459 sc->sc_espstat = (u_char) espstat; 460 sc->sc_espintr = (u_char) espintr; 461 *esc->sc_dmaaddr = p; 462 *esc->sc_pdmalen = cnt; 463 464 if (*esc->sc_pdmalen == 0) 465 esc->sc_tc = NCRSTAT_TC; 466 sc->sc_espstat |= esc->sc_tc; 467 return 0; 468 } 469 470 int 471 esp_pcmcia_dma_setup(sc, addr, len, datain, dmasize) 472 struct ncr53c9x_softc *sc; 473 caddr_t *addr; 474 size_t *len; 475 int datain; 476 size_t *dmasize; 477 { 478 struct esp_pcmcia_softc *esc = (struct esp_pcmcia_softc *)sc; 479 480 esc->sc_dmaaddr = addr; 481 esc->sc_pdmalen = len; 482 esc->sc_datain = datain; 483 esc->sc_dmasize = *dmasize; 484 esc->sc_tc = 0; 485 486 return 0; 487 } 488 489 void 490 esp_pcmcia_dma_go(sc) 491 struct ncr53c9x_softc *sc; 492 { 493 struct esp_pcmcia_softc *esc = (struct esp_pcmcia_softc *)sc; 494 495 esc->sc_active = 1; 496 } 497 498 void 499 esp_pcmcia_dma_stop(sc) 500 struct ncr53c9x_softc *sc; 501 { 502 } 503 504 int 505 esp_pcmcia_dma_isactive(sc) 506 struct ncr53c9x_softc *sc; 507 { 508 struct esp_pcmcia_softc *esc = (struct esp_pcmcia_softc *)sc; 509 510 return (esc->sc_active); 511 } 512
Indexes created Sat Oct 25 07:10:08 GMT 2025