if_xi.c revision 1.47
1 /* $NetBSD: if_xi.c,v 1.47 2004/08/12 18:23:50 mycroft Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.47 2004/08/12 18:23:50 mycroft Exp $"); 59 60 #include "opt_inet.h" 61 #include "opt_ipx.h" 62 #include "bpfilter.h" 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/device.h> 67 #include <sys/ioctl.h> 68 #include <sys/mbuf.h> 69 #include <sys/malloc.h> 70 #include <sys/socket.h> 71 #include <sys/kernel.h> 72 #include <sys/proc.h> 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/if_ether.h> 79 80 #ifdef INET 81 #include <netinet/in.h> 82 #include <netinet/in_systm.h> 83 #include <netinet/in_var.h> 84 #include <netinet/ip.h> 85 #include <netinet/if_inarp.h> 86 #endif 87 88 #ifdef IPX 89 #include <netipx/ipx.h> 90 #include <netipx/ipx_if.h> 91 #endif 92 93 #ifdef NS 94 #include <netns/ns.h> 95 #include <netns/ns_if.h> 96 #endif 97 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 /* 104 * Maximum number of bytes to read per interrupt. Linux recommends 105 * somewhere between 2000-22000. 106 * XXX This is currently a hard maximum. 107 */ 108 #define MAX_BYTES_INTR 12000 109 110 #include <dev/mii/mii.h> 111 #include <dev/mii/miivar.h> 112 113 #include <dev/pcmcia/pcmciareg.h> 114 #include <dev/pcmcia/pcmciavar.h> 115 #include <dev/pcmcia/pcmciadevs.h> 116 117 #include <dev/pcmcia/if_xireg.h> 118 #include <dev/pcmcia/if_xivar.h> 119 120 #ifdef __GNUC__ 121 #define INLINE __inline 122 #else 123 #define INLINE 124 #endif /* __GNUC__ */ 125 126 #define XIDEBUG 127 #define XIDEBUG_VALUE 0 128 129 #ifdef XIDEBUG 130 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 131 132 #define XID_CONFIG 0x01 133 #define XID_MII 0x02 134 #define XID_INTR 0x04 135 #define XID_FIFO 0x08 136 #define XID_MCAST 0x10 137 138 #ifdef XIDEBUG_VALUE 139 int xidebug = XIDEBUG_VALUE; 140 #else 141 int xidebug = 0; 142 #endif 143 #else 144 #define DPRINTF(cat, x) (void)0 145 #endif 146 147 #define STATIC 148 149 STATIC int xi_enable __P((struct xi_softc *)); 150 STATIC void xi_disable __P((struct xi_softc *)); 151 STATIC void xi_cycle_power __P((struct xi_softc *)); 152 STATIC int xi_ether_ioctl __P((struct ifnet *, u_long cmd, caddr_t)); 153 STATIC void xi_full_reset __P((struct xi_softc *)); 154 STATIC void xi_init __P((struct xi_softc *)); 155 STATIC int xi_ioctl __P((struct ifnet *, u_long, caddr_t)); 156 STATIC int xi_mdi_read __P((struct device *, int, int)); 157 STATIC void xi_mdi_write __P((struct device *, int, int, int)); 158 STATIC int xi_mediachange __P((struct ifnet *)); 159 STATIC void xi_mediastatus __P((struct ifnet *, struct ifmediareq *)); 160 STATIC u_int16_t xi_get __P((struct xi_softc *)); 161 STATIC void xi_reset __P((struct xi_softc *)); 162 STATIC void xi_set_address __P((struct xi_softc *)); 163 STATIC void xi_start __P((struct ifnet *)); 164 STATIC void xi_statchg __P((struct device *)); 165 STATIC void xi_stop __P((struct xi_softc *)); 166 STATIC void xi_watchdog __P((struct ifnet *)); 167 168 void 169 xi_attach(sc, myea) 170 struct xi_softc *sc; 171 u_int8_t *myea; 172 { 173 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 174 175 #if 0 176 /* 177 * Configuration as advised by DINGO documentation. 178 * Dingo has some extra configuration registers in the CCR space. 179 */ 180 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 181 struct pcmcia_mem_handle pcmh; 182 int ccr_window; 183 bus_size_t ccr_offset; 184 185 /* get access to the DINGO CCR space */ 186 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 187 &pcmh)) { 188 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 189 goto fail; 190 } 191 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 192 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 193 &pcmh, &ccr_offset, &ccr_window)) { 194 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 195 pcmcia_mem_free(psc->sc_pf, &pcmh); 196 goto fail; 197 } 198 199 /* enable the second function - usually modem */ 200 bus_space_write_1(pcmh.memt, pcmh.memh, 201 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 202 bus_space_write_1(pcmh.memt, pcmh.memh, 203 ccr_offset + PCMCIA_CCR_DCOR1, 204 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 205 bus_space_write_1(pcmh.memt, pcmh.memh, 206 ccr_offset + PCMCIA_CCR_DCOR2, 0); 207 bus_space_write_1(pcmh.memt, pcmh.memh, 208 ccr_offset + PCMCIA_CCR_DCOR3, 0); 209 bus_space_write_1(pcmh.memt, pcmh.memh, 210 ccr_offset + PCMCIA_CCR_DCOR4, 0); 211 212 /* We don't need them anymore and can free them (I think). */ 213 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 214 pcmcia_mem_free(psc->sc_pf, &pcmh); 215 } 216 #endif 217 218 /* Reset and initialize the card. */ 219 xi_full_reset(sc); 220 221 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, ether_sprintf(myea)); 222 223 ifp = &sc->sc_ethercom.ec_if; 224 /* Initialize the ifnet structure. */ 225 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 226 ifp->if_softc = sc; 227 ifp->if_start = xi_start; 228 ifp->if_ioctl = xi_ioctl; 229 ifp->if_watchdog = xi_watchdog; 230 ifp->if_flags = 231 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 232 IFQ_SET_READY(&ifp->if_snd); 233 234 /* 802.1q capability */ 235 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 236 237 /* Attach the interface. */ 238 if_attach(ifp); 239 ether_ifattach(ifp, myea); 240 241 /* 242 * Initialize our media structures and probe the MII. 243 */ 244 sc->sc_mii.mii_ifp = ifp; 245 sc->sc_mii.mii_readreg = xi_mdi_read; 246 sc->sc_mii.mii_writereg = xi_mdi_write; 247 sc->sc_mii.mii_statchg = xi_statchg; 248 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 249 xi_mediastatus); 250 DPRINTF(XID_MII | XID_CONFIG, 251 ("xi: bmsr %x\n", xi_mdi_read(&sc->sc_dev, 0, 1))); 252 253 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 254 MII_OFFSET_ANY, 0); 255 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 256 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 257 NULL); 258 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 259 260 #if NRND > 0 261 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, RND_TYPE_NET, 0); 262 #endif 263 } 264 265 int 266 xi_detach(self, flags) 267 struct device *self; 268 int flags; 269 { 270 struct xi_softc *sc = (void *)self; 271 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 272 273 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 274 275 xi_disable(sc); 276 277 #if NRND > 0 278 rnd_detach_source(&sc->sc_rnd_source); 279 #endif 280 281 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 282 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 283 ether_ifdetach(ifp); 284 if_detach(ifp); 285 286 return 0; 287 } 288 289 int 290 xi_activate(self, act) 291 struct device *self; 292 enum devact act; 293 { 294 struct xi_softc *sc = (void *)self; 295 int s, rv = 0; 296 297 DPRINTF(XID_CONFIG, ("xi_activate()\n")); 298 299 s = splnet(); 300 switch (act) { 301 case DVACT_ACTIVATE: 302 rv = EOPNOTSUPP; 303 break; 304 305 case DVACT_DEACTIVATE: 306 if_deactivate(&sc->sc_ethercom.ec_if); 307 break; 308 } 309 splx(s); 310 return (rv); 311 } 312 313 int 314 xi_intr(arg) 315 void *arg; 316 { 317 struct xi_softc *sc = arg; 318 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 319 u_int8_t esr, rsr, isr, rx_status; 320 u_int16_t tx_status, recvcount = 0, tempint; 321 322 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 323 324 if (sc->sc_enabled == 0 || 325 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 326 return (0); 327 328 ifp->if_timer = 0; /* turn watchdog timer off */ 329 330 PAGE(sc, 0); 331 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 332 /* Disable interrupt (Linux does it). */ 333 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 334 0); 335 } 336 337 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ESR); 338 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ISR0); 339 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 340 341 /* Check to see if card has been ejected. */ 342 if (isr == 0xff) { 343 #ifdef DIAGNOSTIC 344 printf("%s: interrupt for dead card\n", sc->sc_dev.dv_xname); 345 #endif 346 goto end; 347 } 348 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 349 350 PAGE(sc, 0x40); 351 rx_status = 352 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RXST0); 353 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RXST0, 354 ~rx_status & 0xff); 355 tx_status = 356 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST0); 357 tx_status |= 358 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST1) << 8; 359 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST0,0); 360 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST1,0); 361 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 362 tx_status)); 363 364 PAGE(sc, 0); 365 while (esr & FULL_PKT_RCV) { 366 if (!(rsr & RSR_RX_OK)) 367 break; 368 369 /* Compare bytes read this interrupt to hard maximum. */ 370 if (recvcount > MAX_BYTES_INTR) { 371 DPRINTF(XID_INTR, 372 ("xi: too many bytes this interrupt\n")); 373 ifp->if_iqdrops++; 374 /* Drop packet. */ 375 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 376 sc->sc_offset + DO0, DO_SKIP_RX_PKT); 377 } 378 tempint = xi_get(sc); /* XXX doesn't check the error! */ 379 recvcount += tempint; 380 ifp->if_ibytes += tempint; 381 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 382 sc->sc_offset + ESR); 383 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 384 sc->sc_offset + RSR); 385 } 386 387 /* Packet too long? */ 388 if (rsr & RSR_TOO_LONG) { 389 ifp->if_ierrors++; 390 DPRINTF(XID_INTR, ("xi: packet too long\n")); 391 } 392 393 /* CRC error? */ 394 if (rsr & RSR_CRCERR) { 395 ifp->if_ierrors++; 396 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 397 } 398 399 /* Alignment error? */ 400 if (rsr & RSR_ALIGNERR) { 401 ifp->if_ierrors++; 402 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 403 } 404 405 /* Check for rx overrun. */ 406 if (rx_status & RX_OVERRUN) { 407 ifp->if_ierrors++; 408 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 409 CLR_RX_OVERRUN); 410 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 411 } 412 413 /* Try to start more packets transmitting. */ 414 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 415 xi_start(ifp); 416 417 /* Detected excessive collisions? */ 418 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 419 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 420 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 421 RESTART_TX); 422 ifp->if_oerrors++; 423 } 424 425 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 426 ifp->if_oerrors++; 427 428 /* have handled the interrupt */ 429 #if NRND > 0 430 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 431 #endif 432 433 end: 434 /* Reenable interrupts. */ 435 PAGE(sc, 0); 436 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 437 ENABLE_INT); 438 439 return (1); 440 } 441 442 /* 443 * Pull a packet from the card into an mbuf chain. 444 */ 445 STATIC u_int16_t 446 xi_get(sc) 447 struct xi_softc *sc; 448 { 449 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 450 struct mbuf *top, **mp, *m; 451 u_int16_t pktlen, len, recvcount = 0; 452 u_int8_t *data; 453 454 DPRINTF(XID_CONFIG, ("xi_get()\n")); 455 456 PAGE(sc, 0); 457 pktlen = 458 bus_space_read_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RBC0) & 459 RBC_COUNT_MASK; 460 461 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 462 463 if (pktlen == 0) { 464 /* 465 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 466 * when MPE is set. It is not known why. 467 */ 468 return (0); 469 } 470 471 /* XXX should this be incremented now ? */ 472 recvcount += pktlen; 473 474 MGETHDR(m, M_DONTWAIT, MT_DATA); 475 if (m == 0) 476 return (recvcount); 477 m->m_pkthdr.rcvif = ifp; 478 m->m_pkthdr.len = pktlen; 479 m->m_flags |= M_HASFCS; 480 len = MHLEN; 481 top = 0; 482 mp = ⊤ 483 484 while (pktlen > 0) { 485 if (top) { 486 MGET(m, M_DONTWAIT, MT_DATA); 487 if (m == 0) { 488 m_freem(top); 489 return (recvcount); 490 } 491 len = MLEN; 492 } 493 if (pktlen >= MINCLSIZE) { 494 MCLGET(m, M_DONTWAIT); 495 if (!(m->m_flags & M_EXT)) { 496 m_freem(m); 497 m_freem(top); 498 return (recvcount); 499 } 500 len = MCLBYTES; 501 } 502 if (!top) { 503 caddr_t newdata = (caddr_t)ALIGN(m->m_data + 504 sizeof(struct ether_header)) - 505 sizeof(struct ether_header); 506 len -= newdata - m->m_data; 507 m->m_data = newdata; 508 } 509 len = min(pktlen, len); 510 data = mtod(m, u_int8_t *); 511 if (len > 1) { 512 len &= ~1; 513 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, 514 sc->sc_offset + EDP, (u_int16_t *)data, len>>1); 515 } else 516 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 517 sc->sc_offset + EDP); 518 m->m_len = len; 519 pktlen -= len; 520 *mp = m; 521 mp = &m->m_next; 522 } 523 524 /* Skip Rx packet. */ 525 bus_space_write_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + DO0, 526 DO_SKIP_RX_PKT); 527 528 ifp->if_ipackets++; 529 530 #if NBPFILTER > 0 531 if (ifp->if_bpf) 532 bpf_mtap(ifp->if_bpf, top); 533 #endif 534 535 (*ifp->if_input)(ifp, top); 536 return (recvcount); 537 } 538 539 /* 540 * Serial management for the MII. 541 * The DELAY's below stem from the fact that the maximum frequency 542 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 543 * go much faster than that. 544 */ 545 546 /* Let the MII serial management be idle for one period. */ 547 static INLINE void xi_mdi_idle __P((struct xi_softc *)); 548 static INLINE void 549 xi_mdi_idle(sc) 550 struct xi_softc *sc; 551 { 552 bus_space_tag_t bst = sc->sc_bst; 553 bus_space_handle_t bsh = sc->sc_bsh; 554 bus_size_t offset = sc->sc_offset; 555 556 /* Drive MDC low... */ 557 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 558 DELAY(1); 559 560 /* and high again. */ 561 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 562 DELAY(1); 563 } 564 565 /* Pulse out one bit of data. */ 566 static INLINE void xi_mdi_pulse __P((struct xi_softc *, int)); 567 static INLINE void 568 xi_mdi_pulse(sc, data) 569 struct xi_softc *sc; 570 int data; 571 { 572 bus_space_tag_t bst = sc->sc_bst; 573 bus_space_handle_t bsh = sc->sc_bsh; 574 bus_size_t offset = sc->sc_offset; 575 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 576 577 /* First latch the data bit MDIO with clock bit MDC low...*/ 578 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_LOW); 579 DELAY(1); 580 581 /* then raise the clock again, preserving the data bit. */ 582 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_HIGH); 583 DELAY(1); 584 } 585 586 /* Probe one bit of data. */ 587 static INLINE int xi_mdi_probe __P((struct xi_softc *sc)); 588 static INLINE int 589 xi_mdi_probe(sc) 590 struct xi_softc *sc; 591 { 592 bus_space_tag_t bst = sc->sc_bst; 593 bus_space_handle_t bsh = sc->sc_bsh; 594 bus_size_t offset = sc->sc_offset; 595 u_int8_t x; 596 597 /* Pull clock bit MDCK low... */ 598 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 599 DELAY(1); 600 601 /* Read data and drive clock high again. */ 602 x = bus_space_read_1(bst, bsh, offset + GP2); 603 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 604 DELAY(1); 605 606 return (x & MDIO); 607 } 608 609 /* Pulse out a sequence of data bits. */ 610 static INLINE void xi_mdi_pulse_bits __P((struct xi_softc *, u_int32_t, int)); 611 static INLINE void 612 xi_mdi_pulse_bits(sc, data, len) 613 struct xi_softc *sc; 614 u_int32_t data; 615 int len; 616 { 617 u_int32_t mask; 618 619 for (mask = 1 << (len - 1); mask; mask >>= 1) 620 xi_mdi_pulse(sc, data & mask); 621 } 622 623 /* Read a PHY register. */ 624 STATIC int 625 xi_mdi_read(self, phy, reg) 626 struct device *self; 627 int phy; 628 int reg; 629 { 630 struct xi_softc *sc = (struct xi_softc *)self; 631 int i; 632 u_int32_t mask; 633 u_int32_t data = 0; 634 635 PAGE(sc, 2); 636 for (i = 0; i < 32; i++) /* Synchronize. */ 637 xi_mdi_pulse(sc, 1); 638 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 639 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 640 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 641 xi_mdi_idle(sc); /* Turn around. */ 642 xi_mdi_probe(sc); /* Drop initial zero bit. */ 643 644 for (mask = 1 << 15; mask; mask >>= 1) { 645 if (xi_mdi_probe(sc)) 646 data |= mask; 647 } 648 xi_mdi_idle(sc); 649 650 DPRINTF(XID_MII, 651 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 652 653 return (data); 654 } 655 656 /* Write a PHY register. */ 657 STATIC void 658 xi_mdi_write(self, phy, reg, value) 659 struct device *self; 660 int phy; 661 int reg; 662 int value; 663 { 664 struct xi_softc *sc = (struct xi_softc *)self; 665 int i; 666 667 PAGE(sc, 2); 668 for (i = 0; i < 32; i++) /* Synchronize. */ 669 xi_mdi_pulse(sc, 1); 670 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 671 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 672 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 673 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 674 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 675 xi_mdi_idle(sc); /* Idle away. */ 676 677 DPRINTF(XID_MII, 678 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 679 } 680 681 STATIC void 682 xi_statchg(self) 683 struct device *self; 684 { 685 /* XXX Update ifp->if_baudrate */ 686 } 687 688 /* 689 * Change media according to request. 690 */ 691 STATIC int 692 xi_mediachange(ifp) 693 struct ifnet *ifp; 694 { 695 int s; 696 697 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 698 699 if (ifp->if_flags & IFF_UP) { 700 s = splnet(); 701 xi_init(ifp->if_softc); 702 splx(s); 703 } 704 return (0); 705 } 706 707 /* 708 * Notify the world which media we're using. 709 */ 710 STATIC void 711 xi_mediastatus(ifp, ifmr) 712 struct ifnet *ifp; 713 struct ifmediareq *ifmr; 714 { 715 struct xi_softc *sc = ifp->if_softc; 716 717 DPRINTF(XID_CONFIG, ("xi_mediastatus()\n")); 718 719 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 720 mii_pollstat(&sc->sc_mii); 721 ifmr->ifm_status = sc->sc_mii.mii_media_status; 722 ifmr->ifm_active = sc->sc_mii.mii_media_active; 723 } 724 } 725 726 STATIC void 727 xi_reset(sc) 728 struct xi_softc *sc; 729 { 730 int s; 731 732 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 733 734 s = splnet(); 735 xi_stop(sc); 736 xi_init(sc); 737 splx(s); 738 } 739 740 STATIC void 741 xi_watchdog(ifp) 742 struct ifnet *ifp; 743 { 744 struct xi_softc *sc = ifp->if_softc; 745 746 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 747 ++ifp->if_oerrors; 748 749 xi_reset(sc); 750 } 751 752 STATIC void 753 xi_stop(sc) 754 register struct xi_softc *sc; 755 { 756 bus_space_tag_t bst = sc->sc_bst; 757 bus_space_handle_t bsh = sc->sc_bsh; 758 bus_size_t offset = sc->sc_offset; 759 760 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 761 762 PAGE(sc, 0x40); 763 bus_space_write_1(bst, bsh, offset + CMD0, DISABLE_RX); 764 765 /* Disable interrupts. */ 766 PAGE(sc, 0); 767 bus_space_write_1(bst, bsh, offset + CR, 0); 768 769 PAGE(sc, 1); 770 bus_space_write_1(bst, bsh, offset + IMR0, 0); 771 772 /* Cancel watchdog timer. */ 773 sc->sc_ethercom.ec_if.if_timer = 0; 774 } 775 776 STATIC int 777 xi_enable(sc) 778 struct xi_softc *sc; 779 { 780 int error; 781 782 if (!sc->sc_enabled) { 783 error = (*sc->sc_enable)(sc); 784 if (error) 785 return (error); 786 sc->sc_enabled = 1; 787 xi_full_reset(sc); 788 } 789 return (0); 790 } 791 792 STATIC void 793 xi_disable(sc) 794 struct xi_softc *sc; 795 { 796 797 if (sc->sc_enabled) { 798 sc->sc_enabled = 0; 799 (*sc->sc_disable)(sc); 800 } 801 } 802 803 STATIC void 804 xi_init(sc) 805 struct xi_softc *sc; 806 { 807 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 808 bus_space_tag_t bst = sc->sc_bst; 809 bus_space_handle_t bsh = sc->sc_bsh; 810 bus_size_t offset = sc->sc_offset; 811 812 DPRINTF(XID_CONFIG, ("xi_init()\n")); 813 814 /* Setup the ethernet interrupt mask. */ 815 PAGE(sc, 1); 816 bus_space_write_1(bst, bsh, offset + IMR0, 817 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 818 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 819 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 820 /* XXX What is this? Not for Dingo at least. */ 821 /* Unmask TX underrun detection */ 822 bus_space_write_1(bst, bsh, offset + IMR1, 1); 823 } 824 825 /* Enable interrupts. */ 826 PAGE(sc, 0); 827 bus_space_write_1(bst, bsh, offset + CR, ENABLE_INT); 828 829 xi_set_address(sc); 830 831 PAGE(sc, 0x40); 832 bus_space_write_1(bst, bsh, offset + CMD0, ENABLE_RX | ONLINE); 833 834 PAGE(sc, 0); 835 836 /* Set current media. */ 837 mii_mediachg(&sc->sc_mii); 838 839 ifp->if_flags |= IFF_RUNNING; 840 ifp->if_flags &= ~IFF_OACTIVE; 841 842 xi_start(ifp); 843 } 844 845 /* 846 * Start outputting on the interface. 847 * Always called as splnet(). 848 */ 849 STATIC void 850 xi_start(ifp) 851 struct ifnet *ifp; 852 { 853 struct xi_softc *sc = ifp->if_softc; 854 bus_space_tag_t bst = sc->sc_bst; 855 bus_space_handle_t bsh = sc->sc_bsh; 856 bus_size_t offset = sc->sc_offset; 857 unsigned int s, len, pad = 0; 858 struct mbuf *m0, *m; 859 u_int16_t space; 860 861 DPRINTF(XID_CONFIG, ("xi_start()\n")); 862 863 /* Don't transmit if interface is busy or not running. */ 864 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 865 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 866 return; 867 } 868 869 /* Peek at the next packet. */ 870 IFQ_POLL(&ifp->if_snd, m0); 871 if (m0 == 0) 872 return; 873 874 /* We need to use m->m_pkthdr.len, so require the header. */ 875 if (!(m0->m_flags & M_PKTHDR)) 876 panic("xi_start: no header mbuf"); 877 878 len = m0->m_pkthdr.len; 879 880 #if 1 881 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 882 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 883 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 884 #else 885 pad = 0; 886 #endif 887 888 PAGE(sc, 0); 889 890 bus_space_write_2(bst, bsh, offset + TRS, (u_int16_t)len + pad + 2); 891 space = bus_space_read_2(bst, bsh, offset + TSO) & 0x7fff; 892 if (len + pad + 2 > space) { 893 DPRINTF(XID_FIFO, 894 ("xi: not enough space in output FIFO (%d > %d)\n", 895 len + pad + 2, space)); 896 return; 897 } 898 899 IFQ_DEQUEUE(&ifp->if_snd, m0); 900 901 #if NBPFILTER > 0 902 if (ifp->if_bpf) 903 bpf_mtap(ifp->if_bpf, m0); 904 #endif 905 906 /* 907 * Do the output at splhigh() so that an interrupt from another device 908 * won't cause a FIFO underrun. 909 */ 910 s = splhigh(); 911 912 bus_space_write_2(bst, bsh, offset + EDP, (u_int16_t)len + pad); 913 for (m = m0; m; ) { 914 if (m->m_len > 1) 915 bus_space_write_multi_2(bst, bsh, offset + EDP, 916 mtod(m, u_int16_t *), m->m_len>>1); 917 if (m->m_len & 1) { 918 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 919 bus_space_write_1(bst, bsh, offset + EDP, 920 *(mtod(m, u_int8_t *) + m->m_len - 1)); 921 } 922 MFREE(m, m0); 923 m = m0; 924 } 925 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 926 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 927 bus_space_write_1(bst, bsh, offset + CR, TX_PKT | ENABLE_INT); 928 else { 929 for (; pad > 1; pad -= 2) 930 bus_space_write_2(bst, bsh, offset + EDP, 0); 931 if (pad == 1) 932 bus_space_write_1(bst, bsh, offset + EDP, 0); 933 } 934 935 splx(s); 936 937 ifp->if_timer = 5; 938 ++ifp->if_opackets; 939 } 940 941 STATIC int 942 xi_ether_ioctl(ifp, cmd, data) 943 struct ifnet *ifp; 944 u_long cmd; 945 caddr_t data; 946 { 947 struct ifaddr *ifa = (struct ifaddr *)data; 948 struct xi_softc *sc = ifp->if_softc; 949 int error; 950 951 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 952 953 switch (cmd) { 954 case SIOCSIFADDR: 955 if ((error = xi_enable(sc)) != 0) 956 break; 957 958 ifp->if_flags |= IFF_UP; 959 960 switch (ifa->ifa_addr->sa_family) { 961 #ifdef INET 962 case AF_INET: 963 xi_init(sc); 964 arp_ifinit(ifp, ifa); 965 break; 966 #endif /* INET */ 967 968 #ifdef NS 969 case AF_NS: 970 { 971 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 972 973 if (ns_nullhost(*ina)) 974 ina->x_host = *(union ns_host *) 975 LLADDR(ifp->if_sadl); 976 else 977 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 978 ifp->if_addrlen); 979 /* Set new address. */ 980 xi_init(sc); 981 break; 982 } 983 #endif /* NS */ 984 985 default: 986 xi_init(sc); 987 break; 988 } 989 break; 990 991 default: 992 return (EINVAL); 993 } 994 995 return (0); 996 } 997 998 STATIC int 999 xi_ioctl(ifp, cmd, data) 1000 struct ifnet *ifp; 1001 u_long cmd; 1002 caddr_t data; 1003 { 1004 struct xi_softc *sc = ifp->if_softc; 1005 struct ifreq *ifr = (struct ifreq *)data; 1006 int s, error = 0; 1007 1008 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 1009 1010 s = splnet(); 1011 1012 switch (cmd) { 1013 case SIOCSIFADDR: 1014 error = xi_ether_ioctl(ifp, cmd, data); 1015 break; 1016 1017 case SIOCSIFFLAGS: 1018 if ((ifp->if_flags & IFF_UP) == 0 && 1019 (ifp->if_flags & IFF_RUNNING) != 0) { 1020 /* 1021 * If interface is marked down and it is running, 1022 * stop it. 1023 */ 1024 xi_stop(sc); 1025 ifp->if_flags &= ~IFF_RUNNING; 1026 xi_disable(sc); 1027 } else if ((ifp->if_flags & IFF_UP) != 0 && 1028 (ifp->if_flags & IFF_RUNNING) == 0) { 1029 /* 1030 * If interface is marked up and it is stopped, 1031 * start it. 1032 */ 1033 if ((error = xi_enable(sc)) != 0) 1034 break; 1035 xi_init(sc); 1036 } else if ((ifp->if_flags & IFF_UP) != 0) { 1037 /* 1038 * Reset the interface to pick up changes in any 1039 * other flags that affect hardware registers. 1040 */ 1041 xi_set_address(sc); 1042 } 1043 break; 1044 1045 case SIOCADDMULTI: 1046 case SIOCDELMULTI: 1047 if (sc->sc_enabled == 0) { 1048 error = EIO; 1049 break; 1050 } 1051 1052 error = (cmd == SIOCADDMULTI) ? 1053 ether_addmulti(ifr, &sc->sc_ethercom) : 1054 ether_delmulti(ifr, &sc->sc_ethercom); 1055 if (error == ENETRESET) { 1056 /* 1057 * Multicast list has changed; set the hardware 1058 * filter accordingly. 1059 */ 1060 xi_set_address(sc); 1061 error = 0; 1062 } 1063 break; 1064 1065 case SIOCSIFMEDIA: 1066 case SIOCGIFMEDIA: 1067 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1068 break; 1069 1070 default: 1071 error = EINVAL; 1072 break; 1073 } 1074 1075 splx(s); 1076 return (error); 1077 } 1078 1079 STATIC void 1080 xi_set_address(sc) 1081 struct xi_softc *sc; 1082 { 1083 bus_space_tag_t bst = sc->sc_bst; 1084 bus_space_handle_t bsh = sc->sc_bsh; 1085 bus_size_t offset = sc->sc_offset; 1086 struct ethercom *ether = &sc->sc_ethercom; 1087 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1088 struct ether_multistep step; 1089 struct ether_multi *enm; 1090 int page, num; 1091 int i; 1092 u_int8_t x; 1093 u_int8_t *enaddr; 1094 u_int8_t indaddr[64]; 1095 1096 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 1097 1098 enaddr = (u_int8_t *)LLADDR(ifp->if_sadl); 1099 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1100 for (i = 0; i < 6; i++) 1101 indaddr[i] = enaddr[5 - i]; 1102 else 1103 for (i = 0; i < 6; i++) 1104 indaddr[i] = enaddr[i]; 1105 num = 1; 1106 1107 if (ether->ec_multicnt > 9) { 1108 ifp->if_flags |= IFF_ALLMULTI; 1109 goto done; 1110 } 1111 1112 ETHER_FIRST_MULTI(step, ether, enm); 1113 for (; enm; num++) { 1114 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1115 sizeof(enm->enm_addrlo)) != 0) { 1116 /* 1117 * The multicast address is really a range; 1118 * it's easier just to accept all multicasts. 1119 * XXX should we be setting IFF_ALLMULTI here? 1120 */ 1121 ifp->if_flags |= IFF_ALLMULTI; 1122 goto done; 1123 } 1124 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1125 for (i = 0; i < 6; i++) 1126 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 1127 else 1128 for (i = 0; i < 6; i++) 1129 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 1130 ETHER_NEXT_MULTI(step, enm); 1131 } 1132 ifp->if_flags &= ~IFF_ALLMULTI; 1133 1134 done: 1135 if (num < 10) 1136 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 1137 1138 for (page = 0; page < 8; page++) { 1139 #ifdef XIDEBUG 1140 if (xidebug & XID_MCAST) { 1141 printf("page %d before:", page); 1142 for (i = 0; i < 8; i++) 1143 printf(" %02x", indaddr[page * 8 + i]); 1144 printf("\n"); 1145 } 1146 #endif 1147 1148 PAGE(sc, 0x50 + page); 1149 bus_space_write_region_1(bst, bsh, offset + IA, 1150 &indaddr[page * 8], page == 7 ? 4 : 8); 1151 /* 1152 * XXX 1153 * Without this delay, the address registers on my CE2 get 1154 * trashed the first and I have to cycle it. I have no idea 1155 * why. - mycroft, 2004/08/09 1156 */ 1157 DELAY(50); 1158 1159 #ifdef XIDEBUG 1160 if (xidebug & XID_MCAST) { 1161 bus_space_read_region_1(bst, bsh, offset + IA, 1162 &indaddr[page * 8], page == 7 ? 4 : 8); 1163 printf("page %d after: ", page); 1164 for (i = 0; i < 8; i++) 1165 printf(" %02x", indaddr[page * 8 + i]); 1166 printf("\n"); 1167 } 1168 #endif 1169 } 1170 1171 PAGE(sc, 0x42); 1172 x = SWC1_IND_ADDR; 1173 if (ifp->if_flags & IFF_PROMISC) 1174 x |= SWC1_PROMISC; 1175 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) 1176 x |= SWC1_MCAST_PROM; 1177 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1178 x |= SWC1_AUTO_MEDIA; 1179 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + SWC1, x); 1180 } 1181 1182 STATIC void 1183 xi_cycle_power(sc) 1184 struct xi_softc *sc; 1185 { 1186 bus_space_tag_t bst = sc->sc_bst; 1187 bus_space_handle_t bsh = sc->sc_bsh; 1188 bus_size_t offset = sc->sc_offset; 1189 1190 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1191 1192 PAGE(sc, 4); 1193 DELAY(1); 1194 bus_space_write_1(bst, bsh, offset + GP1, 0); 1195 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1196 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1197 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP); 1198 else 1199 /* XXX What is bit 2 (aka AIC)? */ 1200 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP | 4); 1201 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1202 } 1203 1204 STATIC void 1205 xi_full_reset(sc) 1206 struct xi_softc *sc; 1207 { 1208 bus_space_tag_t bst = sc->sc_bst; 1209 bus_space_handle_t bsh = sc->sc_bsh; 1210 bus_size_t offset = sc->sc_offset; 1211 u_int8_t x; 1212 1213 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1214 1215 /* Do an as extensive reset as possible on all functions. */ 1216 xi_cycle_power(sc); 1217 bus_space_write_1(bst, bsh, offset + CR, SOFT_RESET); 1218 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1219 bus_space_write_1(bst, bsh, offset + CR, 0); 1220 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1221 PAGE(sc, 4); 1222 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1223 /* 1224 * Drive GP1 low to power up ML6692 and GP2 high to power up 1225 * the 10MHz chip. XXX What chip is that? The phy? 1226 */ 1227 bus_space_write_1(bst, bsh, offset + GP0, 1228 GP1_OUT | GP2_OUT | GP2_WR); 1229 } 1230 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1231 1232 /* Get revision information. XXX Symbolic constants. */ 1233 sc->sc_rev = bus_space_read_1(bst, bsh, offset + BV) & 1234 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1235 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1236 1237 /* Media selection. XXX Maybe manual overriding too? */ 1238 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1239 /* 1240 * XXX I have no idea what this really does, it is from the 1241 * Linux driver. 1242 */ 1243 bus_space_write_1(bst, bsh, offset + GP0, GP1_OUT); 1244 } 1245 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1246 1247 /* 1248 * Disable source insertion. 1249 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1250 */ 1251 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1252 PAGE(sc, 0x42); 1253 bus_space_write_1(bst, bsh, offset + SWC0, 0x20); 1254 } 1255 1256 /* Set the local memory dividing line. */ 1257 if (sc->sc_rev != 1) { 1258 PAGE(sc, 2); 1259 /* XXX Symbolic constant preferrable. */ 1260 bus_space_write_2(bst, bsh, offset + RBS0, 0x2000); 1261 } 1262 1263 /* 1264 * Apparently the receive byte pointer can be bad after a reset, so 1265 * we hardwire it correctly. 1266 */ 1267 PAGE(sc, 0); 1268 bus_space_write_2(bst, bsh, offset + DO0, DO_CHG_OFFSET); 1269 1270 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1271 PAGE(sc, 0x40); 1272 bus_space_write_1(bst, bsh, offset + RX0MSK, 1273 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1274 bus_space_write_1(bst, bsh, offset + TX0MSK, 1275 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1276 SQE | TX_ABORT | TX_OK); 1277 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1278 /* XXX From Linux, dunno what 0xb0 means. */ 1279 bus_space_write_1(bst, bsh, offset + TX1MSK, 0xb0); 1280 bus_space_write_1(bst, bsh, offset + RXST0, 0); 1281 bus_space_write_1(bst, bsh, offset + TXST0, 0); 1282 bus_space_write_1(bst, bsh, offset + TXST1, 0); 1283 1284 PAGE(sc, 2); 1285 1286 /* Enable MII function if available. */ 1287 x = 0; 1288 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1289 x |= SELECT_MII; 1290 bus_space_write_1(bst, bsh, offset + MSR, x); 1291 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1292 1293 /* Configure the LED registers. */ 1294 /* XXX This is not good for 10base2. */ 1295 bus_space_write_1(bst, bsh, offset + LED, 1296 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1297 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1298 bus_space_write_1(bst, bsh, offset + LED3, 1299 LED_100MB_LINK << LED3_SHIFT); 1300 1301 /* 1302 * The Linux driver says this: 1303 * We should switch back to page 0 to avoid a bug in revision 0 1304 * where regs with offset below 8 can't be read after an access 1305 * to the MAC registers. 1306 */ 1307 PAGE(sc, 0); 1308 } 1309
Indexes created Tue Sep 30 17:09:57 GMT 2025