if_xi.c revision 1.81
1 /* $NetBSD: if_xi.c,v 1.81 2018/06/22 04:17:42 msaitoh Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.81 2018/06/22 04:17:42 msaitoh Exp $"); 59 60 #include "opt_inet.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/device.h> 65 #include <sys/ioctl.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/socket.h> 69 #include <sys/kernel.h> 70 #include <sys/proc.h> 71 72 #include <net/if.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 #include <net/if_types.h> 76 #include <net/if_ether.h> 77 #include <net/bpf.h> 78 79 #ifdef INET 80 #include <netinet/in.h> 81 #include <netinet/in_systm.h> 82 #include <netinet/in_var.h> 83 #include <netinet/ip.h> 84 #include <netinet/if_inarp.h> 85 #endif 86 87 /* 88 * Maximum number of bytes to read per interrupt. Linux recommends 89 * somewhere between 2000-22000. 90 * XXX This is currently a hard maximum. 91 */ 92 #define MAX_BYTES_INTR 12000 93 94 #include <dev/mii/mii.h> 95 #include <dev/mii/miivar.h> 96 97 #include <dev/pcmcia/pcmciareg.h> 98 #include <dev/pcmcia/pcmciavar.h> 99 #include <dev/pcmcia/pcmciadevs.h> 100 101 #include <dev/pcmcia/if_xireg.h> 102 #include <dev/pcmcia/if_xivar.h> 103 104 #ifdef __GNUC__ 105 #define INLINE inline 106 #else 107 #define INLINE 108 #endif /* __GNUC__ */ 109 110 #define XIDEBUG 111 #define XIDEBUG_VALUE 0 112 113 #ifdef XIDEBUG 114 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 115 116 #define XID_CONFIG 0x01 117 #define XID_MII 0x02 118 #define XID_INTR 0x04 119 #define XID_FIFO 0x08 120 #define XID_MCAST 0x10 121 122 #ifdef XIDEBUG_VALUE 123 int xidebug = XIDEBUG_VALUE; 124 #else 125 int xidebug = 0; 126 #endif 127 #else 128 #define DPRINTF(cat, x) (void)0 129 #endif 130 131 #define STATIC 132 133 STATIC int xi_enable(struct xi_softc *); 134 STATIC void xi_disable(struct xi_softc *); 135 STATIC void xi_cycle_power(struct xi_softc *); 136 STATIC int xi_ether_ioctl(struct ifnet *, u_long cmd, void *); 137 STATIC void xi_full_reset(struct xi_softc *); 138 STATIC void xi_init(struct xi_softc *); 139 STATIC int xi_ioctl(struct ifnet *, u_long, void *); 140 STATIC int xi_mdi_read(device_t, int, int); 141 STATIC void xi_mdi_write(device_t, int, int, int); 142 STATIC int xi_mediachange(struct ifnet *); 143 STATIC u_int16_t xi_get(struct xi_softc *); 144 STATIC void xi_reset(struct xi_softc *); 145 STATIC void xi_set_address(struct xi_softc *); 146 STATIC void xi_start(struct ifnet *); 147 STATIC void xi_statchg(struct ifnet *); 148 STATIC void xi_stop(struct xi_softc *); 149 STATIC void xi_watchdog(struct ifnet *); 150 151 void 152 xi_attach(struct xi_softc *sc, u_int8_t *myea) 153 { 154 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 155 156 #if 0 157 /* 158 * Configuration as advised by DINGO documentation. 159 * Dingo has some extra configuration registers in the CCR space. 160 */ 161 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 162 struct pcmcia_mem_handle pcmh; 163 int ccr_window; 164 bus_size_t ccr_offset; 165 166 /* get access to the DINGO CCR space */ 167 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 168 &pcmh)) { 169 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 170 goto fail; 171 } 172 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 173 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 174 &pcmh, &ccr_offset, &ccr_window)) { 175 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 176 pcmcia_mem_free(psc->sc_pf, &pcmh); 177 goto fail; 178 } 179 180 /* enable the second function - usually modem */ 181 bus_space_write_1(pcmh.memt, pcmh.memh, 182 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 183 bus_space_write_1(pcmh.memt, pcmh.memh, 184 ccr_offset + PCMCIA_CCR_DCOR1, 185 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 186 bus_space_write_1(pcmh.memt, pcmh.memh, 187 ccr_offset + PCMCIA_CCR_DCOR2, 0); 188 bus_space_write_1(pcmh.memt, pcmh.memh, 189 ccr_offset + PCMCIA_CCR_DCOR3, 0); 190 bus_space_write_1(pcmh.memt, pcmh.memh, 191 ccr_offset + PCMCIA_CCR_DCOR4, 0); 192 193 /* We don't need them anymore and can free them (I think). */ 194 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 195 pcmcia_mem_free(psc->sc_pf, &pcmh); 196 } 197 #endif 198 199 /* Reset and initialize the card. */ 200 xi_full_reset(sc); 201 202 printf("%s: MAC address %s\n", device_xname(sc->sc_dev), ether_sprintf(myea)); 203 204 ifp = &sc->sc_ethercom.ec_if; 205 /* Initialize the ifnet structure. */ 206 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 207 ifp->if_softc = sc; 208 ifp->if_start = xi_start; 209 ifp->if_ioctl = xi_ioctl; 210 ifp->if_watchdog = xi_watchdog; 211 ifp->if_flags = 212 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 213 IFQ_SET_READY(&ifp->if_snd); 214 215 /* 802.1q capability */ 216 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 217 218 /* Attach the interface. */ 219 if_attach(ifp); 220 if_deferred_start_init(ifp, NULL); 221 ether_ifattach(ifp, myea); 222 223 /* 224 * Initialize our media structures and probe the MII. 225 */ 226 sc->sc_mii.mii_ifp = ifp; 227 sc->sc_mii.mii_readreg = xi_mdi_read; 228 sc->sc_mii.mii_writereg = xi_mdi_write; 229 sc->sc_mii.mii_statchg = xi_statchg; 230 sc->sc_ethercom.ec_mii = &sc->sc_mii; 231 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 232 ether_mediastatus); 233 DPRINTF(XID_MII | XID_CONFIG, 234 ("xi: bmsr %x\n", xi_mdi_read(sc->sc_dev, 0, 1))); 235 236 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 237 MII_OFFSET_ANY, 0); 238 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 239 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 240 NULL); 241 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 242 243 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 244 RND_TYPE_NET, RND_FLAG_DEFAULT); 245 } 246 247 int 248 xi_detach(device_t self, int flags) 249 { 250 struct xi_softc *sc = device_private(self); 251 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 252 253 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 254 255 xi_disable(sc); 256 257 rnd_detach_source(&sc->sc_rnd_source); 258 259 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 260 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 261 ether_ifdetach(ifp); 262 if_detach(ifp); 263 264 return 0; 265 } 266 267 int 268 xi_intr(void *arg) 269 { 270 struct xi_softc *sc = arg; 271 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 272 u_int8_t esr, rsr, isr, rx_status; 273 u_int16_t tx_status, recvcount = 0, tempint; 274 275 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 276 277 if (sc->sc_enabled == 0 || !device_is_active(sc->sc_dev)) 278 return (0); 279 280 ifp->if_timer = 0; /* turn watchdog timer off */ 281 282 PAGE(sc, 0); 283 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 284 /* Disable interrupt (Linux does it). */ 285 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0); 286 } 287 288 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 289 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0); 290 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 291 292 /* Check to see if card has been ejected. */ 293 if (isr == 0xff) { 294 #ifdef DIAGNOSTIC 295 printf("%s: interrupt for dead card\n", 296 device_xname(sc->sc_dev)); 297 #endif 298 goto end; 299 } 300 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 301 302 PAGE(sc, 0x40); 303 rx_status = 304 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0); 305 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff); 306 tx_status = 307 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0); 308 tx_status |= 309 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8; 310 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0); 311 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0); 312 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 313 tx_status)); 314 315 PAGE(sc, 0); 316 while (esr & FULL_PKT_RCV) { 317 if (!(rsr & RSR_RX_OK)) 318 break; 319 320 /* Compare bytes read this interrupt to hard maximum. */ 321 if (recvcount > MAX_BYTES_INTR) { 322 DPRINTF(XID_INTR, 323 ("xi: too many bytes this interrupt\n")); 324 ifp->if_iqdrops++; 325 /* Drop packet. */ 326 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, 327 DO_SKIP_RX_PKT); 328 } 329 tempint = xi_get(sc); /* XXX doesn't check the error! */ 330 recvcount += tempint; 331 ifp->if_ibytes += tempint; 332 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 333 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 334 } 335 336 /* Packet too long? */ 337 if (rsr & RSR_TOO_LONG) { 338 ifp->if_ierrors++; 339 DPRINTF(XID_INTR, ("xi: packet too long\n")); 340 } 341 342 /* CRC error? */ 343 if (rsr & RSR_CRCERR) { 344 ifp->if_ierrors++; 345 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 346 } 347 348 /* Alignment error? */ 349 if (rsr & RSR_ALIGNERR) { 350 ifp->if_ierrors++; 351 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 352 } 353 354 /* Check for rx overrun. */ 355 if (rx_status & RX_OVERRUN) { 356 ifp->if_ierrors++; 357 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN); 358 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 359 } 360 361 /* Try to start more packets transmitting. */ 362 if_schedule_deferred_start(ifp); 363 364 /* Detected excessive collisions? */ 365 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 366 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 367 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX); 368 ifp->if_oerrors++; 369 } 370 371 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 372 ifp->if_oerrors++; 373 374 /* have handled the interrupt */ 375 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 376 377 end: 378 /* Reenable interrupts. */ 379 PAGE(sc, 0); 380 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT); 381 382 return (1); 383 } 384 385 /* 386 * Pull a packet from the card into an mbuf chain. 387 */ 388 STATIC u_int16_t 389 xi_get(struct xi_softc *sc) 390 { 391 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 392 struct mbuf *top, **mp, *m; 393 u_int16_t pktlen, len, recvcount = 0; 394 u_int8_t *data; 395 396 DPRINTF(XID_CONFIG, ("xi_get()\n")); 397 398 PAGE(sc, 0); 399 pktlen = 400 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK; 401 402 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 403 404 if (pktlen == 0) { 405 /* 406 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 407 * when MPE is set. It is not known why. 408 */ 409 return (0); 410 } 411 412 /* XXX should this be incremented now ? */ 413 recvcount += pktlen; 414 415 MGETHDR(m, M_DONTWAIT, MT_DATA); 416 if (m == NULL) 417 return (recvcount); 418 m_set_rcvif(m, ifp); 419 m->m_pkthdr.len = pktlen; 420 len = MHLEN; 421 top = NULL; 422 mp = ⊤ 423 424 while (pktlen > 0) { 425 if (top) { 426 MGET(m, M_DONTWAIT, MT_DATA); 427 if (m == NULL) { 428 m_freem(top); 429 return (recvcount); 430 } 431 len = MLEN; 432 } 433 if (pktlen >= MINCLSIZE) { 434 MCLGET(m, M_DONTWAIT); 435 if (!(m->m_flags & M_EXT)) { 436 m_freem(m); 437 m_freem(top); 438 return (recvcount); 439 } 440 len = MCLBYTES; 441 } 442 if (top == NULL) { 443 char *newdata = (char *)ALIGN(m->m_data + 444 sizeof(struct ether_header)) - 445 sizeof(struct ether_header); 446 len -= newdata - m->m_data; 447 m->m_data = newdata; 448 } 449 len = min(pktlen, len); 450 data = mtod(m, u_int8_t *); 451 if (len > 1) { 452 len &= ~1; 453 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP, 454 (u_int16_t *)data, len>>1); 455 } else 456 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP); 457 m->m_len = len; 458 pktlen -= len; 459 *mp = m; 460 mp = &m->m_next; 461 } 462 463 /* Skip Rx packet. */ 464 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT); 465 466 if (top == NULL) 467 return recvcount; 468 469 /* Trim the CRC off the end of the packet. */ 470 m_adj(top, -ETHER_CRC_LEN); 471 472 if_percpuq_enqueue(ifp->if_percpuq, top); 473 return (recvcount); 474 } 475 476 /* 477 * Serial management for the MII. 478 * The DELAY's below stem from the fact that the maximum frequency 479 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 480 * go much faster than that. 481 */ 482 483 /* Let the MII serial management be idle for one period. */ 484 static INLINE void xi_mdi_idle(struct xi_softc *); 485 static INLINE void 486 xi_mdi_idle(struct xi_softc *sc) 487 { 488 bus_space_tag_t bst = sc->sc_bst; 489 bus_space_handle_t bsh = sc->sc_bsh; 490 491 /* Drive MDC low... */ 492 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 493 DELAY(1); 494 495 /* and high again. */ 496 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 497 DELAY(1); 498 } 499 500 /* Pulse out one bit of data. */ 501 static INLINE void xi_mdi_pulse(struct xi_softc *, int); 502 static INLINE void 503 xi_mdi_pulse(struct xi_softc *sc, int data) 504 { 505 bus_space_tag_t bst = sc->sc_bst; 506 bus_space_handle_t bsh = sc->sc_bsh; 507 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 508 509 /* First latch the data bit MDIO with clock bit MDC low...*/ 510 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW); 511 DELAY(1); 512 513 /* then raise the clock again, preserving the data bit. */ 514 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH); 515 DELAY(1); 516 } 517 518 /* Probe one bit of data. */ 519 static INLINE int xi_mdi_probe(struct xi_softc *sc); 520 static INLINE int 521 xi_mdi_probe(struct xi_softc *sc) 522 { 523 bus_space_tag_t bst = sc->sc_bst; 524 bus_space_handle_t bsh = sc->sc_bsh; 525 u_int8_t x; 526 527 /* Pull clock bit MDCK low... */ 528 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 529 DELAY(1); 530 531 /* Read data and drive clock high again. */ 532 x = bus_space_read_1(bst, bsh, GP2); 533 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 534 DELAY(1); 535 536 return (x & MDIO); 537 } 538 539 /* Pulse out a sequence of data bits. */ 540 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, u_int32_t, int); 541 static INLINE void 542 xi_mdi_pulse_bits(struct xi_softc *sc, u_int32_t data, int len) 543 { 544 u_int32_t mask; 545 546 for (mask = 1 << (len - 1); mask; mask >>= 1) 547 xi_mdi_pulse(sc, data & mask); 548 } 549 550 /* Read a PHY register. */ 551 STATIC int 552 xi_mdi_read(device_t self, int phy, int reg) 553 { 554 struct xi_softc *sc = device_private(self); 555 int i; 556 u_int32_t mask; 557 u_int32_t data = 0; 558 559 PAGE(sc, 2); 560 for (i = 0; i < 32; i++) /* Synchronize. */ 561 xi_mdi_pulse(sc, 1); 562 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 563 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 564 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 565 xi_mdi_idle(sc); /* Turn around. */ 566 xi_mdi_probe(sc); /* Drop initial zero bit. */ 567 568 for (mask = 1 << 15; mask; mask >>= 1) { 569 if (xi_mdi_probe(sc)) 570 data |= mask; 571 } 572 xi_mdi_idle(sc); 573 574 DPRINTF(XID_MII, 575 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 576 577 return (data); 578 } 579 580 /* Write a PHY register. */ 581 STATIC void 582 xi_mdi_write(device_t self, int phy, int reg, int value) 583 { 584 struct xi_softc *sc = device_private(self); 585 int i; 586 587 PAGE(sc, 2); 588 for (i = 0; i < 32; i++) /* Synchronize. */ 589 xi_mdi_pulse(sc, 1); 590 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 591 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 592 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 593 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 594 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 595 xi_mdi_idle(sc); /* Idle away. */ 596 597 DPRINTF(XID_MII, 598 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 599 } 600 601 STATIC void 602 xi_statchg(struct ifnet *ifp) 603 { 604 /* XXX Update ifp->if_baudrate */ 605 } 606 607 /* 608 * Change media according to request. 609 */ 610 STATIC int 611 xi_mediachange(struct ifnet *ifp) 612 { 613 int s; 614 615 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 616 617 if (ifp->if_flags & IFF_UP) { 618 s = splnet(); 619 xi_init(ifp->if_softc); 620 splx(s); 621 } 622 return (0); 623 } 624 625 STATIC void 626 xi_reset(struct xi_softc *sc) 627 { 628 int s; 629 630 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 631 632 s = splnet(); 633 xi_stop(sc); 634 xi_init(sc); 635 splx(s); 636 } 637 638 STATIC void 639 xi_watchdog(struct ifnet *ifp) 640 { 641 struct xi_softc *sc = ifp->if_softc; 642 643 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 644 ++ifp->if_oerrors; 645 646 xi_reset(sc); 647 } 648 649 STATIC void 650 xi_stop(register struct xi_softc *sc) 651 { 652 bus_space_tag_t bst = sc->sc_bst; 653 bus_space_handle_t bsh = sc->sc_bsh; 654 655 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 656 657 PAGE(sc, 0x40); 658 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX); 659 660 /* Disable interrupts. */ 661 PAGE(sc, 0); 662 bus_space_write_1(bst, bsh, CR, 0); 663 664 PAGE(sc, 1); 665 bus_space_write_1(bst, bsh, IMR0, 0); 666 667 /* Cancel watchdog timer. */ 668 sc->sc_ethercom.ec_if.if_timer = 0; 669 } 670 671 STATIC int 672 xi_enable(struct xi_softc *sc) 673 { 674 int error; 675 676 if (!sc->sc_enabled) { 677 error = (*sc->sc_enable)(sc); 678 if (error) 679 return (error); 680 sc->sc_enabled = 1; 681 xi_full_reset(sc); 682 } 683 return (0); 684 } 685 686 STATIC void 687 xi_disable(struct xi_softc *sc) 688 { 689 690 if (sc->sc_enabled) { 691 sc->sc_enabled = 0; 692 (*sc->sc_disable)(sc); 693 } 694 } 695 696 STATIC void 697 xi_init(struct xi_softc *sc) 698 { 699 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 700 bus_space_tag_t bst = sc->sc_bst; 701 bus_space_handle_t bsh = sc->sc_bsh; 702 703 DPRINTF(XID_CONFIG, ("xi_init()\n")); 704 705 /* Setup the ethernet interrupt mask. */ 706 PAGE(sc, 1); 707 bus_space_write_1(bst, bsh, IMR0, 708 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 709 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 710 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 711 /* XXX What is this? Not for Dingo at least. */ 712 /* Unmask TX underrun detection */ 713 bus_space_write_1(bst, bsh, IMR1, 1); 714 } 715 716 /* Enable interrupts. */ 717 PAGE(sc, 0); 718 bus_space_write_1(bst, bsh, CR, ENABLE_INT); 719 720 xi_set_address(sc); 721 722 PAGE(sc, 0x40); 723 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE); 724 725 PAGE(sc, 0); 726 727 /* Set current media. */ 728 mii_mediachg(&sc->sc_mii); 729 730 ifp->if_flags |= IFF_RUNNING; 731 ifp->if_flags &= ~IFF_OACTIVE; 732 733 xi_start(ifp); 734 } 735 736 /* 737 * Start outputting on the interface. 738 * Always called as splnet(). 739 */ 740 STATIC void 741 xi_start(struct ifnet *ifp) 742 { 743 struct xi_softc *sc = ifp->if_softc; 744 bus_space_tag_t bst = sc->sc_bst; 745 bus_space_handle_t bsh = sc->sc_bsh; 746 unsigned int s, len, pad = 0; 747 struct mbuf *m0, *m; 748 u_int16_t space; 749 750 DPRINTF(XID_CONFIG, ("xi_start()\n")); 751 752 /* Don't transmit if interface is busy or not running. */ 753 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 754 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 755 return; 756 } 757 758 /* Peek at the next packet. */ 759 IFQ_POLL(&ifp->if_snd, m0); 760 if (m0 == 0) 761 return; 762 763 /* We need to use m->m_pkthdr.len, so require the header. */ 764 if (!(m0->m_flags & M_PKTHDR)) 765 panic("xi_start: no header mbuf"); 766 767 len = m0->m_pkthdr.len; 768 769 #if 1 770 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 771 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 772 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 773 #else 774 pad = 0; 775 #endif 776 777 PAGE(sc, 0); 778 779 bus_space_write_2(bst, bsh, TRS, (u_int16_t)len + pad + 2); 780 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff; 781 if (len + pad + 2 > space) { 782 DPRINTF(XID_FIFO, 783 ("xi: not enough space in output FIFO (%d > %d)\n", 784 len + pad + 2, space)); 785 return; 786 } 787 788 IFQ_DEQUEUE(&ifp->if_snd, m0); 789 790 bpf_mtap(ifp, m0); 791 792 /* 793 * Do the output at splhigh() so that an interrupt from another device 794 * won't cause a FIFO underrun. 795 */ 796 s = splhigh(); 797 798 bus_space_write_2(bst, bsh, EDP, (u_int16_t)len + pad); 799 for (m = m0; m; ) { 800 if (m->m_len > 1) 801 bus_space_write_multi_2(bst, bsh, EDP, 802 mtod(m, u_int16_t *), m->m_len>>1); 803 if (m->m_len & 1) { 804 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 805 bus_space_write_1(bst, bsh, EDP, 806 *(mtod(m, u_int8_t *) + m->m_len - 1)); 807 } 808 m = m0 = m_free(m); 809 } 810 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 811 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 812 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT); 813 else { 814 for (; pad > 1; pad -= 2) 815 bus_space_write_2(bst, bsh, EDP, 0); 816 if (pad == 1) 817 bus_space_write_1(bst, bsh, EDP, 0); 818 } 819 820 splx(s); 821 822 ifp->if_timer = 5; 823 ++ifp->if_opackets; 824 } 825 826 STATIC int 827 xi_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 828 { 829 struct ifaddr *ifa = (struct ifaddr *)data; 830 struct xi_softc *sc = ifp->if_softc; 831 int error; 832 833 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 834 835 switch (cmd) { 836 case SIOCINITIFADDR: 837 if ((error = xi_enable(sc)) != 0) 838 break; 839 840 ifp->if_flags |= IFF_UP; 841 842 xi_init(sc); 843 switch (ifa->ifa_addr->sa_family) { 844 #ifdef INET 845 case AF_INET: 846 arp_ifinit(ifp, ifa); 847 break; 848 #endif /* INET */ 849 850 851 default: 852 break; 853 } 854 break; 855 856 default: 857 return (EINVAL); 858 } 859 860 return (0); 861 } 862 863 STATIC int 864 xi_ioctl(struct ifnet *ifp, u_long cmd, void *data) 865 { 866 struct xi_softc *sc = ifp->if_softc; 867 int s, error = 0; 868 869 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 870 871 s = splnet(); 872 873 switch (cmd) { 874 case SIOCINITIFADDR: 875 error = xi_ether_ioctl(ifp, cmd, data); 876 break; 877 878 case SIOCSIFFLAGS: 879 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 880 break; 881 /* XXX re-use ether_ioctl() */ 882 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 883 case IFF_RUNNING: 884 /* 885 * If interface is marked down and it is running, 886 * stop it. 887 */ 888 xi_stop(sc); 889 ifp->if_flags &= ~IFF_RUNNING; 890 xi_disable(sc); 891 break; 892 case IFF_UP: 893 /* 894 * If interface is marked up and it is stopped, 895 * start it. 896 */ 897 if ((error = xi_enable(sc)) != 0) 898 break; 899 xi_init(sc); 900 break; 901 case IFF_UP|IFF_RUNNING: 902 /* 903 * Reset the interface to pick up changes in any 904 * other flags that affect hardware registers. 905 */ 906 xi_set_address(sc); 907 break; 908 case 0: 909 break; 910 } 911 break; 912 913 case SIOCADDMULTI: 914 case SIOCDELMULTI: 915 if (sc->sc_enabled == 0) { 916 error = EIO; 917 break; 918 } 919 /*FALLTHROUGH*/ 920 case SIOCSIFMEDIA: 921 case SIOCGIFMEDIA: 922 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 923 /* 924 * Multicast list has changed; set the hardware 925 * filter accordingly. 926 */ 927 if (ifp->if_flags & IFF_RUNNING) 928 xi_set_address(sc); 929 error = 0; 930 } 931 break; 932 933 default: 934 error = ether_ioctl(ifp, cmd, data); 935 break; 936 } 937 938 splx(s); 939 return (error); 940 } 941 942 STATIC void 943 xi_set_address(struct xi_softc *sc) 944 { 945 bus_space_tag_t bst = sc->sc_bst; 946 bus_space_handle_t bsh = sc->sc_bsh; 947 struct ethercom *ether = &sc->sc_ethercom; 948 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 949 struct ether_multistep step; 950 struct ether_multi *enm; 951 int page, num; 952 int i; 953 u_int8_t x; 954 const u_int8_t *enaddr; 955 u_int8_t indaddr[64]; 956 957 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 958 959 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 960 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 961 for (i = 0; i < 6; i++) 962 indaddr[i] = enaddr[5 - i]; 963 else 964 for (i = 0; i < 6; i++) 965 indaddr[i] = enaddr[i]; 966 num = 1; 967 968 if (ether->ec_multicnt > 9) { 969 ifp->if_flags |= IFF_ALLMULTI; 970 goto done; 971 } 972 973 ETHER_FIRST_MULTI(step, ether, enm); 974 for (; enm; num++) { 975 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 976 sizeof(enm->enm_addrlo)) != 0) { 977 /* 978 * The multicast address is really a range; 979 * it's easier just to accept all multicasts. 980 * XXX should we be setting IFF_ALLMULTI here? 981 */ 982 ifp->if_flags |= IFF_ALLMULTI; 983 goto done; 984 } 985 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 986 for (i = 0; i < 6; i++) 987 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 988 else 989 for (i = 0; i < 6; i++) 990 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 991 ETHER_NEXT_MULTI(step, enm); 992 } 993 ifp->if_flags &= ~IFF_ALLMULTI; 994 995 done: 996 if (num < 10) 997 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 998 999 for (page = 0; page < 8; page++) { 1000 #ifdef XIDEBUG 1001 if (xidebug & XID_MCAST) { 1002 printf("page %d before:", page); 1003 for (i = 0; i < 8; i++) 1004 printf(" %02x", indaddr[page * 8 + i]); 1005 printf("\n"); 1006 } 1007 #endif 1008 1009 PAGE(sc, 0x50 + page); 1010 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8], 1011 page == 7 ? 4 : 8); 1012 /* 1013 * XXX 1014 * Without this delay, the address registers on my CE2 get 1015 * trashed the first and I have to cycle it. I have no idea 1016 * why. - mycroft, 2004/08/09 1017 */ 1018 DELAY(50); 1019 1020 #ifdef XIDEBUG 1021 if (xidebug & XID_MCAST) { 1022 bus_space_read_region_1(bst, bsh, IA, 1023 &indaddr[page * 8], page == 7 ? 4 : 8); 1024 printf("page %d after: ", page); 1025 for (i = 0; i < 8; i++) 1026 printf(" %02x", indaddr[page * 8 + i]); 1027 printf("\n"); 1028 } 1029 #endif 1030 } 1031 1032 PAGE(sc, 0x42); 1033 x = SWC1_IND_ADDR; 1034 if (ifp->if_flags & IFF_PROMISC) 1035 x |= SWC1_PROMISC; 1036 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) 1037 x |= SWC1_MCAST_PROM; 1038 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1039 x |= SWC1_AUTO_MEDIA; 1040 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x); 1041 } 1042 1043 STATIC void 1044 xi_cycle_power(struct xi_softc *sc) 1045 { 1046 bus_space_tag_t bst = sc->sc_bst; 1047 bus_space_handle_t bsh = sc->sc_bsh; 1048 1049 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1050 1051 PAGE(sc, 4); 1052 DELAY(1); 1053 bus_space_write_1(bst, bsh, GP1, 0); 1054 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1055 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1056 bus_space_write_1(bst, bsh, GP1, POWER_UP); 1057 else 1058 /* XXX What is bit 2 (aka AIC)? */ 1059 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4); 1060 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1061 } 1062 1063 STATIC void 1064 xi_full_reset(struct xi_softc *sc) 1065 { 1066 bus_space_tag_t bst = sc->sc_bst; 1067 bus_space_handle_t bsh = sc->sc_bsh; 1068 u_int8_t x; 1069 1070 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1071 1072 /* Do an as extensive reset as possible on all functions. */ 1073 xi_cycle_power(sc); 1074 bus_space_write_1(bst, bsh, CR, SOFT_RESET); 1075 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1076 bus_space_write_1(bst, bsh, CR, 0); 1077 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1078 PAGE(sc, 4); 1079 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1080 /* 1081 * Drive GP1 low to power up ML6692 and GP2 high to power up 1082 * the 10MHz chip. XXX What chip is that? The phy? 1083 */ 1084 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR); 1085 } 1086 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1087 1088 /* Get revision information. XXX Symbolic constants. */ 1089 sc->sc_rev = bus_space_read_1(bst, bsh, BV) & 1090 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1091 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1092 1093 /* Media selection. XXX Maybe manual overriding too? */ 1094 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1095 /* 1096 * XXX I have no idea what this really does, it is from the 1097 * Linux driver. 1098 */ 1099 bus_space_write_1(bst, bsh, GP0, GP1_OUT); 1100 } 1101 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1102 1103 /* 1104 * Disable source insertion. 1105 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1106 */ 1107 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1108 PAGE(sc, 0x42); 1109 bus_space_write_1(bst, bsh, SWC0, 0x20); 1110 } 1111 1112 /* Set the local memory dividing line. */ 1113 if (sc->sc_rev != 1) { 1114 PAGE(sc, 2); 1115 /* XXX Symbolic constant preferrable. */ 1116 bus_space_write_2(bst, bsh, RBS0, 0x2000); 1117 } 1118 1119 /* 1120 * Apparently the receive byte pointer can be bad after a reset, so 1121 * we hardwire it correctly. 1122 */ 1123 PAGE(sc, 0); 1124 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET); 1125 1126 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1127 PAGE(sc, 0x40); 1128 bus_space_write_1(bst, bsh, RX0MSK, 1129 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1130 bus_space_write_1(bst, bsh, TX0MSK, 1131 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1132 SQE | TX_ABORT | TX_OK); 1133 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1134 /* XXX From Linux, dunno what 0xb0 means. */ 1135 bus_space_write_1(bst, bsh, TX1MSK, 0xb0); 1136 bus_space_write_1(bst, bsh, RXST0, 0); 1137 bus_space_write_1(bst, bsh, TXST0, 0); 1138 bus_space_write_1(bst, bsh, TXST1, 0); 1139 1140 PAGE(sc, 2); 1141 1142 /* Enable MII function if available. */ 1143 x = 0; 1144 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1145 x |= SELECT_MII; 1146 bus_space_write_1(bst, bsh, MSR, x); 1147 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1148 1149 /* Configure the LED registers. */ 1150 /* XXX This is not good for 10base2. */ 1151 bus_space_write_1(bst, bsh, LED, 1152 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1153 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1154 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT); 1155 1156 /* 1157 * The Linux driver says this: 1158 * We should switch back to page 0 to avoid a bug in revision 0 1159 * where regs with offset below 8 can't be read after an access 1160 * to the MAC registers. 1161 */ 1162 PAGE(sc, 0); 1163 } 1164
Indexes created Tue Sep 30 17:09:57 GMT 2025