if_xi.c revision 1.85
1 /* $NetBSD: if_xi.c,v 1.85 2019/01/22 03:42:27 msaitoh Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.85 2019/01/22 03:42:27 msaitoh Exp $"); 59 60 #include "opt_inet.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/device.h> 65 #include <sys/ioctl.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/socket.h> 69 #include <sys/kernel.h> 70 #include <sys/proc.h> 71 72 #include <net/if.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 #include <net/if_types.h> 76 #include <net/if_ether.h> 77 #include <net/bpf.h> 78 79 #ifdef INET 80 #include <netinet/in.h> 81 #include <netinet/in_systm.h> 82 #include <netinet/in_var.h> 83 #include <netinet/ip.h> 84 #include <netinet/if_inarp.h> 85 #endif 86 87 /* 88 * Maximum number of bytes to read per interrupt. Linux recommends 89 * somewhere between 2000-22000. 90 * XXX This is currently a hard maximum. 91 */ 92 #define MAX_BYTES_INTR 12000 93 94 #include <dev/mii/mii.h> 95 #include <dev/mii/miivar.h> 96 97 #include <dev/pcmcia/pcmciareg.h> 98 #include <dev/pcmcia/pcmciavar.h> 99 #include <dev/pcmcia/pcmciadevs.h> 100 101 #include <dev/pcmcia/if_xireg.h> 102 #include <dev/pcmcia/if_xivar.h> 103 104 #ifdef __GNUC__ 105 #define INLINE inline 106 #else 107 #define INLINE 108 #endif /* __GNUC__ */ 109 110 #define XIDEBUG 111 #define XIDEBUG_VALUE 0 112 113 #ifdef XIDEBUG 114 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 115 116 #define XID_CONFIG 0x01 117 #define XID_MII 0x02 118 #define XID_INTR 0x04 119 #define XID_FIFO 0x08 120 #define XID_MCAST 0x10 121 122 #ifdef XIDEBUG_VALUE 123 int xidebug = XIDEBUG_VALUE; 124 #else 125 int xidebug = 0; 126 #endif 127 #else 128 #define DPRINTF(cat, x) (void)0 129 #endif 130 131 #define STATIC 132 133 STATIC int xi_enable(struct xi_softc *); 134 STATIC void xi_disable(struct xi_softc *); 135 STATIC void xi_cycle_power(struct xi_softc *); 136 STATIC int xi_ether_ioctl(struct ifnet *, u_long cmd, void *); 137 STATIC void xi_full_reset(struct xi_softc *); 138 STATIC void xi_init(struct xi_softc *); 139 STATIC int xi_ioctl(struct ifnet *, u_long, void *); 140 STATIC int xi_mdi_read(device_t, int, int, uint16_t *); 141 STATIC int xi_mdi_write(device_t, int, int, uint16_t); 142 STATIC int xi_mediachange(struct ifnet *); 143 STATIC uint16_t xi_get(struct xi_softc *); 144 STATIC void xi_reset(struct xi_softc *); 145 STATIC void xi_set_address(struct xi_softc *); 146 STATIC void xi_start(struct ifnet *); 147 STATIC void xi_statchg(struct ifnet *); 148 STATIC void xi_stop(struct xi_softc *); 149 STATIC void xi_watchdog(struct ifnet *); 150 151 void 152 xi_attach(struct xi_softc *sc, uint8_t *myea) 153 { 154 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 155 #ifdef XIDEBUG 156 uint16_t bmsr; 157 #endif 158 #if 0 159 /* 160 * Configuration as advised by DINGO documentation. 161 * Dingo has some extra configuration registers in the CCR space. 162 */ 163 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 164 struct pcmcia_mem_handle pcmh; 165 int ccr_window; 166 bus_size_t ccr_offset; 167 168 /* get access to the DINGO CCR space */ 169 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 170 &pcmh)) { 171 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 172 goto fail; 173 } 174 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 175 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 176 &pcmh, &ccr_offset, &ccr_window)) { 177 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 178 pcmcia_mem_free(psc->sc_pf, &pcmh); 179 goto fail; 180 } 181 182 /* enable the second function - usually modem */ 183 bus_space_write_1(pcmh.memt, pcmh.memh, 184 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 185 bus_space_write_1(pcmh.memt, pcmh.memh, 186 ccr_offset + PCMCIA_CCR_DCOR1, 187 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 188 bus_space_write_1(pcmh.memt, pcmh.memh, 189 ccr_offset + PCMCIA_CCR_DCOR2, 0); 190 bus_space_write_1(pcmh.memt, pcmh.memh, 191 ccr_offset + PCMCIA_CCR_DCOR3, 0); 192 bus_space_write_1(pcmh.memt, pcmh.memh, 193 ccr_offset + PCMCIA_CCR_DCOR4, 0); 194 195 /* We don't need them anymore and can free them (I think). */ 196 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 197 pcmcia_mem_free(psc->sc_pf, &pcmh); 198 } 199 #endif 200 201 /* Reset and initialize the card. */ 202 xi_full_reset(sc); 203 204 printf("%s: MAC address %s\n", device_xname(sc->sc_dev), ether_sprintf(myea)); 205 206 ifp = &sc->sc_ethercom.ec_if; 207 /* Initialize the ifnet structure. */ 208 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 209 ifp->if_softc = sc; 210 ifp->if_start = xi_start; 211 ifp->if_ioctl = xi_ioctl; 212 ifp->if_watchdog = xi_watchdog; 213 ifp->if_flags = 214 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 215 IFQ_SET_READY(&ifp->if_snd); 216 217 /* 802.1q capability */ 218 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 219 220 /* Attach the interface. */ 221 if_attach(ifp); 222 if_deferred_start_init(ifp, NULL); 223 ether_ifattach(ifp, myea); 224 225 /* 226 * Initialize our media structures and probe the MII. 227 */ 228 sc->sc_mii.mii_ifp = ifp; 229 sc->sc_mii.mii_readreg = xi_mdi_read; 230 sc->sc_mii.mii_writereg = xi_mdi_write; 231 sc->sc_mii.mii_statchg = xi_statchg; 232 sc->sc_ethercom.ec_mii = &sc->sc_mii; 233 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 234 ether_mediastatus); 235 #ifdef XIDEBUG 236 xi_mdi_read(sc->sc_dev, 0, 1, &bmsr); 237 DPRINTF(XID_MII | XID_CONFIG, ("xi: bmsr %x\n", bmsr)); 238 #endif 239 240 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 241 MII_OFFSET_ANY, 0); 242 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 243 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 244 NULL); 245 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 246 247 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 248 RND_TYPE_NET, RND_FLAG_DEFAULT); 249 } 250 251 int 252 xi_detach(device_t self, int flags) 253 { 254 struct xi_softc *sc = device_private(self); 255 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 256 257 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 258 259 xi_disable(sc); 260 261 rnd_detach_source(&sc->sc_rnd_source); 262 263 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 264 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 265 ether_ifdetach(ifp); 266 if_detach(ifp); 267 268 return 0; 269 } 270 271 int 272 xi_intr(void *arg) 273 { 274 struct xi_softc *sc = arg; 275 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 276 uint8_t esr, rsr, isr, rx_status; 277 uint16_t tx_status, recvcount = 0, tempint; 278 279 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 280 281 if (sc->sc_enabled == 0 || !device_is_active(sc->sc_dev)) 282 return (0); 283 284 ifp->if_timer = 0; /* turn watchdog timer off */ 285 286 PAGE(sc, 0); 287 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 288 /* Disable interrupt (Linux does it). */ 289 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0); 290 } 291 292 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 293 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0); 294 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 295 296 /* Check to see if card has been ejected. */ 297 if (isr == 0xff) { 298 #ifdef DIAGNOSTIC 299 printf("%s: interrupt for dead card\n", 300 device_xname(sc->sc_dev)); 301 #endif 302 goto end; 303 } 304 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 305 306 PAGE(sc, 0x40); 307 rx_status = 308 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0); 309 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff); 310 tx_status = 311 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0); 312 tx_status |= 313 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8; 314 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0); 315 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0); 316 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 317 tx_status)); 318 319 PAGE(sc, 0); 320 while (esr & FULL_PKT_RCV) { 321 if (!(rsr & RSR_RX_OK)) 322 break; 323 324 /* Compare bytes read this interrupt to hard maximum. */ 325 if (recvcount > MAX_BYTES_INTR) { 326 DPRINTF(XID_INTR, 327 ("xi: too many bytes this interrupt\n")); 328 ifp->if_iqdrops++; 329 /* Drop packet. */ 330 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, 331 DO_SKIP_RX_PKT); 332 } 333 tempint = xi_get(sc); /* XXX doesn't check the error! */ 334 recvcount += tempint; 335 ifp->if_ibytes += tempint; 336 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 337 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 338 } 339 340 /* Packet too long? */ 341 if (rsr & RSR_TOO_LONG) { 342 ifp->if_ierrors++; 343 DPRINTF(XID_INTR, ("xi: packet too long\n")); 344 } 345 346 /* CRC error? */ 347 if (rsr & RSR_CRCERR) { 348 ifp->if_ierrors++; 349 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 350 } 351 352 /* Alignment error? */ 353 if (rsr & RSR_ALIGNERR) { 354 ifp->if_ierrors++; 355 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 356 } 357 358 /* Check for rx overrun. */ 359 if (rx_status & RX_OVERRUN) { 360 ifp->if_ierrors++; 361 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN); 362 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 363 } 364 365 /* Try to start more packets transmitting. */ 366 if_schedule_deferred_start(ifp); 367 368 /* Detected excessive collisions? */ 369 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 370 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 371 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX); 372 ifp->if_oerrors++; 373 } 374 375 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 376 ifp->if_oerrors++; 377 378 /* have handled the interrupt */ 379 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 380 381 end: 382 /* Reenable interrupts. */ 383 PAGE(sc, 0); 384 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT); 385 386 return (1); 387 } 388 389 /* 390 * Pull a packet from the card into an mbuf chain. 391 */ 392 STATIC uint16_t 393 xi_get(struct xi_softc *sc) 394 { 395 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 396 struct mbuf *top, **mp, *m; 397 uint16_t pktlen, len, recvcount = 0; 398 uint8_t *data; 399 400 DPRINTF(XID_CONFIG, ("xi_get()\n")); 401 402 PAGE(sc, 0); 403 pktlen = 404 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK; 405 406 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 407 408 if (pktlen == 0) { 409 /* 410 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 411 * when MPE is set. It is not known why. 412 */ 413 return (0); 414 } 415 416 /* XXX should this be incremented now ? */ 417 recvcount += pktlen; 418 419 MGETHDR(m, M_DONTWAIT, MT_DATA); 420 if (m == NULL) 421 return (recvcount); 422 m_set_rcvif(m, ifp); 423 m->m_pkthdr.len = pktlen; 424 len = MHLEN; 425 top = NULL; 426 mp = ⊤ 427 428 while (pktlen > 0) { 429 if (top) { 430 MGET(m, M_DONTWAIT, MT_DATA); 431 if (m == NULL) { 432 m_freem(top); 433 return (recvcount); 434 } 435 len = MLEN; 436 } 437 if (pktlen >= MINCLSIZE) { 438 MCLGET(m, M_DONTWAIT); 439 if (!(m->m_flags & M_EXT)) { 440 m_freem(m); 441 m_freem(top); 442 return (recvcount); 443 } 444 len = MCLBYTES; 445 } 446 if (top == NULL) { 447 char *newdata = (char *)ALIGN(m->m_data + 448 sizeof(struct ether_header)) - 449 sizeof(struct ether_header); 450 len -= newdata - m->m_data; 451 m->m_data = newdata; 452 } 453 len = uimin(pktlen, len); 454 data = mtod(m, uint8_t *); 455 if (len > 1) { 456 len &= ~1; 457 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP, 458 (uint16_t *)data, len>>1); 459 } else 460 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP); 461 m->m_len = len; 462 pktlen -= len; 463 *mp = m; 464 mp = &m->m_next; 465 } 466 467 /* Skip Rx packet. */ 468 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT); 469 470 if (top == NULL) 471 return recvcount; 472 473 /* Trim the CRC off the end of the packet. */ 474 m_adj(top, -ETHER_CRC_LEN); 475 476 if_percpuq_enqueue(ifp->if_percpuq, top); 477 return (recvcount); 478 } 479 480 /* 481 * Serial management for the MII. 482 * The DELAY's below stem from the fact that the maximum frequency 483 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 484 * go much faster than that. 485 */ 486 487 /* Let the MII serial management be idle for one period. */ 488 static INLINE void xi_mdi_idle(struct xi_softc *); 489 static INLINE void 490 xi_mdi_idle(struct xi_softc *sc) 491 { 492 bus_space_tag_t bst = sc->sc_bst; 493 bus_space_handle_t bsh = sc->sc_bsh; 494 495 /* Drive MDC low... */ 496 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 497 DELAY(1); 498 499 /* and high again. */ 500 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 501 DELAY(1); 502 } 503 504 /* Pulse out one bit of data. */ 505 static INLINE void xi_mdi_pulse(struct xi_softc *, int); 506 static INLINE void 507 xi_mdi_pulse(struct xi_softc *sc, int data) 508 { 509 bus_space_tag_t bst = sc->sc_bst; 510 bus_space_handle_t bsh = sc->sc_bsh; 511 uint8_t bit = data ? MDIO_HIGH : MDIO_LOW; 512 513 /* First latch the data bit MDIO with clock bit MDC low...*/ 514 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW); 515 DELAY(1); 516 517 /* then raise the clock again, preserving the data bit. */ 518 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH); 519 DELAY(1); 520 } 521 522 /* Probe one bit of data. */ 523 static INLINE int xi_mdi_probe(struct xi_softc *sc); 524 static INLINE int 525 xi_mdi_probe(struct xi_softc *sc) 526 { 527 bus_space_tag_t bst = sc->sc_bst; 528 bus_space_handle_t bsh = sc->sc_bsh; 529 uint8_t x; 530 531 /* Pull clock bit MDCK low... */ 532 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 533 DELAY(1); 534 535 /* Read data and drive clock high again. */ 536 x = bus_space_read_1(bst, bsh, GP2); 537 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 538 DELAY(1); 539 540 return (x & MDIO); 541 } 542 543 /* Pulse out a sequence of data bits. */ 544 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, uint32_t, int); 545 static INLINE void 546 xi_mdi_pulse_bits(struct xi_softc *sc, uint32_t data, int len) 547 { 548 uint32_t mask; 549 550 for (mask = 1 << (len - 1); mask; mask >>= 1) 551 xi_mdi_pulse(sc, data & mask); 552 } 553 554 /* Read a PHY register. */ 555 STATIC int 556 xi_mdi_read(device_t self, int phy, int reg, uint16_t *val) 557 { 558 struct xi_softc *sc = device_private(self); 559 int i; 560 uint32_t mask; 561 uint16_t data = 0; 562 563 PAGE(sc, 2); 564 for (i = 0; i < 32; i++) /* Synchronize. */ 565 xi_mdi_pulse(sc, 1); 566 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 567 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 568 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 569 xi_mdi_idle(sc); /* Turn around. */ 570 xi_mdi_probe(sc); /* Drop initial zero bit. */ 571 572 for (mask = 1 << 15; mask; mask >>= 1) { 573 if (xi_mdi_probe(sc)) 574 data |= mask; 575 } 576 xi_mdi_idle(sc); 577 578 DPRINTF(XID_MII, 579 ("xi_mdi_read: phy %d reg %d -> %04hx\n", phy, reg, data)); 580 581 *val = data; 582 return 0; 583 } 584 585 /* Write a PHY register. */ 586 STATIC int 587 xi_mdi_write(device_t self, int phy, int reg, uint16_t val) 588 { 589 struct xi_softc *sc = device_private(self); 590 int i; 591 592 PAGE(sc, 2); 593 for (i = 0; i < 32; i++) /* Synchronize. */ 594 xi_mdi_pulse(sc, 1); 595 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 596 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 597 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 598 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 599 xi_mdi_pulse_bits(sc, val, 16); /* Write the data */ 600 xi_mdi_idle(sc); /* Idle away. */ 601 602 DPRINTF(XID_MII, 603 ("xi_mdi_write: phy %d reg %d val %04hx\n", phy, reg, val)); 604 605 return 0; 606 } 607 608 STATIC void 609 xi_statchg(struct ifnet *ifp) 610 { 611 /* XXX Update ifp->if_baudrate */ 612 } 613 614 /* 615 * Change media according to request. 616 */ 617 STATIC int 618 xi_mediachange(struct ifnet *ifp) 619 { 620 int s; 621 622 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 623 624 if (ifp->if_flags & IFF_UP) { 625 s = splnet(); 626 xi_init(ifp->if_softc); 627 splx(s); 628 } 629 return (0); 630 } 631 632 STATIC void 633 xi_reset(struct xi_softc *sc) 634 { 635 int s; 636 637 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 638 639 s = splnet(); 640 xi_stop(sc); 641 xi_init(sc); 642 splx(s); 643 } 644 645 STATIC void 646 xi_watchdog(struct ifnet *ifp) 647 { 648 struct xi_softc *sc = ifp->if_softc; 649 650 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 651 ++ifp->if_oerrors; 652 653 xi_reset(sc); 654 } 655 656 STATIC void 657 xi_stop(register struct xi_softc *sc) 658 { 659 bus_space_tag_t bst = sc->sc_bst; 660 bus_space_handle_t bsh = sc->sc_bsh; 661 662 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 663 664 PAGE(sc, 0x40); 665 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX); 666 667 /* Disable interrupts. */ 668 PAGE(sc, 0); 669 bus_space_write_1(bst, bsh, CR, 0); 670 671 PAGE(sc, 1); 672 bus_space_write_1(bst, bsh, IMR0, 0); 673 674 /* Cancel watchdog timer. */ 675 sc->sc_ethercom.ec_if.if_timer = 0; 676 } 677 678 STATIC int 679 xi_enable(struct xi_softc *sc) 680 { 681 int error; 682 683 if (!sc->sc_enabled) { 684 error = (*sc->sc_enable)(sc); 685 if (error) 686 return (error); 687 sc->sc_enabled = 1; 688 xi_full_reset(sc); 689 } 690 return (0); 691 } 692 693 STATIC void 694 xi_disable(struct xi_softc *sc) 695 { 696 697 if (sc->sc_enabled) { 698 sc->sc_enabled = 0; 699 (*sc->sc_disable)(sc); 700 } 701 } 702 703 STATIC void 704 xi_init(struct xi_softc *sc) 705 { 706 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 707 bus_space_tag_t bst = sc->sc_bst; 708 bus_space_handle_t bsh = sc->sc_bsh; 709 710 DPRINTF(XID_CONFIG, ("xi_init()\n")); 711 712 /* Setup the ethernet interrupt mask. */ 713 PAGE(sc, 1); 714 bus_space_write_1(bst, bsh, IMR0, 715 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 716 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 717 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 718 /* XXX What is this? Not for Dingo at least. */ 719 /* Unmask TX underrun detection */ 720 bus_space_write_1(bst, bsh, IMR1, 1); 721 } 722 723 /* Enable interrupts. */ 724 PAGE(sc, 0); 725 bus_space_write_1(bst, bsh, CR, ENABLE_INT); 726 727 xi_set_address(sc); 728 729 PAGE(sc, 0x40); 730 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE); 731 732 PAGE(sc, 0); 733 734 /* Set current media. */ 735 mii_mediachg(&sc->sc_mii); 736 737 ifp->if_flags |= IFF_RUNNING; 738 ifp->if_flags &= ~IFF_OACTIVE; 739 740 xi_start(ifp); 741 } 742 743 /* 744 * Start outputting on the interface. 745 * Always called as splnet(). 746 */ 747 STATIC void 748 xi_start(struct ifnet *ifp) 749 { 750 struct xi_softc *sc = ifp->if_softc; 751 bus_space_tag_t bst = sc->sc_bst; 752 bus_space_handle_t bsh = sc->sc_bsh; 753 unsigned int s, len, pad = 0; 754 struct mbuf *m0, *m; 755 uint16_t space; 756 757 DPRINTF(XID_CONFIG, ("xi_start()\n")); 758 759 /* Don't transmit if interface is busy or not running. */ 760 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 761 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 762 return; 763 } 764 765 /* Peek at the next packet. */ 766 IFQ_POLL(&ifp->if_snd, m0); 767 if (m0 == 0) 768 return; 769 770 /* We need to use m->m_pkthdr.len, so require the header. */ 771 if (!(m0->m_flags & M_PKTHDR)) 772 panic("xi_start: no header mbuf"); 773 774 len = m0->m_pkthdr.len; 775 776 #if 1 777 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 778 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 779 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 780 #else 781 pad = 0; 782 #endif 783 784 PAGE(sc, 0); 785 786 bus_space_write_2(bst, bsh, TRS, (uint16_t)len + pad + 2); 787 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff; 788 if (len + pad + 2 > space) { 789 DPRINTF(XID_FIFO, 790 ("xi: not enough space in output FIFO (%d > %d)\n", 791 len + pad + 2, space)); 792 return; 793 } 794 795 IFQ_DEQUEUE(&ifp->if_snd, m0); 796 797 bpf_mtap(ifp, m0, BPF_D_OUT); 798 799 /* 800 * Do the output at splhigh() so that an interrupt from another device 801 * won't cause a FIFO underrun. 802 */ 803 s = splhigh(); 804 805 bus_space_write_2(bst, bsh, EDP, (uint16_t)len + pad); 806 for (m = m0; m; ) { 807 if (m->m_len > 1) 808 bus_space_write_multi_2(bst, bsh, EDP, 809 mtod(m, uint16_t *), m->m_len>>1); 810 if (m->m_len & 1) { 811 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 812 bus_space_write_1(bst, bsh, EDP, 813 *(mtod(m, uint8_t *) + m->m_len - 1)); 814 } 815 m = m0 = m_free(m); 816 } 817 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 818 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 819 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT); 820 else { 821 for (; pad > 1; pad -= 2) 822 bus_space_write_2(bst, bsh, EDP, 0); 823 if (pad == 1) 824 bus_space_write_1(bst, bsh, EDP, 0); 825 } 826 827 splx(s); 828 829 ifp->if_timer = 5; 830 ++ifp->if_opackets; 831 } 832 833 STATIC int 834 xi_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 835 { 836 struct ifaddr *ifa = (struct ifaddr *)data; 837 struct xi_softc *sc = ifp->if_softc; 838 int error; 839 840 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 841 842 switch (cmd) { 843 case SIOCINITIFADDR: 844 if ((error = xi_enable(sc)) != 0) 845 break; 846 847 ifp->if_flags |= IFF_UP; 848 849 xi_init(sc); 850 switch (ifa->ifa_addr->sa_family) { 851 #ifdef INET 852 case AF_INET: 853 arp_ifinit(ifp, ifa); 854 break; 855 #endif /* INET */ 856 857 858 default: 859 break; 860 } 861 break; 862 863 default: 864 return (EINVAL); 865 } 866 867 return (0); 868 } 869 870 STATIC int 871 xi_ioctl(struct ifnet *ifp, u_long cmd, void *data) 872 { 873 struct xi_softc *sc = ifp->if_softc; 874 int s, error = 0; 875 876 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 877 878 s = splnet(); 879 880 switch (cmd) { 881 case SIOCINITIFADDR: 882 error = xi_ether_ioctl(ifp, cmd, data); 883 break; 884 885 case SIOCSIFFLAGS: 886 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 887 break; 888 /* XXX re-use ether_ioctl() */ 889 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 890 case IFF_RUNNING: 891 /* 892 * If interface is marked down and it is running, 893 * stop it. 894 */ 895 xi_stop(sc); 896 ifp->if_flags &= ~IFF_RUNNING; 897 xi_disable(sc); 898 break; 899 case IFF_UP: 900 /* 901 * If interface is marked up and it is stopped, 902 * start it. 903 */ 904 if ((error = xi_enable(sc)) != 0) 905 break; 906 xi_init(sc); 907 break; 908 case IFF_UP|IFF_RUNNING: 909 /* 910 * Reset the interface to pick up changes in any 911 * other flags that affect hardware registers. 912 */ 913 xi_set_address(sc); 914 break; 915 case 0: 916 break; 917 } 918 break; 919 920 case SIOCADDMULTI: 921 case SIOCDELMULTI: 922 if (sc->sc_enabled == 0) { 923 error = EIO; 924 break; 925 } 926 /*FALLTHROUGH*/ 927 case SIOCSIFMEDIA: 928 case SIOCGIFMEDIA: 929 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 930 /* 931 * Multicast list has changed; set the hardware 932 * filter accordingly. 933 */ 934 if (ifp->if_flags & IFF_RUNNING) 935 xi_set_address(sc); 936 error = 0; 937 } 938 break; 939 940 default: 941 error = ether_ioctl(ifp, cmd, data); 942 break; 943 } 944 945 splx(s); 946 return (error); 947 } 948 949 STATIC void 950 xi_set_address(struct xi_softc *sc) 951 { 952 bus_space_tag_t bst = sc->sc_bst; 953 bus_space_handle_t bsh = sc->sc_bsh; 954 struct ethercom *ether = &sc->sc_ethercom; 955 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 956 struct ether_multistep step; 957 struct ether_multi *enm; 958 int page, num; 959 int i; 960 uint8_t x; 961 const uint8_t *enaddr; 962 uint8_t indaddr[64]; 963 964 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 965 966 enaddr = (const uint8_t *)CLLADDR(ifp->if_sadl); 967 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 968 for (i = 0; i < 6; i++) 969 indaddr[i] = enaddr[5 - i]; 970 else 971 for (i = 0; i < 6; i++) 972 indaddr[i] = enaddr[i]; 973 num = 1; 974 975 if (ether->ec_multicnt > 9) { 976 ifp->if_flags |= IFF_ALLMULTI; 977 goto done; 978 } 979 980 ETHER_FIRST_MULTI(step, ether, enm); 981 for (; enm; num++) { 982 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 983 sizeof(enm->enm_addrlo)) != 0) { 984 /* 985 * The multicast address is really a range; 986 * it's easier just to accept all multicasts. 987 * XXX should we be setting IFF_ALLMULTI here? 988 */ 989 ifp->if_flags |= IFF_ALLMULTI; 990 goto done; 991 } 992 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 993 for (i = 0; i < 6; i++) 994 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 995 else 996 for (i = 0; i < 6; i++) 997 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 998 ETHER_NEXT_MULTI(step, enm); 999 } 1000 ifp->if_flags &= ~IFF_ALLMULTI; 1001 1002 done: 1003 if (num < 10) 1004 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 1005 1006 for (page = 0; page < 8; page++) { 1007 #ifdef XIDEBUG 1008 if (xidebug & XID_MCAST) { 1009 printf("page %d before:", page); 1010 for (i = 0; i < 8; i++) 1011 printf(" %02x", indaddr[page * 8 + i]); 1012 printf("\n"); 1013 } 1014 #endif 1015 1016 PAGE(sc, 0x50 + page); 1017 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8], 1018 page == 7 ? 4 : 8); 1019 /* 1020 * XXX 1021 * Without this delay, the address registers on my CE2 get 1022 * trashed the first and I have to cycle it. I have no idea 1023 * why. - mycroft, 2004/08/09 1024 */ 1025 DELAY(50); 1026 1027 #ifdef XIDEBUG 1028 if (xidebug & XID_MCAST) { 1029 bus_space_read_region_1(bst, bsh, IA, 1030 &indaddr[page * 8], page == 7 ? 4 : 8); 1031 printf("page %d after: ", page); 1032 for (i = 0; i < 8; i++) 1033 printf(" %02x", indaddr[page * 8 + i]); 1034 printf("\n"); 1035 } 1036 #endif 1037 } 1038 1039 PAGE(sc, 0x42); 1040 x = SWC1_IND_ADDR; 1041 if (ifp->if_flags & IFF_PROMISC) 1042 x |= SWC1_PROMISC; 1043 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) 1044 x |= SWC1_MCAST_PROM; 1045 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1046 x |= SWC1_AUTO_MEDIA; 1047 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x); 1048 } 1049 1050 STATIC void 1051 xi_cycle_power(struct xi_softc *sc) 1052 { 1053 bus_space_tag_t bst = sc->sc_bst; 1054 bus_space_handle_t bsh = sc->sc_bsh; 1055 1056 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1057 1058 PAGE(sc, 4); 1059 DELAY(1); 1060 bus_space_write_1(bst, bsh, GP1, 0); 1061 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1062 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1063 bus_space_write_1(bst, bsh, GP1, POWER_UP); 1064 else 1065 /* XXX What is bit 2 (aka AIC)? */ 1066 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4); 1067 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1068 } 1069 1070 STATIC void 1071 xi_full_reset(struct xi_softc *sc) 1072 { 1073 bus_space_tag_t bst = sc->sc_bst; 1074 bus_space_handle_t bsh = sc->sc_bsh; 1075 uint8_t x; 1076 1077 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1078 1079 /* Do an as extensive reset as possible on all functions. */ 1080 xi_cycle_power(sc); 1081 bus_space_write_1(bst, bsh, CR, SOFT_RESET); 1082 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1083 bus_space_write_1(bst, bsh, CR, 0); 1084 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1085 PAGE(sc, 4); 1086 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1087 /* 1088 * Drive GP1 low to power up ML6692 and GP2 high to power up 1089 * the 10MHz chip. XXX What chip is that? The phy? 1090 */ 1091 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR); 1092 } 1093 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1094 1095 /* Get revision information. XXX Symbolic constants. */ 1096 sc->sc_rev = bus_space_read_1(bst, bsh, BV) & 1097 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1098 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1099 1100 /* Media selection. XXX Maybe manual overriding too? */ 1101 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1102 /* 1103 * XXX I have no idea what this really does, it is from the 1104 * Linux driver. 1105 */ 1106 bus_space_write_1(bst, bsh, GP0, GP1_OUT); 1107 } 1108 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1109 1110 /* 1111 * Disable source insertion. 1112 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1113 */ 1114 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1115 PAGE(sc, 0x42); 1116 bus_space_write_1(bst, bsh, SWC0, 0x20); 1117 } 1118 1119 /* Set the local memory dividing line. */ 1120 if (sc->sc_rev != 1) { 1121 PAGE(sc, 2); 1122 /* XXX Symbolic constant preferrable. */ 1123 bus_space_write_2(bst, bsh, RBS0, 0x2000); 1124 } 1125 1126 /* 1127 * Apparently the receive byte pointer can be bad after a reset, so 1128 * we hardwire it correctly. 1129 */ 1130 PAGE(sc, 0); 1131 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET); 1132 1133 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1134 PAGE(sc, 0x40); 1135 bus_space_write_1(bst, bsh, RX0MSK, 1136 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1137 bus_space_write_1(bst, bsh, TX0MSK, 1138 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1139 SQE | TX_ABORT | TX_OK); 1140 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1141 /* XXX From Linux, dunno what 0xb0 means. */ 1142 bus_space_write_1(bst, bsh, TX1MSK, 0xb0); 1143 bus_space_write_1(bst, bsh, RXST0, 0); 1144 bus_space_write_1(bst, bsh, TXST0, 0); 1145 bus_space_write_1(bst, bsh, TXST1, 0); 1146 1147 PAGE(sc, 2); 1148 1149 /* Enable MII function if available. */ 1150 x = 0; 1151 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1152 x |= SELECT_MII; 1153 bus_space_write_1(bst, bsh, MSR, x); 1154 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1155 1156 /* Configure the LED registers. */ 1157 /* XXX This is not good for 10base2. */ 1158 bus_space_write_1(bst, bsh, LED, 1159 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1160 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1161 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT); 1162 1163 /* 1164 * The Linux driver says this: 1165 * We should switch back to page 0 to avoid a bug in revision 0 1166 * where regs with offset below 8 can't be read after an access 1167 * to the MAC registers. 1168 */ 1169 PAGE(sc, 0); 1170 } 1171
Indexes created Tue Sep 30 17:09:57 GMT 2025